Add Repo: chili-chips-ba_openCologne (part 3)

chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/4.dac/3.build/luttable_lut_module/3.sw/systemverilog/sinewave_code_generator.py

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+import argparse
+import numpy as np
+import math
+
+def generate_unsigned_table(lut_depth, data_width):
+    table_entries = 1 << lut_depth
+    max_value = (1 << data_width) - 1
+
+    sine_data = np.zeros(table_entries, dtype=np.int64)
+
+    for k in range(table_entries):
+        phase = 2.0 * math.pi * k / table_entries
+        # Offset sine wave to start from mid-range (unsigned)
+        sine_data[k] = int((max_value / 2) * (1 + math.sin(phase)))
+
+    return sine_data
+
+def generate_verilog_lut_module(lut_depth, data_width, filename):
+    sine_data = generate_unsigned_table(lut_depth, data_width)
+    table_entries = len(sine_data)
+    
+    verilog_code = f"""
+module sinewave_table #(
+    parameter LUT_DEPTH  = {lut_depth},
+    parameter DATA_WIDTH = {data_width}
+)(
+    input  logic        [LUT_DEPTH-1 :0] address, // {lut_depth}-bit address signal for {table_entries} values
+    output logic [DATA_WIDTH-1:0] value           // {data_width}-bit output signal
+);
+
+    always @(*) begin
+        unique case (address)
+"""
+    for i, value in enumerate(sine_data):
+        verilog_code += f"            {lut_depth}'d{i}: value = {data_width}'h{value:X};\n"
+
+    verilog_code += f"""            default: value = {data_width}'h0;
+        endcase
+    end
+
+endmodule
+"""
+    with open(filename, "w") as f:
+        f.write(verilog_code)
+
+    return verilog_code
+
+def generate_verilog_sinewave_generator(lut_depth, data_width, phase_width, filename):
+    verilog_code = f"""
+module sinewave_generator #(
+    parameter DATA_WIDTH  = {data_width},
+              LUT_DEPTH   = {lut_depth},
+              PHASE_WIDTH = {phase_width}
+) (
+    input  logic                          clk,
+    input  logic                          arst,
+    input  logic                          sample_clk_ce,
+    input  logic signed [PHASE_WIDTH-1:0] phase_increment,
+    output logic [DATA_WIDTH -1:0] sinewave,
+    output logic [DATA_WIDTH -1:0] cosinewave
+);
+
+  logic [PHASE_WIDTH-1:0] phase_accumulator;
+
+  sinewave_table #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .LUT_DEPTH(LUT_DEPTH)
+  ) sinewave_inst (
+    .address(phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH]),
+    .value(sinewave)
+  );
+
+  sinewave_table #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .LUT_DEPTH(LUT_DEPTH)
+  ) cosinewave_inst (
+    .address((phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH] + (1<<(LUT_DEPTH-2))) % (1<<LUT_DEPTH)),
+    .value(cosinewave)
+  );
+
+  always @(posedge clk or posedge arst) begin
+    if (arst == 1'b1)
+      phase_accumulator <= '0;
+    else if (sample_clk_ce == 1'b1)
+      phase_accumulator <= PHASE_WIDTH'(phase_accumulator + phase_increment);
+  end
+
+  //=============================//
+  //       For sim only          //
+  //=============================//
+  //`ifdef SIMULATION
+  initial begin
+    $dumpfile("sinewave_waves.vcd");
+    $dumpvars(0, sinewave_generator);
+  end
+  //`endif
+
+
+endmodule
+"""
+    with open(filename, "w") as f:
+        f.write(verilog_code)
+
+    return verilog_code
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description="Generate Verilog sinewave modules")
+    parser.add_argument("--lut_depth", "-ld", type=int, default=8, help="Number of address bits for the LUT (default: 8)")
+    parser.add_argument("--data_width", "-dw", type=int, default=7, help="Number of output bits for the sine wave (default: 7)")
+    parser.add_argument("--phase_width", "-pw", type=int, default=64, help="Number of bits for the phase accumulator (default: 64)")
+    parser.add_argument("--lut_filename", "-lf", type=str, default="sinewave_table.sv", help="Output filename for the LUT module (default: sinewave_table.sv)")
+    parser.add_argument("--generator_filename", "-gf", type=str, default="sinewave_generator.sv", help="Output filename for the sinewave generator module (default: sinewave_generator.sv)")
+
+    args = parser.parse_args()
+
+    # Generate the LUT Verilog module
+    generate_verilog_lut_module(args.lut_depth, args.data_width, args.lut_filename)
+
+    # Generate the sinewave generator Verilog module
+    generate_verilog_sinewave_generator(args.lut_depth, args.data_width, args.phase_width, args.generator_filename)

chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/4.dac/3.build/luttable_lut_module/3.sw/verilog/sinewave_code_generator.py

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+import argparse
+import numpy as np
+import math
+
+def generate_unsigned_table(lut_depth, data_width):
+    table_entries = 1 << lut_depth
+    max_value = (1 << data_width) - 1  # Maximum unsigned value for the given data width
+
+    sine_data = np.zeros(table_entries, dtype=np.int64)
+
+    for k in range(table_entries):
+        phase = 2.0 * math.pi * k / table_entries
+        # Offset sine wave to start from mid-range (unsigned)
+        sine_data[k] = int((max_value / 2) * (1 + math.sin(phase)))
+
+    return sine_data
+
+def generate_verilog_lut_module(lut_depth, data_width, filename):
+    sine_data = generate_unsigned_table(lut_depth, data_width)
+    table_entries = len(sine_data)
+    
+    verilog_code = f"""
+module sinewave_table #(
+    parameter LUT_DEPTH  = {lut_depth},
+    parameter DATA_WIDTH = {data_width}
+)(
+    input  wire [LUT_DEPTH-1:0] address, // {lut_depth}-bit address signal for {table_entries} values
+    output reg [DATA_WIDTH-1:0] value    // {data_width}-bit unsigned output signal
+);
+
+    always @(*) begin
+        unique case (address)
+"""
+    for i, value in enumerate(sine_data):
+        verilog_code += f"            {lut_depth}'d{i}: value = {data_width}'h{value:X};\n"
+
+    verilog_code += f"""            default: value = {data_width}'h0;
+        endcase
+    end
+
+endmodule
+"""
+    with open(filename, "w") as f:
+        f.write(verilog_code)
+
+    return verilog_code
+
+def generate_verilog_sinewave_generator(lut_depth, data_width, phase_width, filename):
+    verilog_code = f"""
+module sinewave_generator #(
+    parameter DATA_WIDTH  = {data_width},
+              LUT_DEPTH   = {lut_depth},
+              PHASE_WIDTH = {phase_width}
+) (
+    input  wire                          clk,
+    input  wire                          arst,
+    input  wire                          sample_clk_ce,
+    input  wire [PHASE_WIDTH-1:0]        phase_increment,
+    output reg [DATA_WIDTH-1:0]          sinewave,
+    output reg [DATA_WIDTH-1:0]          cosinewave
+);
+
+  reg [PHASE_WIDTH-1:0] phase_accumulator;
+
+  sinewave_table #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .LUT_DEPTH(LUT_DEPTH)
+  ) sinewave_inst (
+    .address(phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH]),
+    .value(sinewave)
+  );
+
+  sinewave_table #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .LUT_DEPTH(LUT_DEPTH)
+  ) cosinewave_inst (
+    .address((phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH] + (1<<(LUT_DEPTH-2))) % (1<<LUT_DEPTH)),
+    .value(cosinewave)
+  );
+
+  always @(posedge clk or posedge arst) begin
+    if (arst == 1'b1)
+      phase_accumulator <= 0;
+    else if (sample_clk_ce == 1'b1)
+      phase_accumulator <= phase_accumulator + phase_increment;
+  end
+
+  //=============================//
+  //       For sim only          //
+  //=============================//
+  //`ifdef SIMULATION
+  initial begin
+    $dumpfile("sinewave_waves.vcd");
+    $dumpvars(0, sinewave_generator);
+  end
+  //`endif
+endmodule
+"""
+    with open(filename, "w") as f:
+        f.write(verilog_code)
+
+    return verilog_code
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description="Generate Verilog sinewave modules")
+    parser.add_argument("--lut_depth", "-ld", type=int, default=8, help="Number of address bits for the LUT (default: 8)")
+    parser.add_argument("--data_width", "-dw", type=int, default=7, help="Number of output bits for the sine wave (default: 7)")
+    parser.add_argument("--phase_width", "-pw", type=int, default=64, help="Number of bits for the phase accumulator (default: 64)")
+    parser.add_argument("--lut_filename", "-lf", type=str, default="sinewave_table.v", help="Output filename for the LUT module (default: sinewave_table.v)")
+    parser.add_argument("--generator_filename", "-gf", type=str, default="sinewave_generator.v", help="Output filename for the sinewave generator module (default: sinewave_generator.v)")
+
+    args = parser.parse_args()
+
+    # Generate the LUT Verilog module
+    generate_verilog_lut_module(args.lut_depth, args.data_width, args.lut_filename)
+
+    # Generate the sinewave generator Verilog module
+    generate_verilog_sinewave_generator(args.lut_depth, args.data_width, args.phase_width, args.generator_filename)

chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/README.md

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+# openCologne - Yamaha OPL3 FM Audio Synth
+## * WORK IN PROGRESS * UNDER CONSTRUCTION *
+> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN'
+
+This is a triple exciting port of @gtaylormb [project](https://github.com/gtaylormb/opl3_fpga) to _Yosys_ and _GateMate_ FPGA.
+ - **Excitment#1**: Original design is super cool on its own, as it is about the heart of the uber-popular _SoundblasterPro_ audio card from the turbulent '90s.
+ - **Excitment#2**: RTL is written in, for opensource, unusally rich  complement of _SystemVerilog_. The original project had vetted this RTL only with Xilinx-proprietary Vivado. These two circumstances make this codebase a formidable [challenge](https://github.com/chili-chips-ba/openCologne/issues/3) for opensource [Yosys](https://github.com/YosysHQ/yosys) synthesis. And yes, with every challenge comes an opportunity :blush:.
+ - **Excitment#3**: As of yet, there are no GateMate designs of this complexity. We are therefore buckled up for a fun, bumpy rollercoaster ride. 
+
+Regarding excitment/challenge#2, having tried [Synlig plugin](https://github.com/chipsalliance/synlig) and [Yosys-Slang](https://github.com/povik/yosys-slang), we ended up converging on @zachjs's [SV2V](https://github.com/zachjs/sv2v). This can also be viewed as an independant validation and confirmation of @pu-cc's advice on the opensource flow that works best for _SystemVerilog_.
+
+To get started, first install SV2V and other tools, as explained in [0.doc](https://github.com/chili-chips-ba/openCologne/blob/main/0.doc/1.README.Tool-Installs.txt). Then:
+```
+% cd 3.build
+% make synth
+```
+
+This OPL3 design produces 100% digital audio in I2S format. To hear anything, it needs to be complemented with an external compatible audio CODEC, such as:
+> - https://github.com/goran-mahovlic/ulx3s-extensions
+> - https://www.waveshare.com/wm8960-audio-board.htm
+   
+For fun, also see OPL3 software emulators. Beware, they are not as good and not as precise as this pure hardware, re-engineered Yamaha chip. 
+> - https://github.com/Wohlstand/libADLMIDI
+> - https://github.com/nukeykt/Nuked-OPL3
+
+
+#### End of Document

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/debounce.v

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+//fpga4student.com: FPGA projects, Verilog projects, VHDL projects
+// Verilog code for button debouncing on FPGA
+// debouncing module without creating another clock domain
+// by using clock enable signal 
+module debounce(
+	input clk,
+	input in,
+	output out
+);
+
+	wire slow_clk_en;
+	wire Q1,Q2,Q2_bar,Q0;
+
+	clock_enable u1(clk,slow_clk_en);
+	my_dff_en d0(clk,slow_clk_en,in,Q0);
+	my_dff_en d1(clk,slow_clk_en,Q0,Q1);
+	my_dff_en d2(clk,slow_clk_en,Q1,Q2);
+	
+	assign Q2_bar = ~Q2;
+	assign out = Q1 & Q2_bar;
+endmodule
+
+// Slow clock enable for debouncing button 
+module clock_enable(
+	input Clk_100M,
+	output slow_clk_en
+);
+    reg [26:0]counter=0;
+	
+    always @(posedge Clk_100M)
+    begin
+       counter <= (counter>=24999) ? 0 : counter + 1;
+    end
+
+    assign slow_clk_en = (counter == 24999) ? 1'b1 : 1'b0;
+endmodule
+
+// D-flip-flop with clock enable signal for debouncing module 
+module my_dff_en(
+	input DFF_CLOCK, 
+	input clock_enable, 
+	input D, 
+	output reg Q=0
+);
+
+    always @ (posedge DFF_CLOCK) 
+	begin
+		if(clock_enable==1) 
+			Q <= D;
+    end
+	
+endmodule 
+

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/gatemate_25MHz_pll.v

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+/*
+ * gatemate_25MHz_pll.v
+ *
+ * Copyright (C) 2022-2024  Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
+ * SPDX-License-Identifier: MIT
+ */
+module pll (
+    input  wire clock_in,
+    input  wire rst_in,
+    output wire clock_out,
+    output reg  locked
+);
+
+wire clk270, clk180, clk90, clk0, usr_ref_out;
+wire usr_pll_lock;
+
+wire pll_clk_nobuf;
+CC_PLL #(
+    .REF_CLK("10.0"),    // reference input in MHz
+    .OUT_CLK("25.0"),    // pll output frequency in MHz
+    .LOCK_REQ(0),        // 1: Lock status required before PLL output enable
+                         // 0: PLL output before lock
+    .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
+    .LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
+    .CI_FILTER_CONST(2), // optional CI filter constant
+    .CP_FILTER_CONST(4)  // optional CP filter constant
+) pll25 (
+    .CLK_REF(clock_in), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0),
+    /* USR_LOCKED_STDY_RST and USR_PLL_LOCKED_STDY are more or less
+     * for debug purpose. USR_PLL_LOCKED_STDY is high after first lock
+     * goes low if PLL unlock and stay low until USR_LOCKED_STDY_RST is
+     * set during 2 clock cycles
+     */
+    .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(),
+    .USR_PLL_LOCKED(usr_pll_lock),
+    .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(pll_clk_nobuf), .CLK_REF_OUT(usr_ref_out)
+);
+CC_BUFG pll_bufg (.I(pll_clk_nobuf), .O(clock_out));
+
+// reset is synced the clock
+reg locked_s1;
+always @(posedge clock_out) begin
+    locked_s1 <= usr_pll_lock & ~rst_in;
+    locked <= locked_s1;
+end
+
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picorv32.v

@@ -0,0 +1,2977 @@
+/*
+ *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ *  Copyright (C) 2015  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+// `default_nettype none
+// `define DEBUGNETS
+// `define DEBUGREGS
+// `define DEBUGASM
+// `define DEBUG
+
+`ifdef DEBUG
+  `define debug(debug_command) debug_command
+`else
+  `define debug(debug_command)
+`endif
+
+`ifdef FORMAL
+  `define FORMAL_KEEP (* keep *)
+  `define assert(assert_expr) assert(assert_expr)
+`else
+  `ifdef DEBUGNETS
+    `define FORMAL_KEEP (* keep *)
+  `else
+    `define FORMAL_KEEP
+  `endif
+  `define assert(assert_expr) empty_statement
+`endif
+
+// uncomment this for register file in extra module
+// `define PICORV32_REGS picorv32_regs
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICORV32_V
+
+
+/***************************************************************
+ * picorv32
+ ***************************************************************/
+
+module picorv32 #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] LATCHED_MEM_RDATA = 0,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0010_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output reg trap,
+
+	output reg        mem_valid,
+	output reg        mem_instr,
+	input             mem_ready,
+
+	output reg [31:0] mem_addr,
+	output reg [31:0] mem_wdata,
+	output reg [ 3:0] mem_wstrb,
+	input      [31:0] mem_rdata,
+
+	// Look-Ahead Interface
+	output            mem_la_read,
+	output            mem_la_write,
+	output     [31:0] mem_la_addr,
+	output reg [31:0] mem_la_wdata,
+	output reg [ 3:0] mem_la_wstrb,
+
+	// Pico Co-Processor Interface (PCPI)
+	output reg        pcpi_valid,
+	output reg [31:0] pcpi_insn,
+	output     [31:0] pcpi_rs1,
+	output     [31:0] pcpi_rs2,
+	input             pcpi_wr,
+	input      [31:0] pcpi_rd,
+	input             pcpi_wait,
+	input             pcpi_ready,
+
+	// IRQ Interface
+	input      [31:0] irq,
+	output reg [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output reg        rvfi_valid,
+	output reg [63:0] rvfi_order,
+	output reg [31:0] rvfi_insn,
+	output reg        rvfi_trap,
+	output reg        rvfi_halt,
+	output reg        rvfi_intr,
+	output reg [ 4:0] rvfi_rs1_addr,
+	output reg [ 4:0] rvfi_rs2_addr,
+	output reg [31:0] rvfi_rs1_rdata,
+	output reg [31:0] rvfi_rs2_rdata,
+	output reg [ 4:0] rvfi_rd_addr,
+	output reg [31:0] rvfi_rd_wdata,
+	output reg [31:0] rvfi_pc_rdata,
+	output reg [31:0] rvfi_pc_wdata,
+	output reg [31:0] rvfi_mem_addr,
+	output reg [ 3:0] rvfi_mem_rmask,
+	output reg [ 3:0] rvfi_mem_wmask,
+	output reg [31:0] rvfi_mem_rdata,
+	output reg [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output reg        trace_valid,
+	output reg [35:0] trace_data
+);
+	localparam integer irq_timer = 0;
+	localparam integer irq_ebreak = 1;
+	localparam integer irq_buserror = 2;
+
+	localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
+	localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+	localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+
+	localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+
+	localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
+	localparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};
+	localparam [35:0] TRACE_IRQ    = {4'b 1000, 32'b 0};
+
+	reg [63:0] count_cycle, count_instr;
+	reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+	reg [4:0] reg_sh;
+
+	reg [31:0] next_insn_opcode;
+	reg [31:0] dbg_insn_opcode;
+	reg [31:0] dbg_insn_addr;
+
+	wire dbg_mem_valid = mem_valid;
+	wire dbg_mem_instr = mem_instr;
+	wire dbg_mem_ready = mem_ready;
+	wire [31:0] dbg_mem_addr  = mem_addr;
+	wire [31:0] dbg_mem_wdata = mem_wdata;
+	wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
+	wire [31:0] dbg_mem_rdata = mem_rdata;
+
+	assign pcpi_rs1 = reg_op1;
+	assign pcpi_rs2 = reg_op2;
+
+	wire [31:0] next_pc;
+
+	reg irq_delay;
+	reg irq_active;
+	reg [31:0] irq_mask;
+	reg [31:0] irq_pending;
+	reg [31:0] timer;
+
+`ifndef PICORV32_REGS
+	reg [31:0] cpuregs [0:regfile_size-1];
+
+	integer i;
+	initial begin
+		if (REGS_INIT_ZERO) begin
+			for (i = 0; i < regfile_size; i = i+1)
+				cpuregs[i] = 0;
+		end
+	end
+`endif
+
+	task empty_statement;
+		// This task is used by the `assert directive in non-formal mode to
+		// avoid empty statement (which are unsupported by plain Verilog syntax).
+		begin end
+	endtask
+
+`ifdef DEBUGREGS
+	wire [31:0] dbg_reg_x0  = 0;
+	wire [31:0] dbg_reg_x1  = cpuregs[1];
+	wire [31:0] dbg_reg_x2  = cpuregs[2];
+	wire [31:0] dbg_reg_x3  = cpuregs[3];
+	wire [31:0] dbg_reg_x4  = cpuregs[4];
+	wire [31:0] dbg_reg_x5  = cpuregs[5];
+	wire [31:0] dbg_reg_x6  = cpuregs[6];
+	wire [31:0] dbg_reg_x7  = cpuregs[7];
+	wire [31:0] dbg_reg_x8  = cpuregs[8];
+	wire [31:0] dbg_reg_x9  = cpuregs[9];
+	wire [31:0] dbg_reg_x10 = cpuregs[10];
+	wire [31:0] dbg_reg_x11 = cpuregs[11];
+	wire [31:0] dbg_reg_x12 = cpuregs[12];
+	wire [31:0] dbg_reg_x13 = cpuregs[13];
+	wire [31:0] dbg_reg_x14 = cpuregs[14];
+	wire [31:0] dbg_reg_x15 = cpuregs[15];
+	wire [31:0] dbg_reg_x16 = cpuregs[16];
+	wire [31:0] dbg_reg_x17 = cpuregs[17];
+	wire [31:0] dbg_reg_x18 = cpuregs[18];
+	wire [31:0] dbg_reg_x19 = cpuregs[19];
+	wire [31:0] dbg_reg_x20 = cpuregs[20];
+	wire [31:0] dbg_reg_x21 = cpuregs[21];
+	wire [31:0] dbg_reg_x22 = cpuregs[22];
+	wire [31:0] dbg_reg_x23 = cpuregs[23];
+	wire [31:0] dbg_reg_x24 = cpuregs[24];
+	wire [31:0] dbg_reg_x25 = cpuregs[25];
+	wire [31:0] dbg_reg_x26 = cpuregs[26];
+	wire [31:0] dbg_reg_x27 = cpuregs[27];
+	wire [31:0] dbg_reg_x28 = cpuregs[28];
+	wire [31:0] dbg_reg_x29 = cpuregs[29];
+	wire [31:0] dbg_reg_x30 = cpuregs[30];
+	wire [31:0] dbg_reg_x31 = cpuregs[31];
+`endif
+
+	// Internal PCPI Cores
+
+	wire        pcpi_mul_wr;
+	wire [31:0] pcpi_mul_rd;
+	wire        pcpi_mul_wait;
+	wire        pcpi_mul_ready;
+
+	wire        pcpi_div_wr;
+	wire [31:0] pcpi_div_rd;
+	wire        pcpi_div_wait;
+	wire        pcpi_div_ready;
+
+	reg        pcpi_int_wr;
+	reg [31:0] pcpi_int_rd;
+	reg        pcpi_int_wait;
+	reg        pcpi_int_ready;
+
+	generate if (ENABLE_FAST_MUL) begin
+		picorv32_pcpi_fast_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else if (ENABLE_MUL) begin
+		picorv32_pcpi_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else begin
+		assign pcpi_mul_wr = 0;
+		assign pcpi_mul_rd = 32'bx;
+		assign pcpi_mul_wait = 0;
+		assign pcpi_mul_ready = 0;
+	end endgenerate
+
+	generate if (ENABLE_DIV) begin
+		picorv32_pcpi_div pcpi_div (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_div_wr    ),
+			.pcpi_rd   (pcpi_div_rd    ),
+			.pcpi_wait (pcpi_div_wait  ),
+			.pcpi_ready(pcpi_div_ready )
+		);
+	end else begin
+		assign pcpi_div_wr = 0;
+		assign pcpi_div_rd = 32'bx;
+		assign pcpi_div_wait = 0;
+		assign pcpi_div_ready = 0;
+	end endgenerate
+
+	always @* begin
+		pcpi_int_wr = 0;
+		pcpi_int_rd = 32'bx;
+		pcpi_int_wait  = |{ENABLE_PCPI && pcpi_wait,  (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait,  ENABLE_DIV && pcpi_div_wait};
+		pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+
+		(* parallel_case *)
+		case (1'b1)
+			ENABLE_PCPI && pcpi_ready: begin
+				pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
+				pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+			end
+			(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+				pcpi_int_wr = pcpi_mul_wr;
+				pcpi_int_rd = pcpi_mul_rd;
+			end
+			ENABLE_DIV && pcpi_div_ready: begin
+				pcpi_int_wr = pcpi_div_wr;
+				pcpi_int_rd = pcpi_div_rd;
+			end
+		endcase
+	end
+
+
+	// Memory Interface
+
+	reg [1:0] mem_state;
+	reg [1:0] mem_wordsize;
+	reg [31:0] mem_rdata_word;
+	reg [31:0] mem_rdata_q;
+	reg mem_do_prefetch;
+	reg mem_do_rinst;
+	reg mem_do_rdata;
+	reg mem_do_wdata;
+
+	wire mem_xfer;
+	reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
+	wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
+	wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
+
+	reg prefetched_high_word;
+	reg clear_prefetched_high_word;
+	reg [15:0] mem_16bit_buffer;
+
+	wire [31:0] mem_rdata_latched_noshuffle;
+	wire [31:0] mem_rdata_latched;
+
+	wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
+	assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
+
+	wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
+	wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
+			(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
+
+	assign mem_la_write = resetn && !mem_state && mem_do_wdata;
+	assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
+			(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
+	assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
+
+	assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+
+	assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			mem_la_firstword_reg <= 0;
+			last_mem_valid <= 0;
+		end else begin
+			if (!last_mem_valid)
+				mem_la_firstword_reg <= mem_la_firstword;
+			last_mem_valid <= mem_valid && !mem_ready;
+		end
+	end
+
+	always @* begin
+		(* full_case *)
+		case (mem_wordsize)
+			0: begin
+				mem_la_wdata = reg_op2;
+				mem_la_wstrb = 4'b1111;
+				mem_rdata_word = mem_rdata;
+			end
+			1: begin
+				mem_la_wdata = {2{reg_op2[15:0]}};
+				mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
+				case (reg_op1[1])
+					1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
+					1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
+				endcase
+			end
+			2: begin
+				mem_la_wdata = {4{reg_op2[7:0]}};
+				mem_la_wstrb = 4'b0001 << reg_op1[1:0];
+				case (reg_op1[1:0])
+					2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
+					2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
+					2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
+					2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
+				endcase
+			end
+		endcase
+	end
+
+	always @(posedge clk) begin
+		if (mem_xfer) begin
+			mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+			next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+		end
+
+		if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
+			case (mem_rdata_latched[1:0])
+				2'b00: begin // Quadrant 0
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.ADDI4SPN
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
+						end
+						3'b010: begin // C.LW
+							mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b 110: begin // C.SW
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+				2'b01: begin // Quadrant 1
+					case (mem_rdata_latched[15:13])
+						3'b 000: begin // C.ADDI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 010: begin // C.LI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 011: begin
+							if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
+										mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
+							end else begin // C.LUI
+								mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+						end
+						3'b100: begin
+							if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
+								mem_rdata_q[31:25] <= 7'b0000000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
+								mem_rdata_q[31:25] <= 7'b0100000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+								mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+							if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+								if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
+								if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
+								if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
+								if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
+							end
+						end
+						3'b 110: begin // C.BEQZ
+							mem_rdata_q[14:12] <= 3'b000;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+						3'b 111: begin // C.BNEZ
+							mem_rdata_q[14:12] <= 3'b001;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+					endcase
+				end
+				2'b10: begin // Quadrant 2
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.SLLI
+							mem_rdata_q[31:25] <= 7'b0000000;
+							mem_rdata_q[14:12] <= 3'b 001;
+						end
+						3'b010: begin // C.LWSP
+							mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b100: begin
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+						end
+						3'b110: begin // C.SWSP
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		if (resetn && !trap) begin
+			if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
+				`assert(!mem_do_wdata);
+
+			if (mem_do_prefetch || mem_do_rinst)
+				`assert(!mem_do_rdata);
+
+			if (mem_do_rdata)
+				`assert(!mem_do_prefetch && !mem_do_rinst);
+
+			if (mem_do_wdata)
+				`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
+
+			if (mem_state == 2 || mem_state == 3)
+				`assert(mem_valid || mem_do_prefetch);
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!resetn || trap) begin
+			if (!resetn)
+				mem_state <= 0;
+			if (!resetn || mem_ready)
+				mem_valid <= 0;
+			mem_la_secondword <= 0;
+			prefetched_high_word <= 0;
+		end else begin
+			if (mem_la_read || mem_la_write) begin
+				mem_addr <= mem_la_addr;
+				mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
+			end
+			if (mem_la_write) begin
+				mem_wdata <= mem_la_wdata;
+			end
+			case (mem_state)
+				0: begin
+					if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
+						mem_valid <= !mem_la_use_prefetched_high_word;
+						mem_instr <= mem_do_prefetch || mem_do_rinst;
+						mem_wstrb <= 0;
+						mem_state <= 1;
+					end
+					if (mem_do_wdata) begin
+						mem_valid <= 1;
+						mem_instr <= 0;
+						mem_state <= 2;
+					end
+				end
+				1: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
+					`assert(mem_valid == !mem_la_use_prefetched_high_word);
+					`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
+					if (mem_xfer) begin
+						if (COMPRESSED_ISA && mem_la_read) begin
+							mem_valid <= 1;
+							mem_la_secondword <= 1;
+							if (!mem_la_use_prefetched_high_word)
+								mem_16bit_buffer <= mem_rdata[31:16];
+						end else begin
+							mem_valid <= 0;
+							mem_la_secondword <= 0;
+							if (COMPRESSED_ISA && !mem_do_rdata) begin
+								if (~&mem_rdata[1:0] || mem_la_secondword) begin
+									mem_16bit_buffer <= mem_rdata[31:16];
+									prefetched_high_word <= 1;
+								end else begin
+									prefetched_high_word <= 0;
+								end
+							end
+							mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
+						end
+					end
+				end
+				2: begin
+					`assert(mem_wstrb != 0);
+					`assert(mem_do_wdata);
+					if (mem_xfer) begin
+						mem_valid <= 0;
+						mem_state <= 0;
+					end
+				end
+				3: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch);
+					if (mem_do_rinst) begin
+						mem_state <= 0;
+					end
+				end
+			endcase
+		end
+
+		if (clear_prefetched_high_word)
+			prefetched_high_word <= 0;
+	end
+
+
+	// Instruction Decoder
+
+	reg instr_lui, instr_auipc, instr_jal, instr_jalr;
+	reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
+	reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
+	reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
+	reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
+	reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
+	reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+	wire instr_trap;
+
+	reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
+	reg [31:0] decoded_imm, decoded_imm_uj;
+	reg decoder_trigger;
+	reg decoder_trigger_q;
+	reg decoder_pseudo_trigger;
+	reg decoder_pseudo_trigger_q;
+	reg compressed_instr;
+
+	reg is_lui_auipc_jal;
+	reg is_lb_lh_lw_lbu_lhu;
+	reg is_slli_srli_srai;
+	reg is_jalr_addi_slti_sltiu_xori_ori_andi;
+	reg is_sb_sh_sw;
+	reg is_sll_srl_sra;
+	reg is_lui_auipc_jal_jalr_addi_add_sub;
+	reg is_slti_blt_slt;
+	reg is_sltiu_bltu_sltu;
+	reg is_beq_bne_blt_bge_bltu_bgeu;
+	reg is_lbu_lhu_lw;
+	reg is_alu_reg_imm;
+	reg is_alu_reg_reg;
+	reg is_compare;
+
+	assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
+			instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
+			instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
+			instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
+			instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
+			instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
+			instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
+
+	wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
+	assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
+
+	reg [63:0] new_ascii_instr;
+	`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
+	`FORMAL_KEEP reg [31:0] dbg_insn_imm;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rd;
+	`FORMAL_KEEP reg [31:0] dbg_rs1val;
+	`FORMAL_KEEP reg [31:0] dbg_rs2val;
+	`FORMAL_KEEP reg dbg_rs1val_valid;
+	`FORMAL_KEEP reg dbg_rs2val_valid;
+
+	always @* begin
+		new_ascii_instr = "";
+
+		if (instr_lui)      new_ascii_instr = "lui";
+		if (instr_auipc)    new_ascii_instr = "auipc";
+		if (instr_jal)      new_ascii_instr = "jal";
+		if (instr_jalr)     new_ascii_instr = "jalr";
+
+		if (instr_beq)      new_ascii_instr = "beq";
+		if (instr_bne)      new_ascii_instr = "bne";
+		if (instr_blt)      new_ascii_instr = "blt";
+		if (instr_bge)      new_ascii_instr = "bge";
+		if (instr_bltu)     new_ascii_instr = "bltu";
+		if (instr_bgeu)     new_ascii_instr = "bgeu";
+
+		if (instr_lb)       new_ascii_instr = "lb";
+		if (instr_lh)       new_ascii_instr = "lh";
+		if (instr_lw)       new_ascii_instr = "lw";
+		if (instr_lbu)      new_ascii_instr = "lbu";
+		if (instr_lhu)      new_ascii_instr = "lhu";
+		if (instr_sb)       new_ascii_instr = "sb";
+		if (instr_sh)       new_ascii_instr = "sh";
+		if (instr_sw)       new_ascii_instr = "sw";
+
+		if (instr_addi)     new_ascii_instr = "addi";
+		if (instr_slti)     new_ascii_instr = "slti";
+		if (instr_sltiu)    new_ascii_instr = "sltiu";
+		if (instr_xori)     new_ascii_instr = "xori";
+		if (instr_ori)      new_ascii_instr = "ori";
+		if (instr_andi)     new_ascii_instr = "andi";
+		if (instr_slli)     new_ascii_instr = "slli";
+		if (instr_srli)     new_ascii_instr = "srli";
+		if (instr_srai)     new_ascii_instr = "srai";
+
+		if (instr_add)      new_ascii_instr = "add";
+		if (instr_sub)      new_ascii_instr = "sub";
+		if (instr_sll)      new_ascii_instr = "sll";
+		if (instr_slt)      new_ascii_instr = "slt";
+		if (instr_sltu)     new_ascii_instr = "sltu";
+		if (instr_xor)      new_ascii_instr = "xor";
+		if (instr_srl)      new_ascii_instr = "srl";
+		if (instr_sra)      new_ascii_instr = "sra";
+		if (instr_or)       new_ascii_instr = "or";
+		if (instr_and)      new_ascii_instr = "and";
+
+		if (instr_rdcycle)  new_ascii_instr = "rdcycle";
+		if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
+		if (instr_rdinstr)  new_ascii_instr = "rdinstr";
+		if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+
+		if (instr_getq)     new_ascii_instr = "getq";
+		if (instr_setq)     new_ascii_instr = "setq";
+		if (instr_retirq)   new_ascii_instr = "retirq";
+		if (instr_maskirq)  new_ascii_instr = "maskirq";
+		if (instr_waitirq)  new_ascii_instr = "waitirq";
+		if (instr_timer)    new_ascii_instr = "timer";
+	end
+
+	reg [63:0] q_ascii_instr;
+	reg [31:0] q_insn_imm;
+	reg [31:0] q_insn_opcode;
+	reg [4:0] q_insn_rs1;
+	reg [4:0] q_insn_rs2;
+	reg [4:0] q_insn_rd;
+	reg dbg_next;
+
+	wire launch_next_insn;
+	reg dbg_valid_insn;
+
+	reg [63:0] cached_ascii_instr;
+	reg [31:0] cached_insn_imm;
+	reg [31:0] cached_insn_opcode;
+	reg [4:0] cached_insn_rs1;
+	reg [4:0] cached_insn_rs2;
+	reg [4:0] cached_insn_rd;
+
+	always @(posedge clk) begin
+		q_ascii_instr <= dbg_ascii_instr;
+		q_insn_imm <= dbg_insn_imm;
+		q_insn_opcode <= dbg_insn_opcode;
+		q_insn_rs1 <= dbg_insn_rs1;
+		q_insn_rs2 <= dbg_insn_rs2;
+		q_insn_rd <= dbg_insn_rd;
+		dbg_next <= launch_next_insn;
+
+		if (!resetn || trap)
+			dbg_valid_insn <= 0;
+		else if (launch_next_insn)
+			dbg_valid_insn <= 1;
+
+		if (decoder_trigger_q) begin
+			cached_ascii_instr <= new_ascii_instr;
+			cached_insn_imm <= decoded_imm;
+			if (&next_insn_opcode[1:0])
+				cached_insn_opcode <= next_insn_opcode;
+			else
+				cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
+			cached_insn_rs1 <= decoded_rs1;
+			cached_insn_rs2 <= decoded_rs2;
+			cached_insn_rd <= decoded_rd;
+		end
+
+		if (launch_next_insn) begin
+			dbg_insn_addr <= next_pc;
+		end
+	end
+
+	always @* begin
+		dbg_ascii_instr = q_ascii_instr;
+		dbg_insn_imm = q_insn_imm;
+		dbg_insn_opcode = q_insn_opcode;
+		dbg_insn_rs1 = q_insn_rs1;
+		dbg_insn_rs2 = q_insn_rs2;
+		dbg_insn_rd = q_insn_rd;
+
+		if (dbg_next) begin
+			if (decoder_pseudo_trigger_q) begin
+				dbg_ascii_instr = cached_ascii_instr;
+				dbg_insn_imm = cached_insn_imm;
+				dbg_insn_opcode = cached_insn_opcode;
+				dbg_insn_rs1 = cached_insn_rs1;
+				dbg_insn_rs2 = cached_insn_rs2;
+				dbg_insn_rd = cached_insn_rd;
+			end else begin
+				dbg_ascii_instr = new_ascii_instr;
+				if (&next_insn_opcode[1:0])
+					dbg_insn_opcode = next_insn_opcode;
+				else
+					dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
+				dbg_insn_imm = decoded_imm;
+				dbg_insn_rs1 = decoded_rs1;
+				dbg_insn_rs2 = decoded_rs2;
+				dbg_insn_rd = decoded_rd;
+			end
+		end
+	end
+
+`ifdef DEBUGASM
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
+		end
+	end
+`endif
+
+`ifdef DEBUG
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			if (&dbg_insn_opcode[1:0])
+				$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+			else
+				$display("DECODE: 0x%08x     0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+		end
+	end
+`endif
+
+	always @(posedge clk) begin
+		is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
+		is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
+		is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
+		is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
+		is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
+		is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
+
+		if (mem_do_rinst && mem_done) begin
+			instr_lui     <= mem_rdata_latched[6:0] == 7'b0110111;
+			instr_auipc   <= mem_rdata_latched[6:0] == 7'b0010111;
+			instr_jal     <= mem_rdata_latched[6:0] == 7'b1101111;
+			instr_jalr    <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
+			instr_retirq  <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
+			instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
+
+			is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
+			is_lb_lh_lw_lbu_lhu          <= mem_rdata_latched[6:0] == 7'b0000011;
+			is_sb_sh_sw                  <= mem_rdata_latched[6:0] == 7'b0100011;
+			is_alu_reg_imm               <= mem_rdata_latched[6:0] == 7'b0010011;
+			is_alu_reg_reg               <= mem_rdata_latched[6:0] == 7'b0110011;
+
+			{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
+
+			decoded_rd <= mem_rdata_latched[11:7];
+			decoded_rs1 <= mem_rdata_latched[19:15];
+			decoded_rs2 <= mem_rdata_latched[24:20];
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
+				decoded_rs1[regindex_bits-1] <= 1; // instr_getq
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
+				decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
+
+			compressed_instr <= 0;
+			if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
+				compressed_instr <= 1;
+				decoded_rd <= 0;
+				decoded_rs1 <= 0;
+				decoded_rs2 <= 0;
+
+				{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
+				  decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
+
+				case (mem_rdata_latched[1:0])
+					2'b00: begin // Quadrant 0
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.ADDI4SPN
+								is_alu_reg_imm <= |mem_rdata_latched[12:5];
+								decoded_rs1 <= 2;
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b010: begin // C.LW
+								is_lb_lh_lw_lbu_lhu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b110: begin // C.SW
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+							end
+						endcase
+					end
+					2'b01: begin // Quadrant 1
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.NOP / C.ADDI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= mem_rdata_latched[11:7];
+							end
+							3'b001: begin // C.JAL
+								instr_jal <= 1;
+								decoded_rd <= 1;
+							end
+							3'b 010: begin // C.LI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= 0;
+							end
+							3'b 011: begin
+								if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
+									if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+										is_alu_reg_imm <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= mem_rdata_latched[11:7];
+									end else begin // C.LUI
+										instr_lui <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= 0;
+									end
+								end
+							end
+							3'b100: begin
+								if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+								if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								end
+								if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+									is_alu_reg_reg <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+								end
+							end
+							3'b101: begin // C.J
+								instr_jal <= 1;
+							end
+							3'b110: begin // C.BEQZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+							3'b111: begin // C.BNEZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+						endcase
+					end
+					2'b10: begin // Quadrant 2
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.SLLI
+								if (!mem_rdata_latched[12]) begin
+									is_alu_reg_imm <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+							end
+							3'b010: begin // C.LWSP
+								if (mem_rdata_latched[11:7]) begin
+									is_lb_lh_lw_lbu_lhu <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 2;
+								end
+							end
+							3'b100: begin
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+									instr_jalr <= 1;
+									decoded_rd <= 0;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 0;
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+									instr_jalr <= 1;
+									decoded_rd <= 1;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+							end
+							3'b110: begin // C.SWSP
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 2;
+								decoded_rs2 <= mem_rdata_latched[6:2];
+							end
+						endcase
+					end
+				endcase
+			end
+		end
+
+		if (decoder_trigger && !decoder_pseudo_trigger) begin
+			pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
+
+			instr_beq   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
+			instr_bne   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
+			instr_blt   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
+			instr_bge   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
+			instr_bltu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
+			instr_bgeu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
+
+			instr_lb    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
+			instr_lh    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
+			instr_lw    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
+			instr_lbu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
+			instr_lhu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
+
+			instr_sb    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
+			instr_sh    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
+			instr_sw    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
+
+			instr_addi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
+			instr_slti  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
+			instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
+			instr_xori  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
+			instr_ori   <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
+			instr_andi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
+
+			instr_slli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srai  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+
+			instr_add   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sub   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_sll   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_slt   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sltu  <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_xor   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srl   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sra   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_or    <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_and   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
+
+			instr_rdcycle  <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
+			instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+			instr_rdinstr  <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
+			instr_rdinstrh <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+
+			instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
+					(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+
+			instr_getq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_setq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
+			instr_timer   <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+
+			is_slli_srli_srai <= is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b000,
+				mem_rdata_q[14:12] == 3'b010,
+				mem_rdata_q[14:12] == 3'b011,
+				mem_rdata_q[14:12] == 3'b100,
+				mem_rdata_q[14:12] == 3'b110,
+				mem_rdata_q[14:12] == 3'b111
+			};
+
+			is_sll_srl_sra <= is_alu_reg_reg && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_lui_auipc_jal_jalr_addi_add_sub <= 0;
+			is_compare <= 0;
+
+			(* parallel_case *)
+			case (1'b1)
+				instr_jal:
+					decoded_imm <= decoded_imm_uj;
+				|{instr_lui, instr_auipc}:
+					decoded_imm <= mem_rdata_q[31:12] << 12;
+				|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
+					decoded_imm <= $signed(mem_rdata_q[31:20]);
+				is_beq_bne_blt_bge_bltu_bgeu:
+					decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
+				is_sb_sh_sw:
+					decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
+				default:
+					decoded_imm <= 1'bx;
+			endcase
+		end
+
+		if (!resetn) begin
+			is_beq_bne_blt_bge_bltu_bgeu <= 0;
+			is_compare <= 0;
+
+			instr_beq   <= 0;
+			instr_bne   <= 0;
+			instr_blt   <= 0;
+			instr_bge   <= 0;
+			instr_bltu  <= 0;
+			instr_bgeu  <= 0;
+
+			instr_addi  <= 0;
+			instr_slti  <= 0;
+			instr_sltiu <= 0;
+			instr_xori  <= 0;
+			instr_ori   <= 0;
+			instr_andi  <= 0;
+
+			instr_add   <= 0;
+			instr_sub   <= 0;
+			instr_sll   <= 0;
+			instr_slt   <= 0;
+			instr_sltu  <= 0;
+			instr_xor   <= 0;
+			instr_srl   <= 0;
+			instr_sra   <= 0;
+			instr_or    <= 0;
+			instr_and   <= 0;
+		end
+	end
+
+
+	// Main State Machine
+
+	localparam cpu_state_trap   = 8'b10000000;
+	localparam cpu_state_fetch  = 8'b01000000;
+	localparam cpu_state_ld_rs1 = 8'b00100000;
+	localparam cpu_state_ld_rs2 = 8'b00010000;
+	localparam cpu_state_exec   = 8'b00001000;
+	localparam cpu_state_shift  = 8'b00000100;
+	localparam cpu_state_stmem  = 8'b00000010;
+	localparam cpu_state_ldmem  = 8'b00000001;
+
+	reg [7:0] cpu_state;
+	reg [1:0] irq_state;
+
+	`FORMAL_KEEP reg [127:0] dbg_ascii_state;
+
+	always @* begin
+		dbg_ascii_state = "";
+		if (cpu_state == cpu_state_trap)   dbg_ascii_state = "trap";
+		if (cpu_state == cpu_state_fetch)  dbg_ascii_state = "fetch";
+		if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
+		if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
+		if (cpu_state == cpu_state_exec)   dbg_ascii_state = "exec";
+		if (cpu_state == cpu_state_shift)  dbg_ascii_state = "shift";
+		if (cpu_state == cpu_state_stmem)  dbg_ascii_state = "stmem";
+		if (cpu_state == cpu_state_ldmem)  dbg_ascii_state = "ldmem";
+	end
+
+	reg set_mem_do_rinst;
+	reg set_mem_do_rdata;
+	reg set_mem_do_wdata;
+
+	reg latched_store;
+	reg latched_stalu;
+	reg latched_branch;
+	reg latched_compr;
+	reg latched_trace;
+	reg latched_is_lu;
+	reg latched_is_lh;
+	reg latched_is_lb;
+	reg [regindex_bits-1:0] latched_rd;
+
+	reg [31:0] current_pc;
+	assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
+
+	reg [3:0] pcpi_timeout_counter;
+	reg pcpi_timeout;
+
+	reg [31:0] next_irq_pending;
+	reg do_waitirq;
+
+	reg [31:0] alu_out, alu_out_q;
+	reg alu_out_0, alu_out_0_q;
+	reg alu_wait, alu_wait_2;
+
+	reg [31:0] alu_add_sub;
+	reg [31:0] alu_shl, alu_shr;
+	reg alu_eq, alu_ltu, alu_lts;
+
+	generate if (TWO_CYCLE_ALU) begin
+		always @(posedge clk) begin
+			alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq <= reg_op1 == reg_op2;
+			alu_lts <= $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu <= reg_op1 < reg_op2;
+			alu_shl <= reg_op1 << reg_op2[4:0];
+			alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end else begin
+		always @* begin
+			alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq = reg_op1 == reg_op2;
+			alu_lts = $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu = reg_op1 < reg_op2;
+			alu_shl = reg_op1 << reg_op2[4:0];
+			alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end endgenerate
+
+	always @* begin
+		alu_out_0 = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			instr_beq:
+				alu_out_0 = alu_eq;
+			instr_bne:
+				alu_out_0 = !alu_eq;
+			instr_bge:
+				alu_out_0 = !alu_lts;
+			instr_bgeu:
+				alu_out_0 = !alu_ltu;
+			is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_lts;
+			is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_ltu;
+		endcase
+
+		alu_out = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			is_lui_auipc_jal_jalr_addi_add_sub:
+				alu_out = alu_add_sub;
+			is_compare:
+				alu_out = alu_out_0;
+			instr_xori || instr_xor:
+				alu_out = reg_op1 ^ reg_op2;
+			instr_ori || instr_or:
+				alu_out = reg_op1 | reg_op2;
+			instr_andi || instr_and:
+				alu_out = reg_op1 & reg_op2;
+			BARREL_SHIFTER && (instr_sll || instr_slli):
+				alu_out = alu_shl;
+			BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
+				alu_out = alu_shr;
+		endcase
+
+`ifdef RISCV_FORMAL_BLACKBOX_ALU
+		alu_out_0 = $anyseq;
+		alu_out = $anyseq;
+`endif
+	end
+
+	reg clear_prefetched_high_word_q;
+	always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
+
+	always @* begin
+		clear_prefetched_high_word = clear_prefetched_high_word_q;
+		if (!prefetched_high_word)
+			clear_prefetched_high_word = 0;
+		if (latched_branch || irq_state || !resetn)
+			clear_prefetched_high_word = COMPRESSED_ISA;
+	end
+
+	reg cpuregs_write;
+	reg [31:0] cpuregs_wrdata;
+	reg [31:0] cpuregs_rs1;
+	reg [31:0] cpuregs_rs2;
+	reg [regindex_bits-1:0] decoded_rs;
+
+	always @* begin
+		cpuregs_write = 0;
+		cpuregs_wrdata = 'bx;
+
+		if (cpu_state == cpu_state_fetch) begin
+			(* parallel_case *)
+			case (1'b1)
+				latched_branch: begin
+					cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
+					cpuregs_write = 1;
+				end
+				latched_store && !latched_branch: begin
+					cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[0]: begin
+					cpuregs_wrdata = reg_next_pc | latched_compr;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[1]: begin
+					cpuregs_wrdata = irq_pending & ~irq_mask;
+					cpuregs_write = 1;
+				end
+			endcase
+		end
+	end
+
+`ifndef PICORV32_REGS
+	always @(posedge clk) begin
+		if (resetn && cpuregs_write && latched_rd)
+			cpuregs[latched_rd] <= cpuregs_wrdata;
+	end
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
+`else
+			cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
+			cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
+`endif
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
+`else
+			cpuregs_rs1 = decoded_rs ? $anyseq : 0;
+`endif
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`else
+	wire[31:0] cpuregs_rdata1;
+	wire[31:0] cpuregs_rdata2;
+
+	wire [5:0] cpuregs_waddr = latched_rd;
+	wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
+	wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
+
+	`PICORV32_REGS cpuregs (
+		.clk(clk),
+		.wen(resetn && cpuregs_write && latched_rd),
+		.waddr(cpuregs_waddr),
+		.raddr1(cpuregs_raddr1),
+		.raddr2(cpuregs_raddr2),
+		.wdata(cpuregs_wrdata),
+		.rdata1(cpuregs_rdata1),
+		.rdata2(cpuregs_rdata2)
+	);
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+			cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+			cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`endif
+
+	assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
+
+	always @(posedge clk) begin
+		trap <= 0;
+		reg_sh <= 'bx;
+		reg_out <= 'bx;
+		set_mem_do_rinst = 0;
+		set_mem_do_rdata = 0;
+		set_mem_do_wdata = 0;
+
+		alu_out_0_q <= alu_out_0;
+		alu_out_q <= alu_out;
+
+		alu_wait <= 0;
+		alu_wait_2 <= 0;
+
+		if (launch_next_insn) begin
+			dbg_rs1val <= 'bx;
+			dbg_rs2val <= 'bx;
+			dbg_rs1val_valid <= 0;
+			dbg_rs2val_valid <= 0;
+		end
+
+		if (WITH_PCPI && CATCH_ILLINSN) begin
+			if (resetn && pcpi_valid && !pcpi_int_wait) begin
+				if (pcpi_timeout_counter)
+					pcpi_timeout_counter <= pcpi_timeout_counter - 1;
+			end else
+				pcpi_timeout_counter <= ~0;
+			pcpi_timeout <= !pcpi_timeout_counter;
+		end
+
+		if (ENABLE_COUNTERS) begin
+			count_cycle <= resetn ? count_cycle + 1 : 0;
+			if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
+		end else begin
+			count_cycle <= 'bx;
+			count_instr <= 'bx;
+		end
+
+		next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
+
+		if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
+			if (timer - 1 == 0)
+				next_irq_pending[irq_timer] = 1;
+			timer <= timer - 1;
+		end
+
+		if (ENABLE_IRQ) begin
+			next_irq_pending = next_irq_pending | irq;
+		end
+
+		decoder_trigger <= mem_do_rinst && mem_done;
+		decoder_trigger_q <= decoder_trigger;
+		decoder_pseudo_trigger <= 0;
+		decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
+		do_waitirq <= 0;
+
+		trace_valid <= 0;
+
+		if (!ENABLE_TRACE)
+			trace_data <= 'bx;
+
+		if (!resetn) begin
+			reg_pc <= PROGADDR_RESET;
+			reg_next_pc <= PROGADDR_RESET;
+			if (ENABLE_COUNTERS)
+				count_instr <= 0;
+			latched_store <= 0;
+			latched_stalu <= 0;
+			latched_branch <= 0;
+			latched_trace <= 0;
+			latched_is_lu <= 0;
+			latched_is_lh <= 0;
+			latched_is_lb <= 0;
+			pcpi_valid <= 0;
+			pcpi_timeout <= 0;
+			irq_active <= 0;
+			irq_delay <= 0;
+			irq_mask <= ~0;
+			next_irq_pending = 0;
+			irq_state <= 0;
+			eoi <= 0;
+			timer <= 0;
+			if (~STACKADDR) begin
+				latched_store <= 1;
+				latched_rd <= 2;
+				reg_out <= STACKADDR;
+			end
+			cpu_state <= cpu_state_fetch;
+		end else
+		(* parallel_case, full_case *)
+		case (cpu_state)
+			cpu_state_trap: begin
+				trap <= 1;
+			end
+
+			cpu_state_fetch: begin
+				mem_do_rinst <= !decoder_trigger && !do_waitirq;
+				mem_wordsize <= 0;
+
+				current_pc = reg_next_pc;
+
+				(* parallel_case *)
+				case (1'b1)
+					latched_branch: begin
+						current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
+						`debug($display("ST_RD:  %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
+					end
+					latched_store && !latched_branch: begin
+						`debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
+					end
+					ENABLE_IRQ && irq_state[0]: begin
+						current_pc = PROGADDR_IRQ;
+						irq_active <= 1;
+						mem_do_rinst <= 1;
+					end
+					ENABLE_IRQ && irq_state[1]: begin
+						eoi <= irq_pending & ~irq_mask;
+						next_irq_pending = next_irq_pending & irq_mask;
+					end
+				endcase
+
+				if (ENABLE_TRACE && latched_trace) begin
+					latched_trace <= 0;
+					trace_valid <= 1;
+					if (latched_branch)
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
+					else
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
+				end
+
+				reg_pc <= current_pc;
+				reg_next_pc <= current_pc;
+
+				latched_store <= 0;
+				latched_stalu <= 0;
+				latched_branch <= 0;
+				latched_is_lu <= 0;
+				latched_is_lh <= 0;
+				latched_is_lb <= 0;
+				latched_rd <= decoded_rd;
+				latched_compr <= compressed_instr;
+
+				if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
+					irq_state <=
+						irq_state == 2'b00 ? 2'b01 :
+						irq_state == 2'b01 ? 2'b10 : 2'b00;
+					latched_compr <= latched_compr;
+					if (ENABLE_IRQ_QREGS)
+						latched_rd <= irqregs_offset | irq_state[0];
+					else
+						latched_rd <= irq_state[0] ? 4 : 3;
+				end else
+				if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
+					if (irq_pending) begin
+						latched_store <= 1;
+						reg_out <= irq_pending;
+						reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+						mem_do_rinst <= 1;
+					end else
+						do_waitirq <= 1;
+				end else
+				if (decoder_trigger) begin
+					`debug($display("-- %-0t", $time);)
+					irq_delay <= irq_active;
+					reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+					if (ENABLE_TRACE)
+						latched_trace <= 1;
+					if (ENABLE_COUNTERS) begin
+						count_instr <= count_instr + 1;
+						if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
+					end
+					if (instr_jal) begin
+						mem_do_rinst <= 1;
+						reg_next_pc <= current_pc + decoded_imm_uj;
+						latched_branch <= 1;
+					end else begin
+						mem_do_rinst <= 0;
+						mem_do_prefetch <= !instr_jalr && !instr_retirq;
+						cpu_state <= cpu_state_ld_rs1;
+					end
+				end
+			end
+
+			cpu_state_ld_rs1: begin
+				reg_op1 <= 'bx;
+				reg_op2 <= 'bx;
+
+				(* parallel_case *)
+				case (1'b1)
+					(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
+						if (WITH_PCPI) begin
+							`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+							reg_op1 <= cpuregs_rs1;
+							dbg_rs1val <= cpuregs_rs1;
+							dbg_rs1val_valid <= 1;
+							if (ENABLE_REGS_DUALPORT) begin
+								pcpi_valid <= 1;
+								`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+								reg_sh <= cpuregs_rs2;
+								reg_op2 <= cpuregs_rs2;
+								dbg_rs2val <= cpuregs_rs2;
+								dbg_rs2val_valid <= 1;
+								if (pcpi_int_ready) begin
+									mem_do_rinst <= 1;
+									pcpi_valid <= 0;
+									reg_out <= pcpi_int_rd;
+									latched_store <= pcpi_int_wr;
+									cpu_state <= cpu_state_fetch;
+								end else
+								if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+									pcpi_valid <= 0;
+									`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+									if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+										next_irq_pending[irq_ebreak] = 1;
+										cpu_state <= cpu_state_fetch;
+									end else
+										cpu_state <= cpu_state_trap;
+								end
+							end else begin
+								cpu_state <= cpu_state_ld_rs2;
+							end
+						end else begin
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_rdcycle:
+								reg_out <= count_cycle[31:0];
+							instr_rdcycleh && ENABLE_COUNTERS64:
+								reg_out <= count_cycle[63:32];
+							instr_rdinstr:
+								reg_out <= count_instr[31:0];
+							instr_rdinstrh && ENABLE_COUNTERS64:
+								reg_out <= count_instr[63:32];
+						endcase
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lui_auipc_jal: begin
+						reg_op1 <= instr_lui ? 0 : reg_pc;
+						reg_op2 <= decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_rd <= latched_rd | irqregs_offset;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_retirq: begin
+						eoi <= 0;
+						irq_active <= 0;
+						latched_branch <= 1;
+						latched_store <= 1;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_maskirq: begin
+						latched_store <= 1;
+						reg_out <= irq_mask;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						irq_mask <= cpuregs_rs1 | MASKED_IRQ;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
+						latched_store <= 1;
+						reg_out <= timer;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						timer <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lb_lh_lw_lbu_lhu && !instr_trap: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_ldmem;
+						mem_do_rinst <= 1;
+					end
+					is_slli_srli_srai && !BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_sh <= decoded_rs2;
+						cpu_state <= cpu_state_shift;
+					end
+					is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					default: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						if (ENABLE_REGS_DUALPORT) begin
+							`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+							reg_sh <= cpuregs_rs2;
+							reg_op2 <= cpuregs_rs2;
+							dbg_rs2val <= cpuregs_rs2;
+							dbg_rs2val_valid <= 1;
+							(* parallel_case *)
+							case (1'b1)
+								is_sb_sh_sw: begin
+									cpu_state <= cpu_state_stmem;
+									mem_do_rinst <= 1;
+								end
+								is_sll_srl_sra && !BARREL_SHIFTER: begin
+									cpu_state <= cpu_state_shift;
+								end
+								default: begin
+									if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+										alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+										alu_wait <= 1;
+									end else
+										mem_do_rinst <= mem_do_prefetch;
+									cpu_state <= cpu_state_exec;
+								end
+							endcase
+						end else
+							cpu_state <= cpu_state_ld_rs2;
+					end
+				endcase
+			end
+
+			cpu_state_ld_rs2: begin
+				`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+				reg_sh <= cpuregs_rs2;
+				reg_op2 <= cpuregs_rs2;
+				dbg_rs2val <= cpuregs_rs2;
+				dbg_rs2val_valid <= 1;
+
+				(* parallel_case *)
+				case (1'b1)
+					WITH_PCPI && instr_trap: begin
+						pcpi_valid <= 1;
+						if (pcpi_int_ready) begin
+							mem_do_rinst <= 1;
+							pcpi_valid <= 0;
+							reg_out <= pcpi_int_rd;
+							latched_store <= pcpi_int_wr;
+							cpu_state <= cpu_state_fetch;
+						end else
+						if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+							pcpi_valid <= 0;
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					is_sb_sh_sw: begin
+						cpu_state <= cpu_state_stmem;
+						mem_do_rinst <= 1;
+					end
+					is_sll_srl_sra && !BARREL_SHIFTER: begin
+						cpu_state <= cpu_state_shift;
+					end
+					default: begin
+						if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+							alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+							alu_wait <= 1;
+						end else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+				endcase
+			end
+
+			cpu_state_exec: begin
+				reg_out <= reg_pc + decoded_imm;
+				if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
+					mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
+					alu_wait <= alu_wait_2;
+				end else
+				if (is_beq_bne_blt_bge_bltu_bgeu) begin
+					latched_rd <= 0;
+					latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					if (mem_done)
+						cpu_state <= cpu_state_fetch;
+					if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+						decoder_trigger <= 0;
+						set_mem_do_rinst = 1;
+					end
+				end else begin
+					latched_branch <= instr_jalr;
+					latched_store <= 1;
+					latched_stalu <= 1;
+					cpu_state <= cpu_state_fetch;
+				end
+			end
+
+			cpu_state_shift: begin
+				latched_store <= 1;
+				if (reg_sh == 0) begin
+					reg_out <= reg_op1;
+					mem_do_rinst <= mem_do_prefetch;
+					cpu_state <= cpu_state_fetch;
+				end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
+					endcase
+					reg_sh <= reg_sh - 4;
+				end else begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
+					endcase
+					reg_sh <= reg_sh - 1;
+				end
+			end
+
+			cpu_state_stmem: begin
+				if (ENABLE_TRACE)
+					reg_out <= reg_op2;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_wdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_sb: mem_wordsize <= 2;
+							instr_sh: mem_wordsize <= 1;
+							instr_sw: mem_wordsize <= 0;
+						endcase
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_wdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						cpu_state <= cpu_state_fetch;
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+					end
+				end
+			end
+
+			cpu_state_ldmem: begin
+				latched_store <= 1;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_rdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_lb || instr_lbu: mem_wordsize <= 2;
+							instr_lh || instr_lhu: mem_wordsize <= 1;
+							instr_lw: mem_wordsize <= 0;
+						endcase
+						latched_is_lu <= is_lbu_lhu_lw;
+						latched_is_lh <= instr_lh;
+						latched_is_lb <= instr_lb;
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_rdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							latched_is_lu: reg_out <= mem_rdata_word;
+							latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
+							latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
+						endcase
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+				end
+			end
+		endcase
+
+		if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
+			if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
+				`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+			if (mem_wordsize == 1 && reg_op1[0] != 0) begin
+				`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+		end
+		if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
+			`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
+			if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+				next_irq_pending[irq_buserror] = 1;
+			end else
+				cpu_state <= cpu_state_trap;
+		end
+		if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
+			cpu_state <= cpu_state_trap;
+		end
+
+		if (!resetn || mem_done) begin
+			mem_do_prefetch <= 0;
+			mem_do_rinst <= 0;
+			mem_do_rdata <= 0;
+			mem_do_wdata <= 0;
+		end
+
+		if (set_mem_do_rinst)
+			mem_do_rinst <= 1;
+		if (set_mem_do_rdata)
+			mem_do_rdata <= 1;
+		if (set_mem_do_wdata)
+			mem_do_wdata <= 1;
+
+		irq_pending <= next_irq_pending & ~MASKED_IRQ;
+
+		if (!CATCH_MISALIGN) begin
+			if (COMPRESSED_ISA) begin
+				reg_pc[0] <= 0;
+				reg_next_pc[0] <= 0;
+			end else begin
+				reg_pc[1:0] <= 0;
+				reg_next_pc[1:0] <= 0;
+			end
+		end
+		current_pc = 'bx;
+	end
+
+`ifdef RISCV_FORMAL
+	reg dbg_irq_call;
+	reg dbg_irq_enter;
+	reg [31:0] dbg_irq_ret;
+	always @(posedge clk) begin
+		rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
+		rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
+
+		rvfi_insn <= dbg_insn_opcode;
+		rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
+		rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
+		rvfi_pc_rdata <= dbg_insn_addr;
+		rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
+		rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
+		rvfi_trap <= trap;
+		rvfi_halt <= trap;
+		rvfi_intr <= dbg_irq_enter;
+
+		if (!resetn) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= 0;
+		end else
+		if (rvfi_valid) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= dbg_irq_call;
+		end else
+		if (irq_state == 1) begin
+			dbg_irq_call <= 1;
+			dbg_irq_ret <= next_pc;
+		end
+
+		if (!resetn) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end else
+		if (cpuregs_write && !irq_state) begin
+			rvfi_rd_addr <= latched_rd;
+			rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
+		end else
+		if (rvfi_valid) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end
+
+		casez (dbg_insn_opcode)
+			32'b 0000000_?????_000??_???_?????_0001011: begin // getq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+			32'b 0000001_?????_?????_???_000??_0001011: begin // setq
+				rvfi_rd_addr <= 0;
+				rvfi_rd_wdata <= 0;
+			end
+			32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+		endcase
+
+		if (!dbg_irq_call) begin
+			if (dbg_mem_instr) begin
+				rvfi_mem_addr <= 0;
+				rvfi_mem_rmask <= 0;
+				rvfi_mem_wmask <= 0;
+				rvfi_mem_rdata <= 0;
+				rvfi_mem_wdata <= 0;
+			end else
+			if (dbg_mem_valid && dbg_mem_ready) begin
+				rvfi_mem_addr <= dbg_mem_addr;
+				rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
+				rvfi_mem_wmask <= dbg_mem_wstrb;
+				rvfi_mem_rdata <= dbg_mem_rdata;
+				rvfi_mem_wdata <= dbg_mem_wdata;
+			end
+		end
+	end
+
+	always @* begin
+		rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
+	end
+`endif
+
+	// Formal Verification
+`ifdef FORMAL
+	reg [3:0] last_mem_nowait;
+	always @(posedge clk)
+		last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
+
+	// stall the memory interface for max 4 cycles
+	restrict property (|last_mem_nowait || mem_ready || !mem_valid);
+
+	// resetn low in first cycle, after that resetn high
+	restrict property (resetn != $initstate);
+
+	// this just makes it much easier to read traces. uncomment as needed.
+	// assume property (mem_valid || !mem_ready);
+
+	reg ok;
+	always @* begin
+		if (resetn) begin
+			// instruction fetches are read-only
+			if (mem_valid && mem_instr)
+				assert (mem_wstrb == 0);
+
+			// cpu_state must be valid
+			ok = 0;
+			if (cpu_state == cpu_state_trap)   ok = 1;
+			if (cpu_state == cpu_state_fetch)  ok = 1;
+			if (cpu_state == cpu_state_ld_rs1) ok = 1;
+			if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
+			if (cpu_state == cpu_state_exec)   ok = 1;
+			if (cpu_state == cpu_state_shift)  ok = 1;
+			if (cpu_state == cpu_state_stmem)  ok = 1;
+			if (cpu_state == cpu_state_ldmem)  ok = 1;
+			assert (ok);
+		end
+	end
+
+	reg last_mem_la_read = 0;
+	reg last_mem_la_write = 0;
+	reg [31:0] last_mem_la_addr;
+	reg [31:0] last_mem_la_wdata;
+	reg [3:0] last_mem_la_wstrb = 0;
+
+	always @(posedge clk) begin
+		last_mem_la_read <= mem_la_read;
+		last_mem_la_write <= mem_la_write;
+		last_mem_la_addr <= mem_la_addr;
+		last_mem_la_wdata <= mem_la_wdata;
+		last_mem_la_wstrb <= mem_la_wstrb;
+
+		if (last_mem_la_read) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wstrb == 0);
+		end
+		if (last_mem_la_write) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wdata == last_mem_la_wdata);
+			assert(mem_wstrb == last_mem_la_wstrb);
+		end
+		if (mem_la_read || mem_la_write) begin
+			assert(!mem_valid || mem_ready);
+		end
+	end
+`endif
+endmodule
+
+// This is a simple example implementation of PICORV32_REGS.
+// Use the PICORV32_REGS mechanism if you want to use custom
+// memory resources to implement the processor register file.
+// Note that your implementation must match the requirements of
+// the PicoRV32 configuration. (e.g. QREGS, etc)
+module picorv32_regs (
+	input clk, wen,
+	input [5:0] waddr,
+	input [5:0] raddr1,
+	input [5:0] raddr2,
+	input [31:0] wdata,
+	output [31:0] rdata1,
+	output [31:0] rdata2
+);
+	reg [31:0] regs [0:30];
+
+	always @(posedge clk)
+		if (wen) regs[~waddr[4:0]] <= wdata;
+
+	assign rdata1 = regs[~raddr1[4:0]];
+	assign rdata2 = regs[~raddr2[4:0]];
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_mul
+ ***************************************************************/
+
+module picorv32_pcpi_mul #(
+	parameter STEPS_AT_ONCE = 1,
+	parameter CARRY_CHAIN = 4
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg pcpi_wait_q;
+	wire mul_start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_mul <= 0;
+		instr_mulh <= 0;
+		instr_mulhsu <= 0;
+		instr_mulhu <= 0;
+
+		if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul <= 1;
+				3'b001: instr_mulh <= 1;
+				3'b010: instr_mulhsu <= 1;
+				3'b011: instr_mulhu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_mul;
+		pcpi_wait_q <= pcpi_wait;
+	end
+
+	reg [63:0] rs1, rs2, rd, rdx;
+	reg [63:0] next_rs1, next_rs2, this_rs2;
+	reg [63:0] next_rd, next_rdx, next_rdt;
+	reg [6:0] mul_counter;
+	reg mul_waiting;
+	reg mul_finish;
+	integer i, j;
+
+	// carry save accumulator
+	always @* begin
+		next_rd = rd;
+		next_rdx = rdx;
+		next_rs1 = rs1;
+		next_rs2 = rs2;
+
+		for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
+			this_rs2 = next_rs1[0] ? next_rs2 : 0;
+			if (CARRY_CHAIN == 0) begin
+				next_rdt = next_rd ^ next_rdx ^ this_rs2;
+				next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
+				next_rd = next_rdt;
+			end else begin
+				next_rdt = 0;
+				for (j = 0; j < 64; j = j + CARRY_CHAIN)
+					{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
+							next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
+				next_rdx = next_rdt << 1;
+			end
+			next_rs1 = next_rs1 >> 1;
+			next_rs2 = next_rs2 << 1;
+		end
+	end
+
+	always @(posedge clk) begin
+		mul_finish <= 0;
+		if (!resetn) begin
+			mul_waiting <= 1;
+		end else
+		if (mul_waiting) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+
+			rd <= 0;
+			rdx <= 0;
+			mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
+			mul_waiting <= !mul_start;
+		end else begin
+			rd <= next_rd;
+			rdx <= next_rdx;
+			rs1 <= next_rs1;
+			rs2 <= next_rs2;
+
+			mul_counter <= mul_counter - STEPS_AT_ONCE;
+			if (mul_counter[6]) begin
+				mul_finish <= 1;
+				mul_waiting <= 1;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_wr <= 0;
+		pcpi_ready <= 0;
+		if (mul_finish && resetn) begin
+			pcpi_wr <= 1;
+			pcpi_ready <= 1;
+			pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
+		end
+	end
+endmodule
+
+module picorv32_pcpi_fast_mul #(
+	parameter EXTRA_MUL_FFS = 0,
+	parameter EXTRA_INSN_FFS = 0,
+	parameter MUL_CLKGATE = 0
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output            pcpi_wr,
+	output     [31:0] pcpi_rd,
+	output            pcpi_wait,
+	output            pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg shift_out;
+	reg [3:0] active;
+	reg [32:0] rs1, rs2, rs1_q, rs2_q;
+	reg [63:0] rd, rd_q;
+
+	wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
+	reg pcpi_insn_valid_q;
+
+	always @* begin
+		instr_mul = 0;
+		instr_mulh = 0;
+		instr_mulhsu = 0;
+		instr_mulhu = 0;
+
+		if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul = 1;
+				3'b001: instr_mulh = 1;
+				3'b010: instr_mulhsu = 1;
+				3'b011: instr_mulhu = 1;
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_insn_valid_q <= pcpi_insn_valid;
+		if (!MUL_CLKGATE || active[0]) begin
+			rs1_q <= rs1;
+			rs2_q <= rs2;
+		end
+		if (!MUL_CLKGATE || active[1]) begin
+			rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
+		end
+		if (!MUL_CLKGATE || active[2]) begin
+			rd_q <= rd;
+		end
+	end
+
+	always @(posedge clk) begin
+		if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+			active[0] <= 1;
+		end else begin
+			active[0] <= 0;
+		end
+
+		active[3:1] <= active;
+		shift_out <= instr_any_mulh;
+
+		if (!resetn)
+			active <= 0;
+	end
+
+	assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
+	assign pcpi_wait = 0;
+	assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
+`ifdef RISCV_FORMAL_ALTOPS
+	assign pcpi_rd =
+			instr_mul    ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
+			instr_mulh   ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
+			instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
+			instr_mulhu  ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
+`else
+	assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
+`endif
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_div
+ ***************************************************************/
+
+module picorv32_pcpi_div (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_div, instr_divu, instr_rem, instr_remu;
+	wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
+
+	reg pcpi_wait_q;
+	wire start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_div <= 0;
+		instr_divu <= 0;
+		instr_rem <= 0;
+		instr_remu <= 0;
+
+		if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b100: instr_div <= 1;
+				3'b101: instr_divu <= 1;
+				3'b110: instr_rem <= 1;
+				3'b111: instr_remu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_div_rem && resetn;
+		pcpi_wait_q <= pcpi_wait && resetn;
+	end
+
+	reg [31:0] dividend;
+	reg [62:0] divisor;
+	reg [31:0] quotient;
+	reg [31:0] quotient_msk;
+	reg running;
+	reg outsign;
+
+	always @(posedge clk) begin
+		pcpi_ready <= 0;
+		pcpi_wr <= 0;
+		pcpi_rd <= 'bx;
+
+		if (!resetn) begin
+			running <= 0;
+		end else
+		if (start) begin
+			running <= 1;
+			dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
+			divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
+			outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
+			quotient <= 0;
+			quotient_msk <= 1 << 31;
+		end else
+		if (!quotient_msk && running) begin
+			running <= 0;
+			pcpi_ready <= 1;
+			pcpi_wr <= 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			case (1)
+				instr_div:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
+				instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
+				instr_rem:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
+				instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
+			endcase
+`else
+			if (instr_div || instr_divu)
+				pcpi_rd <= outsign ? -quotient : quotient;
+			else
+				pcpi_rd <= outsign ? -dividend : dividend;
+`endif
+		end else begin
+			if (divisor <= dividend) begin
+				dividend <= dividend - divisor;
+				quotient <= quotient | quotient_msk;
+			end
+			divisor <= divisor >> 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			quotient_msk <= quotient_msk >> 5;
+`else
+			quotient_msk <= quotient_msk >> 1;
+`endif
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi
+ ***************************************************************/
+
+module picorv32_axi #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output trap,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	wire        mem_instr;
+	wire        mem_ready;
+	wire [31:0] mem_rdata;
+
+	picorv32_axi_adapter axi_adapter (
+		.clk            (clk            ),
+		.resetn         (resetn         ),
+		.mem_axi_awvalid(mem_axi_awvalid),
+		.mem_axi_awready(mem_axi_awready),
+		.mem_axi_awaddr (mem_axi_awaddr ),
+		.mem_axi_awprot (mem_axi_awprot ),
+		.mem_axi_wvalid (mem_axi_wvalid ),
+		.mem_axi_wready (mem_axi_wready ),
+		.mem_axi_wdata  (mem_axi_wdata  ),
+		.mem_axi_wstrb  (mem_axi_wstrb  ),
+		.mem_axi_bvalid (mem_axi_bvalid ),
+		.mem_axi_bready (mem_axi_bready ),
+		.mem_axi_arvalid(mem_axi_arvalid),
+		.mem_axi_arready(mem_axi_arready),
+		.mem_axi_araddr (mem_axi_araddr ),
+		.mem_axi_arprot (mem_axi_arprot ),
+		.mem_axi_rvalid (mem_axi_rvalid ),
+		.mem_axi_rready (mem_axi_rready ),
+		.mem_axi_rdata  (mem_axi_rdata  ),
+		.mem_valid      (mem_valid      ),
+		.mem_instr      (mem_instr      ),
+		.mem_ready      (mem_ready      ),
+		.mem_addr       (mem_addr       ),
+		.mem_wdata      (mem_wdata      ),
+		.mem_wstrb      (mem_wstrb      ),
+		.mem_rdata      (mem_rdata      )
+	);
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi_adapter
+ ***************************************************************/
+
+module picorv32_axi_adapter (
+	input clk, resetn,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Native PicoRV32 memory interface
+
+	input         mem_valid,
+	input         mem_instr,
+	output        mem_ready,
+	input  [31:0] mem_addr,
+	input  [31:0] mem_wdata,
+	input  [ 3:0] mem_wstrb,
+	output [31:0] mem_rdata
+);
+	reg ack_awvalid;
+	reg ack_arvalid;
+	reg ack_wvalid;
+	reg xfer_done;
+
+	assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
+	assign mem_axi_awaddr = mem_addr;
+	assign mem_axi_awprot = 0;
+
+	assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
+	assign mem_axi_araddr = mem_addr;
+	assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
+
+	assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
+	assign mem_axi_wdata = mem_wdata;
+	assign mem_axi_wstrb = mem_wstrb;
+
+	assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
+	assign mem_axi_bready = mem_valid && |mem_wstrb;
+	assign mem_axi_rready = mem_valid && !mem_wstrb;
+	assign mem_rdata = mem_axi_rdata;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			ack_awvalid <= 0;
+		end else begin
+			xfer_done <= mem_valid && mem_ready;
+			if (mem_axi_awready && mem_axi_awvalid)
+				ack_awvalid <= 1;
+			if (mem_axi_arready && mem_axi_arvalid)
+				ack_arvalid <= 1;
+			if (mem_axi_wready && mem_axi_wvalid)
+				ack_wvalid <= 1;
+			if (xfer_done || !mem_valid) begin
+				ack_awvalid <= 0;
+				ack_arvalid <= 0;
+				ack_wvalid <= 0;
+			end
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_wb
+ ***************************************************************/
+
+module picorv32_wb #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	output trap,
+
+	// Wishbone interfaces
+	input wb_rst_i,
+	input wb_clk_i,
+
+	output reg [31:0] wbm_adr_o,
+	output reg [31:0] wbm_dat_o,
+	input [31:0] wbm_dat_i,
+	output reg wbm_we_o,
+	output reg [3:0] wbm_sel_o,
+	output reg wbm_stb_o,
+	input wbm_ack_i,
+	output reg wbm_cyc_o,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data,
+
+	output mem_instr
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	reg         mem_ready;
+	reg [31:0] mem_rdata;
+
+	wire clk;
+	wire resetn;
+
+	assign clk = wb_clk_i;
+	assign resetn = ~wb_rst_i;
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+
+	localparam IDLE = 2'b00;
+	localparam WBSTART = 2'b01;
+	localparam WBEND = 2'b10;
+
+	reg [1:0] state;
+
+	wire we;
+	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
+
+	always @(posedge wb_clk_i) begin
+		if (wb_rst_i) begin
+			wbm_adr_o <= 0;
+			wbm_dat_o <= 0;
+			wbm_we_o <= 0;
+			wbm_sel_o <= 0;
+			wbm_stb_o <= 0;
+			wbm_cyc_o <= 0;
+			state <= IDLE;
+		end else begin
+			case (state)
+				IDLE: begin
+					if (mem_valid) begin
+						wbm_adr_o <= mem_addr;
+						wbm_dat_o <= mem_wdata;
+						wbm_we_o <= we;
+						wbm_sel_o <= mem_wstrb;
+
+						wbm_stb_o <= 1'b1;
+						wbm_cyc_o <= 1'b1;
+						state <= WBSTART;
+					end else begin
+						mem_ready <= 1'b0;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBSTART:begin
+					if (wbm_ack_i) begin
+						mem_rdata <= wbm_dat_i;
+						mem_ready <= 1'b1;
+
+						state <= WBEND;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBEND: begin
+					mem_ready <= 1'b0;
+
+					state <= IDLE;
+				end
+				default:
+					state <= IDLE;
+			endcase
+		end
+	end
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc.sdc

@@ -0,0 +1 @@
+create_clock -period 10 clk_bufg

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc_noflash.v

@@ -0,0 +1,266 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  This is a modified PicoSoC example which has removed the requirement
+ *  for an external SPI flash. The PicoRV32 program is stored in ROM implemented
+ *  as a number of case statements. The ROM file is generated using an external
+ *  script.
+ *
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`ifndef PICORV32_REGS
+`ifdef PICORV32_V
+//`error "picosoc.v must be read before picorv32.v!"
+`endif
+
+`define PICORV32_REGS picosoc_regs
+`endif
+
+module picosoc_noflash (
+	input clk,
+	input resetn,
+
+	output        iomem_valid,
+	input         iomem_ready,
+	output [ 3:0] iomem_wstrb,
+	output [31:0] iomem_addr,
+	output [31:0] iomem_wdata,
+	input  [31:0] iomem_rdata,
+	
+	// Rewrite firmware 
+    input		  progmem_wen,
+	input  [31:0] progmem_waddr,
+	input  [31:0] progmem_wdata,
+	
+	input  irq_5,
+	input  irq_6,
+	input  irq_7,
+
+	output ser_tx,
+	input  ser_rx
+);
+	parameter integer MEM_WORDS = 8192;
+	parameter [31:0] STACKADDR = (4*MEM_WORDS);       // end of memory
+	parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
+
+	reg [31:0] irq;
+	wire irq_stall = 0;
+	wire irq_uart = 0;
+
+	always @* begin
+		irq = 0;
+		irq[3] = irq_stall;
+		irq[4] = irq_uart;
+		irq[5] = irq_5;
+		irq[6] = irq_6;
+		irq[7] = irq_7;
+	end
+
+	wire mem_valid;
+	wire mem_instr;
+	wire mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+	wire [31:0] mem_rdata;
+
+	wire progmem_ready;
+	wire [31:0] progmem_rdata;
+
+	reg ram_ready;
+	wire [31:0] ram_rdata;
+
+	assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
+	assign iomem_wstrb = mem_wstrb;
+	assign iomem_addr = mem_addr;
+	assign iomem_wdata = mem_wdata;
+
+	wire        spimemio_cfgreg_sel    = mem_valid && (mem_addr == 32'h 0200_0000);
+
+	wire        simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
+	wire [31:0] simpleuart_reg_div_do;
+
+	wire        simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
+	wire [31:0] simpleuart_reg_dat_do;
+	wire        simpleuart_reg_dat_wait;
+
+	assign mem_ready = 
+            (iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel ||
+			simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
+
+	assign mem_rdata = 
+            (iomem_valid && iomem_ready) ? iomem_rdata :
+            progmem_ready ? progmem_rdata :
+            ram_ready ? ram_rdata :
+            spimemio_cfgreg_sel ? 32'h0000_0000 : // Mockup, will always read 0
+			simpleuart_reg_div_sel ? simpleuart_reg_div_do :
+			simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
+
+`ifdef SIMULATION    
+	wire        trace_valid;
+	wire [35:0] trace_data;
+    integer     trace_file;
+`endif
+
+	picorv32 #(
+		.STACKADDR(STACKADDR),
+		.PROGADDR_RESET(PROGADDR_RESET),
+		.PROGADDR_IRQ(32'h 0000_0000),
+		.BARREL_SHIFTER(1),
+		.COMPRESSED_ISA(1),
+		.ENABLE_MUL(1),
+		.ENABLE_DIV(1),
+		.ENABLE_IRQ(1),
+`ifdef SIMULATION    
+		.ENABLE_IRQ_QREGS(0),
+        .ENABLE_TRACE(1)
+`else
+		.ENABLE_IRQ_QREGS(0)
+`endif
+	) cpu (
+		.clk         (clk        ),
+		.resetn      (resetn     ),
+		.mem_valid   (mem_valid  ),
+		.mem_instr   (mem_instr  ),
+		.mem_ready   (mem_ready  ),
+		.mem_addr    (mem_addr   ),
+		.mem_wdata   (mem_wdata  ),
+		.mem_wstrb   (mem_wstrb  ),
+		.mem_rdata   (mem_rdata  ),
+`ifdef SIMULATION
+		.irq         (irq        ),
+		.trace_valid (trace_valid),
+		.trace_data  (trace_data )
+`else
+		.irq         (irq        )
+`endif
+	);
+
+    // This it the program ROM memory for the PicoRV32
+    progmem progmem (
+        .clk    (clk),
+        .rstn   (resetn),
+
+        .valid  (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
+        .ready  (progmem_ready),
+        .addr   (mem_addr),
+        .rdata  (progmem_rdata),
+		.wen	(progmem_wen),
+		.waddr	(progmem_waddr),
+		.wdata	(progmem_wdata)
+    );
+
+	simpleuart simpleuart (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+
+		.ser_tx      (ser_tx      ),
+		.ser_rx      (ser_rx      ),
+
+		.reg_div_we  (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
+		.reg_div_di  (mem_wdata),
+		.reg_div_do  (simpleuart_reg_div_do),
+
+		.reg_dat_we  (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
+		.reg_dat_re  (simpleuart_reg_dat_sel && !mem_wstrb),
+		.reg_dat_di  (mem_wdata),
+		.reg_dat_do  (simpleuart_reg_dat_do),
+		.reg_dat_wait(simpleuart_reg_dat_wait)
+	);
+
+	always @(posedge clk)
+		ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
+
+	picosoc_mem #(.WORDS(MEM_WORDS)) memory (
+		.clk(clk),
+		.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
+		.addr(mem_addr[23:2]),
+		.wdata(mem_wdata),
+		.rdata(ram_rdata)
+	);
+
+    // Simulation debug
+`ifdef SIMULATION
+    always @(posedge clk)
+        if (resetn) begin
+            if ( mem_instr && mem_valid && mem_ready)
+                $display("Inst rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
+            if (!mem_instr && mem_valid && mem_ready)
+                $display("Data rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
+        end
+
+    // Trace
+    initial begin
+
+        trace_file = $fopen("testbench.trace", "w");
+        repeat (10) @(posedge clk);
+
+        while(1) begin
+            @(posedge clk)
+            if (resetn && trace_valid)
+                $fwrite(trace_file, "%x\n", trace_data);
+                $fflush(trace_file);
+                //$display("Trace  : %09X", trace_data);
+        end
+    end
+
+`endif // SIMULATION
+
+endmodule
+
+// Implementation note:
+// Replace the following two modules with wrappers for your SRAM cells.
+
+module picosoc_regs (
+	input clk, wen,
+	input [5:0] waddr,
+	input [5:0] raddr1,
+	input [5:0] raddr2,
+	input [31:0] wdata,
+	output [31:0] rdata1,
+	output [31:0] rdata2
+);
+	(* ram_style = "block" *) reg [31:0] regs [0:31]; // distribuirani bio
+
+	always @(posedge clk)
+		if (wen) regs[waddr[4:0]] <= wdata;
+
+	assign rdata1 = regs[raddr1[4:0]];
+	assign rdata2 = regs[raddr2[4:0]];
+endmodule
+
+module picosoc_mem #(
+	parameter integer WORDS = 32
+) (
+	input clk,
+	input [3:0] wen,
+	input [21:0] addr,
+	input [31:0] wdata,
+	output reg [31:0] rdata
+);
+	(* ram_style = "block" *) reg [31:0] mem [0:WORDS-1];
+
+	//initial $readmemh("firmware.hex", mem);
+	always @(posedge clk) begin
+		rdata <= mem[addr];
+		if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
+		if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
+		if (wen[2]) mem[addr][23:16] <= wdata[23:16];
+		if (wen[3]) mem[addr][31:24] <= wdata[31:24];
+	end
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/simpleuart.v

@@ -0,0 +1,132 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module simpleuart (
+    input clk,
+    input resetn,
+
+    output ser_tx,
+    input  ser_rx,
+
+    input  [ 3:0] reg_div_we,
+    input  [31:0] reg_div_di,
+    output [31:0] reg_div_do,
+
+    input         reg_dat_we,
+    input         reg_dat_re,
+    input  [31:0] reg_dat_di,
+    output [31:0] reg_dat_do,
+    output        reg_dat_wait
+);
+  reg [31:0] cfg_divider;
+
+  reg [3:0] recv_state;
+  reg [31:0] recv_divcnt;
+  reg [7:0] recv_pattern;
+  reg [7:0] recv_buf_data;
+  reg recv_buf_valid;
+
+  reg [9:0] send_pattern;
+  reg [3:0] send_bitcnt;
+  reg [31:0] send_divcnt;
+  reg send_dummy;
+
+  assign reg_div_do   = cfg_divider;
+
+  assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
+  assign reg_dat_do   = recv_buf_valid ? recv_buf_data : ~0;
+
+  always @(posedge clk) begin
+    if (!resetn) begin
+      cfg_divider <= 1;
+    end else begin
+      if (reg_div_we[0]) cfg_divider[7:0] <= reg_div_di[7:0];
+      if (reg_div_we[1]) cfg_divider[15:8] <= reg_div_di[15:8];
+      if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
+      if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
+    end
+  end
+
+  always @(posedge clk) begin
+    if (!resetn) begin
+      recv_state <= 0;
+      recv_divcnt <= 0;
+      recv_pattern <= 0;
+      recv_buf_data <= 0;
+      recv_buf_valid <= 0;
+    end else begin
+      recv_divcnt <= recv_divcnt + 1;
+      if (reg_dat_re) recv_buf_valid <= 0;
+      case (recv_state)
+        0: begin
+          if (!ser_rx) recv_state <= 1;
+          recv_divcnt <= 0;
+        end
+        1: begin
+          if (2 * recv_divcnt > cfg_divider) begin
+            recv_state  <= 2;
+            recv_divcnt <= 0;
+          end
+        end
+        10: begin
+          if (recv_divcnt > cfg_divider) begin
+            recv_buf_data <= recv_pattern;
+            recv_buf_valid <= 1;
+            recv_state <= 0;
+          end
+        end
+        default: begin
+          if (recv_divcnt > cfg_divider) begin
+            recv_pattern <= {ser_rx, recv_pattern[7:1]};
+            recv_state   <= recv_state + 1;
+            recv_divcnt  <= 0;
+          end
+        end
+      endcase
+    end
+  end
+
+  assign ser_tx = send_pattern[0];
+
+  always @(posedge clk) begin
+    if (reg_div_we) send_dummy <= 1;
+    send_divcnt <= send_divcnt + 1;
+    if (!resetn) begin
+      send_pattern <= ~0;
+      send_bitcnt  <= 0;
+      send_divcnt  <= 0;
+      send_dummy   <= 1;
+    end else begin
+      if (send_dummy && !send_bitcnt) begin
+        send_pattern <= ~0;
+        send_bitcnt  <= 15;
+        send_divcnt  <= 0;
+        send_dummy   <= 0;
+      end else if (reg_dat_we && !send_bitcnt) begin
+        send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
+        send_bitcnt  <= 10;
+        send_divcnt  <= 0;
+      end else if (send_divcnt > cfg_divider && send_bitcnt) begin
+        send_pattern <= {1'b1, send_pattern[9:1]};
+        send_bitcnt  <= send_bitcnt - 1;
+        send_divcnt  <= 0;
+      end
+    end
+  end
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/top.v

@@ -0,0 +1,315 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1ns / 1ps
+
+module top (
+   input wire clk_10mhz,      // 10MHz clock
+
+   //output wire led_olimex,     // LED output
+
+   output tx,
+   input  rx,
+
+   input  btnC,
+   input  btnU,
+   input  btnD,
+   input  btnL,
+   input  btnR,
+   
+   input  [15:0] sw,
+   output [15:0] led,
+   output [7:0] cathodes,
+   output [3:0] anodes,
+
+   output hsync,       // to VGA connector
+   output vsync,       // to VGA connector
+   output [11:0] rgb,  // to DAC, to VGA connector
+
+    output [7:0] jb
+);
+   
+   // command protocol constants:
+   parameter [7:0]  C_SOP = 8'h23;
+   parameter [7:0]  C_EOP = 8'h0d;
+   
+   // commands:
+   parameter [7:0]  C_REGISTER_RD = 8'h08;
+   parameter [7:0]  C_REGISTER_WR = 8'h07;
+   
+   wire        rx_busy, tx_busy, converted, data_valid;
+   reg [15:0]     data_length, data_cnt;
+   reg [7:0]      command;  
+
+   // Local control logic variables
+   // FSM state  
+   reg [3:0] state;
+
+   // This variable is super critical in preventing wrong FSM state changes
+   reg allow_next;     // Local signal to prevent race conditions 
+    
+   // IO related variables
+   reg flush_ctrl;    // Flush the RX data after reading
+   reg tx_enable_ctrl;    // Allow tranmission of output, after data is settled
+
+   wire [7:0]    uart_data;   // The actual RX UART data      
+   reg  [7:0]    out_data;   // The data that will be sent over TX    
+
+   reg ram_wen; 
+   reg [31:0] ram_data, ram_addr;
+   reg [15:0] display_data;
+   reg [7:0] checksum;
+   reg [8:0] leds;
+
+   // UART clock related variables
+   reg [4:0]  counter; 
+   
+   // VGA signals
+   wire [9:0]     w_x, w_y;
+   wire          w_video_on, w_p_tick;
+   reg  [11:0]   rgb_reg;
+   wire [11:0]   rgb_next;
+
+   ///////////////////////////////////
+   // Power-on Reset
+   ///////////////////////////////////
+   reg [7:0] reset_cnt = 0;
+   wire resetn = &reset_cnt;
+	
+	   wire clk, lock;
+
+   pll pll_inst (
+      .clock_in(clk_10mhz), // 10 MHz
+      .rst_in(),
+      .clock_out(clk),// 25 MHz, 0 deg
+      .locked(lock)
+   );
+	
+	   reg sw_dl1, sw_dl2;
+   always @(posedge clk) 
+   begin
+      sw_dl1 <= sw[15];
+      sw_dl2 <= sw_dl1;
+      if(sw_dl2 && !sw[15]) begin
+         reset_cnt <= 0;
+      end else begin
+         reset_cnt <= reset_cnt + !resetn;
+      end
+    end 
+   
+   wire btnC_out;
+    debounce debBtnC (
+        .clk    (clk),
+        .in     (btnC),
+        .out    (btnC_out)
+    );
+    wire btnL_out;
+    debounce debBtnL (
+        .clk    (clk),
+        .in     (btnL),
+        .out    (btnL_out)
+    );
+    wire btnR_out;
+    debounce debBtnR (
+        .clk    (clk),
+        .in     (btnR),
+        .out    (btnR_out)
+    );
+    wire btnD_out;
+    debounce debBtnD (
+        .clk    (clk),
+        .in     (btnD),
+        .out    (btnD_out)
+    );
+    wire btnU_out;
+    debounce debBtnU (
+        .clk    (clk),
+        .in     (btnU),
+        .out    (btnU_out)
+    );
+    ///////////////////////////////////
+    // Peripheral Bus
+    ///////////////////////////////////   
+   wire        iomem_valid;
+   wire        iomem_ready;
+   wire [ 3:0] iomem_wstrb;
+   wire [31:0] iomem_addr;
+   wire [31:0] iomem_wdata;
+   wire [31:0] iomem_rdata;
+
+   reg  [31:0] gpio;
+   wire [4:0]  debug_pins_char_gen;
+   reg  [31:0] gpio_iomem_rdata;
+   reg      gpio_iomem_ready;
+   wire     vga_iomem_ready;
+   
+
+   wire[4:0] buttons;
+   assign buttons = { btnC_out, btnD_out, btnL_out, btnR_out, btnU_out};
+
+   
+    // enable signals for each of the peripherals
+    wire gpio_en    = (iomem_addr[31:24] == 8'h03); /* GPIO mapped to 0x03xx_xxxx */
+    wire video_en   = (iomem_addr[31:24] == 8'h05); /* Video device mapped to 0x05xx_xxxx */
+   
+   assign led[5:0] = leds[5:0];
+   //assign led[10:6] = buttons;
+   assign led[11] = w_video_on;  
+   assign led[12] = allow_next;
+   assign led[13] = ram_wen;
+   assign led[14] = r_CLK_1HZ;   
+   assign led[15] = sw[15];   
+
+   assign iomem_ready = gpio_en ? gpio_iomem_ready : ( video_en ? vga_iomem_ready : 1'b0);      
+   assign iomem_rdata = gpio_en ? gpio_iomem_rdata : 32'h00000000;   
+   
+
+   always @(posedge clk) 
+   begin
+      if (!resetn) begin
+         gpio <= 0;
+      end else begin
+         gpio_iomem_ready <= 0;
+         if (iomem_valid && !iomem_ready && gpio_en) begin
+            gpio_iomem_ready <= 1;
+            gpio_iomem_rdata <= {8'h00, 1'b0, 1'b0, 1'b0, buttons[4:0], gpio[15:0]};
+            if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
+            if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
+            if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
+            if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];               
+         end
+      end
+   end
+   
+   wire tx_uc, rx_uc, tx_prog, rx_prog;
+   
+   assign tx = sw[15] ? tx_prog : tx_uc;  
+   assign rx_uc = sw[15] ? 1'bz : rx;
+   assign rx_prog = sw[15] ? rx : 1'bz;
+   
+   // uC Circuit     
+   picosoc_noflash soc (
+      .clk  (clk),    
+      .resetn  (resetn),
+
+      .ser_tx  (tx_uc),
+      .ser_rx  (rx_uc),
+
+      .irq_5   (1'b0),
+      .irq_6   (1'b0),
+      .irq_7   (1'b0),
+
+      .iomem_valid(iomem_valid),
+      .iomem_ready(iomem_ready),
+      .iomem_wstrb(iomem_wstrb),
+      .iomem_addr (iomem_addr),
+      .iomem_wdata(iomem_wdata),
+      .iomem_rdata(iomem_rdata),
+      
+      .progmem_wen   (progmem_wen),
+      .progmem_waddr (ram_addr),
+      .progmem_wdata (ram_data)     
+   ); 
+   
+    // VGA Controller
+    vga_controller vga(
+      .clk(clk), 
+      .reset(!resetn),     
+      .hsync(hsync), 
+      .vsync(vsync),
+      .video_on(w_video_on), 
+      .p_tick(w_p_tick), 
+      .x(w_x), 
+      .y(w_y)
+   );
+
+    // VGA Wrapper
+    vga_wrapper at(
+      .clk(clk),
+      .reset(!resetn),     
+      .vga_iomem_ready(vga_iomem_ready),
+      
+      .iomem_valid(iomem_valid && video_en),
+      .iomem_ready(iomem_ready),
+      .iomem_wstrb(iomem_wstrb),
+      .iomem_addr(iomem_addr),
+      .iomem_wdata(iomem_wdata),
+
+      .video_on(w_video_on), 
+      .x(w_x), 
+      .y(w_y), 
+      .rgb(rgb_next),
+      
+      .o_debug_pins(debug_pins_char_gen)
+   );
+   
+    // RGB buffer
+   always @(posedge clk)
+   begin
+        //if(w_p_tick)
+            rgb_reg <= rgb_next;
+   end
+   
+   // output
+   assign rgb = rgb_reg;
+
+
+   wire I_write = (command==C_REGISTER_WR);
+   wire I_read  = (command==C_REGISTER_RD);
+
+   initial begin
+      counter = 0;
+
+      flush_ctrl = 0;
+      tx_enable_ctrl = 0;
+      allow_next = 0;   
+      out_data = 0;
+      checksum = 0;
+      display_data = 0;
+      command = 0;
+      data_length = 0;
+      data_cnt = 0;
+      progmem_wen = 0;
+      ram_wen = 0;
+      ram_addr = 32'hFFFFFFFF;
+      ram_data = 32'd0;
+   end
+   
+   reg progmem_wen;
+   
+    // Constants (parameters) to create the frequencies needed:
+    // Input clock is 100.0 MHz, system clock.
+    // Formula is: (100000 KHz / 1 Hz) * 50% duty cycle    
+    // So for 1/2 Hz: (100000000 / 1) * 0.5 = 50000000, Input clock is generated 100MHz        
+    parameter c_CNT_CLK_HZ = 50000000;        
+    // These signals will be the counters:        
+    reg [31:0] r_CNT_CLK_HZ = 0;       
+    // These signals will toggle at the frequencies needed:          
+    reg r_CLK_1HZ       = 1'b0;        
+    always @(posedge clk)  
+    begin        
+        if (r_CNT_CLK_HZ == c_CNT_CLK_HZ-1) begin// -1, since counter starts at 0                
+            r_CLK_1HZ <= !r_CLK_1HZ;
+            r_CNT_CLK_HZ <= 0;
+        end else
+            r_CNT_CLK_HZ <= r_CNT_CLK_HZ + 1;            
+    end                                         
+    //------------------------------------------------------------------------------    
+      
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_rx.v

@@ -0,0 +1,238 @@
+`timescale 10ns/1ns
+
+/*
+ * Custom UART RX design, with all requisite customization options
+ * Written by Shubhayu Das, November 2021
+ * Version: 1.2.0
+ * Last updated: 27th November, 2021
+ * 
+ * The clock frequency and the baud rate have to be calculated and set manually.
+ * As it stands now, this module will automatically calculate the prescalar needed.
+ * This division will be done in software, which is inefficient, and wastes power
+ * 
+ ***************************
+ *
+ * THEORY OF WORKING of this module:
+ *
+ * CLOCKS:
+ * - An input clock of 25MHz is expected.
+ * - Internally, a "slow_clk_en" pulse is generated, depending on baud rate.
+ *
+ * UART:
+ * An active low signal starts receiving.
+ * I am implementing oversampling. Each RX bit is sampled 15 times,
+ * then the "obtained_bit" function is used to calculate the detected bit
+ *
+ * An FSM is used to handle the operation of the module.
+ * FSM states:
+ *  - IDLE          : Waiting for start bit(0)
+ *  - DETECT_START  : Possible start bit detected. Oversample and decide
+ *  - STARTED       : Receiving started, oversample and decide individual bits
+ *  - CONVERSION    : RX complete, run parity check, retain data until flushed 
+ *
+ * Oversampling:
+ * The incoming RX signal is oversampled, and the oversampled bits are stored in
+ * the "oversampled_bit" buffer. Once the buffer is full, the "obtained_bit"
+ * function is used to find the accurate bit. This bit is stored in "sampled_rx_data",
+ * at the correct location
+ *
+ * RX:
+ * Oversampling is continued until all bits are received. The "sampled_rx_data"
+ * contains the final data. This data must be read only AFTER the converted flag goes high.
+ *
+ ***************************
+ * Parameters in the module:
+ *
+ * FRAME_BITS   - The number of bits in the data frame. Allowed values: 5-9 bits/frame
+ * PARITY_BIT   - Set to "2" to disable parity check. Set to "0/1" for odd/even parity resp.
+ * STOP_BITS    - The number of stop bits, Allowed values: 1-2 bits
+ *
+ ***************************
+ * Inputs to the module:
+ *
+ * rx       - The input rx signal
+ * i_clk    - The clock of the local system, used for sampling the bits and FSM sync
+ * flush    - Clear the converted data from the register
+ * 
+ ***************************
+ * Outputs of the module
+ *
+ * data         - The final converted data, of appropriate bit-width
+ * converted    - Active high signal indicating successfully received frame
+ * data_valid   - Active high signal indicating if received data is valid(if parity is enabled)
+ * busy         - Indicates if data reception has started and system is busy
+ * 
+ ***************************
+ * In this version, the oversampling factor is 15.
+ * 
+ * Note that due to small mismatches, between the input clock frequency and the target baud rate,
+ * there will a drift over time. This needs to be taken care of in the parent module.
+ *
+ ***************************
+ *
+ * Sample input clock setup for Basys 3:
+ * Set the clock to 100MHz in the constraints file. 
+ * Then divide the clock to get a time period of 540ns
+ *
+ ***************************
+ * TODO: handling lost bits, using timeout
+ * Actually looking at the stop bit(s)
+*/
+
+//`define DEBUG
+
+module uart_rx #(
+    parameter FRAME_BITS = 8, // Number of data bits, can be 7/8
+    PARITY_BIT = 2, // Parity disabled by default
+    STOP_BITS = 1   // Using only 1 stop bit
+) (
+    input rx,
+    input i_clk,
+    input flush,
+    output reg [FRAME_BITS-1:0] data,
+    output reg converted,
+    output reg data_valid,
+    output reg busy
+);
+
+// FSM states
+localparam IDLE         = 0;
+localparam DETECT_START = 1;
+localparam STARTED      = 2;
+localparam CONVERSION   = 3;
+
+// Calculating the total number of bits that need to be stored
+localparam TOTAL_RX_BITS = (PARITY_BIT < 2 ) ? FRAME_BITS + STOP_BITS + 1 : FRAME_BITS + STOP_BITS;
+
+// Hardcoding the number of samples per bit.
+// Change this according to the input clock frequency
+localparam OVERSAMPLE_FACTOR = 15;
+
+// Three parameters used by the "obtained_bit" function
+localparam integer SAMPLE_LOC_1 = (OVERSAMPLE_FACTOR / 2) - 1;
+localparam integer SAMPLE_LOC_2  = (OVERSAMPLE_FACTOR / 2);
+localparam integer SAMPLE_LOC_3 = (OVERSAMPLE_FACTOR / 2) + 1;
+
+reg [1:0] state;            // FSM state
+
+reg [3:0] bit_location;     // Indexing variable for the received data
+reg [3:0] insert_location;  //  current index of data in oversampling buffer
+
+reg [OVERSAMPLE_FACTOR-1:0] oversampled_bit;    // oversampling buffer
+reg [TOTAL_RX_BITS-1:0] sampled_rx_data;        // RX buffer
+
+initial begin
+    
+    `ifdef DEBUG
+        $display("Oversampling factor: %2d", OVERSAMPLE_FACTOR);
+    `endif
+
+    state = IDLE;
+
+    busy = 0;
+    bit_location = 0;
+    insert_location = 0;
+    sampled_rx_data = {(TOTAL_RX_BITS-1){1'b0}};
+end
+
+// Managing the states of the conversion FSM
+always @(posedge i_clk) begin
+    case (state)
+
+        // Unless "0" is detected on RX line, wait
+        IDLE :
+            state <= rx ? IDLE : DETECT_START;
+            
+        // Once "0" is seen on RX line, sample certain times, decide if RX started
+        // If RX started, go to next state
+        DETECT_START: begin
+            if(insert_location == (OVERSAMPLE_FACTOR-4))
+                if(busy)
+                    state <= STARTED;
+                else begin
+                    state <= IDLE;
+                end
+            end
+
+        // Receive all bits of the RX data, with oversampling
+        STARTED:
+            state <= (bit_location == TOTAL_RX_BITS) ? CONVERSION : STARTED;
+
+        // Check parity, then retain data until data is flushed
+        CONVERSION: 
+            state <= (flush) ? IDLE : CONVERSION;        
+    endcase
+end
+
+// Actual logic in each state
+always @(posedge i_clk) begin
+    case (state)
+    
+        // Simply reset all the vectors
+        IDLE: begin
+            converted <= 0;
+            data_valid <= 0;
+            busy <= 0;
+            bit_location <= 0;
+            insert_location <= 0; // Not really needed
+            oversampled_bit <= 15'b0;
+            sampled_rx_data = {(TOTAL_RX_BITS-1){1'b0}};
+            data <= {FRAME_BITS{1'b0}};
+        end
+        
+        // Try to detect if a zero bit is detected, marking start of transmission
+        DETECT_START: begin
+            if (insert_location == (OVERSAMPLE_FACTOR - 5)) begin
+                busy <= ~obtained_bit(oversampled_bit);    // Decide what bit was received
+                oversampled_bit <= 15'b0;   // Reset the oversampling buffer
+            end
+            else
+                oversampled_bit[insert_location] <= rx; // Fill the oversample buffer
+
+            if(busy)
+                insert_location <= 0; // Increment insertion location
+            else
+                insert_location <= insert_location + 1;
+        end
+        
+        // Once transmission start is confirmed, start receiving the data, with oversampling
+        STARTED: begin
+            oversampled_bit[insert_location] <= rx;
+            insert_location <= insert_location + 1;
+
+            // Once oversampling buffer is full, decide what bit was received
+            if (insert_location == OVERSAMPLE_FACTOR - 1) begin
+                sampled_rx_data[bit_location] <= obtained_bit(oversampled_bit);
+                oversampled_bit <= 15'b0;   // Reset the oversampling buffer
+                
+                bit_location <= bit_location + 1;
+            end
+        end
+        
+        // Transmission complete, check parity, put out data and other flag bits
+        CONVERSION: begin
+            if(~converted) begin
+                converted <= 1;
+                data <= sampled_rx_data[FRAME_BITS-1:0];
+    
+                if(PARITY_BIT < 2) begin
+                    if (^data == PARITY_BIT)
+                        data_valid <= 1;
+                    else
+                        data_valid <= 0;
+                end
+                else
+                    data_valid <= 1;
+            end
+        end
+    endcase
+end
+
+// Function to decide the received bit, depending on the oversampled data bits
+function obtained_bit (input [OVERSAMPLE_FACTOR-1:0] oversampled_vector);
+    obtained_bit =  (oversampled_vector[SAMPLE_LOC_1] & oversampled_vector[SAMPLE_LOC_2]) | 
+                    (oversampled_vector[SAMPLE_LOC_2] & oversampled_vector[SAMPLE_LOC_3]) | 
+                    (oversampled_vector[SAMPLE_LOC_1] & oversampled_vector[SAMPLE_LOC_3]);
+endfunction
+    
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_tx.v

@@ -0,0 +1,183 @@
+`timescale 10ns / 1ns
+
+/*
+ * Custom TX design, to match the RX module
+ * Author: Shubhayu Das
+ * Date: 27th November, 2021
+ * Version: 1.2
+ * Last update: 28th Nov, 2021: Changed order of bytes to big-endian
+ *
+ ********************
+ * Inputs:
+ * clk: UART clk, which MUST match the clock on the RX module
+ * tx_enable: start transmitting data ASAP
+ * data: the actual data to be transmitted
+ ******************** 
+ * Parameters:
+ * FRAME_BITS: Number of data bits per transaction
+ * PARITY_BITS: 0/1 indicate odd or even parity, 2 disables parity
+ * STOP_BITS: Number of stop bits to send
+ * RETENTION_DURATION: Compensate for oversampling UART clock
+ *
+ ********************
+ * Outputs:
+ * tx: The TX data line
+ * tx_busy: signal to indicate TX line is busy, don't start anything else
+ *
+ ********************
+ * Features of this module:
+ *
+ * This module automatically compensates for the faster UART clock being used
+ * for oversampling in the RX module. This is controlled by the 
+ * RETENTION_DURATION" parameter.
+ *
+ * The input data is sampled as soon as "tx_enable" is set(on the next clock posedge)
+ * The input data is stored locally, the source register's value can change
+ * freely, without corrupting the TX activity.
+ *
+ * The data being sent is automatically flipped. So data[7:0] is sent as data[0:7]
+*/
+
+
+module uart_tx #(
+    parameter FRAME_BITS = 8,   // Number of data bits, can be 7/8
+    PARITY_BIT = 2,             // Parity disabled by default
+    STOP_BITS = 1,              // Using only 1 stop bit
+    RETENTION_DURATION = 15     // Compensate for oversampling in RX
+)(
+    input clk,
+    input tx_enable,
+    input [FRAME_BITS-1:0] data,
+    output reg tx,
+    output reg tx_busy
+);
+
+function integer clog2;
+    input integer value;
+          integer temp;
+    begin
+        temp = value - 1;
+        for (clog2 = 0; temp > 0; clog2 = clog2 + 1) begin
+            temp = temp >> 1;
+        end
+    end
+endfunction
+
+// Knowing how bits need to be sent
+localparam N_TX_BITS = (PARITY_BIT < 2) ? 
+                        (1+FRAME_BITS+1+STOP_BITS) : (1+FRAME_BITS+STOP_BITS);
+localparam INDEX_SIZE = clog2(N_TX_BITS);
+
+// FSM states
+localparam IDLE = 0;        // Wait for tx_enable to be set
+localparam CAPTURE = 1;     // Copy data into local_data, with parity, stop bits
+localparam TRANSMITTING = 2;// Data being put on TX line
+
+reg [2:0] state;
+reg data_framed;            // Indicates data has been copied to local_data
+
+reg [INDEX_SIZE:0] bit_index;
+
+reg [0:N_TX_BITS-1] local_data; // local data register
+
+// Keeps TX high for requisite number of cycles
+reg [clog2(RETENTION_DURATION):0] retention_counter;
+
+
+initial begin
+    tx = 1;
+    tx_busy = 0;
+    
+    state = IDLE;
+    bit_index = 0;
+    data_framed = 0;
+    local_data = 0;
+    
+    // This is NOT a mistake
+    // This compensates for the immediate addition that happens
+    // in "TRANSMITTING" state
+    retention_counter = RETENTION_DURATION;
+end
+
+// Handle the state changes
+always @(posedge clk) begin
+    case(state)
+        IDLE:
+            state <= (tx_enable) ? CAPTURE : IDLE;
+        
+        CAPTURE:
+            state <= (data_framed) ? TRANSMITTING : CAPTURE;
+            
+        TRANSMITTING:
+            state <= (bit_index == N_TX_BITS) ? IDLE : TRANSMITTING;
+    endcase 
+end
+
+always @(posedge clk) begin
+    case(state)
+        IDLE: begin
+                tx <= 1;
+                tx_busy <= 0;
+                bit_index <= 0;
+                local_data <= 0;
+                data_framed <= 0;
+                retention_counter <= RETENTION_DURATION;
+            end
+            
+        CAPTURE: begin
+            tx_busy <= 1;
+            
+            // The data needs to be reversed
+            if(PARITY_BIT < 2) begin
+                local_data <= {
+                    1'b0,       // Start bit
+                    data[0],    // Reversed data
+                    data[1],
+                    data[2],
+                    data[3],
+                    data[4],
+                    data[5],
+                    data[6],
+                    data[7],
+                    ^data,      // Parity
+                    {(STOP_BITS){1'b1}} // Stop bit(s)
+                };
+                data_framed <= 1;
+            end
+            else begin
+                // Same as above, but without parity
+                local_data <= {
+                    1'b0,
+                    data[0],
+                    data[1],
+                    data[2],
+                    data[3],
+                    data[4],
+                    data[5],
+                    data[6],
+                    data[7],
+                    {(STOP_BITS){1'b1}}
+                };
+                data_framed <= 1;
+            end
+        end
+        
+        TRANSMITTING: begin
+            if(retention_counter == 0) begin
+                tx <= local_data[bit_index];
+                bit_index <= bit_index + 1;
+                
+                if(bit_index == N_TX_BITS)
+                    tx_busy <= 0;
+                
+            end
+            
+            if(retention_counter < RETENTION_DURATION)
+                retention_counter <= retention_counter + 1;
+            else
+                retention_counter <= 0;
+        end
+    endcase
+end
+
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_controller.v

@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Reference Book: 
+// Chu, Pong P.
+// Wiley, 2008
+// "FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version" 
+// 
+// Adapted for the Basys 3 by David J. Marion
+// Comments by David J. Marion
+//
+// FOR USE WITH AN FPGA THAT HAS A 100MHz CLOCK SIGNAL ONLY.
+// VGA Mode
+// 640x480 pixels VGA screen with 25MHz pixel rate based on 60 Hz refresh rate
+// 800 pixels/line * 525 lines/screen * 60 screens/second = ~25.2M pixels/second
+//
+// A 25MHz signal will suffice. The Basys 3 has a 100MHz signal available, so a
+// 25MHz tick is created for syncing the pixel counts, pixel tick, horiz sync, 
+// vert sync, and video on signals.
+//////////////////////////////////////////////////////////////////////////////////
+
+module vga_controller(
+    input wire clk,   // from Basys 3
+    input reset,        // system reset
+    output video_on,    // ON while pixel counts for x and y and within display area
+    output hsync,       // horizontal sync
+    output vsync,       // vertical sync
+    output p_tick,      // the 25MHz pixel/second rate signal, pixel tick
+    output [9:0] x,     // pixel count/position of pixel x, max 0-799
+    output [9:0] y      // pixel count/position of pixel y, max 0-524
+    );
+    
+    // Based on VGA standards found at vesa.org for 640x480 resolution
+    // Total horizontal width of screen = 800 pixels, partitioned  into sections
+    parameter HD = 640;             // horizontal display area width in pixels
+    parameter HF = 48;              // horizontal front porch width in pixels
+    parameter HB = 16;              // horizontal back porch width in pixels
+    parameter HR = 96;              // horizontal retrace width in pixels
+    parameter HMAX = HD+HF+HB+HR-1; // max value of horizontal counter = 799
+    // Total vertical length of screen = 525 pixels, partitioned into sections
+    parameter VD = 480;             // vertical display area length in pixels 
+    parameter VF = 10;              // vertical front porch length in pixels  
+    parameter VB = 33;              // vertical back porch length in pixels   
+    parameter VR = 2;               // vertical retrace length in pixels  
+    parameter VMAX = VD+VF+VB+VR-1; // max value of vertical counter = 524   
+    
+    // Counter Registers, two each for buffering to avoid glitches
+    reg [9:0] h_count_reg, h_count_next;
+    reg [9:0] v_count_reg, v_count_next;
+    
+    // Output Buffers
+    reg v_sync_reg, h_sync_reg;
+    wire v_sync_next, h_sync_next;
+    
+    always @(posedge clk or posedge reset) 
+        if (reset) begin
+            v_count_reg <= 0;
+            h_count_reg <= 0;
+            v_sync_reg  <= 1'b0;
+            h_sync_reg  <= 1'b0;
+        end else begin
+            // Logika za horizontalni brojač
+            if (h_count_reg == HMAX) begin
+                h_count_reg <= 0;
+                // Logika za vertikalni brojač
+                if (v_count_reg == VMAX) 
+                    v_count_reg <= 0;
+                else 
+                    v_count_reg <= v_count_reg + 1;
+            end else begin
+                h_count_reg <= h_count_reg + 1;
+            end
+            
+            // Ažuriranje sinhronizacije
+            v_sync_reg <= v_sync_next;
+            h_sync_reg <= h_sync_next;
+        end
+
+    // reg r_25MHz;
+	// wire w_25MHz;
+	
+	// always @(posedge clk or posedge reset)
+	// 	if(reset)
+	// 	  r_25MHz <= 0;
+	// 	else
+	// 	  r_25MHz <= r_25MHz + 1;
+	
+	// assign w_25MHz = (r_25MHz == 0) ? 1 : 0; // assert tick 1/2 of the time
+
+    // // Register Control
+    // always @(posedge clk or posedge reset)
+    //     if(reset) begin
+    //         v_count_reg <= 0;
+    //         h_count_reg <= 0;
+    //         v_sync_reg  <= 1'b0;
+    //         h_sync_reg  <= 1'b0;
+    //     end
+    //     else begin
+    //         v_count_reg <= v_count_next;
+    //         h_count_reg <= h_count_next;
+    //         v_sync_reg  <= v_sync_next;
+    //         h_sync_reg  <= h_sync_next;
+    //     end
+         
+    // //Logic for horizontal counter
+    // always @(posedge w_25MHz or posedge reset)      // pixel tick
+    //     if(reset)
+    //         h_count_next = 0;
+    //     else
+    //         if(h_count_reg == HMAX)                 // end of horizontal scan
+    //             h_count_next = 0;
+    //         else
+    //             h_count_next = h_count_reg + 1;         
+  
+    // // Logic for vertical counter
+    // always @(posedge w_25MHz or posedge reset)
+    //     if(reset)
+    //         v_count_next = 0;
+    //     else
+    //         if(h_count_reg == HMAX)                 // end of horizontal scan
+    //             if((v_count_reg == VMAX))           // end of vertical scan
+    //                 v_count_next = 0;
+    //             else
+    //                 v_count_next = v_count_reg + 1;
+        
+    // h_sync_next asserted within the horizontal retrace area
+    assign h_sync_next = (h_count_reg >= (HD+HB) && h_count_reg <= (HD+HB+HR-1));
+    
+    // v_sync_next asserted within the vertical retrace area
+    assign v_sync_next = (v_count_reg >= (VD+VB) && v_count_reg <= (VD+VB+VR-1));
+    
+    // Video ON/OFF - only ON while pixel counts are within the display area
+    assign video_on = (h_count_reg < HD) && (v_count_reg < VD); // 0-639 and 0-479 respectively
+            
+    // Outputs
+    assign hsync  = h_sync_reg;
+    assign vsync  = v_sync_reg;
+    assign x      = h_count_reg;
+    assign y      = v_count_reg;
+    assign p_tick = clk;
+            
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_map_ram.v

@@ -0,0 +1,30 @@
+
+module vga_map_ram (
+    input clk,	
+	input wen, 
+	input [11:0] waddr,
+	input [3:0] wdata,	
+    input ren,	
+	input [11:0] raddr,		    	
+    output reg [3:0] rdata
+);
+	//parameter MEM_INIT_FILE = "vid_ram.mem";
+	(* ram_style = "block" *) reg [3:0] map_ram [0:1199];   // memory for 40 x 30 position mega character with value between 0-15 for character id
+	
+	//initial
+	//if (MEM_INIT_FILE != "")
+	//	$readmemh(MEM_INIT_FILE, map_ram);
+		
+    always @(posedge clk) 
+	begin
+		if (ren)
+			rdata <= map_ram[raddr];
+	end		
+			
+    always @(posedge clk) 
+	begin			
+		if (wen)
+			map_ram[waddr] <= wdata;
+    end
+	
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_ram.v

@@ -0,0 +1,30 @@
+
+module vga_ram (
+    input clk,	
+	input wen, 
+	input [11:0] waddr,
+	input [11:0] wdata,	
+    input ren,	
+	input [11:0] raddr,		    	
+    output reg [11:0] rdata
+);
+	//parameter MEM_INIT_FILE = "vid_ram.mem";
+	(* ram_style = "block" *) reg [11:0] ram [0:4095];   //  memory for 16 character with dimension 16x16 pixels @ 12bpp // bio distribuirani
+	
+	//initial
+	//if (MEM_INIT_FILE != "")
+	//	$readmemh(MEM_INIT_FILE, ram);
+		
+    always @(posedge clk) 
+	begin
+		if (ren)
+			rdata <= ram[raddr];
+	end		
+			
+    always @(posedge clk) 
+	begin			
+		if (wen)
+			ram[waddr] <= wdata;
+    end
+	
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_wrapper.v

@@ -0,0 +1,89 @@
+`timescale 1ns / 1ps
+
+module vga_wrapper (
+    input clk,	
+	input reset,        // system reset	
+
+	output reg vga_iomem_ready,
+	input iomem_valid,
+	input iomem_ready,
+	input [3:0]  iomem_wstrb,
+	input [31:0] iomem_addr,
+	input [31:0] iomem_wdata,	
+	
+    input video_on,
+    input [9:0] x, y,
+    output reg [11:0] rgb,
+	
+	output[4:0]   o_debug_pins
+);
+    
+    // signal declarations
+	wire charset_on, charset_on1, charset_on2;	
+	reg char_mem_write, map_mem_write;
+	wire [11:0] write_address;    
+	wire [11:0] read_address, map_read_address;
+	wire [11:0] rgb_rdata;
+	wire [3:0] map_rdata;		
+	
+	always @(posedge clk) 
+	begin
+		if (reset) begin			
+			char_mem_write <= 0;	
+			map_mem_write <= 0;
+		end else begin
+			vga_iomem_ready <= 0;
+			char_mem_write <= 0;
+			map_mem_write <= 0;
+			if (iomem_valid && !iomem_ready) begin
+				vga_iomem_ready <= 1;				
+				if(iomem_addr[23:20]==4'h1) begin
+					if(iomem_wstrb[0]) begin
+						char_mem_write <= 1;						
+					end				
+				end else if(iomem_addr[23:20]==4'h2) begin
+					if(iomem_wstrb[0]) begin
+						map_mem_write <= 1;
+					end
+				end
+			end
+		end
+	end
+	
+	assign write_address = (iomem_addr[15:0]/4);
+	assign read_address = {map_rdata, y[3:0], x[3:0]};
+	assign map_read_address = ( y >> 4 ) * 6'd40 + ( x >> 4 );
+
+	vga_map_ram map(
+		.clk(clk),
+		.wen(map_mem_write),			
+		.waddr(write_address),		
+		.wdata(iomem_wdata[3:0]),
+		.ren(video_on), 
+		.raddr(map_read_address), 
+		.rdata(map_rdata)
+	);
+	
+	vga_ram ram(
+		.clk(clk),
+		.wen(char_mem_write),			
+		.waddr(write_address),		
+		.wdata(iomem_wdata[11:0]),
+		.ren(video_on), 
+		.raddr(read_address), 
+		.rdata(rgb_rdata)
+	);
+	
+
+    // rgb multiplexing circuit
+    always @(*)
+	begin
+        if(~video_on)
+            rgb = 12'h000;      // blank
+        else	
+			rgb = rgb_rdata;				
+	end
+	
+	assign o_debug_pins = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0};	
+	
+endmodule

chili-chips-ba_openCologne/5.TetriSaraj/2.sim/README.md

@@ -0,0 +1,44 @@
+# HW/SW co-sim with VProc VIP
+by Simon Southwell
+<p align="center">
+<img src="0.doc/wyvernSemi.png">
+</p>
+
+
+## First things first
+- [Vproc Intro](https://drive.google.com/file/d/1V81Q9Ue9HjQIpum2KXUp8eKwzed-kwfm)
+- [VProc Manual](https://github.com/wyvernSemi/vproc/blob/master/doc/VProc.pdf)
+
+
+## Native Mode
+<img src="0.doc/vproc_tb_native.png">
+
+
+## ISS Mode
+<img src="0.doc/vproc_tb_iss.png">
+
+
+## Testbench structure
+<img src="0.doc/vid_ctlr_tb_vproc.png">
+
+## How to build and run it
+
+## Misc Tidbits: VProc Node
+Node is simply memory mapped in _display.v_ for cross referencing. When using the C API or when creating a new C++ API object, the node number must be used to connect to a given VProc instantiation which might, accidently, be the wrong one. This simply gives a means, if desired, to check that the API object is connected to the expected node for safety and avoiding unexpected behaviour. It does not have to be there for VProc to work.
+
+## Misc Tidbits: VProc Delta-Cycle Processing
+The "delta-cycle" process can't be a clock in order to access more than 32 bits  to read and/or update in a single cycle. Conceivably if one needed to access, say, ten 32-bit ports, then VProc could be run 10 times faster to update by the end of the external clock, but this is an arbitrary number and might not work for all possible cases. 
+
+It would likely run slower than using the delta-cycle updates. It's only needed, in any case, if using VProc to memory map ports---and the jury is out for _display.v_ and I need to measure its impact on performance. 
+
+The whole delta cycle logic can be disabled by setting VProc's **DISABLE_DELTA** generic to non-zero, and the **Update** and **UpdateResponse** signals are then unconnected. In a test bench that only has VProcs used as a 32-bit memory mapped virtual CPUs, then this feature can be ignored and configured out. 
+
+Delta cycle accesses are used for pcievhost, but it might conceivably be configured out for a single lane 8b10b bit in and out port (20 bits) and a electrical idle in and out, but two lanes or more is not possible as this will require multiple accesses per cycle.
+
+## References
+- [LI-2024-01](https://www.linkedin.com/pulse/vproc-virtual-processor-vip-simon-southwell-pjmpe)
+- [LI-2024-10](https://www.linkedin.com/posts/simon-southwell-7684482_riscv-iss-embeddedsoftware-activity-7256311551178027008-1nlZ?utm_source=share&utm_medium=member_desktop)
+- [VGASIM](https://github.com/wyvernSemi/vgasim)
+
+
+#### End of Document

chili-chips-ba_openCologne/5.TetriSaraj/2.sw/main.c

@@ -0,0 +1,1212 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Coyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, coy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  coyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// INCLUDES AND DEFINES--------------------------------------------------
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "uart.h"
+
+#define RAM_TOTAL 0x2000 // 8 KB
+
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004)
+#define reg_uart_data (*(volatile uint32_t*)0x02000008)
+
+#define reg_gpio (*(volatile uint32_t*) 0x03000000)
+#define reg_video_char  ((volatile uint32_t*)0x05100000)
+#define reg_video_map   ((volatile uint32_t*)0x05200000)
+
+#define BUTTON_UP 0x01     // 0000 0001
+#define BUTTON_RIGHT 0x02  // 0000 0010
+#define BUTTON_LEFT 0x04   // 0000 0100
+#define BUTTON_DOWN 0x08   // 0000 1000
+#define BUTTON_CENTER 0x10 // 0001 0000
+
+#define DELAY   2500
+
+#define  fieldWidth  40
+#define  fieldHeight 30
+
+// GLOBAL VARIABLES--------------------------------------------------------
+
+uint8_t buttons;
+static uint32_t delay = DELAY;
+static uint8_t field[1200];
+
+static uint8_t tetrominoes[7][16]={{1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0},
+                           {0,0,1,0,0,1,1,0,0,0,1,0,0,0,0,0},
+                           {0,0,0,0,0,1,1,0,0,1,1,0,0,0,0,0},
+                           {0,0,1,0,0,1,1,0,0,1,0,0,0,0,0,0},
+                           {0,1,0,0,0,1,1,0,0,0,1,0,0,0,0,0},
+                           {0,1,0,0,0,1,0,0,0,1,1,0,0,0,0,0},
+                           {0,0,1,0,0,0,1,0,0,1,1,0,0,0,0,0}};
+
+// PRIVATE FUNCTIONS DECLARATIONS--------------------------------------------
+
+static void CharactersInit(void);
+static void DisplayProjectName(void);
+static void DisplayCompanyName(void);
+static void DisplayGameName(void);
+static void DisplayHeart(int x_start, int y_start, int color);
+static void setScreenColor(int color);
+static void DisplayGameOverScreen(int numLives );
+static void DisplayTheEndScreen(void);
+static void GetButtonStates(void);
+static int  Rotate(int x, int y, int r);
+static bool DoesPieceFit(int ntetrominoes, int nRotation, int nPosX, int nPosY);                  
+static void DisplayDigit(uint8_t number, uint8_t startX, uint8_t startY);
+static void WriteScore(int score); 
+
+// PRIVATE FUNCTIONS IMPLEMENTATION-------------------------------------------
+
+/* 
+ * brief   reads the gpio register and changes the state of buttons variable
+ * return  void
+ */
+void GetButtonStates() {  
+   buttons = (uint8_t)(reg_gpio >> 16)&0xFF;
+}
+
+/* 
+ * brief   displays GATEMATE Demo on the screen
+ * return  void
+ */
+void DisplayProjectName() 
+{
+    uint8_t nameY = 3;
+    for (uint8_t y = 0; y < 30; y++)
+    { 
+        for (uint8_t x = 0; x < 40; x++) // Board Boundary
+        {
+            reg_video_map[y * 40 + x] = 12; // Background color
+            //G
+            if ((y == nameY && (x >= 3 && x <= 5)) || (y == nameY + 4 && (x >= 3 && x <= 5)) || (x == 3 && (y >= nameY && y <= nameY + 4)) || (x == 5 && (y >= nameY + 2 && y <= nameY + 4)))
+                reg_video_map[y * 40 + x] = 0;
+            //a
+            if((x == 7 || x == 9) && (y >= nameY + 1 && y <= nameY + 4) || (x == 8 && y == nameY + 2) || (x == 8 && y == nameY))
+            reg_video_map[y * 40 + x] = 0;
+            //t
+            if ((y == nameY && (x >= 11 && x <= 13)) || (x == 12 && (y >= nameY && y <= nameY + 4)))
+                reg_video_map[y * 40 + x] = 0;
+            //e
+            if (((y == nameY || y == nameY + 4) && (x >= 15 && x <= 17)) || (y == nameY + 2 && x == 16) || (x == 15 && (y >= nameY && y <= nameY + 4)))
+                reg_video_map[y * 40 + x] = 0;
+            //M
+            if ((y == nameY && (x == 20 || x == 21 || x == 23 || x == 24)) || (x == 20 && (y >= nameY && y <= nameY + 4)) || (x == 24 && (y >= nameY && y <= nameY + 4)) || (x == 22 && y == nameY + 1))
+                reg_video_map[y * 40 + x] = 11;
+            //a
+            if((x == 26 || x == 28) && (y >= nameY + 1 && y <= nameY + 4) || (x == 27 && y == nameY + 2) || (x == 27 && y == nameY))
+            reg_video_map[y * 40 + x] = 11;
+            //t
+            if ((y == nameY && (x >= 30 && x <= 32)) || (x == 31 && (y >= nameY && y <= nameY + 4)))
+            reg_video_map[y * 40 + x] = 11;
+            //e
+            if (((y == nameY || y == nameY + 4) && (x >= 34 && x <= 36)) || (y == nameY + 2 && x == 35) || (x == 34 && (y >= nameY && y <= nameY + 4)))
+             reg_video_map[y * 40 + x] = 11;
+        }
+    }
+} 
+
+
+/* 
+ * brief   displays CHILI CHIPS on the screen
+ * return  void
+ */
+void DisplayCompanyName() 
+{  
+   uint8_t lineY = 11;
+   uint8_t lineXStart = 3, lineXEnd = 36;
+   uint8_t nameY = 14;
+   for (uint8_t y = 0; y < 30; y++)
+   { 
+      for (uint8_t x = 0; x < 40; x++) // Board Boundary
+      {
+         // blue line
+         if (y == lineY && (x >= lineXStart && x <= lineXEnd))
+            reg_video_map[y * 40 + x] = 10;
+         
+         //C
+         if (x == 4 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if (y == nameY && (x == 5 || x == 6))
+            reg_video_map[y * 40 + x] = 7;
+         if (y == nameY + 4 && (x == 5 || x == 6))
+            reg_video_map[y * 40 + x] = 7;
+         //h
+         if (x == 8 && (y >= nameY && y <= nameY + 4) )
+            reg_video_map[y*40+x]=7;
+         if (y == nameY + 2 && (x == 9 || x == 10))
+            reg_video_map[y * 40 + x] = 7;
+         if (x == 10 && (y >= nameY + 2 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         // i 
+         if (x == 12 && (y >= nameY + 2 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if (x == 12 && y == nameY)
+            reg_video_map[y * 40 + x] = 7;
+         // l 
+         if (x == 14 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x]=7;
+         // i 
+         if (x == 16 && (y >= nameY + 2 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if (x == 16 && y == nameY)
+            reg_video_map[y * 40 + x] = 7;
+         // C 
+         if (x == 19 && (y >= nameY && y <= nameY + 4) )
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY && (x == 20 || x == 21))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY + 4 && (x == 20 || x == 21))
+            reg_video_map[y * 40 + x] = 2;
+         //H
+         if (x == 23 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY + 2 && (x == 24 || x == 25))
+            reg_video_map[y * 40 + x] = 2;
+         if (x == 25 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         // I
+         if (x == 27 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         // P
+         if (x == 29 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY && (x == 30 || x == 31))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY + 2 && (x == 30 || x == 31))
+            reg_video_map[y * 40 + x] = 2;
+         if (x == 31 && (y >= nameY && y <= nameY + 2))
+            reg_video_map[y * 40 + x] = 2;
+         // S 
+         if (y == nameY && (x >= 33 && x <= 35 ))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY + 2 && (x >= 33 && x <= 35))
+            reg_video_map[y * 40 + x] = 2;
+         if (y == nameY + 4 && (x >= 33 && x <= 35))
+            reg_video_map[y * 40 + x] = 2;
+         if (x == 33 && y == nameY + 1)
+            reg_video_map[y * 40 + x] = 2;
+         if (x == 35 && y == nameY + 3)
+            reg_video_map[y * 40 + x] = 2;
+      }
+   }
+}
+
+/* 
+ * brief   displays TETRISARAJ on the screen
+ * return  void
+ */
+void DisplayGameName() 
+{
+   uint8_t nameY = 22;
+   for (uint8_t y = 0; y < 30; y++)
+   { 
+      for (uint8_t x = 0; x < 40; x++) // Board Boundary
+      {
+         //T
+         if(y == nameY && (x>=2 && x<=4) || (x == 3 && (y >= nameY && y <= nameY + 4)))
+            reg_video_map[y * 40 + x] = 2;
+         //E
+         if (((y == nameY || y == nameY + 4) && (x >= 6 && x <= 8)) || (y == nameY + 2 && x == 7) || (x == 6 && (y >= nameY && y <= nameY + 4)))
+            reg_video_map[y * 40 + x] = 2;
+          //T
+         if(y == nameY && (x >= 10 && x <= 12))
+            reg_video_map[y * 40 + x] = 2;
+         if(x == 11 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+          //R
+         if(x == 14 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         if(x == 15 && y== nameY)
+            reg_video_map[y * 40 + x] = 2;
+         if(x == 16 && y == nameY + 1)
+            reg_video_map[y * 40 + x] = 2;
+         if(x == 15 && y == nameY + 2)
+            reg_video_map[y * 40 + x] = 2;
+         if(x == 16 && (y == nameY + 3 || y == nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         //I
+         if(x == 18 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 2;
+         //S
+         if(y == nameY && (x == 20 || x == 21))
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 20 && (y == nameY + 1 || y == nameY + 2 || y == nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 21 && (y >= nameY + 2 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         //A
+         if((x == 23 || x == 25) && (y >= nameY + 1 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 24 && y == nameY + 2)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 24 && y == nameY)
+            reg_video_map[y * 40 + x] = 7;
+         //R
+         if(x == 27 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 28 && y == nameY)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 29 && y == nameY + 1)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 28 && y == nameY + 2)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 29 && (y == nameY + 3 || y == nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         //A
+         if((x == 31 || x == 33) && (y >= nameY + 1 && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 32 && y == nameY + 2)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 32 && y == nameY)
+            reg_video_map[y * 40 + x] = 7;
+         //J
+         if(x == 37 && (y >= nameY && y <= nameY + 4))
+            reg_video_map[y * 40 + x] = 7;
+         if((x == 35 || x == 36) && y == nameY + 4)
+            reg_video_map[y * 40 + x] = 7;
+         if(x == 35 && y == nameY + 3)
+            reg_video_map[y * 40 + x] = 7; 
+      }
+   }
+}
+/* 
+ * brief   displays heart on screen 
+ * return  void
+ */
+void DisplayHeart(int x_start, int y_start, int color){
+   for (int y = 0; y < 30; y++)
+   { 
+      for (int x = 0; x < 40; x++) // Board Boundary
+      {
+         if((x==2+x_start || x==3+x_start || x==7+x_start || x==8+x_start) && y==y_start)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==1+x_start || x==4+x_start || x==6+x_start || x==9+x_start) && y==y_start+1)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==x_start || x==5+x_start || x==10+x_start) && y==y_start+2)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==x_start || x==10+x_start) && y==y_start+3)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==1+x_start || x==9+x_start) && y==y_start+4)
+            reg_video_map[y * 40 + x] = 0;   
+         if((x==2+x_start || x==8+x_start) && y==y_start+5)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==3+x_start || x==7+x_start) && y==y_start+6)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==4+x_start || x==6+x_start) && y==y_start+7)
+            reg_video_map[y * 40 + x] = 0;
+         if((x==5+x_start) && y==y_start+8)
+            reg_video_map[y * 40 + x] = 0;
+         
+         if((x==2+x_start || x==3+x_start || x==7+x_start || x==8+x_start) && y==y_start+1)
+            reg_video_map[y * 40 + x] = color;
+         if(((x>=1+x_start && x<=4+x_start) || (x>=6+x_start && x<=9+x_start)) && y==y_start+2)
+            reg_video_map[y * 40 + x] = color;
+         if((x>=1+x_start && x<=9+x_start) && y==y_start+3)
+            reg_video_map[y * 40 + x] = color;
+         if((x>=2+x_start && x<=8+x_start) && y==y_start+4)
+            reg_video_map[y * 40 + x] = color;
+         if((x>=3+x_start && x<=7+x_start) && y==y_start+5)
+            reg_video_map[y * 40 + x] = color;
+         if((x>=4+x_start && x<=6+x_start) && y==y_start+6)
+            reg_video_map[y * 40 + x] = color;
+         if(x==5+x_start && y==y_start+7)
+            reg_video_map[y * 40 + x] = color;
+         
+      }
+   }
+
+}
+/* 
+ * brief   set screen color
+ * return  void
+ */
+ void setScreenColor(int color){
+   for (uint8_t y = 0; y < 30; y++)
+   { 
+      for (uint8_t x = 0; x < 40; x++) // Board Boundary
+      {
+         reg_video_map[y * 40 + x] = color;
+      }
+   }
+ }
+/* 
+ * brief   displays game over screen 
+ * return  void
+ */
+void DisplayGameOverScreen(int numLives )
+{
+   uint8_t nameY = 1;
+   for (uint8_t y = 0; y < 30; y++)
+   { 
+      for (uint8_t x = 0; x < 40; x++) // Board Boundary
+      {
+         reg_video_map[y * 40 + x] = 9;
+         
+         //G
+         if((x == 5 && (y >= nameY+2 && y <= nameY+5)) || (x == 6 && (y == nameY+1 || y == nameY+6)) || ((x >= 7 && x<= 11) && (y == nameY || y==nameY+7)) || (x==11 && (y>=nameY+4 && y<=nameY+7)) || (x >= 8 && x<= 11) && (y == nameY+4) )
+         reg_video_map[y * 40 + x] = 3;
+
+         //A   
+         if((x==16 && y==nameY) || ((x==15 || x==17) && y==nameY+1) || ((x==14 || x==18) && (y>=nameY+2 && y<=nameY+3)) || ((x>=13 && x<=19) && y==nameY+4) || ((x==13 || x==19) && (y>=nameY+5 && y<=nameY+7)))
+         reg_video_map[y * 40 + x] = 1;
+
+         //M
+         if(((x==21 || x==28) && (y>=nameY && y<=nameY+7)) || ((x==22 || x==27) && y==nameY) || ((x==23 || x==26) && (y>=nameY+1 && y<=nameY+2)) || ((x==24 || x==25) && y==nameY+3))
+         reg_video_map[y * 40 + x] = 2;
+
+         //E
+         if(((x>=30 && x<=34) && (y==nameY || y==nameY+7)) || (x==30 && (y>=nameY+1 && y<=nameY+6)) || ((x>=31 && x<=33) && y==nameY+4))
+         reg_video_map[y * 40 + x] = 4;
+
+
+         //O
+         if(((x==7 || x==12) && (y>=nameY+11 && y<=nameY+16)) || ((y==nameY+10 || y==nameY+17) && (x>=8 && x<=11)))
+         reg_video_map[y * 40 + x] = 3;
+
+         //V
+         if(((x==14 || x==20) && (y>=nameY+10 && y<=nameY+12)) || ((x==15 || x==19) && (y>=nameY+13 && y<=nameY+14)) || ((x==16 || x==18) && (y==nameY+15)) || ((x==17) && (y>=nameY+16 && y<=nameY+17)))
+         reg_video_map[y * 40 + x] = 1;
+
+         //E
+         if(((x>=22 && x<=26) && (y==nameY+10 || y==nameY+17)) || (x==22 && (y>=nameY+11 && y<=nameY+16)) || ((x>=23 && x<=25) && y==nameY+14))
+         reg_video_map[y * 40 + x] = 2;
+
+         //R
+         if((x==28 && (y>=nameY+10 && y<=nameY+17)) || ((x>=29 && x<=31) && (y==nameY+14 || y==nameY+10)) || ((x==32) && (y>=nameY+11 && y<=nameY+13)) || (x==30 && y==nameY+15) || (x==31 && y==nameY+16) || (x==32 && y==nameY+17))        
+         reg_video_map[y * 40 + x] = 4;
+      }
+   }
+      // Lives
+         if(numLives==3){
+            DisplayHeart(5,21,3);
+            DisplayHeart(15,21,3);
+            DisplayHeart(25,21,3);
+         }
+         
+         if(numLives==2){
+            DisplayHeart(5,21,3);
+            DisplayHeart(15,21,3);
+            DisplayHeart(25,21,9);
+         }
+         
+         if(numLives==1){
+            DisplayHeart(5,21,3);
+            DisplayHeart(15,21,9);
+            DisplayHeart(25,21,9);
+         }
+}
+/* 
+ * brief   displays THE END screen 
+ * return  void
+ */
+void DisplayTheEndScreen(void)
+{
+   uint8_t nameY = 8;
+   for (uint8_t y = 0; y < 23; y++)
+   { 
+      for (uint8_t x = 0; x < 40; x++) // Board Boundary
+      {
+         reg_video_map[y * 40 + x] = 0;
+         
+         // T
+         if ((y == nameY && (x >= 5 && x <= 7)) || (x == 6 && (y >= nameY && y <= nameY + 4)))
+            reg_video_map[y * 40 + x] = 3;
+         
+         // H
+         if ((y == nameY + 2 && (x >= 9 && x <= 11)) || ((x == 9 || x == 11) && (y >= nameY && y <= nameY + 4)))        
+            reg_video_map[y * 40 + x] = 3;
+         
+         // E
+         if (((y == nameY || y == nameY + 4) && (x >= 13 && x <= 15)) || (x == 13 && (y >= nameY && y <= nameY + 4)) || (y == nameY + 2 && (x >= 13 && x <= 14)))       
+            reg_video_map[y * 40 + x] = 3;
+         
+         // E
+         if (((y == nameY || y == nameY + 4) && (x >= 20 && x <= 22)) || (x == 20 && (y >= nameY && y <= nameY + 4)) || (y == nameY + 2 && (x >= 20 && x <= 21)))       
+            reg_video_map[y * 40 + x] = 3;
+         
+         // N
+         if ((y == nameY + 2 && x == 25) || (y == nameY + 3 && x == 26) || ((x == 24 || x == 27) && (y >= nameY && y <= nameY + 4)))         
+            reg_video_map[y * 40 + x] = 3;
+         
+         // D
+         if ((x == 31 && (y >= nameY + 1 && y <= nameY + 3)) || ((y == nameY || y == nameY + 4) && (x >= 29 && x <= 30)) || (x == 29 && (y >= nameY && y <= nameY + 4)))
+            reg_video_map[y * 40 + x] = 3;
+         
+         // !
+         if ((x == 33 && (y >= nameY && y <= nameY + 2)) || (x == 33 && y == nameY + 4))
+            reg_video_map[y * 40 + x] = 3;
+      }
+   }
+}
+
+/* 
+ * brief   defines all characters that can be used
+ * return  void
+ */
+void CharactersInit() {
+   uint32_t pixel = 0x00000FFF;
+   for(uint8_t z = 0; z < 16; z++) 
+   {
+      for(uint8_t y = 0; y < 16; y++) 
+      {
+         for(uint8_t x = 0; x < 16; x++) 
+         {
+            if(z == 0) // color black
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000222;
+               else if (x == 14 || x == 15) pixel = 0x00000111; 
+               else pixel = 0x00000000; 
+            } 
+            else if(z == 1) // color green
+            {  
+               if(y == 0 || y == 1) pixel = 0x00000080; 
+               else if (x == 14 || x == 15) pixel = 0x00000080;
+               else pixel = 0x000008B4; 
+            } 
+            else if(z == 2) // color blue
+            {
+               if(y == 0 || y == 1) pixel = 0x0000000B;
+               else if (x == 14 || x == 15) pixel = 0x0000000B;
+               else pixel = 0x0000009F; 
+            } 
+            else if(z == 3) // color red
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000A00;
+               else if (x == 14 || x == 15) pixel = 0x00000B00; 
+               else pixel = 0x00000F00; 
+            } 
+            else if(z == 4) // color yellow
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000FD8; 
+               else if (x == 14 || x == 15) pixel = 0x00000FD4; 
+               else pixel = 0x00000FD2; 
+            } 
+            else if(z == 5) // color purple
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000075D;
+               else if (x == 14 || x == 15) pixel = 0x00000074D; 
+               else pixel = 0x00000070D; 
+            } 
+            else if(z == 6) // color pink
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000FAF;
+               else if (x == 14 || x == 15) pixel = 0x00000F6F; 
+               else pixel = 0x00000F0F;
+            } 
+            else if(z == 7) // color orange
+            { 
+               if(y == 0 || y == 1) pixel = 0x00000FB0; 
+               else if (x == 14 || x == 15) pixel = 0x00000F90;
+               else pixel = 0x00000F63; 
+            } 
+            else if(z == 8)  // not used
+            {
+               pixel = 0x000000A0;     
+            } 
+            else if(z == 9) // color gray
+            { 
+               if (x == 14 || x == 15) pixel = 0x00000CCC; 
+               else if(y == 0 || y == 1) pixel = 0x00000111; 
+               else pixel = 0x00000AAA;   
+            } 
+            else if(z == 10) // color light blue
+            {
+               if(y == 0 || y == 1) pixel = 0x0000000B;
+               else if (x == 14 || x == 15) pixel = 0x0000000B;
+               else pixel = 0x00000007; 
+            } 
+            else if(z == 11) // GateMate blue
+            {
+               if(y == 0 || y == 1) pixel = 0x0000000B;
+               else if (x == 14 || x == 15) pixel = 0x0000000B;
+               else pixel = 0x0000006C; 
+            } 
+            else if(z == 12) // not used 
+            {
+               // Yellow pixels (color FD2)
+               if ((x == 2 && y == 0) || (x == 7 && y == 0) || (x == 8 && y == 0) ||
+               (x == 13 && y == 0) || (x == 1 && y == 1) || (x == 6 && y == 1) || 
+               (x == 9 && y == 1) || (x == 14 && y == 1) || (x == 0 && y == 2) || 
+               (x == 5 && y == 2) || (x == 10 && y == 2) || (x == 15 && y == 2) || 
+               (x == 2 && y == 3) || (x == 3 && y == 3) || (x == 4 && y == 3) || 
+               (x == 11 && y == 3) || (x == 12 && y == 3) || (x == 13 && y == 3) ||
+               (x == 2 && y == 4) || (x == 13 && y == 4) || (x == 2 && y == 5) || 
+               (x == 13 && y == 5) || (x == 1 && y == 6) || (x == 14 && y == 6) || 
+               (x == 0 && y == 7) || (x == 15 && y == 7) || (x == 1 && y == 8) || 
+               (x == 14 && y == 8) || (x == 2 && y == 9) || (x == 13 && y == 9) ||
+               (x == 2 && y == 10) || (x == 13 && y == 10) || (x == 2 && y == 11) || 
+               (x == 3 && y == 11) || (x == 4 && y == 11) || (x == 11 && y == 11) ||
+               (x == 12 && y == 11) || (x == 13 && y == 11) || (x == 5 && y == 12) || 
+               (x == 10 && y == 12) || (x == 0 && y == 13) || (x == 6 && y == 13) || 
+               (x == 9 && y == 13) || (x == 15 && y == 13) || (x == 1 && y == 14) || 
+               (x == 7 && y == 14) || (x == 8 && y == 14) || (x == 14 && y == 14) ||
+               (x == 2 && y == 15) || (x == 3 && y == 15) || (x == 4 && y == 15) || 
+               (x == 5 && y == 15) || (x == 6 && y == 15) || (x == 7 && y == 15) ||
+               (x == 8 && y == 15) || (x == 9 && y == 15) || (x == 10 && y == 15) ||
+               (x == 11 && y == 15) || (x == 12 && y == 15) || (x == 13 && y == 15)) 
+               {
+                pixel = 0x00000FD2; // Yellow color (FD2)
+               }
+               // White pixels
+               else 
+               {
+                  pixel = 0xFFFFFFFF; // White color
+               }
+            }
+            else if(z == 13) // not used 
+            {
+               pixel = 0x00000A0A;
+            } 
+            else if(z == 14) // not used 
+            {
+               pixel = 0x00000FFF;           
+            } 
+            else 
+            {
+               pixel = 0x00000000;
+            }
+            reg_video_char[z * 256 + y * 16 + x] = pixel;
+         }
+      }  
+   }
+}
+
+/* 
+ * brief   handles the rotation of the piece
+ * return  index of the rotated piece
+ */
+int Rotate(int x, int y, int r)
+{
+    int pi = 0;
+    switch (r % 4)
+    {
+        case 0: // 0 degrees        // 0  1  2  3
+            pi = y * 4 + x;         // 4  5  6  7
+            break;                  // 8  9 10 11
+            //12 13 14 15
+
+        case 1: // 90 degrees       //12  8  4  0
+            pi = 12 + y - (x * 4);  //13  9  5  1
+            break;                  //14 10  6  2
+            //15 11  7  3
+
+        case 2: // 180 degrees         //15 14 13 12
+            pi = 15 - (y * 4) - x;  //11 10  9  8
+            break;                  // 7  6  5  4
+            // 3  2  1  0
+
+        case 3: // 270 degrees         // 3  7 11 15
+            pi = 3 - y + (x * 4);      // 2  6 10 14
+            break;                  // 1  5  9 13
+    }                         // 0  4  8 12
+
+    return pi;
+}
+
+/* 
+ * brief   checks if the piece can be moved to a specified position
+ * return  true if the piece can fit and false otherwise
+ */
+bool DoesPieceFit(int tetrominosIndex, int nRotation, int nPosX, int nPosY)
+{
+   // All Field cells >0 are occupied
+   for (int x = 0; x < 4; x++)
+      for (int y = 0; y < 4; y++)
+      {
+         // Get index into piece
+         int pi = Rotate(x, y, nRotation);
+
+         // Get index into field
+         int fi = (nPosY + y) * fieldWidth + (nPosX + x);
+
+         // Check that test is in bounds. Note out of bounds does
+         // not necessarily mean a fail, as the long vertical piece
+         // can have cells that lie outside the boundary, so we'll
+         // just ignore them
+         if (nPosX + x >= 0 && nPosX + x < fieldWidth)
+         {
+            if (nPosY + y >= 0 && nPosY + y < fieldHeight)
+            {
+                  // In Bounds so do collision check
+                  if ((tetrominoes[tetrominosIndex][pi] != 0 && field[fi] != 0) /* || (tetrominoes[ntetrominoes][pi] != 0 && (nPosY+y)==0) */) // dodali smo || ....
+                  return false; // fail on first hit
+            }
+         }
+      }
+
+    return true;
+}
+
+/* 
+ * brief   displays a digit on specified location
+ * return  void
+ */
+void DrawDigit(int number, int startX, int startY)
+{
+   for (uint8_t y = startY; y < startY + 5; y++)
+   { 
+      for (uint8_t x = startX; x < startX + 3; x++) 
+      {
+         switch (number)
+         {
+            case 0:
+               if (x == startX || x == startX + 2 || y == startY || y == startY + 4)
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 1:
+               if (x == startX + 2 || y == startY + 1)
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 2:
+               if (y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX + 2) || (y == startY + 3 && x == startX))
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 3:
+               if (x == startX + 2 || y == startY || y == startY + 2 ||y == startY + 4)
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 4:
+               if (x == startX + 2 || y == startY + 2 || (y <= startY + 2 && x == startX))
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 5:
+               if (y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX) || (y == startY + 3 && x == startX + 2))
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 6:
+               if (x == startX || y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 3 && x == startX + 2))
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 7:
+               if (x == startX + 2 || y == startY)
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 8:
+               if (x == startX || x == startX + 2 || y == startY || y == startY + 2 || y == startY + 4)
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            case 9:
+               if (x == startX + 2 || y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX))
+                  field[y * fieldWidth + x] = 0;
+               else
+                  field[y * fieldWidth + x] = 9;
+               break;
+            default:
+               break;
+         }
+      }
+   }
+}
+
+/* 
+ * brief   displays the current player score
+ * return  void
+ */
+void DisplayScore(int score, int startX, int startY)
+{
+   int digits[4] = {0,0,0,0};
+   int i = 0;
+   while (score != 0)
+   {
+      digits[i++] = score % 10;
+      score /= 10;
+   }
+   
+   for (i = 3; i >= 0; i--)
+   {
+      DrawDigit(digits[i], startX + (3 - i)*4, startY);
+   }
+}
+
+/* 
+ * brief   displays the word score on the screen
+ * return  void
+ */
+void WriteScore(int score) 
+{
+   for (uint8_t y = 24; y < 29; y++) {
+      for (uint8_t x = 3; x < 21; x++) {
+         if (x == 3 || x == 4) // letter S
+         {
+            if (y == 24 || y == 26 || y == 28 || (x == 3 && y == 25) || (x == 4 && y == 27))
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+         else if (x == 6 || x == 7) // letter C
+         {
+            if (x == 6 || y == 24 || y == 28)
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+         else if (x == 9 || x == 10 || x == 11) // letter O
+         {
+            if (x == 9 || x == 11 || y == 24 || y == 28)
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+         else if (x == 13 || x == 14 || x == 15) // letter R
+         {
+            if (x == 13 || (x == 14 && (y == 24 || y == 26)) || (x == 15 && (y == 25 || y > 26)))
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+         else if (x == 17 || x == 18) // letter E
+         {
+            if (x == 17 || (x == 18 && y % 2 == 0))
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+         else if (x == 20) // colon
+         {
+            if (y == 25 || y == 27)
+               field[y * fieldWidth + x] = 0;
+            else 
+               field[y * fieldWidth + x] = 9;
+         }
+      }
+   }
+   
+   DisplayScore(score, 22, 24);
+}
+/* 
+ * brief   creating the initial field
+ * return  void
+ */
+void FieldInitialization(){
+
+   for (uint8_t y = 0; y < fieldHeight; y++) 
+   {
+      for (uint8_t x = 0; x < fieldWidth; x++)
+      {        
+         field[y * fieldWidth + x] = (y == 0 ||
+                                           y >= fieldHeight - 7 ||
+                                           x + 1 == fieldWidth / 2 ||
+                                           x == fieldWidth / 2 ) ? 9u : 0u;
+      }
+   }
+}
+
+/* 
+ * brief   delay function, u32_delay = 40000 -> approx. 5 seconds
+ * return  void
+ */
+static inline void _delay(uint32_t u32_delay)
+{ 
+   uint16_t local = 0;
+   for (uint32_t i = 0u; i<u32_delay; i++)
+   {
+      print("_delay called");
+      if (i % 2 == 0) local++;
+   }
+}
+/* 
+ * brief   generates a 32-bit random number using XORSHIFT algorithm
+ * param   state: Pointer to the state variable for the random number generator
+ * return  unsigned int: The generated random number.
+ */
+unsigned int xorshift32(unsigned int *state) {
+   unsigned int x = *state;
+   x ^= x << 13;
+   x ^= x >> 17;
+   x ^= x << 5;
+   *state = x;
+   return x;
+}
+/* 
+ * brief   generates a random binary number (0 or 1)
+ * return  int: The generated random binary number (0 or 1)
+ */
+int generateRandomBinary() {
+    static unsigned int state = 123456789;  
+    return xorshift32(&state) % 2;
+}
+/* 
+ * brief   generates a random number within the specified range [min, max]
+ * param   min: The minimum value of the range
+ * param   max: The maximum value of the range
+ * return  int: The generated random number within the range [min, max]
+ */
+int generateRandomNumber(int min, int max) {
+   static unsigned int state = 123456789; 
+   unsigned int range = max - min + 1;
+   unsigned int randomValue = xorshift32(&state) % range + min;
+   return randomValue;
+}
+
+
+void main()
+{
+   reg_uart_clkdiv = 217; 
+   print("TetriSaraj!\n");
+
+   bool rightButton = false, downButton = false, centerButton = false, upButton = false, leftButton = false;   
+   
+   reg_gpio = 0x0;   
+   
+   CharactersInit();
+   DisplayProjectName();
+   _delay(3000); // 15000
+
+   DisplayCompanyName(); 
+   _delay(3000);
+   
+   DisplayGameName();
+   _delay(3000);
+   
+   FieldInitialization();
+   
+   setScreenColor(12);
+
+   DisplayHeart(5,9,3);
+   DisplayHeart(15,9,3);
+   DisplayHeart(25,9,3);
+   _delay(4000); // 20000
+   
+   // Game Logic
+   uint16_t pieceIndex = 0;
+   uint8_t pieceRotation = 3;
+   uint8_t pieceXCoordinate = 0;
+   uint8_t pieceYCoordinate = fieldHeight / 2;
+  
+   uint8_t speed = 15;
+   uint8_t gameTicksCount = 0;
+   uint8_t numLives=3;
+   bool movePiece = false;
+   bool rotationFlag = true;
+
+   uint16_t pieceCount = 0;
+   uint16_t score = 0;
+
+   uint8_t linesXCoordinates[4] = {0, 0, 0, 0};
+   uint8_t linesCount = 0;
+   bool isGameOver = false;
+   bool isTheEnd = false;
+   uint8_t previousSide = 0;
+   bool hasScoreChanged = false;
+   
+   uint8_t randomSideGenerator = 0;  // left - 0, right - 1
+   
+   WriteScore(score);
+
+   while (1) {
+      
+      if(isGameOver && numLives==1){
+         isTheEnd=true;
+         isGameOver=false;
+      }
+      
+      if (isGameOver)
+      {
+         numLives=numLives-1;
+         DisplayGameOverScreen(numLives);
+         
+         _delay(4000); // 18000
+         
+         for (uint8_t y = 0; y < fieldHeight; y++) 
+         {
+            for (uint8_t x = 0; x < fieldWidth; x++)
+            {
+               field[y * fieldWidth + x] = (y == 0 ||
+                              y >= fieldHeight - 7 ||
+                              x + 1 == fieldWidth / 2 ||
+                              x == fieldWidth / 2 ) ? 9u : 0u;
+            }
+         }
+         isGameOver=false;
+         WriteScore(score);
+      }
+      
+      if (isTheEnd)
+      {
+               DisplayTheEndScreen();
+            
+               while (!(buttons & BUTTON_CENTER))
+               {
+                  // Press center button to restart the game
+                  GetButtonStates();
+               }
+               
+               for (uint8_t y = 0; y < fieldHeight; y++) 
+               {
+                  for (uint8_t x = 0; x < fieldWidth; x++)
+                  {
+                     field[y * fieldWidth + x] = (y == 0 ||
+                                    y >= fieldHeight - 7 ||
+                                    x + 1 == fieldWidth / 2 ||
+                                    x == fieldWidth / 2 ) ? 9u : 0u;
+                  }
+               }
+               isTheEnd=false;
+
+               score=0;
+               speed=15;
+               
+               WriteScore(score);
+      }
+      delay--;
+            
+      GetButtonStates();
+      
+      if (buttons & BUTTON_UP)
+      {
+         upButton = true;
+         print("BUTTON_UP\n");
+      }  
+      if (buttons & BUTTON_DOWN)
+      {
+         downButton = true;         
+         print("BUTTON_DOWN\n");
+      }     
+      if (buttons & BUTTON_RIGHT)
+      {
+         rightButton = true;        
+         print("BUTTON_RIGHT\n");
+      }
+      if (buttons & BUTTON_LEFT) 
+      {
+         leftButton = true;         
+         print("BUTTON_LEFT\n");
+      }
+      if (buttons & BUTTON_CENTER)
+      {
+         centerButton = true;       
+         print("BUTTON_CENTER\n");
+      }
+      reg_gpio = 0x00000100 | buttons; // first 9 leds            
+         
+         
+      // Game Logic
+      if (delay == 0)
+      {  
+         delay = DELAY;       
+         gameTicksCount++;
+         movePiece = (gameTicksCount == speed);       
+
+
+         // Player input handling
+         if (!randomSideGenerator) // left part of the screen
+         {
+            pieceYCoordinate += (downButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate + 1)) ? 1 : 0;
+            pieceYCoordinate -= (upButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate - 1)) ? 1 : 0;
+            pieceXCoordinate += (rightButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate + 1, pieceYCoordinate)) ? 1 : 0;
+         }
+         else // right part of the screen
+         { 
+            pieceYCoordinate -= (upButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate - 1)) ? 1 : 0;
+            pieceYCoordinate += (downButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate + 1)) ? 1 : 0;
+            pieceXCoordinate -= (leftButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate - 1, pieceYCoordinate)) ? 1 : 0;
+         } 
+
+         if (centerButton)
+         {
+            pieceRotation += (rotationFlag && DoesPieceFit(pieceIndex, pieceRotation + 1, pieceXCoordinate, pieceYCoordinate)) ? 1 : 0;
+            rotationFlag = false;
+         }
+         else
+            rotationFlag = true;
+      
+         // Move the piece "down" the playfield if it's time
+         if (movePiece)
+         {
+            // Update difficulty every 50 pieces
+            gameTicksCount = 0;
+            pieceCount++;
+             if (pieceCount % 50 == 0)
+               if (speed >= 10) speed--; 
+
+            // Test if piece can be moved down
+            if (DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate + 1, pieceYCoordinate) && !randomSideGenerator)
+            {
+               pieceXCoordinate++;
+            }
+            else if (DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate - 1, pieceYCoordinate) && randomSideGenerator)
+            {
+               pieceXCoordinate--;
+            }
+            else
+            {
+               // Lock the piece in place
+               for (int x = 0; x < 4; x++)
+               {  
+                  for (int y = 0; y < 4; y++)
+                  {
+                     if (tetrominoes[pieceIndex][Rotate(x, y, pieceRotation)] != 0)
+                     {
+                        field[(pieceYCoordinate + y) * fieldWidth + (pieceXCoordinate + x)] = pieceIndex + 1;
+                     }
+                  }
+               }
+
+               // Check if any lines formed
+               for (int x = 0; x < 4; x++)
+               {
+                  bool bLine = true;
+                  for (int y = 1; y < fieldHeight - 7; y++)
+                  {
+                     if (field[(pieceXCoordinate + x) + fieldWidth * y] == 0 || field[(pieceXCoordinate + x) + fieldWidth * y] == 9u) 
+                     {
+                        bLine = false;
+                        break;
+                     }
+                  }
+
+                  if (bLine)
+                  {
+                     // Remove the line
+                     for (int y = 1; y < fieldHeight - 7; y++)
+                     {
+                        field[(pieceXCoordinate + x) + fieldWidth * y] = 0;
+                     }
+                     
+                     // Remember the coordinates of the removed line
+                     linesXCoordinates[linesCount] = pieceXCoordinate + x;
+                     linesCount++;
+                  }
+               }
+               previousSide = randomSideGenerator;
+
+               // Score handling
+               score += 1;
+               if (linesCount != 0) score += (1 << linesCount) * 20;
+               hasScoreChanged = true;
+               
+               // Generate new piece
+               pieceYCoordinate = generateRandomNumber(2,19);
+               // Generate new side
+               randomSideGenerator= generateRandomBinary();
+
+               if (!randomSideGenerator) 
+               {
+                  pieceRotation = 3;
+                  pieceXCoordinate = 0;
+               }
+               else 
+               {
+                  pieceRotation = 3;
+                  pieceXCoordinate = fieldWidth - 4;
+               }
+
+               pieceIndex = pieceCount % 7;
+
+               // Game is over if the piece doesn't fit at the beginning
+               isGameOver = !DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate);
+            }
+         }
+
+         // Rendering part
+         if (hasScoreChanged)
+         {
+            hasScoreChanged = false;
+            DisplayScore(score, 22, 24);
+         }
+
+         // Display the current field state
+          for (int y = 0; y < fieldHeight; y++) 
+          {
+            for (int x = 0; x < fieldWidth; x++) 
+            {
+               reg_video_map[y * fieldWidth + x] = field[y * fieldWidth + x];
+            }
+         }
+
+         // Display the current piece on the field
+         for (int x = 0; x < 4; x++)
+         {
+            for (int y = 0; y < 4; y++)
+            {
+               if (tetrominoes[pieceIndex][Rotate(x, y, pieceRotation)] != 0)
+               {
+                  reg_video_map[(pieceYCoordinate + y) * fieldWidth + (pieceXCoordinate + x)] = pieceIndex + 1; 
+               }
+            }
+          }    
+
+         // Handle the lines removal
+         if (linesCount != 0)
+         {
+            if (previousSide == 0)
+            {
+               for (uint8_t v = 0; v < linesCount; v++) 
+               {
+                  for (uint8_t x = linesXCoordinates[v]; x > 0; x--) 
+                  {
+                     for (uint8_t y = 1; y < fieldHeight - 7; y++)
+                     {
+                        field[x + fieldWidth * y] = field[x - 1 + fieldWidth * y];
+                     }
+                  }
+               }
+            } 
+            else
+            {
+               for (uint8_t v = linesCount; v > 0; v--)
+               {
+                  for (uint8_t x = linesXCoordinates[v - 1]; x < fieldWidth - 1; x++)
+                  {
+                     for (uint8_t y = 1; y < fieldHeight - 7; y++) 
+                     {
+                        field[x + fieldWidth * y] = field[x + 1 + fieldWidth * y];
+                     }
+                  }
+               }
+
+            }
+            
+            // clear the coordinates array
+            linesXCoordinates[0] = 0;
+            linesXCoordinates[1] = 0;
+            linesXCoordinates[2] = 0;
+            linesXCoordinates[3] = 0;
+            linesCount = 0;      
+         }
+
+         rightButton = false;
+         downButton = false;
+         centerButton = false;
+         upButton = false;
+         leftButton = false;     
+      }
+   }
+}
+

chili-chips-ba_openCologne/5.TetriSaraj/README.md

@@ -0,0 +1,94 @@
+# TetriSaraj on GateMate
+
+## Introduction
+
+This project is a demonstration of a complex digital hardware/software system. 
+
+The hardware consists of a custom SoC with RISC-V CPU and our special _Video Controller_ that operates with _Mega Characters (MC)_, which are a close kin to the infamous _"Sprites"_. 
+
+The software is bare-metal, w/o an OS, and implements a well-known, classic game, now rotated by 90 degrees and mirror-duplicated. 
+
+The whole thing is called _TetriSaraj_, and essentially a port:
+- from Digilent _Basys3_ (Artix7-35T) with openXC7 tools
+- to Olimex _GateMate1-EVB_ board with CologneChip tools.
+
+For the complete design detail (game logic, system block diagram, memory mapping etc.), please visit the original project repo: 
+- https://github.com/chili-chips-ba/openXC7-TetriSaraj
+
+## Surprise, surprise...
+
+Other than the expected changes related to constraints, pinouts, makefile etc., the operating clock frequency emerged as the main (and indeed unexpected) difference between these two designs.
+
+The original TetriSaraj ran on Artix-7 at `100MHz` w/o problems, even when built with openXC7 PNR, as opposed to Xilinx-proprietary Vivado. That was however far from possible on GateMate FPGA, where the `Fmax for the original design was 16MHz`, and for a reduced/optimized version barely reached 31 MHz, even at the highest VDD_CORE setting. 
+
+With VGA sub-system needing at least 25MHz, we decided to scale down the clock of the entire (already reduced) system to the `25MHz`. This then caused multiple timing issues in the video generation section (such as within _vga_controller.v_ and _top.v_), calling for significant timing-driven adaptations, in some instances even an overhaul. 
+
+## Hardware setup
+
+Since Olimex comes with only 1 user button, we had to plug-in _SimpleIO Extension Board_ that brings additional buttons. 
+
+The game needs 5 buttons:
+- 4 arrows for the direction of movement
+- plus 1 for the rotation.
+
+The complete setup is shown below:
+
+<img width=400 src="https://github.com/user-attachments/assets/ae35220d-a01d-4727-a8b0-39b207c47629">
+
+In addition to the _GateMateA1-EVB_, you will also need:
+- monitor with VGA port connected to it.
+- _SimpleIO Extension Board_ or, yet better, the new _**joyIO**_ card
+
+<img width=400 src="https://github.com/chili-chips-ba/openCologne/blob/main/0.doc/Intergalaktik/joyIO.png">
+
+## The Gameplay
+
+Our progam starts with a small, but full-custom Splash 😄:
+
+<img width=400 src="https://github.com/user-attachments/assets/62c2cd11-c261-4846-bbc2-cd59c46a0b8e">
+
+But, you start with three lives, that is three hearts:
+
+<img width=400 src="https://github.com/user-attachments/assets/b3558a6a-6a9b-4704-ad9c-fcdc21c5b5f6">
+
+As you're playin', you can earn more hearts, or lose them. 
+The more you earn, the harder we make it for you to play and win.
+
+<img width=400 src="https://github.com/user-attachments/assets/8e191741-83f5-4792-80df-5bba1fc767ef">
+
+Sorry, it's _"Game Over"_ when you lose your last heart.
+
+<img width=400 src="https://github.com/user-attachments/assets/cb28b561-fd35-4a46-918c-065b71d953db">
+
+Time to try again...
+
+<img width=400 src="https://github.com/user-attachments/assets/8e982547-ae1c-4c15-9c74-409e79cbc810">
+
+## Demo stream
+
+https://github.com/user-attachments/assets/12611cf4-5f7c-42ba-97fa-0026c773a5dd
+
+## How to build TetriSaraj for GateMate?!
+
+To synthesize and run the design locally, one must install the _CologneChip toolchain_ and adapt the _Makefile_. The whole process is explained in `3.build/Makefile`.
+
+## Our next play shall be audible
+
+Stay tuned for the arrival of stereo soundtrack to TetriSaraj play...
+
+## References
+1) Also available on [Xilinx Artix7](https://github.com/chili-chips-ba/openXC7-TetriSaraj) and [Gowin LittleBee](https://github.com/chili-chips-ba/openXC7-TetriSaraj/tree/main/99.more-boards/0.tang-nano-9k), thanks to [SymbioticEDA](https://www.symbioticeda.com) support
+
+2) Postings and mentions:
+> - [Dec.15, 2024](https://www.linkedin.com/feed/update/urn:li:activity:7273353028055769089?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7273353028055769089%2C7274166171325607936%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287274166171325607936%2Curn%3Ali%3Aactivity%3A7273353028055769089%29)
+> - [Oct.15, 2024](https://www.linkedin.com/posts/chili-chips_tetrisaraj-gatemate-opensource-activity-7252167674741301249-gOgI?utm_source=share&utm_medium=member_desktop)
+> - [Oct.11, 2024](https://www.linkedin.com/feed/update/urn:li:activity:7250565052359921665?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7250565052359921665%2C7250724417754836992%29&replyUrn=urn%3Ali%3Acomment%3A%28activity%3A7250565052359921665%2C7251814253668544513%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287250724417754836992%2Curn%3Ali%3Aactivity%3A7250565052359921665%29&dashReplyUrn=urn%3Ali%3Afsd_comment%3A%287251814253668544513%2Curn%3Ali%3Aactivity%3A7250565052359921665%29)
+> - [Oct.1, 2024](https://www.linkedin.com/feed/update/urn:li:ugcPost:7246625338787602434?commentUrn=urn%3Ali%3Acomment%3A%28ugcPost%3A7246625338787602434%2C7247337428045209600%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287247337428045209600%2Curn%3Ali%3AugcPost%3A7246625338787602434%29)
+> - [SarajevoMakerFaire 2024](https://sarajevo.makerfaire.com/maker/entry/143)
+> - [May 2023](https://www.linkedin.com/posts/chili-chips_fpga-education-riscv-activity-7076630631165689858-wgK_?utm_source=share&utm_medium=member_desktop)
+> - [April 2023](https://www.linkedin.com/posts/chili-chips_fpga-foss-yosys-activity-7069758169639505920-LRyG?utm_source=share&utm_medium=member_desktop)
+> - and more...
+
+<img width=500 src="0.doc/TetriSaraj-joyIO.png">
+
+#### End of Document

chili-chips-ba_openCologne/6.PCB.advanced/README.md

@@ -0,0 +1,59 @@
+# PCB2 - Advanced (ULX5M-GS)
+
+For more, please see:
+- [Extension_Boards_for_Olimex_GateMate repo](https://github.com/intergalaktik/ulx5m-gs)
+- [PCB Request Issues](https://github.com/chili-chips-ba/openCologne/issues?q=label%3A%22PCB+request%22+)
+
+### ---Conceptual Design---
+<p align="center">
+   <img width=500 src="0.doc/ulx5m.concept1.jpg">
+   <img width=500 src="0.doc/ulx5m.concept2.png">
+</p>
+
+### ---Version1 Design--- 
+
+#### V01 layout
+<p align="center">
+   <img width=800 src="0.doc/ulx5m-gs.v01.1.routed.png">
+</p>
+
+#### V01 manufactured PCB
+<p align="center">
+   <img width=800 src="0.doc/ulx5m-gs.v01.2.barePCB.jpg">
+</p>
+
+#### V01 bringup/debug 
+<p align="center">
+   <img width=800 src="0.doc/ulx5m-gs.v01.3.debug.jpg">
+</p>
+
+### ---Version2 Design---
+
+##### V02 draft for team review
+<p align="center">
+   <img width=500 src="0.doc/ulx5m-gs.v02.1.top.jpg">
+   <img width=500 src="0.doc/ulx5m-gs.v02.2.bottom.jpg">
+</p>
+
+##### V02 assembled prototype
+<p align="center">
+   <img width=800 src="0.doc/ulx5m-gs.v02.3.jpg">
+</p>
+
+#### V02 bringup/debug
+[![ULX5M blinks LEDs on its own](0.doc/ulx5m-gs.v02.4.debug.jpg)](https://www.youtube.com/watch?v=LA20pfW7X00 "ULX5M is counting!")
+
+
+#### V02 mounted on the CM4-BB3 carrier card
+<p align="center">
+   <img width=600 src="0.doc/ulx5m-gs.v02.5.with-CM4_BB3.jpg">
+   <img width=600 src="0.doc/ulx5m-gs.v02.6.with-CM4_BB3.HDMI.jpg">
+</p>
+
+#### V02 mounted on the CM4 "Piunora" carrier card
+<p align="center">
+   <img width=600 src="0.doc/ulx5m-gs.v02.7.with-CM4_Piunora.jpg">
+   <img width=600 src="0.doc/ulx5m-gs.v02.8.with-CM4_Piunora.HDMI.jpg">
+</p>
+
+#### End of Document

chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/README.md

@@ -0,0 +1,145 @@
+# SerDes App for GateMate
+
+## References
+- Measuring Eye Diagrams on [Rigol MSO5000](https://www.youtube.com/watch?si=vo3GYcDNML9LsX7S&v=JcJbcKl5llo&feature=youtu.be)
+  
+## Verifying board setup
+
+Using the provided serdestool we can verify that our board setup is functioning correctrly. We can run a loopback test ( `./sedestool --tcloopback `) :
+
+```
+    INFO:  Found 1 device in JTAG chain.
+    INFO:  Starting SerDes loopback testcases
+    
+    INFO:  Enabling TX PMA Loopback (Mode 0)
+    INFO:  Configuring SerDes ADPLL
+    INFO:  SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s
+    INFO:  Disabling SerDes ADPLL
+    INFO:  Writing SerDes ADPLL divider settings
+    INFO:  Stopping SerDes ADPLL self-calibration
+    INFO:  Starting SerDes ADPLL
+    INFO:  Starting SerDes ADPLL self-calibration
+    INFO:  SerDes ADPLL locked
+    INFO:  PFDAC result: max reached: 0, ac_result:  98320, CP:  3
+    INFO:  ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT:  708 SY:   0 ST: 2
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 32-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 16-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 8-Bit comma alignment
+    
+    INFO:  Enabling TX PMA Loopback (Mode 1)
+    INFO:  Configuring SerDes ADPLL
+    INFO:  SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s
+    INFO:  Disabling SerDes ADPLL
+    INFO:  Writing SerDes ADPLL divider settings
+    INFO:  Stopping SerDes ADPLL self-calibration
+    INFO:  Starting SerDes ADPLL
+    INFO:  Starting SerDes ADPLL self-calibration
+    INFO:  SerDes ADPLL locked
+    INFO:  PFDAC result: max reached: 0, ac_result:     16, CP:  6
+    INFO:  ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT:  706 SY:   0 ST: 2
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 32-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 16-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 8-Bit comma alignment
+    
+    INFO:  Enabling TX PCS Loopback
+    INFO:  Configuring SerDes ADPLL
+    INFO:  SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s
+    INFO:  Disabling SerDes ADPLL
+    INFO:  Writing SerDes ADPLL divider settings
+    INFO:  Stopping SerDes ADPLL self-calibration
+    INFO:  Starting SerDes ADPLL
+    INFO:  Starting SerDes ADPLL self-calibration
+    INFO:  SerDes ADPLL locked
+    INFO:  PFDAC result: max reached: 0, ac_result:  98330, CP: 25
+    INFO:  ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT:  707 SY:   0 ST: 2
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 32-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 16-Bit comma alignment
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Sending data (this might take a while) ...
+    INFO:  Checking 8-Bit comma alignment
+
+``` 
+as well as a PRBS test (`./serdestool --tcprbs`):
+
+
+```
+    INFO:  Found 1 device in JTAG chain.
+    INFO:  Starting SerDes PRBS testcases
+    INFO:  Configuring SerDes ADPLL
+    INFO:  SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s
+    INFO:  Disabling SerDes ADPLL
+    INFO:  Writing SerDes ADPLL divider settings
+    INFO:  Stopping SerDes ADPLL self-calibration
+    INFO:  Starting SerDes ADPLL
+    INFO:  Starting SerDes ADPLL self-calibration
+    INFO:  SerDes ADPLL locked
+    INFO:  PFDAC result: max reached: 0, ac_result:     19, CP: 28
+    INFO:  ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT:  708 SY:   0 ST: 2
+    INFO:  Resetting SerDes TX
+    INFO:  Resetting SerDes RX
+    INFO:  Setting up PRBS-7
+    INFO:  Sending data (this might take a while) ...
+    INFO:  0/10
+    INFO:  1/10
+    INFO:  2/10
+    INFO:  3/10
+    INFO:  4/10
+    INFO:  5/10
+    INFO:  6/10
+    INFO:  7/10
+    INFO:  8/10
+    INFO:  9/10
+    INFO:  RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 0
+    INFO:  Starting error injection
+    INFO:  RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 6
+    INFO:  Setting up PRBS-15
+    INFO:  Sending data (this might take a while) ...
+    INFO:  0/10
+    INFO:  1/10
+    INFO:  2/10
+    INFO:  3/10
+    INFO:  4/10
+    INFO:  5/10
+    INFO:  6/10
+    INFO:  7/10
+    INFO:  8/10
+    INFO:  9/10
+    INFO:  RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 0
+    INFO:  Starting error injection
+    INFO:  RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 7
+```
+
+P and N signals of the TX and RX channel are connected as in the following image:
+
+<p align="center" width="100%">
+    <img width="50%" src="../0.doc/SerDes-Loopback.jpg">
+</p>
+
+
+
+### End of Document

chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdes_lb.v

@@ -0,0 +1,473 @@
+`timescale 1ns / 1ps
+
+
+// #  serdestool -- GateMate FPGA SerDes Toolkit
+// #
+// #  Permission to use, copy, modify, and/or distribute this software for any
+// #  purpose with or without fee is hereby granted, provided that the above
+// #  copyright notice and this permission notice appear in all copies.
+// #
+// #  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// #  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// #  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// #  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// #  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// #  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// #  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+// #
+// #  Visit https://colognechip.com for more information.
+// #
+// #  Copyright (C) 2022 - 2025 Cologne Chip AG <support@colognechip.com>
+// #  Authors: Patrick Urban
+
+module serdes_lb (
+    input pll_rstn_i,
+    input trx_rstn_i,
+    input ref_clk,
+
+    input RX_PRBS_CNT_RESET_I,
+    input TX_PRBS_FORCE_ERR_I,
+
+    output [63:0] RX_DATA_O,
+    output PLL_CLK_O,
+    output RX_CLK_O,
+
+    output RX_RESET_DONE_O_N, TX_RESET_DONE_O_N,
+    output TX_DETECT_RX_PRESENT_O_N, TX_DETECT_RX_DONE_O_N,
+    output TX_BUF_ERR_O_N, RX_BUF_ERR_O_N,
+    output RX_PRBS_ERR_O_N
+);
+
+    wire RX_COMMA_DETECT_EN_I = 1'b1;
+
+    // reset
+    reg [8:0] rst_cnt = 0;
+    wire rstn = &rst_cnt;
+    wire rst = !rstn;
+
+    always @(posedge ref_clk) begin
+        rst_cnt <= rst_cnt + !rstn;
+    end
+
+    wire trx_rst_i = ~trx_rstn_i | rst;
+    wire pll_rst_i = ~pll_rstn_i | rst;
+
+    wire CLK_CORE_PLL_O_N;
+
+    wire TX_RESET_DONE_O;
+    wire RX_RESET_DONE_O;
+    assign TX_RESET_DONE_O_N = ~TX_RESET_DONE_O;
+    assign RX_RESET_DONE_O_N = ~RX_RESET_DONE_O;
+
+    wire TX_DETECT_RX_PRESENT_O;
+    wire TX_DETECT_RX_DONE_O;
+    assign TX_DETECT_RX_PRESENT_O_N = ~TX_DETECT_RX_PRESENT_O;
+    assign TX_DETECT_RX_DONE_O_N = ~TX_DETECT_RX_DONE_O;
+
+    wire RX_PRBS_ERR_O;
+    assign RX_PRBS_ERR_O_N = ~RX_PRBS_ERR_O;
+
+    wire TX_BUF_ERR_O;
+    wire RX_BUF_ERR_O;
+    assign TX_BUF_ERR_O_N  = ~TX_BUF_ERR_O;
+    assign RX_BUF_ERR_O_N  = ~RX_BUF_ERR_O;
+
+    wire [63:0] RX_DATA_O;
+
+    wire RX_EI_EN_O, REGFILE_RDY_O, CLK_CORE_RX_O;
+    wire [7:0]  RX_CHAR_IS_K_O, RX_CHAR_IS_COMMA_O, RX_NOT_IN_TABLE_O;
+    wire [15:0] REGFILE_DO_O;
+
+    // 8b/10b control bytes
+    parameter [27:0] kChar =
+        //{8'hxx, 10'h000, 10'h000}; // K28_5
+        //{8'h1C, 10'h303, 10'h0FC}; // K28_0
+        //{8'h3C, 10'h343, 10'h1FC}; // K28_1
+        //{8'h5C, 10'h383, 10'h27C}; // K28_2
+        //{8'h7C, 10'h3C3, 10'h2FC}; // K28_3
+        //{8'h9C, 10'h443, 10'h37C}; // K28_4
+        {8'hBC, 10'h283, 10'h17C}; // K28_5
+        //{8'hDC, 10'h4C3, 10'h3FC}; // K28_6
+        //{8'hFC, 10'h503, 10'h47C}; // K28_7
+        //{8'hFB, 10'h11C, 10'h38C}; // K27_7
+        //{8'hFD, 10'h11C, 10'h38C}; // K29_7
+        //{8'hFE, 10'h11C, 10'h38C}; // K30_7
+
+    // ADPLL clock settings
+    parameter N1 = 1; // 1/2
+    parameter N2 = 2; // 2/3/4/5
+    parameter N3 = 3; // 3/4/5
+    parameter OUTDIV = 4; // 1/2/4
+
+    parameter DATAPATH = 80; // 80, 40, 20
+
+    parameter ENABLE_8B10B = 1'b1;
+    parameter ENABLE_COMMADETECT = 1'b1;
+
+    parameter [2:0] PRBS_SEL =
+        3'b000; // PRBS checker disabled
+        //3'b001; // PRBS-7
+        //3'b010; // PRBS-15
+        //3'b011; // PRBS-23
+        //3'b100; // PRBS-31
+        //3'b101; // RESERVED
+        //3'b110; // 2 UI square wave (TX ONLY)
+        //3'b111; // 20/40/80 UI square wave, depending on data path width (TX ONLY)
+
+    parameter [2:0] LOOPBACK_SEL =
+        3'b000; // normal operation
+        //3'b001; // near-end PCS Loopback
+        //3'b010; // near-end PMA Loopback
+        //3'b011; // reserved
+        //3'b100; // far-end PMA Loopback
+        //3'b101; // reserved
+        //3'b110; // far-end PCS Loopback
+        //3'b111; // reserved
+
+    parameter [1:0] TX_PMA_LOOPBACK =
+        2'b00; // disabled
+        //2'b01; // loopback from TX driver
+        //2'b10; // loopback from TX pads
+
+    parameter [1:0] DATAPATH_SEL = {
+        (DATAPATH == 80) ? 2'b11 : (DATAPATH == 40) ? 2'b01 : (DATAPATH == 20) ? 2'b00 : 2'bx
+    }; // default: 2'h3
+
+    parameter [5:0] PLL_FCNTRL = {
+        DATAPATH == 80 ? 6'h3A : (DATAPATH == 40 ? 6'h3A : (DATAPATH == 20 ? 6'd26 : 6'bx))
+    }; // default: 6'h3A = 58 ^= 20;
+
+    parameter [5:0] PLL_MAIN_DIVSEL = {
+        1'b0, // PLL_MAINDIV[5]: not used
+        N3 == 3 ? 2'b00 : (N3 == 4 ? 2'b10 : (N3 == 5 ? 2'b11 : 2'bx)),
+        N1 == 1 ? 1'b0  : (N1 == 2 ? 1'b1  : 1'bx),
+        N2 == 3 ? 2'b00 : (N2 == 2 ? 2'b01 : (N2 == 4 ? 2'b10 : (N2 == 5 ? 2'b11 : 2'bx)))
+    }; // default: 6'h1B;
+
+    parameter [1:0] PLL_OUT_DIVSEL = {
+        OUTDIV == 1 ? 2'b00 : OUTDIV == 2 ? 2'b01 : OUTDIV == 4 ? 2'b11 : 2'bx
+    }; // default: 2'h0;
+
+    parameter [14:0] RX_EYE_MEAS_CFG = {11'b0, 3'b0};
+
+    parameter K_POS = 0;
+
+    function [63:0] calcTxData(input integer pos, input comma);
+    begin
+        if (comma == 1'b1) begin
+            calcTxData =
+                (pos == 0) ? 64'h4A4A4A4A_4A4A4ABC :
+                (pos == 1) ? 64'h4A4A4A4A_4A4ABC4A :
+                (pos == 2) ? 64'h4A4A4A4A_4ABC4A4A :
+                (pos == 3) ? 64'h4A4A4A4A_BC4A4A4A :
+                (pos == 4) ? 64'h4A4A4ABC_4A4A4A4A :
+                (pos == 5) ? 64'h4A4ABC4A_4A4A4A4A :
+                (pos == 6) ? 64'h4ABC4A4A_4A4A4A4A : 64'hBC4A4A4A_4A4A4A4A;
+        end
+        else begin
+            calcTxData =
+                (pos == 0) ? 64'h08070605_04030201 :
+                (pos == 1) ? 64'h07060504_03020108 :
+                (pos == 2) ? 64'h06050403_02010807 :
+                (pos == 3) ? 64'h05040302_01080706 :
+                (pos == 4) ? 64'h04030201_08070605 :
+                (pos == 5) ? 64'h03020108_07060504 :
+                (pos == 6) ? 64'h02010807_06050403 : 64'h01080706_05040302;
+        end
+    end
+    endfunction
+
+    function [7:0] calcTxK(input integer pos, input comma);
+    begin
+        if (comma == 1'b1) begin
+            calcTxK =
+                (comma_pos == 0) ? 8'b0000_0001 :
+                (comma_pos == 1) ? 8'b0000_0010 :
+                (comma_pos == 2) ? 8'b0000_0100 :
+                (comma_pos == 3) ? 8'b0000_1000 :
+                (comma_pos == 4) ? 8'b0001_0000 :
+                (comma_pos == 5) ? 8'b0010_0000 :
+                (comma_pos == 6) ? 8'b0100_0000 : 8'b1000_0000;
+        end
+        else begin
+            calcTxK = 8'b0000_0000;
+        end
+    end
+    endfunction
+
+
+// CC_SERDES instance generator
+// generated: 2024-01-31 13:57:01
+
+CC_SERDES #(
+    .RX_BUF_RESET_TIME(5'h3),
+    .RX_PCS_RESET_TIME(5'h3),
+    .RX_RESET_TIMER_PRESC(5'h0),
+    .RX_RESET_DONE_GATE(1'h0),
+    .RX_CDR_RESET_TIME(5'h3),
+    .RX_EQA_RESET_TIME(5'h3),
+    .RX_PMA_RESET_TIME(5'h3),
+    .RX_WAIT_CDR_LOCK(1'b0), // turn off if loopback enabled
+    .RX_CALIB_EN(1'h1),
+    .RX_CALIB_OVR(1'h0),
+    .RX_CALIB_VAL(4'h0),
+    .RX_RTERM_VCMSEL(3'h4),
+    .RX_RTERM_PD(1'h0),
+    .RX_EQA_CKP_LF(8'hA3),
+    .RX_EQA_CKP_HF(8'hA3),
+    .RX_EQA_CKP_OFFSET(8'h01),
+    .RX_EN_EQA(1'h0),
+    .RX_EQA_LOCK_CFG(4'h0),
+    .RX_TH_MON1(5'h8),
+    .RX_EN_EQA_EXT_VALUE(4'h0),
+    .RX_TH_MON2(5'h8),
+    .RX_TAPW(5'h8),
+    .RX_AFE_OFFSET(5'h8),
+    .RX_EQA_CONFIG(16'h1C0),
+    .RX_AFE_PEAK(5'hF),
+    .RX_AFE_GAIN(4'h8),
+    .RX_AFE_VCMSEL(3'h4),
+    .RX_CDR_CKP(8'hF8),
+    .RX_CDR_CKI(8'h00),
+    .RX_CDR_TRANS_TH(9'h80), // h15?
+    .RX_CDR_LOCK_CFG(6'hB),
+    .RX_CDR_FREQ_ACC(15'h0),
+    .RX_CDR_PHASE_ACC(16'h0000),
+    .RX_CDR_SET_ACC_CONFIG(2'h0),
+    .RX_CDR_FORCE_LOCK(1'h0),
+    .RX_ALIGN_MCOMMA_VALUE(kChar[19:10]),
+    .RX_MCOMMA_ALIGN_OVR(1'h0),
+    .RX_MCOMMA_ALIGN(1'h0),
+    .RX_ALIGN_PCOMMA_VALUE(kChar[9:0]),
+    .RX_PCOMMA_ALIGN_OVR(1'h0),
+    .RX_PCOMMA_ALIGN(1'h0),
+    .RX_ALIGN_COMMA_WORD(2'h3), // 11: 32 bit, 01: 16 bit, 00: 8 bit
+    .RX_ALIGN_COMMA_ENABLE(10'h3FF),
+    .RX_SLIDE_MODE(2'b00), // !!!
+    .RX_COMMA_DETECT_EN_OVR(1'h0),
+    .RX_COMMA_DETECT_EN(1'h0),
+    .RX_SLIDE(2'h0),
+    .RX_EYE_MEAS_EN(1'h0),
+    .RX_EYE_MEAS_CFG(RX_EYE_MEAS_CFG),
+    .RX_MON_PH_OFFSET(6'h0),
+    .RX_EI_BIAS(4'h4),
+    .RX_EI_BW_SEL(4'h4),
+    .RX_EN_EI_DETECTOR_OVR(1'h0),
+    .RX_EN_EI_DETECTOR(1'h0),
+    .RX_DATA_SEL(1'h0),
+    .RX_BUF_BYPASS(1'h0),
+    .RX_CLKCOR_USE(1'h0),
+    .RX_CLKCOR_MIN_LAT(6'h20),
+    .RX_CLKCOR_MAX_LAT(6'h27),
+    .RX_CLKCOR_SEQ_1_0(10'h1F7),
+    .RX_CLKCOR_SEQ_1_1(10'h1F7),
+    .RX_CLKCOR_SEQ_1_2(10'h1F7),
+    .RX_CLKCOR_SEQ_1_3(10'h1F7),
+    .RX_PMA_LOOPBACK(1'h0),
+    .RX_PCS_LOOPBACK(1'h0),
+    .RX_DATAPATH_SEL(DATAPATH_SEL),
+    .RX_PRBS_OVR(1'b0),
+    .RX_PRBS_SEL(PRBS_SEL),
+    .RX_LOOPBACK_OVR(1'h0),
+    .RX_PRBS_CNT_RESET(1'h0),
+    .RX_POWER_DOWN_OVR(1'h0),
+    .RX_POWER_DOWN_N(1'h1),
+    .RX_RESET_OVR(1'h0),
+    .RX_RESET(1'h0),
+    .RX_PMA_RESET_OVR(1'h0),
+    .RX_PMA_RESET(1'h0),
+    .RX_EQA_RESET_OVR(1'h0),
+    .RX_EQA_RESET(1'h0),
+    .RX_CDR_RESET_OVR(1'h0),
+    .RX_CDR_RESET(1'h0),
+    .RX_PCS_RESET_OVR(1'h0),
+    .RX_PCS_RESET(1'h0),
+    .RX_BUF_RESET_OVR(1'h0),
+    .RX_BUF_RESET(1'h0),
+    .RX_POLARITY_OVR(1'h0),
+    .RX_POLARITY(1'h0),
+    .RX_8B10B_EN_OVR(1'h0),
+    .RX_8B10B_EN(1'h0),
+    .RX_8B10B_BYPASS(8'h0),
+    .RX_BYTE_REALIGN(1'h0),
+    .TX_SEL_PRE(5'h0),
+    .TX_SEL_POST(5'h0),
+    .TX_AMP(5'hF),
+    .TX_BRANCH_EN_PRE(5'h0),
+    .TX_BRANCH_EN_MAIN(6'h3F),
+    .TX_BRANCH_EN_POST(5'h0),
+    .TX_TAIL_CASCODE(3'h4),
+    .TX_DC_ENABLE(7'h3F),
+    .TX_DC_OFFSET(5'h8), // ? note: set to 8
+    .TX_CM_RAISE(5'h0),
+    .TX_CM_THRESHOLD_0(5'hE),
+    .TX_CM_THRESHOLD_1(5'h10),
+    .TX_SEL_PRE_EI(5'h0),
+    .TX_SEL_POST_EI(5'h0),
+    .TX_AMP_EI(5'hF),
+    .TX_BRANCH_EN_PRE_EI(5'h0),
+    .TX_BRANCH_EN_MAIN_EI(6'h3F),
+    .TX_BRANCH_EN_POST_EI(5'h0),
+    .TX_TAIL_CASCODE_EI(3'h4),
+    .TX_DC_ENABLE_EI(7'h3F),
+    .TX_DC_OFFSET_EI(5'h0),
+    .TX_CM_RAISE_EI(5'h0),
+    .TX_CM_THRESHOLD_0_EI(5'hE),
+    .TX_CM_THRESHOLD_1_EI(5'h10),
+    .TX_SEL_PRE_RXDET(5'h0),
+    .TX_SEL_POST_RXDET(5'h0),
+    .TX_AMP_RXDET(5'hF),
+    .TX_BRANCH_EN_PRE_RXDET(5'h0),
+    .TX_BRANCH_EN_MAIN_RXDET(6'h3F),
+    .TX_BRANCH_EN_POST_RXDET(5'h0),
+    .TX_TAIL_CASCODE_RXDET(3'h4),
+    .TX_DC_ENABLE_RXDET(7'h3F),
+    .TX_DC_OFFSET_RXDET(5'h0),
+    .TX_CM_RAISE_RXDET(5'h0),
+    .TX_CM_THRESHOLD_0_RXDET(5'hE),
+    .TX_CM_THRESHOLD_1_RXDET(5'h10),
+    .TX_CALIB_EN(1'h0),
+    .TX_CALIB_OVR(1'h0),
+    .TX_CALIB_VAL(4'h0),
+    .TX_CM_REG_KI(8'h80),
+    .TX_CM_SAR_EN(1'h0),
+    .TX_CM_REG_EN(1'h1),
+    .TX_PMA_RESET_TIME(5'h3),
+    .TX_PCS_RESET_TIME(5'h3),
+    .TX_PCS_RESET_OVR(1'h0),
+    .TX_PCS_RESET(1'h0),
+    .TX_PMA_RESET_OVR(1'h0),
+    .TX_PMA_RESET(1'h0),
+    .TX_RESET_OVR(1'h0),
+    .TX_RESET(1'h0),
+    .TX_PMA_LOOPBACK(TX_PMA_LOOPBACK),
+    .TX_PCS_LOOPBACK(1'h0),
+    .TX_DATAPATH_SEL(DATAPATH_SEL),
+    .TX_PRBS_OVR(1'b0),
+    .TX_PRBS_SEL(PRBS_SEL),
+    .TX_PRBS_FORCE_ERR(1'h0),
+    .TX_LOOPBACK_OVR(1'h0),
+    .TX_POWER_DOWN_OVR(1'h0),
+    .TX_POWER_DOWN_N(1'h1),
+    .TX_ELEC_IDLE_OVR(1'h0),
+    .TX_ELEC_IDLE(1'h0),
+    .TX_DETECT_RX_OVR(1'h0),
+    .TX_DETECT_RX(1'h0),
+    .TX_POLARITY_OVR(1'h0),
+    .TX_POLARITY(1'h0),
+    .TX_8B10B_EN_OVR(1'h0),
+    .TX_8B10B_EN(1'h0),
+    .TX_DATA_OVR(1'h0),
+    .TX_DATA_CNT(3'h0),
+    .TX_DATA_VALID(1'h0),
+    .PLL_EN_ADPLL_CTRL(1'h1),
+    .PLL_CONFIG_SEL(1'h1), // 0: internal, 1: regfile
+    .PLL_SET_OP_LOCK(1'h0),
+    .PLL_ENFORCE_LOCK(1'h0),
+    .PLL_DISABLE_LOCK(1'h0),
+    .PLL_LOCK_WINDOW(1'h1), // 0: long, 1: short
+    .PLL_FAST_LOCK(1'h1),
+    .PLL_SYNC_BYPASS(1'h0),
+    .PLL_PFD_SELECT(1'h0),
+    .PLL_REF_BYPASS(1'h0),
+    .PLL_REF_SEL(1'h1), // 0: single-ended, 1: lvds
+    .PLL_REF_RTERM(1'h1),
+    .PLL_FCNTRL(PLL_FCNTRL),
+    .PLL_MAIN_DIVSEL(PLL_MAIN_DIVSEL),
+    .PLL_OUT_DIVSEL(PLL_OUT_DIVSEL),
+    .PLL_CI(5'h3),
+    .PLL_CP(10'h50),
+    .PLL_AO(4'h0),
+    .PLL_SCAP(3'h0),
+    .PLL_FILTER_SHIFT(2'h2),
+    .PLL_SAR_LIMIT(3'h2),
+    .PLL_FT(11'h200),
+    .PLL_OPEN_LOOP(1'h0),
+    .PLL_SCAP_AUTO_CAL(1'h1),
+    .PLL_BISC_MODE(3'h5), // MODE B, enable
+    .PLL_BISC_TIMER_MAX(4'hC),
+    .PLL_BISC_OPT_DET_IND(1'h0),
+    .PLL_BISC_PFD_SEL(1'h0),
+    .PLL_BISC_DLY_DIR(1'h0),
+    .PLL_BISC_COR_DLY(3'h1),
+    .PLL_BISC_CAL_SIGN(1'h1),
+    .PLL_BISC_CAL_AUTO(1'h1),
+    .PLL_BISC_CP_MIN(5'h6),
+    .PLL_BISC_CP_MAX(5'h1E),
+    .PLL_BISC_CP_START(5'h6),
+    .PLL_BISC_DLY_PFD_MON_REF(5'h0),
+    .PLL_BISC_DLY_PFD_MON_DIV(5'h2),
+    .SERDES_ENABLE(1'h1),
+    .SERDES_AUTO_INIT(1'h0),
+    .SERDES_TESTMODE(1'h1)
+) i_cc_serdes (
+    // ADPLL
+    .RX_CLK_O(RX_CLK_O), // CDR CLK
+    .PLL_CLK_O(PLL_CLK_O),
+    // LOPPBACK
+    .LOOPBACK_I(LOOPBACK_SEL),
+    // RESET
+    .TX_RESET_I(trx_rst_i),
+    .RX_RESET_I(trx_rst_i),
+    .RX_PMA_RESET_I(1'b0),
+    .RX_EQA_RESET_I(1'b0),
+    .RX_CDR_RESET_I(1'b0),
+    .RX_PCS_RESET_I(1'b0),
+    .RX_BUF_RESET_I(1'b0),
+    .TX_PCS_RESET_I(1'b0),
+    .TX_PMA_RESET_I(1'b0),
+    .PLL_RESET_I(pll_rst_i),
+    .TX_RESET_DONE_O(TX_RESET_DONE_O),
+    .RX_RESET_DONE_O(RX_RESET_DONE_O),
+    // TX
+    .TX_CLK_I(PLL_CLK_O),
+    .TX_DATA_I(calcTxData(K_POS, 1'b1)),
+    .TX_POWER_DOWN_N_I(1'h1),
+    .TX_POLARITY_I(1'h0),
+    .TX_PRBS_SEL_I(PRBS_SEL),
+    .TX_PRBS_FORCE_ERR_I(TX_PRBS_FORCE_ERR_I),
+    .TX_8B10B_EN_I(ENABLE_8B10B),
+    .TX_8B10B_BYPASS_I(8'h0),
+    .TX_CHAR_IS_K_I(calcTxK(K_POS, RX_COMMA_DETECT_EN_I)),
+    .TX_CHAR_DISPMODE_I(8'h0),
+    .TX_CHAR_DISPVAL_I(8'h0),
+    .TX_ELEC_IDLE_I(1'h0),
+    .TX_DETECT_RX_I(1'b1),
+    .TX_BUF_ERR_O(TX_BUF_ERR_O),
+    // RX
+    .RX_CLK_I(RX_CLK_O),
+    .RX_POWER_DOWN_N_I(1'h1),
+    .RX_POLARITY_I(1'h0),
+    .RX_PRBS_SEL_I(PRBS_SEL),
+    .RX_PRBS_CNT_RESET_I(RX_PRBS_CNT_RESET_I),
+    .RX_PRBS_ERR_O(RX_PRBS_ERR_O),
+    .RX_8B10B_EN_I(ENABLE_8B10B),
+    .RX_8B10B_BYPASS_I(8'h0),
+    .RX_EN_EI_DETECTOR_I(1'h0),
+    .RX_COMMA_DETECT_EN_I(RX_COMMA_DETECT_EN_I),
+    .RX_SLIDE_I(1'h0),
+    .RX_MCOMMA_ALIGN_I(RX_COMMA_DETECT_EN_I),
+    .RX_PCOMMA_ALIGN_I(RX_COMMA_DETECT_EN_I),
+    .RX_DATA_O(RX_DATA_O),
+    .RX_NOT_IN_TABLE_O(),
+    .RX_CHAR_IS_COMMA_O(),
+    .RX_CHAR_IS_K_O(),
+    .RX_DISP_ERR_O(),
+    .TX_DETECT_RX_DONE_O(TX_DETECT_RX_DONE_O),
+    .TX_DETECT_RX_PRESENT_O(TX_DETECT_RX_PRESENT_O),
+    .RX_BUF_ERR_O(RX_BUF_ERR_O),
+    .RX_BYTE_IS_ALIGNED_O(),
+    .RX_BYTE_REALIGN_O(),
+    .RX_EI_EN_O(),
+    // REGFILE
+    .REGFILE_CLK_I(1'h0),
+    .REGFILE_WE_I(1'h0),
+    .REGFILE_EN_I(1'h0),
+    .REGFILE_ADDR_I(8'h0),
+    .REGFILE_DI_I(16'h0),
+    .REGFILE_MASK_I(16'h0),
+    .REGFILE_DO_O(REGFILE_DO_O),
+    .REGFILE_RDY_O(REGFILE_RDY_O)
+);
+
+endmodule

chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdestool.py

@@ -0,0 +1,1584 @@
+#!/usr/bin/env python3
+#
+#  serdestool -- GateMate FPGA SerDes Toolkit
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+#  Visit https://colognechip.com for more information.
+#
+#  Copyright (C) 2022 - 2025 Cologne Chip AG <support@colognechip.com>
+#  Authors: Patrick Urban
+#
+
+import re
+import sys
+import math
+import curses
+import random
+import signal
+import argparse
+import datetime
+import threading
+
+from time import sleep
+from itertools import chain
+
+from pyftdi.ftdi import Ftdi
+from pyftdi.jtag import JtagEngine
+from pyftdi.usbtools import UsbTools
+from pyftdi.bits import BitSequence
+
+Boards_e = ['auto', 'pgm', 'evb']
+ArgEpilog = 'example usage: python3 serdestool.py'
+
+SER_CLK_PERIOD_NS = 10.0
+
+class bcolors:
+    OK    = '\033[92m' # GREEN
+    WARN  = '\033[93m' # YELLOW
+    FAIL  = '\033[91m' # RED
+    OVR   = '\033[94m' # BLUE
+    RESET = '\033[0m'  # RESET COLOR
+
+def ArgHzRegex(value, pat=re.compile(r"^[0-9]+[kM]")):
+    if not pat.match(value):
+        raise argparse.ArgumentTypeError
+    return value
+
+def ArgHzParse(value) -> int:
+    freq = 0
+    if value.endswith('k'):
+        freq = int(value[:-1]) * 1e3
+    elif value.endswith('M'):
+        freq = int(value[:-1]) * 1e6
+    else:
+        freq = int(value)
+    return freq
+
+def FindAndFormatFtdiAddr(idx=0) -> str:
+    ftdiname = {
+        0x6010: '2232h',
+        0x6014: '232h'
+    }
+    usb = UsbTools()
+    vps_lst = list()
+    vps_lst.append((0x0403, 0x6010)) # evb: FT2232H
+    vps_lst.append((0x0403, 0x6014)) # pgm: FT232H
+    d = usb.find_all(vps=vps_lst)
+    if not d:
+        raise Exception('Error: No FTDI device found.')
+    d = d[idx][0]
+    return f'ftdi://ftdi:{ftdiname[d[1]]}/1'
+
+class ColorFormatter:
+    pos_cond = ["DONE", "PRESENT", "LOCKED", "IS_ALIGNED", "EN_ADPLL_CTRL", "CONFIG_SEL", "SERDES_ENABLE"]
+    neg_cond = ["ERR", "DOWN", "TESTMODE"]
+    ovr_cond = ["OVR"]
+
+    @staticmethod
+    def get_color_pair(key, value):
+        """Returns the curses color pair based on the value conditions."""
+        try:
+            value = int(value)  # Convert safely to integer
+        except ValueError:
+            return 0  # Default color if conversion fails
+
+        if any(cond in key for cond in ColorFormatter.pos_cond):
+            return 1 if value != 0 else 2  # Green for positive, Yellow for zero
+        elif any(cond in key for cond in ColorFormatter.neg_cond) and not any(cond in key for cond in ColorFormatter.ovr_cond):
+            return 3 if (value < 1 if key.endswith('_N') else value > 0) else 0  # Red for errors
+        elif any(cond in key for cond in ColorFormatter.ovr_cond) and value > 0:
+            return 4  # Blue for "OVR" values
+        return 0  # Default
+
+class JtagTool:
+    CMD_JTAG_ID                = '000000' # 0x00
+    CMD_JTAG_BYPASS            = '111111' # 0x3F
+    CMD_JTAG_CONFIGURE         = '000110' # 0x06
+    CMD_JTAG_WR_SERDES_REGFILE = '100101' # 0x25
+    CMD_JTAG_RD_SERDES_REGFILE = '100110' # 0x26
+
+    CMD_JTAG_STATUS_PLL0       = '011100' # 0x1C
+    CMD_JTAG_STATUS_PLL1       = '011101' # 0x1D
+    CMD_JTAG_STATUS_PLL2       = '011110' # 0x1E
+    CMD_JTAG_STATUS_PLL3       = '011111' # 0x1F
+
+    _chain_idx = 0
+    _taps_before = 0
+
+    def __init__(self, engine):
+        self._engine = engine
+        self._chain_idx = args.idx
+        self.idcode()
+
+    def write_ir(self, instruction) -> None:
+        byp_before = BitSequence('1'*6*self._taps_before, msb=True)
+        byp_after = BitSequence('1'*6*self._chain_idx, msb=True)
+        self._engine.write_ir(byp_before+instruction+byp_after)
+
+    def write_dr(self, data) -> None:
+        byp_before = BitSequence('0'*self._taps_before, msb=True)
+        byp_after = BitSequence('0'*self._chain_idx, msb=True)
+        self._engine.write_dr(byp_after+data+byp_before)
+
+    def read_dr(self, length: int) -> BitSequence:
+        word = self._engine.read_dr(length+self._taps_before)
+        if self._chain_idx > 0:
+            return word[self._taps_before:-self._chain_idx]
+        else:
+            return word[self._taps_before:]
+
+    def get_chunk(self, data, start, length):
+        return (data >> start) & ((1 << length) - 1)
+
+    # Read the IDCODE right after JTAG reset
+    def idcode(self) -> int:
+        idcodes = self._engine.read_dr(128)
+        self._engine.go_idle()
+        chain_len = 0
+        for i in range(0, 128, 32):
+            chunk_data = self.get_chunk(int(idcodes), i, 32)
+            if chunk_data != 0:
+                chain_len += 1
+        print(f'INFO:  Found {chain_len} device{"s" if chain_len > 1 else ""} in JTAG chain.')
+        self._taps_before = chain_len - self._chain_idx - 1
+        return chain_len
+
+    # Read the IDCODE using CMD_JTAG_ID
+    def idcode_seq(self) -> int:
+        self.write_ir(BitSequence(self.CMD_JTAG_ID, msb=True))
+        status = self.read_dr(32)
+        self._engine.go_idle()
+        return int(status)
+
+    # Configure FPGA using CMD_JTAG_CONFIGURE
+    def wr_cfg(self, cfg_data):
+        a = []
+        b = bytearray(cfg_data)
+
+        for i in range(len(b)):
+            a.append(int(b[i]))
+
+        seq = BitSequence(bytes_=a[:-1], length=len(b)*8, msb=False, msby=True)
+
+        self.write_ir(BitSequence(self.CMD_JTAG_CONFIGURE, msb=True))
+        self.write_dr(seq)
+        self._engine.go_idle()
+
+    def wr_serdes_regfile(self, addr, data, mask, wren):
+        self.write_ir(BitSequence(self.CMD_JTAG_WR_SERDES_REGFILE, msb=True))
+        cmd  = BitSequence(value=addr, length=8,  msb=False, msby=True)
+        cmd += BitSequence(value=data, length=16, msb=False, msby=True)
+        cmd += BitSequence(value=mask, length=16, msb=False, msby=True)
+        cmd += BitSequence(value=wren, length=1, msb=False, msby=True)
+        self.write_dr(cmd)
+        self._engine.go_idle()
+
+    def rd_serdes_regfile(self):
+        self.write_ir(BitSequence(self.CMD_JTAG_RD_SERDES_REGFILE, msb=True))
+        word = self.read_dr(16)
+        self._engine.go_idle()
+        return word
+
+    def rd_status_pll(self, device=1, pll=0, verbose=0):
+        bs = BitSequence()
+        if pll == 0:
+            bs += BitSequence(self.CMD_JTAG_STATUS_PLL0, msb=True)
+        elif pll == 1:
+            bs += BitSequence(self.CMD_JTAG_STATUS_PLL1, msb=True)
+        elif pll == 2:
+            bs += BitSequence(self.CMD_JTAG_STATUS_PLL2, msb=True)
+        elif pll == 3:
+            bs += BitSequence(self.CMD_JTAG_STATUS_PLL3, msb=True)
+        else:
+            raise JtagError("Invalid PLL number: %s" % pll)
+            return 0
+        self._engine.write_ir(bs)
+        status = self._engine.read_dr(17)
+        self._engine.go_idle()
+
+        pll_status_bin = '{:017b}'.format(int(status))
+        if verbose:
+            print('pll{}: 0x{:05X}'.format(pll, int(status)))
+            print('pll%d: 0b%s' %(pll, pll_status_bin))
+
+            #     0: fine tune overflow flag
+            #     1: fine tune underflow flag
+            # 11: 2: fine tune value
+            # 13:12: state
+            # 16:14: coarse tune value
+            print('pll%d: fine tune overflow flag : %s ' %(pll, pll_status_bin[-1]))
+            print('pll%d: fine tune underflow flag : %s ' %(pll, pll_status_bin[-2]))
+            print('pll%d: fine tune value : %s ' %(pll, pll_status_bin[-12:-2]))
+
+            #S_IDLE = ‘d0; S_LOCK_IN = ‘d1; S_LOCKED = ‘d2; S_FAST_LOCK = ‘d3;
+            if pll_status_bin[-14:-12] == '00':
+                print('pll%d: state : %s  -> S_IDLE' %(pll, pll_status_bin[-14:-12]))
+            elif pll_status_bin[-14:-12] == '01':
+                print('pll%d: state : %s  -> S_LOCK_IN' %(pll, pll_status_bin[-14:-12]))
+            elif pll_status_bin[-14:-12] == '10':
+                print('pll%d: state : %s  -> S_LOCKED' %(pll, pll_status_bin[-14:-12]))
+            elif pll_status_bin[-14:-12] == '11':
+                print('pll%d: state : %s  -> S_FAST_LOCK' %(pll, pll_status_bin[-14:-12]))
+            print('pll%d: coarse tune value : %s ' %(pll, pll_status_bin[-17:-14]))
+        return (pll_status_bin[-14:-12] == '10') # locked
+
+class SerdesRegfile:
+    def __init__(self, initial_fields):
+        self.fields = initial_fields
+
+class SerdesTool:
+    regfile = SerdesRegfile({
+        'RX_BUF_RESET_TIME':        {'addr': 0x00, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 3},
+        'RX_PCS_RESET_TIME':        {'addr': 0x00, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 3},
+        'RX_RESET_TIMER_PRESC':     {'addr': 0x00, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0},
+        'RX_RESET_DONE_GATE':       {'addr': 0x00, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_CDR_RESET_TIME':        {'addr': 0x01, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 3},
+        'RX_EQA_RESET_TIME':        {'addr': 0x01, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 3},
+        'RX_PMA_RESET_TIME':        {'addr': 0x01, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 3},
+        'RX_WAIT_CDR_LOCK':         {'addr': 0x01, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_CALIB_EN':              {'addr': 0x02, 'mode': 'W/C', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_CALIB_DONE':            {'addr': 0x02, 'mode': 'R',   'hbit':  1, 'lbit':  1, 'val': 1},
+        'RX_CALIB_OVR':             {'addr': 0x02, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'RX_CALIB_VAL':             {'addr': 0x02, 'mode': 'R/W', 'hbit':  6, 'lbit':  3, 'val': 0},
+        'RX_CALIB_CAL':             {'addr': 0x02, 'mode': 'R',   'hbit': 10, 'lbit':  7, 'val': 0},
+        'RX_RTERM_VCMSEL':          {'addr': 0x02, 'mode': 'R/W', 'hbit': 13, 'lbit': 11, 'val': 4},
+        'RX_RTERM_PD':              {'addr': 0x02, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0},
+        'RX_EQA_CKP_LF':            {'addr': 0x03, 'mode': 'R/W', 'hbit':  7, 'lbit':  0, 'val': 0xA3},
+        'RX_EQA_CKP_HF':            {'addr': 0x03, 'mode': 'R/W', 'hbit': 15, 'lbit':  8, 'val': 0xA3},
+        'RX_EQA_CKP_OFFSET':        {'addr': 0x04, 'mode': 'R/W', 'hbit':  7, 'lbit':  0, 'val': 1},
+        'RX_EN_EQA':                {'addr': 0x04, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'RX_EQA_LOCK_CFG':          {'addr': 0x04, 'mode': 'R/W', 'hbit': 12, 'lbit':  9, 'val': 0},
+        'RX_EQA_LOCKED':            {'addr': 0x04, 'mode': 'R',   'hbit': 13, 'lbit': 13, 'val': 0},
+        'RX_TH_MON1':               {'addr': 0x05, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 8},
+        'RX_EN_EQA_EXT_VALUE[0]':   {'addr': 0x05, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 0},
+        'RX_TH_MON2':               {'addr': 0x05, 'mode': 'R/W', 'hbit': 10, 'lbit':  6, 'val': 8},
+        'RX_EN_EQA_EXT_VALUE[1]':   {'addr': 0x05, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_TAPW':                  {'addr': 0x06, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 8},
+        'RX_EN_EQA_EXT_VALUE[2]':   {'addr': 0x06, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 0},
+        'RX_AFE_OFFSET':            {'addr': 0x06, 'mode': 'R/W', 'hbit': 10, 'lbit':  6, 'val': 8},
+        'RX_EN_EQA_EXT_VALUE[3]':   {'addr': 0x06, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_EQA_TAPW':              {'addr': 0x07, 'mode': 'R',   'hbit':  4, 'lbit':  0, 'val': 0},
+        'RX_TH_MON':                {'addr': 0x07, 'mode': 'R',   'hbit':  9, 'lbit':  5, 'val': 0},
+        'RX_OFFSET':                {'addr': 0x07, 'mode': 'R',   'hbit': 13, 'lbit': 10, 'val': 0},
+        'RX_EQA_CONFIG':            {'addr': 0x08, 'mode': 'R/W', 'hbit': 15, 'lbit':  0, 'val': 0x01C0},
+        'RX_AFE_PEAK':              {'addr': 0x09, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 15},
+        'RX_AFE_GAIN':              {'addr': 0x09, 'mode': 'R/W', 'hbit':  8, 'lbit':  5, 'val': 8},
+        'RX_AFE_VCMSEL':            {'addr': 0x09, 'mode': 'R/W', 'hbit': 11, 'lbit':  9, 'val': 4},
+        'RX_CDR_CKP':               {'addr': 0x0A, 'mode': 'R/W', 'hbit':  7, 'lbit':  0, 'val': 0xF8},
+        'RX_CDR_CKI':               {'addr': 0x0A, 'mode': 'R/W', 'hbit': 15, 'lbit':  8, 'val': 0},
+        'RX_CDR_TRANS_TH':          {'addr': 0x0B, 'mode': 'R/W', 'hbit':  8, 'lbit':  0, 'val': 128},
+        'RX_CDR_LOCK_CFG':          {'addr': 0x0B, 'mode': 'R/W', 'hbit': 14, 'lbit':  9, 'val': 0x0B},
+        'RX_CDR_LOCKED':            {'addr': 0x0B, 'mode': 'R',   'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_CDR_FREQ_ACC_VAL':      {'addr': 0x0C, 'mode': 'R',   'hbit': 14, 'lbit':  0, 'val': 0},
+        'RX_CDR_PHASE_ACC_VAL':     {'addr': 0x0D, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_CDR_FREQ_ACC':          {'addr': 0x0E, 'mode': 'R/W', 'hbit': 14, 'lbit':  0, 'val': 0},
+        'RX_CDR_PHASE_ACC':         {'addr': 0x0F, 'mode': 'R/W', 'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_CDR_SET_ACC_CONFIG':    {'addr': 0x10, 'mode': 'R/W', 'hbit':  1, 'lbit':  0, 'val': 0},
+        'RX_CDR_FORCE_LOCK':        {'addr': 0x10, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'RX_ALIGN_MCOMMA_VALUE':    {'addr': 0x11, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x283},
+        'RX_MCOMMA_ALIGN_OVR':      {'addr': 0x11, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'RX_MCOMMA_ALIGN':          {'addr': 0x11, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_ALIGN_PCOMMA_VALUE':    {'addr': 0x12, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x17C},
+        'RX_PCOMMA_ALIGN_OVR':      {'addr': 0x12, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'RX_PCOMMA_ALIGN':          {'addr': 0x12, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_ALIGN_COMMA_WORD':      {'addr': 0x12, 'mode': 'R/W', 'hbit': 13, 'lbit': 12, 'val': 0},
+        'RX_ALIGN_COMMA_ENABLE':    {'addr': 0x13, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x3FF},
+        'RX_SLIDE_MODE':            {'addr': 0x13, 'mode': 'R/W', 'hbit': 11, 'lbit': 10, 'val': 0},
+        'RX_COMMA_DETECT_EN_OVR':   {'addr': 0x13, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0},
+        'RX_COMMA_DETECT_EN':       {'addr': 0x13, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0},
+        'RX_SLIDE[0]':              {'addr': 0x13, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0},
+        'RX_SLIDE[1]':              {'addr': 0x13, 'mode': 'W/C', 'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_EYE_MEAS_EN':           {'addr': 0x14, 'mode': 'W/C', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_CFG':          {'addr': 0x14, 'mode': 'R/W', 'hbit': 15, 'lbit':  1, 'val': 0},
+        'RX_MON_PH_OFFSET':         {'addr': 0x15, 'mode': 'R/W', 'hbit':  5, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_CORRECT_11S':  {'addr': 0x16, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_WRONG_11S':    {'addr': 0x17, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_CORRECT_00S':  {'addr': 0x18, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_WRONG_00S':    {'addr': 0x19, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_CORRECT_001S': {'addr': 0x1A, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_WRONG_001S':   {'addr': 0x1B, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_CORRECT_110S': {'addr': 0x1C, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EYE_MEAS_WRONG_110S':   {'addr': 0x1D, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_EI_BIAS':               {'addr': 0x1E, 'mode': 'R/W', 'hbit':  3, 'lbit':  0, 'val': 4},
+        'RX_EI_BW_SEL':             {'addr': 0x1E, 'mode': 'R/W', 'hbit':  7, 'lbit':  4, 'val': 4},
+        'RX_EN_EI_DETECTOR_OVR':    {'addr': 0x1E, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'RX_EN_EI_DETECTOR':        {'addr': 0x1E, 'mode': 'R/W', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'RX_EI_EN':                 {'addr': 0x1E, 'mode': 'R',   'hbit': 10, 'lbit': 10, 'val': 0},
+        'RX_PRBS_ERR_CNT':          {'addr': 0x1F, 'mode': 'R',   'hbit': 14, 'lbit':  0, 'val': 0},
+        'RX_PRBS_LOCKED':           {'addr': 0x1F, 'mode': 'R',   'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_DATA_SEL':              {'addr': 0x20, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_DATA[15:0]':            {'addr': 0x20, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_DATA[31:16]':           {'addr': 0x21, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_DATA[47:32]':           {'addr': 0x22, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_DATA[63:48]':           {'addr': 0x23, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_DATA[79:64]':           {'addr': 0x24, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'RX_BUF_BYPASS':            {'addr': 0x25, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_CLKCOR_USE':            {'addr': 0x25, 'mode': 'R/W', 'hbit':  1, 'lbit':  1, 'val': 0},
+        'RX_CLKCOR_MIN_LAT':        {'addr': 0x25, 'mode': 'R/W', 'hbit':  7, 'lbit':  2, 'val': 32},
+        'RX_CLKCOR_MAX_LAT':        {'addr': 0x25, 'mode': 'R/W', 'hbit': 13, 'lbit':  8, 'val': 39},
+        'RX_CLKCOR_SEQ_1_0':        {'addr': 0x26, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x1F7},
+        'RX_CLKCOR_SEQ_1_1':        {'addr': 0x27, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x1F7},
+        'RX_CLKCOR_SEQ_1_2':        {'addr': 0x28, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x1F7},
+        'RX_CLKCOR_SEQ_1_3':        {'addr': 0x29, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0x1F7},
+        'RX_PMA_LOOPBACK':          {'addr': 0x2A, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_PCS_LOOPBACK':          {'addr': 0x2A, 'mode': 'R/W', 'hbit':  1, 'lbit':  1, 'val': 0},
+        'RX_DATAPATH_SEL':          {'addr': 0x2A, 'mode': 'R/W', 'hbit':  3, 'lbit':  2, 'val': 3},
+        'RX_PRBS_OVR':              {'addr': 0x2A, 'mode': 'R/W', 'hbit':  4, 'lbit':  4, 'val': 0},
+        'RX_PRBS_SEL':              {'addr': 0x2A, 'mode': 'R/W', 'hbit':  7, 'lbit':  5, 'val': 0},
+        'RX_LOOPBACK_OVR':          {'addr': 0x2A, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'RX_PRBS_CNT_RESET':        {'addr': 0x2A, 'mode': 'W/C', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'RX_POWER_DOWN_OVR':        {'addr': 0x2A, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'RX_POWER_DOWN_N':          {'addr': 0x2A, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_PRESENT':               {'addr': 0x2A, 'mode': 'R',   'hbit': 12, 'lbit': 12, 'val': 0},
+        'RX_DETECT_DONE':           {'addr': 0x2A, 'mode': 'R',   'hbit': 13, 'lbit': 13, 'val': 0},
+        'RX_BUF_ERR':               {'addr': 0x2A, 'mode': 'R',   'hbit': 14, 'lbit': 14, 'val': 0},
+        'RX_RESET_OVR':             {'addr': 0x2B, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'RX_RESET':                 {'addr': 0x2B, 'mode': 'W/C', 'hbit':  1, 'lbit':  1, 'val': 0},
+        'RX_PMA_RESET_OVR':         {'addr': 0x2B, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'RX_PMA_RESET':             {'addr': 0x2B, 'mode': 'W/C', 'hbit':  3, 'lbit':  3, 'val': 0},
+        'RX_EQA_RESET_OVR':         {'addr': 0x2B, 'mode': 'R/W', 'hbit':  4, 'lbit':  4, 'val': 0},
+        'RX_EQA_RESET':             {'addr': 0x2B, 'mode': 'W/C', 'hbit':  5, 'lbit':  5, 'val': 0},
+        'RX_CDR_RESET_OVR':         {'addr': 0x2B, 'mode': 'R/W', 'hbit':  6, 'lbit':  6, 'val': 0},
+        'RX_CDR_RESET':             {'addr': 0x2B, 'mode': 'W/C', 'hbit':  7, 'lbit':  7, 'val': 0},
+        'RX_PCS_RESET_OVR':         {'addr': 0x2B, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'RX_PCS_RESET':             {'addr': 0x2B, 'mode': 'W/C', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'RX_BUF_RESET_OVR':         {'addr': 0x2B, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'RX_BUF_RESET':             {'addr': 0x2B, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'RX_POLARITY_OVR':          {'addr': 0x2B, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0},
+        'RX_POLARITY':              {'addr': 0x2B, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0},
+        'RX_8B10B_EN_OVR':          {'addr': 0x2B, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0},
+        'RX_8B10B_EN':              {'addr': 0x2B, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0},
+        'RX_8B10B_BYPASS':          {'addr': 0x2C, 'mode': 'R/W', 'hbit':  7, 'lbit':  0, 'val': 0},
+        'RX_BYTE_IS_ALIGNED':       {'addr': 0x2C, 'mode': 'R',   'hbit':  8, 'lbit':  8, 'val': 0},
+        'RX_BYTE_REALIGN':          {'addr': 0x2C, 'mode': 'R/C', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'RX_RESET_DONE':            {'addr': 0x2C, 'mode': 'R',   'hbit': 10, 'lbit': 10, 'val': 0},
+        #'RX_DBG_EN':               {'addr': 0x2D, 'mode': 'W/C', 'hbit':  0, 'lbit':  0, 'val': 0},
+        #'RX_DBG_SEL':              {'addr': 0x2D, 'mode': 'R/W', 'hbit':  4, 'lbit':  1, 'val': 0},
+        #'RX_DBG_MODE':             {'addr': 0x2D, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 0},
+        #'RX_DBG_SRAM_DELAY':       {'addr': 0x2D, 'mode': 'R/W', 'hbit': 11, 'lbit':  6, 'val': 5},
+        #'RX_DBG_ADDR':             {'addr': 0x2E, 'mode': 'R/W', 'hbit':  9, 'lbit':  0, 'val': 0},
+        #'RX_DBG_RE':               {'addr': 0x2E, 'mode': 'W/C', 'hbit': 10, 'lbit': 10, 'val': 0},
+        #'RX_DBG_WE':               {'addr': 0x2E, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0},
+        #'RX_DBG_DATA[3:0]':        {'addr': 0x2E, 'mode': 'R/W', 'hbit': 15, 'lbit': 12, 'val': 0},
+        #'RX_DBG_DATA[19:4]':       {'addr': 0x2F, 'mode': 'R/W', 'hbit': 15, 'lbit':  0, 'val': 0},
+        'TX_SEL_PRE':               {'addr': 0x30, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_SEL_POST':              {'addr': 0x30, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 0},
+        'TX_AMP':                   {'addr': 0x30, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15},
+        'TX_BRANCH_EN_PRE':         {'addr': 0x31, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_BRANCH_EN_MAIN':        {'addr': 0x31, 'mode': 'R/W', 'hbit': 10, 'lbit':  5, 'val': 0x3F},
+        'TX_BRANCH_EN_POST':        {'addr': 0x31, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0},
+        'TX_TAIL_CASCODE':          {'addr': 0x32, 'mode': 'R/W', 'hbit':  2, 'lbit':  0, 'val': 4},
+        'TX_DC_ENABLE':             {'addr': 0x32, 'mode': 'R/W', 'hbit':  9, 'lbit':  3, 'val': 63},
+        'TX_DC_OFFSET':             {'addr': 0x32, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 8},
+        'TX_CM_RAISE':              {'addr': 0x33, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_CM_THRESHOLD_0':        {'addr': 0x33, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 14},
+        'TX_CM_THRESHOLD_1':        {'addr': 0x33, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16},
+        'TX_SEL_PRE_EI':            {'addr': 0x34, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_SEL_POST_EI':           {'addr': 0x34, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 0},
+        'TX_AMP_EI':                {'addr': 0x34, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15},
+        'TX_BRANCH_EN_PRE_EI':      {'addr': 0x35, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_BRANCH_EN_MAIN_EI':     {'addr': 0x35, 'mode': 'R/W', 'hbit': 10, 'lbit':  5, 'val': 0x3F},
+        'TX_BRANCH_EN_POST_EI':     {'addr': 0x35, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0},
+        'TX_TAIL_CASCODE_EI':       {'addr': 0x36, 'mode': 'R/W', 'hbit':  2, 'lbit':  0, 'val': 4},
+        'TX_DC_ENABLE_EI':          {'addr': 0x36, 'mode': 'R/W', 'hbit':  9, 'lbit':  3, 'val': 63},
+        'TX_DC_OFFSET_EI':          {'addr': 0x36, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0},
+        'TX_CM_RAISE_EI':           {'addr': 0x37, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_CM_THRESHOLD_0_EI':     {'addr': 0x37, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 14},
+        'TX_CM_THRESHOLD_1_EI':     {'addr': 0x37, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16},
+        'TX_SEL_PRE_RXDET':         {'addr': 0x38, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_SEL_POST_RXDET':        {'addr': 0x38, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 0},
+        'TX_AMP_RXDET':             {'addr': 0x38, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15},
+        'TX_BRANCH_EN_PRE_RXDET':   {'addr': 0x39, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_BRANCH_EN_MAIN_RXDET':  {'addr': 0x39, 'mode': 'R/W', 'hbit': 10, 'lbit':  5, 'val': 0x3F},
+        'TX_BRANCH_EN_POST_RXDET':  {'addr': 0x39, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0},
+        'TX_TAIL_CASCODE_RXDET':    {'addr': 0x3A, 'mode': 'R/W', 'hbit':  2, 'lbit':  0, 'val': 4},
+        'TX_DC_ENABLE_RXDET':       {'addr': 0x3A, 'mode': 'R/W', 'hbit':  9, 'lbit':  3, 'val': 63},
+        'TX_DC_OFFSET_RXDET':       {'addr': 0x3A, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0},
+        'TX_CM_RAISE_RXDET':        {'addr': 0x3B, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_CM_THRESHOLD_0_RXDET':  {'addr': 0x3B, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 14},
+        'TX_CM_THRESHOLD_1_RXDET':  {'addr': 0x3B, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16},
+        'TX_CALIB_EN':              {'addr': 0x3C, 'mode': 'W/C', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'TX_CALIB_DONE':            {'addr': 0x3C, 'mode': 'R',   'hbit':  1, 'lbit':  1, 'val': 1},
+        'TX_CALIB_OVR':             {'addr': 0x3C, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'TX_CALIB_VAL':             {'addr': 0x3C, 'mode': 'R/W', 'hbit':  6, 'lbit':  3, 'val': 0},
+        'TX_CALIB_CAL':             {'addr': 0x3C, 'mode': 'R',   'hbit': 10, 'lbit':  7, 'val': 0},
+        'TX_CM_REG_KI':             {'addr': 0x3D, 'mode': 'R/W', 'hbit':  7, 'lbit':  0, 'val': 0x80},
+        'TX_CM_SAR_EN':             {'addr': 0x3D, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'TX_CM_REG_EN':             {'addr': 0x3D, 'mode': 'R/W', 'hbit':  9, 'lbit':  9, 'val': 1},
+        'TX_CM_SAR_RESULT_0':       {'addr': 0x3E, 'mode': 'R',   'hbit':  4, 'lbit':  0, 'val': 0},
+        'TX_CM_SAR_RESULT_1':       {'addr': 0x3E, 'mode': 'R',   'hbit':  9, 'lbit':  5, 'val': 0},
+        'TX_PMA_RESET_TIME':        {'addr': 0x3F, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 3},
+        'TX_PCS_RESET_TIME':        {'addr': 0x3F, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 3},
+        'TX_PCS_RESET_OVR':         {'addr': 0x3F, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'TX_PCS_RESET':             {'addr': 0x3F, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'TX_PMA_RESET_OVR':         {'addr': 0x3F, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0},
+        'TX_PMA_RESET':             {'addr': 0x3F, 'mode': 'W/C', 'hbit': 13, 'lbit': 13, 'val': 0},
+        'TX_RESET_OVR':             {'addr': 0x3F, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0},
+        'TX_RESET':                 {'addr': 0x3F, 'mode': 'W/C', 'hbit': 15, 'lbit': 15, 'val': 0},
+        'TX_PMA_LOOPBACK':          {'addr': 0x40, 'mode': 'R/W', 'hbit':  1, 'lbit':  0, 'val': 0},
+        'TX_PCS_LOOPBACK':          {'addr': 0x40, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'TX_DATAPATH_SEL':          {'addr': 0x40, 'mode': 'R/W', 'hbit':  4, 'lbit':  3, 'val': 3},
+        'TX_PRBS_OVR':              {'addr': 0x40, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 0},
+        'TX_PRBS_SEL':              {'addr': 0x40, 'mode': 'R/W', 'hbit':  8, 'lbit':  6, 'val': 0},
+        'TX_PRBS_FORCE_ERR':        {'addr': 0x40, 'mode': 'W/C', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'TX_LOOPBACK_OVR':          {'addr': 0x40, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0},
+        'TX_POWER_DOWN_OVR':        {'addr': 0x40, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'TX_POWER_DOWN_N':          {'addr': 0x40, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0},
+        'TX_ELEC_IDLE_OVR':         {'addr': 0x41, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'TX_ELEC_IDLE':             {'addr': 0x41, 'mode': 'R/W', 'hbit':  1, 'lbit':  1, 'val': 0},
+        'TX_DETECT_RX_OVR':         {'addr': 0x41, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'TX_DETECT_RX':             {'addr': 0x41, 'mode': 'R/W', 'hbit':  3, 'lbit':  3, 'val': 0},
+        'TX_POLARITY_OVR':          {'addr': 0x41, 'mode': 'R/W', 'hbit':  4, 'lbit':  4, 'val': 0},
+        'TX_POLARITY':              {'addr': 0x41, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 0},
+        'TX_8B10B_EN_OVR':          {'addr': 0x41, 'mode': 'R/W', 'hbit':  6, 'lbit':  6, 'val': 0},
+        'TX_8B10B_EN':              {'addr': 0x41, 'mode': 'R/W', 'hbit':  7, 'lbit':  7, 'val': 0},
+        'TX_DATA_OVR':              {'addr': 0x41, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'TX_DATA_CNT':              {'addr': 0x41, 'mode': 'R/W', 'hbit': 11, 'lbit':  9, 'val': 0},
+        'TX_DATA_VALID':            {'addr': 0x41, 'mode': 'W/C', 'hbit': 12, 'lbit': 12, 'val': 0},
+        'TX_BUF_ERR':               {'addr': 0x41, 'mode': 'R',   'hbit': 13, 'lbit': 13, 'val': 0},
+        'TX_RESET_DONE':            {'addr': 0x41, 'mode': 'R',   'hbit': 14, 'lbit': 14, 'val': 0},
+        'TX_DATA':                  {'addr': 0x42, 'mode': 'R/W', 'hbit': 15, 'lbit':  0, 'val': 0},
+        # 0x43..0x4F unused
+        'PLL_EN_ADPLL_CTRL':        {'addr': 0x50, 'mode': 'R/W', 'hbit':  0, 'lbit':  0, 'val': 0},
+        'PLL_CONFIG_SEL':           {'addr': 0x50, 'mode': 'R/W', 'hbit':  1, 'lbit':  1, 'val': 1},
+        'PLL_SET_OP_LOCK':          {'addr': 0x50, 'mode': 'R/W', 'hbit':  2, 'lbit':  2, 'val': 0},
+        'PLL_ENFORCE_LOCK':         {'addr': 0x50, 'mode': 'R/W', 'hbit':  3, 'lbit':  3, 'val': 0},
+        'PLL_DISABLE_LOCK':         {'addr': 0x50, 'mode': 'R/W', 'hbit':  4, 'lbit':  4, 'val': 0},
+        'PLL_LOCK_WINDOW':          {'addr': 0x50, 'mode': 'R/W', 'hbit':  5, 'lbit':  5, 'val': 1},
+        'PLL_FAST_LOCK':            {'addr': 0x50, 'mode': 'R/W', 'hbit':  6, 'lbit':  6, 'val': 1},
+        'PLL_SYNC_BYPASS':          {'addr': 0x50, 'mode': 'R/W', 'hbit':  7, 'lbit':  7, 'val': 0},
+        'PLL_PFD_SELECT':           {'addr': 0x50, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'PLL_REF_BYPASS':           {'addr': 0x50, 'mode': 'R/W', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'PLL_REF_SEL':              {'addr': 0x50, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 1},
+        'PLL_REF_RTERM':            {'addr': 0x50, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 1},
+        'PLL_FCNTRL':               {'addr': 0x51, 'mode': 'R/W', 'hbit':  5, 'lbit':  0, 'val': 58},
+        'PLL_MAIN_DIVSEL':          {'addr': 0x51, 'mode': 'R/W', 'hbit': 11, 'lbit':  6, 'val': 27},
+        'PLL_OUT_DIVSEL':           {'addr': 0x51, 'mode': 'R/W', 'hbit': 13, 'lbit': 12, 'val': 0},
+        'PLL_CI':                   {'addr': 0x52, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 3},
+        'PLL_CP':                   {'addr': 0x52, 'mode': 'R/W', 'hbit': 14, 'lbit':  5, 'val': 80},
+        'PLL_AO':                   {'addr': 0x53, 'mode': 'R/W', 'hbit':  3, 'lbit':  0, 'val': 0},
+        'PLL_SCAP':                 {'addr': 0x53, 'mode': 'R/W', 'hbit':  6, 'lbit':  4, 'val': 0},
+        'PLL_FILTER_SHIFT':         {'addr': 0x53, 'mode': 'R/W', 'hbit':  8, 'lbit':  7, 'val': 2},
+        'PLL_SAR_LIMIT':            {'addr': 0x53, 'mode': 'R/W', 'hbit': 11, 'lbit':  9, 'val': 2},
+        'PLL_FT':                   {'addr': 0x54, 'mode': 'R/W', 'hbit': 10, 'lbit':  0, 'val': 512},
+        'PLL_OPEN_LOOP':            {'addr': 0x54, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0},
+        'PLL_SCAP_AUTO_CAL':        {'addr': 0x54, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 1},
+        'PLL_LOCKED':               {'addr': 0x55, 'mode': 'R',   'hbit':  0, 'lbit':  0, 'val': 0},
+        'PLL_CAP_FT_OF':            {'addr': 0x55, 'mode': 'R',   'hbit':  1, 'lbit':  1, 'val': 0},
+        'PLL_CAP_FT_UF':            {'addr': 0x55, 'mode': 'R',   'hbit':  2, 'lbit':  2, 'val': 0},
+        'PLL_CAP_FT':               {'addr': 0x55, 'mode': 'R',   'hbit': 12, 'lbit':  3, 'val': 0},
+        'PLL_CAP_STATE':            {'addr': 0x55, 'mode': 'R',   'hbit': 14, 'lbit': 13, 'val': 0},
+        'PLL_SYNC_VALUE':           {'addr': 0x56, 'mode': 'R',   'hbit':  7, 'lbit':  0, 'val': 0},
+        'PLL_BISC_MODE':            {'addr': 0x57, 'mode': 'R/W', 'hbit':  2, 'lbit':  0, 'val': 4},
+        'PLL_BISC_TIMER_MAX':       {'addr': 0x57, 'mode': 'R/W', 'hbit':  6, 'lbit':  3, 'val': 15},
+        'PLL_BISC_OPT_DET_IND':     {'addr': 0x57, 'mode': 'R/W', 'hbit':  7, 'lbit':  7, 'val': 0},
+        'PLL_BISC_PFD_SEL':         {'addr': 0x57, 'mode': 'R/W', 'hbit':  8, 'lbit':  8, 'val': 0},
+        'PLL_BISC_DLY_DIR':         {'addr': 0x57, 'mode': 'R/W', 'hbit':  9, 'lbit':  9, 'val': 0},
+        'PLL_BISC_COR_DLY':         {'addr': 0x57, 'mode': 'R/W', 'hbit': 12, 'lbit': 10, 'val': 1},
+        'PLL_BISC_CAL_SIGN':        {'addr': 0x57, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0},
+        'PLL_BISC_CAL_AUTO':        {'addr': 0x57, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 1},
+        'PLL_BISC_CP_MIN':          {'addr': 0x58, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 4},
+        'PLL_BISC_CP_MAX':          {'addr': 0x58, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 18},
+        'PLL_BISC_CP_START':        {'addr': 0x58, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 12},
+        'PLL_BISC_DLY_PFD_MON_REF': {'addr': 0x59, 'mode': 'R/W', 'hbit':  4, 'lbit':  0, 'val': 0},
+        'PLL_BISC_DLY_PFD_MON_DIV': {'addr': 0x59, 'mode': 'R/W', 'hbit':  9, 'lbit':  5, 'val': 2},
+        'PLL_BISC_TIMER_DONE':      {'addr': 0x5A, 'mode': 'R',   'hbit':  0, 'lbit':  0, 'val': 0},
+        'PLL_BISC_CP':              {'addr': 0x5A, 'mode': 'R',   'hbit':  7, 'lbit':  1, 'val': 0}, # BISC_RESULT[15:1]
+        'PLL_BISC_CO':              {'addr': 0x5B, 'mode': 'R',   'hbit': 15, 'lbit':  0, 'val': 0},
+        'SERDES_ENABLE':            {'addr': 0x5C, 'mode': 'R/C', 'hbit':  0, 'lbit':  0, 'val': 1},
+        'SERDES_AUTO_INIT':         {'addr': 0x5C, 'mode': 'R/C', 'hbit':  1, 'lbit':  1, 'val': 0},
+        'SERDES_TESTMODE':          {'addr': 0x5C, 'mode': 'R/C', 'hbit':  2, 'lbit':  2, 'val': 0},
+    })
+
+    ports = {
+        # name: width
+        'TX_DATA_I': 64,
+        'TX_RESET_I': 1,
+        'TX_PCS_RESET_I': 1,
+        'TX_PMA_RESET_I': 1,
+        'PLL_RESET_I': 1,
+        'TX_POWER_DOWN_N_I': 1,
+        'TX_POLARITY_I': 1,
+        'TX_PRBS_SEL_I': 3,
+        'TX_PRBS_FORCE_ERR_I': 1,
+        'TX_8B10B_EN_I': 1,
+        'TX_8B10B_BYPASS_I': 8,
+        'TX_CHAR_IS_K_I': 8,
+        'TX_CHAR_DISPMODE_I': 8,
+        'TX_CHAR_DISPVAL_I': 8,
+        'TX_ELEC_IDLE_I': 1,
+        'TX_DETECT_RX_I': 1,
+        'LOOPBACK_I': 3,
+        'TX_CLK_I': 1,
+        'RX_CLK_I': 1,
+        'RX_RESET_I': 1,
+        'RX_PMA_RESET_I': 1,
+        'RX_EQA_RESET_I': 1,
+        'RX_CDR_RESET_I': 1,
+        'RX_PCS_RESET_I': 1,
+        'RX_BUF_RESET_I': 1,
+        'RX_POWER_DOWN_N_I': 1,
+        'RX_POLARITY_I': 1,
+        'RX_PRBS_SEL_I': 3,
+        'RX_PRBS_CNT_RESET_I': 1,
+        'RX_8B10B_EN_I': 1,
+        'RX_8B10B_BYPASS_I': 8,
+        'RX_EN_EI_DETECTOR_I': 1,
+        'RX_COMMA_DETECT_EN_I': 1,
+        'RX_SLIDE_I': 1,
+        'RX_MCOMMA_ALIGN_I': 1,
+        'RX_PCOMMA_ALIGN_I': 1,
+        'REGFILE_CLK_I': 1,
+        'REGFILE_WE_I': 1,
+        'REGFILE_EN_I': 1,
+        'REGFILE_ADDR_I': 8,
+        'REGFILE_DI_I': 16,
+        'REGFILE_MASK_I': 16,
+        'RX_DATA_O': 64,
+        'RX_NOT_IN_TABLE_O': 8,
+        'RX_CHAR_IS_COMMA_O': 8,
+        'RX_CHAR_IS_K_O': 8,
+        'RX_DISP_ERR_O': 8,
+        'TX_DETECT_RX_DONE_O': 1,
+        'TX_DETECT_RX_PRESENT_O': 1,
+        'TX_BUF_ERR_O': 1,
+        'TX_RESET_DONE_O': 1,
+        'RX_PRBS_ERR_O': 1,
+        'RX_BUF_ERR_O': 1,
+        'RX_BYTE_IS_ALIGNED_O': 1,
+        'RX_BYTE_REALIGN_O': 1,
+        'RX_RESET_DONE_O': 1,
+        'RX_EI_EN_O': 1,
+        'RX_CLK_O': 1,
+        'PLL_CLK_O': 1,
+        'REGFILE_DO_O': 16,
+        'REGFILE_RDY_O': 1
+    }
+
+    olclkg = { # open loop clock generator
+        # fcntrl : N
+         0:    1,  1:     2,  2:    3,  3:  3.5,
+         4:  3.5,  5:  3.75,  6:    4,  7:    4,
+         8:  4.5,  9:  5.25, 10:    5, 11:  5.5,
+        12:  5.5, 13:  5.75, 14:    6, 15:    6,
+        16:    6, 17:     7, 18:    6, 19:    7,
+        20:    7, 21:   7.5, 22:    8, 23:    8,
+        24:    9, 25:  10.5, 26:   10, 27:   11,
+        28:   11, 29:  11.5, 30:   12, 31:   12,
+        32:    9, 33:  10.5, 34:    9, 35: 10.5,
+        36: 10.5, 37: 11.25, 38:   12, 39:   12,
+        40: 13.5, 41: 15.75, 42:   15, 43: 16.5,
+        44: 16.5, 45: 17.25, 46:   18, 47:   18,
+        48:   12, 49:    14, 50:   12, 51:   14,
+        52:   14, 53: 15.75, 54: 16.5, 55: 16.5,
+        56:   18, 57:    21, 58:   20, 59:   22,
+        60:   22, 61:    23, 62:   24, 63:   24,
+    }
+
+    # keywords for conditional coloring
+    pos_cond = ["DONE", "PRESENT", "LOCKED", "IS_ALIGNED", "EN_ADPLL_CTRL", "CONFIG_SEL", "SERDES_ENABLE"]
+    neg_cond = ["ERR", "DOWN", "TESTMODE"]
+    ovr_cond = ["OVR"]
+
+    # PFDAC settings
+    ADPLL_PFDAC_TIMER    = 12
+    ADPLL_PFDAC_COR_DLY  = 1
+    ADPLL_PFDAC_CP_MIN   = 6
+    ADPLL_PFDAC_CP_MAX   = 30
+    ADPLL_PFDAC_CP_START = 6
+    ADPLL_PFDAC_CAL_SIGN = 1
+    ADPLL_PFDAC_AUTO_CAL = 1
+
+    # Thread-safe lock for updating values
+    param_lock = threading.Lock()
+
+    def __init__(self, args, jtag, hwinit):
+        if hwinit:
+            self._jtag = jtag
+            self._board = args.board
+            if self._jtag is not None:
+                self.configure()
+
+    def configure(self):
+        if self._board == Boards_e[0]: # auto
+            self._jtag.configure(FindAndFormatFtdiAddr(0))
+        elif self._board == Boards_e[1]: # pgm
+            self._jtag.configure('ftdi://ftdi:232h/1')
+        elif self._board == Boards_e[2]: # evb
+            self._jtag.configure('ftdi://ftdi:2232h/1')
+
+        self._jtag.reset()
+        self._tool = JtagTool(self._jtag)
+
+    def rd_id(self):
+        self._tool.idcode()
+
+    def wr_cfg(self, bitfile):
+        self._tool.wr_cfg(bitfile)
+
+    def gen_module_vlog(self, filename):
+        print(f'Generate verilog template: {filename}')
+        with open(filename, 'w') as file:
+            file.write('// CC_SERDES instance generator\n')
+            file.write(f'// generated: {datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")}\n')
+            file.write('\n')
+            file.write('CC_SERDES #(\n')
+            for idx, (param, data) in enumerate(self.regfile.fields.items()):
+                end = '' if idx == len(self.regfile.fields.items())-1 else ','
+                if data['mode'] != 'R':
+                    width = data['hbit']-data['lbit']+1
+                    file.write(f'    .{param}({width}\'h{data['val']:X}){end}\n')
+            file.write(') i_cc_serdes (\n')
+            for idx, (port, width) in enumerate(self.ports.items()):
+                end = '' if idx == len(self.ports.items())-1 else ','
+                if port.endswith('_I'):
+                    file.write(f'    .{port}({width}\'h{0:X}){end}\n')
+                else: # port.endswith('_O'):
+                    file.write(f'    .{port}(){end}\n')
+            file.write(');\n')
+
+    def gen_module_vhdl(self, filename):
+        print(f'Generate VHDL template: {filename}')
+        with open(filename, 'w') as file:
+            file.write('-- CC_SERDES instance generator\n')
+            file.write(f'-- generated: {datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")}\n')
+            # component
+            file.write('\n')
+            file.write('component CC_SERDES is\n')
+            file.write('generic (\n')
+            for idx, (param, data) in enumerate(self.regfile.fields.items()):
+                end = '' if (idx == len(self.regfile.fields.items())-1) else ';'
+                if data['mode'] != 'R':
+                    hbit = data['hbit']-data['lbit']
+                    file.write(f'    {param} : bit_vector({hbit} downto 0){end}\n')
+            file.write(');\n')
+            file.write('port (\n')
+            for idx, (port, width) in enumerate(self.ports.items()):
+                end = '' if idx == len(self.ports.items())-1 else ';'
+                if port.endswith('_I'):
+                    if width > 1:
+                        file.write(f'    {port} : in std_logic_vector({width-1} downto 0){end}\n')
+                    else:
+                        file.write(f'    {port} : in std_logic{end}\n')
+                else: # port.endswith('_O'):
+                    if width > 1:
+                        file.write(f'    {port} : out std_logic_vector({width-1} downto 0){end}\n')
+                    else:
+                        file.write(f'    {port} : out std_logic{end}\n')
+            file.write(');\n')
+            file.write('end component;\n')
+            # instance
+            file.write('\n')
+            file.write('i_cc_serdes: CC_SERDES\n')
+            file.write('generic map (\n')
+            for idx, (param, data) in enumerate(self.regfile.fields.items()):
+                end = '' if (idx == len(self.regfile.fields.items())-1) else ','
+                if data['mode'] != 'R':
+                    width = data['hbit']-data['lbit']+1
+                    file.write(f'    {param} => {width}X"{data['val']:X}"{end}\n')
+            file.write(')\n')
+            file.write('port map (\n')
+            for idx, (port, width) in enumerate(self.ports.items()):
+                end = '' if idx == len(self.ports.items())-1 else ','
+                if port.endswith('_I'):
+                    if width > 1:
+                        file.write(f'    {port} => (others => \'0\'){end}\n')
+                    else:
+                        file.write(f'    {port} => \'{0}\'{end}\n')
+                else: # port.endswith('_O'):
+                    file.write(f'    {port} => open{end}\n')
+            file.write(');\n')
+
+    def fprint(self, key, value, line):
+        if any(cond in key for cond in self.pos_cond) and int(value) != 0:
+            print(bcolors.OK + line + bcolors.RESET)
+        elif any(cond in key for cond in self.pos_cond) and int(value) == 0:
+            print(bcolors.WARN + line + bcolors.RESET)
+        elif any(cond in key for cond in self.neg_cond) and (int(value) < 1 if key.endswith('_N') else int(value) > 0):
+            print(bcolors.FAIL + line + bcolors.RESET)
+        elif any(cond in key for cond in self.ovr_cond) and int(value) > 0:
+            print(bcolors.OVR + line + bcolors.RESET)
+        else:
+            print(line)
+
+    def rd_regfile(self, addr) -> int:
+        self._tool.wr_serdes_regfile(addr=addr, data=0, mask=0, wren=0)
+        return self._tool.rd_serdes_regfile()
+
+    def wr_regfile(self, addr, data, mask):
+        self._tool.wr_serdes_regfile(addr=addr, data=data, mask=mask, wren=1)
+        self._tool.rd_serdes_regfile()
+
+    def rd_regfile_rx(self, verbose=0):
+        for addr in range(0x00, 0x30):
+            word = self.rd_regfile(addr)
+            if verbose == 1:
+                print(f'{addr:02X}: 0x{int(word):04X}')
+            elif verbose == 2:
+                filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr}
+                for (key, value) in filtered_entries.items():
+                    v = word[value['lbit']:value['hbit']+1]
+                    line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d'
+                    self.fprint(key, v, line)
+
+    def rd_regfile_rx_data(self):
+        rxd_80bit = BitSequence()
+        for addr in range(0x20, 0x25):
+            rxd_80bit += self.rd_regfile(addr)
+        rxd_64bit = rxd_80bit[0:7+1] + rxd_80bit[10:17+1] + rxd_80bit[20:27+1] + rxd_80bit[30:37+1] + rxd_80bit[40:47+1] + rxd_80bit[50:57+1] + rxd_80bit[60:67+1] + rxd_80bit[70:77+1]
+        return rxd_64bit, rxd_80bit
+
+    def print_regfile_rx_data(self, verbose=0):
+        rx_data_80bit = 0
+        word_idx = 0
+        for addr in range(0x20, 0x25):
+            word = self.rd_regfile(addr)
+            if verbose == 1:
+                print(f'{addr:02X}: 0x{int(word):04X}')
+            rx_fields = {
+                key: field for key, field in self.regfile.fields.items()
+                if field['addr'] == addr and key.startswith('RX_DATA[')
+            }
+            for field_name, field_info in rx_fields.items():
+                # Extract the relevant bits from the word
+                bit_slice = word[field_info['lbit']:field_info['hbit'] + 1]
+                rx_data_80bit |= int(bit_slice) << (16 * word_idx)
+                word_idx += 1
+
+        if verbose == 2:
+            print(f'{"RX_DATA[79:0]":24} {rx_data_80bit:020X}\'h')
+
+        # Convert to 64-bit format by packing every 10 bits into bytes
+        rx_data_64bit = 0
+        byte_position = 0
+        for bit_offset in range(0, 80, 10):
+            byte_value = (rx_data_80bit >> bit_offset) & 0xFF
+            rx_data_64bit |= byte_value << (byte_position * 8)
+            byte_position += 1
+
+        if verbose == 2:
+            print(f'{"RX_DATA[63:0]":24} {rx_data_64bit:016X}\'h')
+
+        return rx_data_64bit, rx_data_80bit
+
+    def wr_regfile_tx_data(self, data):
+        self.wr_regfile(addr=0x41, data=0x1000, mask=0x1F00) # TX_DATA_OVR=1, TX_DATA_CNT=0, TX_DATA_VALID=0
+        for i in range(5):
+            self.wr_regfile(addr=0x42, data=(data >> 16*i) & 0xFFFF, mask=0xFFFF) # auto inc
+        self.wr_regfile(addr=0x41, data=0x1B00, mask=0x1F00) # TX_DATA_OVR=1, TX_DATA_CNT=5, TX_DATA_VALID=1
+
+    def rd_regfile_tx(self, verbose=0):
+        for addr in range(0x30, 0x43): # 0x43..0x4F unused
+            word = self.rd_regfile(addr)
+            if verbose == 1:
+                print(f'{addr:02X}: 0x{int(word):04X}')
+            elif verbose == 2:
+                filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr}
+                for (key, value) in filtered_entries.items():
+                    v = word[value['lbit']:value['hbit']+1]
+                    line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d'
+                    self.fprint(key, v, line)
+
+    def rd_regfile_pll(self, verbose=0):
+        for addr in range(0x50, 0x5D):
+            word = self.rd_regfile(addr)
+            if verbose == 1:
+                print(f'{addr:02X}: 0x{int(word):04X}')
+            elif verbose == 2:
+                filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr}
+                for (key, value) in filtered_entries.items():
+                    v = word[value['lbit']:value['hbit']+1]
+                    line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d'
+                    self.fprint(key, v, line)
+
+    def rd_regfile_pll_div_settings(self):
+        word = self.rd_regfile(addr=0x51)
+        FCNTRL = word[0:5+1]
+        MAIN_DIVSEL = word[6:11+1]
+        OUT_DIVSEL = word[12:13+1]
+        n1 = MAIN_DIVSEL[2]
+        n2 = MAIN_DIVSEL[0:1+1]
+        n3 = MAIN_DIVSEL[3:4+1]
+        return n1, n2, n3, OUT_DIVSEL
+
+    def rd_regfile_pll_status(self):
+        return self.rd_regfile(addr=0x55) + self.rd_regfile(addr=0x56)
+
+    def rd_regfile_pll_bisc_status(self):
+        return self.rd_regfile(addr=0x5A) + self.rd_regfile(addr=0x5B)
+
+    def reset_serdes_tx(self):
+        print('INFO:  Resetting SerDes TX')
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+        # TX reset
+        self.wr_regfile(addr=0x3F, data=0xC000, mask=0xC000) # TX_RESET_OVR=1, TX_RESET=1
+        self.wr_regfile(addr=0x3F, data=0x0000, mask=0xC000) # TX_RESET_OVR=0, TX_RESET=0
+        word = self.rd_regfile(addr=0x41)
+        timeout = 5
+        while timeout > 0:
+            if (int(word[14]) != 1): # TX_RESET_DONE
+                timeout = timeout - 1
+                if timeout == 0:
+                    print(f'ERROR: TX_RESET_DONE timeout')
+            else:
+                break
+
+    def set_serdes_datapath(self, mode=80):
+        if mode == 0 or mode == 20:
+            self.wr_regfile(addr=0x2A, data=0x0000, mask=0x000C) # RX_DATAPATH_SEL=0
+            self.wr_regfile(addr=0x40, data=0x0000, mask=0x0018) # TX_DATAPATH_SEL=0 (16/20)
+        elif mode == 1 or mode == 40:
+            datapath_sel = 1
+            self.wr_regfile(addr=0x2A, data=0x0001, mask=0x000C) # RX_DATAPATH_SEL=1
+            self.wr_regfile(addr=0x40, data=0x0008, mask=0x0018) # TX_DATAPATH_SEL=1 (32/40)
+        elif mode == 2 or mode == 3 or mode == 80:
+            datapath_sel = 3
+            self.wr_regfile(addr=0x2A, data=0x000C, mask=0x000C) # RX_DATAPATH_SEL=3
+            self.wr_regfile(addr=0x40, data=0x0018, mask=0x0018) # TX_DATAPATH_SEL=3 (64/80)
+        else:
+            print(f'ERROR: Invalid datapath configruation {mode}')
+
+    def check_serdes_datapath(self, mode):
+        check = 3 if mode == 80 else 1 if mode == 40 else 0 if mode == 20 else mode
+        word = self.rd_regfile(addr=0x2A)
+        if (int(word[2:3+1]) != check):
+            print(f'ERROR: RX_DATAPATH_SEL != {check} ({int(word[2:3+1]):2X})')
+        word = self.rd_regfile(addr=0x40)
+        if (int(word[3:4+1]) != check):
+            print(f'ERROR: TX_DATAPATH_SEL != {check} ({int(word[3:4+1]):2X})')
+
+    def reset_serdes_rx(self):
+        print('INFO:  Resetting SerDes RX')
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+        # RX reset
+        self.wr_regfile(addr=0x2B, data=0x0003, mask=0x0003) # RX_RESET_OVR=1, RX_RESET=1
+        self.wr_regfile(addr=0x3F, data=0x0000, mask=0x0003) # RX_RESET_OVR=0, RX_RESET=0
+        word = self.rd_regfile(addr=0x2C)
+        timeout = 5
+        while timeout > 0:
+            if (int(word[10]) != 1): # RX_RESET_DONE
+                timeout = timeout - 1
+                if timeout == 0:
+                    print(f'ERROR: RX_RESET_DONE timeout')
+            else:
+                break
+
+    def reset_serdes_trx(self):
+        self.reset_serdes_tx()
+        self.reset_serdes_rx()
+
+    def start_serdes_pll(self, n1=1, n2=2, n3=3, outdiv=4, calib=False):
+        print('INFO:  Configuring SerDes ADPLL')
+
+        if (n1 < 1 or n1 > 2):
+            print(f'ERROR: Main divider N1 is out of range 1..2')
+            return
+        if (n2 < 2 or n2 > 5):
+            print(f'ERROR: Main divider N2 is out of range 2..5')
+            return
+        if (n3 < 3 or n3 > 5):
+            print(f'ERROR: Main divider N3 is out of range 3..5')
+            return
+        if (outdiv != 1 and outdiv != 2 and outdiv != 4):
+            print(f'ERROR: Output divider N3 is limited to 1, 2 or 4')
+            return
+
+        dco = 1000.0 / SER_CLK_PERIOD_NS * n1 * n2 * n3
+        freq = dco / outdiv
+        print(f'INFO:  SerDes ADPLL frequency / data rate is {freq} MHz / {freq*2} Mbit/s')
+
+        status = self.rd_regfile_pll_status()
+        if (status[0] == 1):
+            print('INFO:  Disabling SerDes ADPLL')
+            self.wr_regfile(addr=0x50, data=0x0000, mask=0x0001)
+
+        if outdiv == 1:
+            pll_div = 0x0000
+        elif outdiv == 2:
+            pll_div = 0x1000
+        else:
+            pll_div = 0x3000
+        if n2 == 5:
+            pll_div = (pll_div & ~(0b11 << 6)) | (0b11 << 6)
+        elif n2 == 4:
+            pll_div = (pll_div & ~(0b11 << 6)) | (0b10 << 6)
+        elif n2 == 2:
+            pll_div = (pll_div & ~(0b11 << 6)) | (0b01 << 6)
+        if n1 == 2:
+            pll_div |= (1 << 8)
+        if n3 == 5:
+            pll_div = (pll_div & ~(0b11 << 9)) | (0b11 << 9)
+        elif n3 == 4:
+            pll_div = (pll_div & ~(0b11 << 9)) | (0b10 << 9)
+
+        print('INFO:  Writing SerDes ADPLL divider settings')
+        self.wr_regfile(addr=0x51, data=pll_div, mask=0x3FC0)
+
+        if (calib):
+            print('INFO:  Stopping SerDes ADPLL self-calibration')
+            self.wr_regfile(addr=0x57, data=0x0004, mask=0x0007)
+            self.wr_regfile(addr=0x57, data=
+                ((self.ADPLL_PFDAC_TIMER    & 0x000F) <<  3) |
+                ((self.ADPLL_PFDAC_COR_DLY  & 0x0007) << 10) |
+                ((self.ADPLL_PFDAC_CAL_SIGN & 0x0001) << 13) |
+                ((self.ADPLL_PFDAC_AUTO_CAL & 0x0001) << 14),
+                mask=0xFFF8)
+            self.wr_regfile(addr=0x58, data=
+                ((self.ADPLL_PFDAC_COR_DLY  & 0x001F) << 0) |
+                ((self.ADPLL_PFDAC_CAL_SIGN & 0x001F) << 5) |
+                ((self.ADPLL_PFDAC_AUTO_CAL & 0x001F) << 10),
+                mask=0xFFFF)
+
+        print('INFO:  Starting SerDes ADPLL')
+        self.wr_regfile(addr=0x50, data=0x0002, mask=0x0007)
+        self.wr_regfile(addr=0x50, data=0x0003, mask=0x0003)
+
+        if (calib):
+            print('INFO:  Starting SerDes ADPLL self-calibration')
+            self.wr_regfile(addr=0x57, data=0x0004, mask=0x0007)
+            self.wr_regfile(addr=0x57, data=0x0005, mask=0x0007) # BISC mode B, enable
+
+        timeout = 5
+        while timeout > 0:
+            sleep(0.5)
+            status = self.rd_regfile_pll_status()
+            if (status[0] == 0):
+                timeout = timeout - 1
+                print(f'INFO:  LCK: {int(status[0]):1d} FTO: {int(status[1]):1d} FTU: {int(status[2]):1d} FT: {int(status[3:12+1]):4d} SY: {int(status[16:23+1]):3d} ST: {int(status[13:14+1]):1d}')
+                if timeout == 0:
+                    print(f'ERROR: SerDes ADPLL lock timeout')
+            else:
+                print(f'INFO:  SerDes ADPLL locked')
+                break
+
+        if (calib):
+            result = self.rd_regfile_pll_bisc_status()
+            print(f'INFO:  PFDAC result: max reached: {int(result[0]):1d}, ac_result: {int(result[1:17+1]):6d}, CP: {int(result[18:22+1]):2d}')
+
+        print(f'INFO:  ADPLL status: LCK: {int(status[0]):1d} FTO: {int(status[1]):1d} FTU: {int(status[2]):1d} FT: {int(status[3:12+1]):4d} SY: {int(status[16:23+1]):3d} ST: {int(status[13:14+1]):1d}')
+
+    def tc_prbs(self, force_err=False):
+        print(f'INFO:  Starting SerDes PRBS testcases')
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+        # set 80-bit datapath
+        self.set_serdes_datapath(80)
+
+        self.start_serdes_pll(n1=1, n2=5, n3=5, outdiv=4, calib=True) # 1250 Mbit/s, PFDAC=on
+        self.reset_serdes_trx()
+
+        # check datapath
+        self.check_serdes_datapath(80)
+
+        # disable testmode?
+        self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=0, RX_PRBS_CNT_RESET=1
+
+        for i in range(0, 2):
+            prbs = 7 if i == 0 else 15 if i == 1 else 23 if i == 2 else 31 if i == 3 else 0
+            print(f'INFO:  Setting up PRBS-{prbs}')
+
+            self.wr_regfile(addr=0x40, data=((i+1) << 6) | (1 << 5), mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=i
+            word = self.rd_regfile(addr=0x40)
+            #if (word[5] == 1):
+            #    print(f'ERROR: TX PRBS overwrite is not disabled')
+            if (int(word[6:8+1]) != i+1):
+                print(f'ERROR: TX PRBS mode is invalid')
+
+            self.wr_regfile(addr=0x2A, data=((i+1) << 5) | (1 << 4), mask=0x00F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=i
+            word = self.rd_regfile(addr=0x2A)
+            #if (word[4] == 1):
+            #    print(f'ERROR: RX PRBS overwrite is not disabled')
+            if (word[9] == 1):
+                print(f'ERROR: RX_PRBS_CNT_RESET is active')
+            if (int(word[5:7+1]) != i+1):
+                print(f'ERROR: RX PRBS mode is invalid')
+
+            # send data
+            print(f'INFO:  Sending data (this might take a while) ...')
+            n = 10
+            for i in range(n):
+                print(f'INFO:  {i}/{n}')
+                sleep(1)
+
+            word = self.rd_regfile(addr=0x1F)
+            print(f'INFO:  RX_PRBS_LOCKED: {int(word[15]):1d}, RX_PRBS_ERR_CNT: {int(word[0:14+1]):X}')
+            if (word[15] == 0):
+                print(f'ERROR: RX PRBS did not lock')
+            if (int(word[0:14+1]) > 0):
+                print(f'ERROR: RX PRBS errors detected ({int(word[0:14+1])})')
+
+            if (force_err):
+                print(f'INFO:  Starting error injection')
+                self.wr_regfile(addr=0x40, data=0x0200, mask=0x0200) # TX_PRBS_FORCE_ERR=1
+                word = self.rd_regfile(addr=0x1F)
+                print(f'INFO:  RX_PRBS_LOCKED: {int(word[15]):1d}, RX_PRBS_ERR_CNT: {int(word[0:14+1]):X}')
+                if (int(word[0:14+1]) == 0):
+                    print(f'ERROR: RX PRBS error detection failed')
+
+            self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_CNT_RESET=1, RX_PRBS_OVR=1, RX_PRBS_SEL=0
+            self.wr_regfile(addr=0x40, data=0x0020, mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=0
+        return
+
+    def tc_uipattern(self, mode=0):
+        print(f'INFO:  Starting SerDes UI pattern testcase')
+
+        if not mode in [0,2,20,40,80]:
+            print(f'ERROR: Invalid UI pattern mode ({mode}), must be in [0,2,20,40,80]')
+            return
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+        # set datapath if mode in [20,40,80]
+        self.set_serdes_datapath(mode)
+
+        self.start_serdes_pll(n1=1, n2=2, n3=3, outdiv=4, calib=True) # 300 Mbit/s, PFDAC=on
+        self.reset_serdes_trx()
+
+        # check datapath
+        self.check_serdes_datapath(mode)
+
+        # disable testmode?
+        self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=0, RX_PRBS_CNT_RESET=1
+
+        print(f'INFO:  Setting up {mode} UI square wave')
+
+        i = 5 if mode == 2 else 6 if mode in [20,40,80] else 0
+        self.wr_regfile(addr=0x40, data=((i+1) << 6) | (1 << 5), mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=i
+        word = self.rd_regfile(addr=0x40)
+        if (int(word[6:8+1]) != i+1):
+            print(f'ERROR: TX PRBS mode is invalid')
+
+    def tc_eyemeas(self):
+        print(f'INFO:  Starting SerDes eye measurement')
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+    def tc_loopback(self):
+        print(f'INFO:  Starting SerDes loopback testcases')
+
+        word = self.rd_regfile(addr=0x5C)
+        if (word[0] != 1 or word[2] != 1):
+            print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}')
+            return
+
+        # testcases:
+        #
+        # 0: TX PMA (near-end, mode 1: pre-driver), TX_PMA_LOOPBACK=01 or TX_PMA_LOOPBACK=11
+        # 1: TX PMA (near-end, mode 2: pad), TX_PMA_LOOPBACK=10, NOTE: requires termination!
+        # 3: TX PCS (near-end)
+        for j in [0, 1, 3]:
+            if (j < 3):
+                print(f'\nINFO:  Enabling TX PMA Loopback (Mode {j:1d})')
+            else:
+                print(f'\nINFO:  Enabling TX PCS Loopback')
+
+            # TX_LOOPBACK_OVR=1 | TX_PMA_LOOPBACK=(001=pma-drv, 011=pma-drv, 010=pma-pad, 100=pcs)
+            self.wr_regfile(addr=0x40, data=(0x0400 | (j+1) & 0x7), mask=0x0407)
+            word = self.rd_regfile(addr=0x40)
+            if (word[10] == 0):
+                print(f'ERROR: TX loopback overwrite is not enabled')
+            if (int(word[0:1+1]) != j+1 and j < 3):
+                print(f'ERROR: TX PMA loopback is not enabled')
+            if (word[2] == 0 and j == 3):
+                print(f'ERROR: TX PCS loopback is not enabled')
+
+            # turn tx driver off
+            if (j == 1 or j == 3):
+                self.wr_regfile(addr=0x30, data=0x0000, mask=0x001F) # TODO TX_SEL_PRE=0, TX_SEL_POST=x, TX_AMP=x
+                self.wr_regfile(addr=0x31, data=0x07E0, mask=0x07E0) # TX_BRANCH_EN_MAIN=63
+                word = self.rd_regfile(addr=0x30)
+                if (int(word[0:4+1]) != 0):
+                    print(f'ERROR: Invalid TX_SEL_PRE driver setting')
+                word = self.rd_regfile(addr=0x31)
+                if (int(word[5:10+1]) != 63):
+                    print(f'ERROR: Invalid TX_BRANCH_EN_MAIN setting')
+            else:
+                self.wr_regfile(addr=0x30, data=0x0001, mask=0x001F) # TODO TX_SEL_PRE=1, TX_SEL_POST=x, TX_AMP=x
+                self.wr_regfile(addr=0x31, data=0x0000, mask=0x07E0) # TX_BRANCH_EN_MAIN=0
+                word = self.rd_regfile(addr=0x30)
+                if (int(word[0:4+1]) != 1):
+                    print(f'ERROR: Invalid TX_SEL_PRE driver setting')
+                word = self.rd_regfile(addr=0x31)
+                if (int(word[5:10+1]) != 0):
+                    print(f'ERROR: Invalid TX_BRANCH_EN_MAIN setting')
+
+            self.start_serdes_pll(n1=1, n2=5, n3=5, outdiv=4, calib=True) # 1250 Mbit/s, PFDAC=on
+            self.reset_serdes_trx()
+
+            self.wr_regfile(addr=0x41, data=0x00C0, mask=0x00C0) # TX_8B10B_EN_OVR=1, TX_8B10B_EN=1
+            self.wr_regfile(addr=0x2B, data=0xC000, mask=0xC000) # RX_8B10B_EN_OVR=1, RX_8B10B_EN=1
+
+            # 32-Bit comma alignment test
+            self.wr_regfile(addr=0x12, data=0x3000, mask=0x3000) # RX_ALIGN_COMMA_WORD=3 (32 bit)
+
+            # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001
+            self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC
+
+            self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1
+
+            print(f'INFO:  Sending data (this might take a while) ...')
+            sleep(2)
+
+            self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0
+            self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0
+
+            print(f'INFO:  Checking 32-Bit comma alignment')
+            rx_data, _ = self.rd_regfile_rx_data()
+            align_pos = 0 if int(rx_data[0:7+1]) == 0xBC else 1
+            rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else 0x4A4A4ABC4A4A4A4A
+
+            if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC):
+                print(f'ERROR: Comma is not aligned to 32-Bit boundary')
+            if (int(rx_data) != rx_recv):
+                print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}')
+
+            # 16-Bit comma alignment test
+            self.reset_serdes_trx()
+            self.wr_regfile(addr=0x12, data=0x1000, mask=0x3000) # RX_ALIGN_COMMA_WORD=1 (16 bit)
+
+            # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001
+            self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC
+
+            self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1
+
+            print(f'INFO:  Sending data (this might take a while) ...')
+            sleep(2)
+
+            self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0
+            self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0
+
+            print(f'INFO:  Checking 16-Bit comma alignment')
+            rx_data, _ = self.rd_regfile_rx_data()
+            align_pos = 0 if int(rx_data[  0:7+1]) == 0xBC else \
+                        1 if int(rx_data[16:23+1]) == 0xBC else \
+                        2 if int(rx_data[32:39+1]) == 0xBC else 3
+            rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else \
+                      0x4A4A4A4A4ABC4A4A if align_pos == 1 else \
+                      0x4A4A4ABC4A4A4A4A if align_pos == 2 else 0x4ABC4A4A4A4A4A4A
+
+            if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[16:23+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC and int(rx_data[48:55+1]) != 0xBC):
+                print(f'ERROR: Comma is not aligned to 16-Bit boundary')
+            if (int(rx_data) != rx_recv):
+                print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}')
+
+            # 8-Bit comma alignment test
+            self.reset_serdes_trx()
+            self.wr_regfile(addr=0x12, data=0x0000, mask=0x3000) # RX_ALIGN_COMMA_WORD=0 (8 bit)
+
+            # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001
+            self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC
+
+            self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1
+            self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1
+
+            print(f'INFO:  Sending data (this might take a while) ...')
+            sleep(2)
+
+            self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0
+            self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0
+
+            print(f'INFO:  Checking 8-Bit comma alignment')
+            rx_data, _ = self.rd_regfile_rx_data()
+            align_pos = 0 if int(rx_data[  0:7+1]) == 0xBC else \
+                        1 if int(rx_data[ 8:15+1]) == 0xBC else \
+                        2 if int(rx_data[16:23+1]) == 0xBC else \
+                        3 if int(rx_data[24:31+1]) == 0xBC else \
+                        4 if int(rx_data[32:39+1]) == 0xBC else \
+                        5 if int(rx_data[40:47+1]) == 0xBC else \
+                        6 if int(rx_data[48:55+1]) == 0xBC else 7
+            rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else \
+                      0x4A4A4A4A4A4ABC4A if align_pos == 1 else \
+                      0x4A4A4A4A4ABC4A4A if align_pos == 2 else \
+                      0x4A4A4A4ABC4A4A4A if align_pos == 3 else \
+                      0x4A4A4ABC4A4A4A4A if align_pos == 4 else \
+                      0x4A4ABC4A4A4A4A4A if align_pos == 5 else \
+                      0x4ABC4A4A4A4A4A4A if align_pos == 6 else 0xBC4A4A4A4A4A4A4A
+
+            if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[ 8:15+1]) != 0xBC and int(rx_data[16:23+1]) != 0xBC and int(rx_data[24:31+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC and int(rx_data[40:47+1]) != 0xBC and int(rx_data[48:55+1]) != 0xBC and int(rx_data[56:63+1]) != 0xBC):
+                print(f'ERROR: Comma is not aligned to 8-Bit boundary')
+            if (int(rx_data) != rx_recv):
+                print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}')
+
+    def calc_rxterm_vcm(self, vddio=1.0, vcmsel=None) -> float:
+        if vcmsel is None:
+            vcmsel = self.rd_regfile(addr=0x02)
+            vcmsel = int(vcmsel[11:13+1])
+        return (vcmsel/29) * vddio
+
+    def update_values(self):
+        while True:
+            sleep(0.5) # 500ms update interval
+            with self.param_lock:
+                #for param in self.regfile.fields:
+                #    self.regfile.fields[param]['val'] = random.randint(0, 16)
+                for addr in chain(range(0x00, 0x30), range(0x30, 0x43), range(0x50, 0x5D)):
+                    word = self.rd_regfile(addr)
+                    filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr}
+                    for (key, value) in filtered_entries.items():
+                        val = word[value['lbit']:value['hbit']+1]
+                        self.regfile.fields[key]['val'] = int(val)
+
+    def draw_parameters(self, stdscr):
+        curses.curs_set(0)
+        stdscr.keypad(True)
+        stdscr.timeout(10) #stdscr.nodelay(True)  # Non-blocking input
+
+        # Initialize colors
+        curses.start_color()
+        curses.init_pair(1, curses.COLOR_GREEN, curses.COLOR_BLACK)   # OK (Green)
+        curses.init_pair(2, curses.COLOR_YELLOW, curses.COLOR_BLACK)  # WARN (Yellow)
+        curses.init_pair(3, curses.COLOR_RED, curses.COLOR_BLACK)     # FAIL (Red)
+        curses.init_pair(4, curses.COLOR_BLUE, curses.COLOR_BLACK)    # OVR (Blue)
+        curses.init_pair(5, curses.COLOR_WHITE, curses.COLOR_BLACK)   # Normal text
+
+        def handle_resize(signum, frame):
+            curses.endwin()
+            stdscr.refresh()
+
+        signal.signal(signal.SIGWINCH, handle_resize)
+
+        selected_index = 0
+        show_hex = False
+        search_results = []
+        search_index = 0
+
+        while True:
+            max_y, max_x = stdscr.getmaxyx()
+            max_name_length = max(len(name) for name in self.regfile.fields.keys())
+            col_width = max_name_length + 8
+            num_columns = max(1, max_x // col_width)
+            num_rows = math.ceil(len(self.regfile.fields) / num_columns)
+            param_list = list(self.regfile.fields.items())
+
+            # Extract values for bit rate calculation
+            PLL_MAIN_DIVSEL = self.regfile.fields.get("PLL_MAIN_DIVSEL", {}).get("val", 0x1B)
+            PLL_OUT_DIVSEL = self.regfile.fields.get("PLL_OUT_DIVSEL", {}).get("val", 0x0)
+            TX_DATAPATH_SEL = self.regfile.fields.get("TX_DATAPATH_SEL", {}).get("val", 0x0)
+
+            # Decode PLL values
+            N3 = {0b00: 3, 0b10: 4, 0b11: 5}.get((PLL_MAIN_DIVSEL >> 3) & 0b11, None)
+            N1 = {0b0: 1, 0b1: 2}.get((PLL_MAIN_DIVSEL >> 2) & 0b1, None)
+            N2 = {0b00: 3, 0b01: 2, 0b10: 4, 0b11: 5}.get(PLL_MAIN_DIVSEL & 0b11, None)
+            OUTDIV = {0b00: 1, 0b01: 2, 0b11: 4}.get(PLL_OUT_DIVSEL, None)
+
+            bit_rate_clock = 2 * 100e6 * N1 * N2 * N3 / OUTDIV if None not in (N1, N2, N3, OUTDIV) else None
+
+            # Decode TX_DATAPATH_SEL
+            datapath_mode = (TX_DATAPATH_SEL & 0b10) >> 1  # Extract MSB
+            is_64_bit = datapath_mode == 1  # If `1x`, it is 64-bit
+
+            # Determine AddDiv based on OUTDIV
+            if is_64_bit:
+                AddDiv = {0b00: 2, 0b01: 4, 0b11: 8}.get(PLL_OUT_DIVSEL, None)
+            else:
+                AddDiv = {0b00: 1, 0b01: 2, 0b11: 4}.get(PLL_OUT_DIVSEL, None)
+
+            PLL_FCNTRL = self.regfile.fields.get("PLL_FCNTRL", {}).get("val", 0x0)
+            data_path_clock = (100e6 * N1 * N2 * N3) / (self.olclkg[PLL_FCNTRL] * AddDiv) if None not in (N1, N2, N3, OUTDIV, AddDiv) else None
+
+            bit_rate_str = f"Bit Rate Clock: {bit_rate_clock / 1e6:.2f} MHz" if bit_rate_clock else "Invalid PLL Config"
+            data_path_str = f"TX Data Path Clock: {data_path_clock / 1e6:.2f} MHz" if data_path_clock else "Invalid Data Path Config"
+
+            stdscr.clear()
+            stdscr.addstr(0, 2, " FPGA SerDes Parameters (Auto-Update Enabled) ", curses.A_BOLD | curses.A_REVERSE)
+
+            with self.param_lock:
+                for row in range(num_rows):
+                    for col in range(num_columns):
+                        index = row + col * num_rows
+                        if index >= len(param_list):
+                            continue
+
+                        name, data = param_list[index]
+                        value = data['val']
+                        mode = data['mode']  # Get mode (R/W, W/C, R/C, R)
+                        color_pair = ColorFormatter.get_color_pair(name, value)
+
+                        formatted_value = f"0x{value:X}" if show_hex else f"{value}"
+
+                        # Read-only and Write/Clear (dimmed text)
+                        text_attr = curses.color_pair(color_pair) | curses.A_DIM if mode in ["R", "R/C"] else curses.color_pair(color_pair)
+
+                        x_pos = col * col_width + 2
+                        y_pos = row + 2
+
+                        # Highlight selected row
+                        if index == selected_index:
+                            stdscr.addstr(y_pos, x_pos, f"{name:<{max_name_length}} {formatted_value:<8}", curses.A_REVERSE)
+                        else:
+                            # Print parameter name (dimmed for R & W/C)
+                            stdscr.addstr(y_pos, x_pos, f"{name:<{max_name_length}}", text_attr)
+
+                            # Print value in color
+                            stdscr.addstr(y_pos, x_pos + max_name_length + 1, f"{formatted_value:<8}", curses.color_pair(color_pair))
+
+
+            stdscr.addstr(max_y - 5, 2, bit_rate_str)
+            stdscr.addstr(max_y - 4, 2, data_path_str)
+
+            search_hint = "[n] Next match  |  " if search_results else ""
+            stdscr.addstr(max_y - 2, 2, f"{search_hint}[Arrow Keys] Navigate | [Enter] Edit | [/] Find | [h] Toggle HEX/DEC | [q] Quit", curses.A_BOLD)
+
+            stdscr.refresh()
+
+            try:
+                key = stdscr.getch()
+            except curses.error:
+                key = -1  # No input
+
+            if key == ord("h"):
+                show_hex = not show_hex
+            elif key == curses.KEY_UP and selected_index - 1 >= 0:
+                selected_index -= 1
+            elif key == curses.KEY_DOWN and selected_index + 1 < len(param_list):
+                selected_index += 1
+            elif key == curses.KEY_LEFT and selected_index - num_rows >= 0:
+                selected_index -= num_rows
+            elif key == curses.KEY_RIGHT and selected_index + num_rows < len(param_list):
+                selected_index += num_rows
+            elif key == ord("\n"):
+                if param_list[selected_index][1]['mode'] in ["R", "R/C"]:
+                    self.error_message(stdscr, "Cannot edit read-only parameter!")
+                else:
+                    self.edit_value_popup(stdscr, param_list[selected_index])
+            elif key == ord("/"):
+                search_results, search_index = self.find_parameter(stdscr, param_list)
+                if search_results:
+                    selected_index = search_results[search_index]
+            elif key == ord("n") and search_results:
+                search_index = (search_index + 1) % len(search_results)
+                selected_index = search_results[search_index]
+            elif key == ord("q"):
+                break
+
+    def edit_value_popup(self, stdscr, param):
+        name, data = param
+        max_y, max_x = stdscr.getmaxyx()
+
+        # Calculate the valid range from `hbit` and `lbit`
+        hbit, lbit = data['hbit'], data['lbit']
+        mask = ((1 << (hbit - lbit + 1)) - 1) << lbit
+        addr = data['addr']
+        min_value = 0
+        max_value = (1 << (hbit - lbit + 1)) - 1  # Compute max based on bit range
+
+        win_height, win_width = 9, 50
+        start_y = (max_y - win_height) // 2
+        start_x = (max_x - win_width) // 2
+
+        win = curses.newwin(win_height, win_width, start_y, start_x)
+        win.box()
+        win.addstr(1, 2, f"Editing:  {name}", curses.A_BOLD)
+        win.addstr(2, 2, f"Position: addr=0x{addr:02X} mask=0x{mask:04X}")
+        win.addstr(3, 2, f"Current:  {data['val']}  (Range: {min_value} - {max_value})")  # Show valid range
+        win.addstr(5, 2, "New value: ")
+        win.addstr(7, 2, "[Enter] Save  |  [ESC/q] Cancel", curses.A_DIM)
+
+        win.refresh()
+        curses.curs_set(1)
+        win.keypad(True)
+
+        curses.echo()
+        new_val = ""
+
+        while True:
+            key = win.getch()
+
+            if key in (27, ord("q")):
+                break
+            elif key == ord("\n"):
+                try:
+                    entered_value = int(new_val, 0)  # Convert input to integer
+                    if min_value <= entered_value <= max_value:
+                        with self.param_lock:
+                            #data['val'] = entered_value  # Apply change if within range
+                            self._tool.wr_serdes_regfile(addr=addr, data=entered_value << lbit, mask=mask, wren=1)
+                            self._tool.rd_serdes_regfile()
+                        break
+                    else:
+                        win.addstr(6, 2, "Out of range! Try again.", curses.A_BOLD | curses.color_pair(3))
+                        win.refresh()
+                        time.sleep(1)
+                        win.addstr(6, 2, " " * 30)  # Clear error message
+                except ValueError:
+                    win.addstr(6, 2, "Invalid input!", curses.A_BOLD | curses.color_pair(3))
+                    win.refresh()
+                    time.sleep(1)
+                    win.addstr(6, 2, " " * 30)  # Clear error message
+            elif key in (curses.KEY_BACKSPACE, 127):
+                new_val = new_val[:-1]
+                win.addstr(5, 13, " " * 10)  # Clear previous input
+            elif key in range(32, 127):
+                new_val += chr(key)
+
+            win.addstr(5, 13, new_val)
+            win.refresh()
+
+        curses.noecho()
+        curses.curs_set(0)
+
+    def find_parameter(self, stdscr, param_list):
+        max_y, max_x = stdscr.getmaxyx()
+        win_height, win_width = 4, 50
+        start_y = (max_y - win_height) // 2
+        start_x = (max_x - win_width) // 2
+
+        win = curses.newwin(win_height, win_width, start_y, start_x)
+        win.box()
+        win.addstr(1, 2, "Find: ")
+        win.addstr(2, 2, "[ESC/q] Cancel", curses.A_DIM)
+
+        win.refresh()
+        curses.curs_set(1)
+        curses.echo()
+
+        search_term = ""
+
+        while True:
+            key = win.getch()
+
+            if key in (27, ord("q")):
+                return [], 0
+            elif key == ord("\n"):
+                break
+            elif key in (curses.KEY_BACKSPACE, 127):
+                search_term = search_term[:-1]
+                win.addstr(1, 8, " " * 40)
+            elif key in range(32, 127):
+                search_term += chr(key)
+
+            win.addstr(1, 8, search_term)
+            win.refresh()
+
+        curses.noecho()
+        curses.curs_set(0)
+
+        search_term = search_term.strip().lower()
+
+        if not search_term:
+            return [], 0
+
+        matches = [i for i, (name, _) in enumerate(param_list) if search_term in name.lower()]
+
+        if not matches:
+            self.error_message(stdscr, "No matches found!")
+            return [], 0
+
+        return matches, 0
+
+    def error_message(self, stdscr, message):
+        max_y, max_x = stdscr.getmaxyx()
+        win_height, win_width = 3, len(message) + 10
+        start_y = (max_y - win_height) // 2
+        start_x = (max_x - win_width) // 2
+
+        win = curses.newwin(win_height, win_width, start_y, start_x)
+        win.box()
+        win.addstr(1, 2, message, curses.A_BOLD)
+
+        win.refresh()
+        curses.napms(1500)
+        del win
+
+
+if __name__ == '__main__':
+    try:
+        p = argparse.ArgumentParser(prog='serdestool', description='', epilog=ArgEpilog)
+
+        p.add_argument('-l', '--list', dest='listdev', action='store_true', help='list available boards/programmers and exit')
+        p.add_argument('-b', dest='board', type=str, metavar=Boards_e, default=Boards_e[0], required=False, help='select board (default: %(default)s)')
+        p.add_argument('--index-chain', dest='idx', default=0, required=False, help='device index in JTAG chain (default: %(default)s)')
+        p.add_argument('--freq', type=ArgHzRegex, default='20M', metavar="[0 - 30M]", required=False, help='frequency setting; append "k" to the argument for kilohertz or "M" for megahertz (default: %(default)s)')
+        p.add_argument('-m', dest='genmod', type=str, required=False, help='generate verilog or vhdl module and exit; specify the file format with extension .v or .vhd')
+        p.add_argument('--rdregrx', dest='rdregrx', action='store_true', help='read rx regfile')
+        p.add_argument('--rdregrxdata', dest='rdregrxdata', action='store_true', help='read rx data')
+        p.add_argument('--rdregtx', dest='rdregtx', action='store_true', help='read tx regfile')
+        p.add_argument('--rdregpll', dest='rdregpll', action='store_true', help='read pll regfile')
+        p.add_argument('--rdstatuspll', dest='rdstatuspll', action='store_true', help='read pll status registers')
+        p.add_argument('--gui', dest='gui', action='store_true', help='start curses gui')
+        p.add_argument('--tcprbs', dest='tcprbs', action='store_true', help='testcase: prbs')
+        p.add_argument('--tcloopback', dest='tcloopback', action='store_true', help='testcase: loopback')
+        p.add_argument('--tcuipattern', dest='tcuipattern', choices=['0','2','20','40','80'], default=None, required=False, help='testcase: 2,20,40,80 UI square wave pattern')
+
+        args = p.parse_args()
+        usb  = UsbTools()
+        jtag = JtagEngine(frequency=ArgHzParse(args.freq))
+
+        if args.listdev:
+            vps_lst = list()
+            vps_lst.append((0x0403, 0x6010)) # evb: FT2232H
+            vps_lst.append((0x0403, 0x6014)) # pgm: FT232H
+            for line in usb.find_all(vps=vps_lst):
+                print(*line)
+            sys.exit()
+
+        s = SerdesTool(args, jtag, hwinit=not args.genmod)
+
+        if args.genmod is not None:
+            filename = args.genmod.lower()
+            if filename.endswith('.v') or filename.endswith('.sv'):
+                s.gen_module_vlog(filename)
+            elif filename.endswith('.vhd') or filename.endswith('.vhdl'):
+                s.gen_module_vhdl(filename)
+            sys.exit()
+
+        if args.gui:
+            update_thread = threading.Thread(target=s.update_values, daemon=True)
+            update_thread.start()
+            curses.wrapper(s.draw_parameters)
+        else:
+            if args.tcprbs:
+                s.tc_prbs(force_err=True)
+            if args.tcloopback:
+                s.tc_loopback()
+            if args.tcuipattern is not None:
+                s.tc_uipattern(int(args.tcuipattern))
+            if args.rdregrx:
+                s.rd_regfile_rx(verbose=2)
+            if args.rdregrxdata:
+                s.print_regfile_rx_data(verbose=2)
+            if args.rdregtx:
+                s.rd_regfile_tx(verbose=2)
+            if args.rdregpll:
+                s.rd_regfile_pll(verbose=2)
+            if args.rdstatuspll:
+                [s._tool.rd_status_pll(pll=i, verbose=1) for i in range(4)]
+
+    except Exception as e:
+        print(e)

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/README.md

@@ -0,0 +1,102 @@
+[> Bare Metal Demo App
+----------------------
+
+This directory provides a minimal bare metal demo app that demonstrates how to easily create a bare metal C application and load it/run it on the CPU of a SoC.
+
+[> Build and Load over LiteX-Term
+---------------------------------
+
+To build a LiteX SoC for the Arty board (available in LiteX-Boards) and build the demo app for it, execute the following commands:
+```
+python3 -m litex_boards.targets.digilent_arty --build --load
+litex_bare_metal_demo --build-path=build/digilent_arty
+```
+Where `--build-path` is the build path to the Arty build directory. The Arty board is used here but almost any another board supported in LiteX-Boards could be used. When no external RAM is provided directly by the board, `--integrated-main-ram-size` argument could be used to add some integrated RAM in the SoC and be able to execute the demo from it. (ex `--integrated-main-ram-size=0x8000` will add 32KB of integrated RAM).
+
+Loading the compiled demo app can be done in different ways as explain in LiteX's wiki:
+https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU
+
+Since our app is small and for simplicity we'll just load it over serial here:
+ `$ litex_term /dev/ttyUSBX --kernel=demo.bin`
+
+You should see the minimal demo app running and should be able to interact with it:
+
+    --============== Boot ==================--
+    Booting from serial...
+    Press Q or ESC to abort boot completely.
+    sL5DdSMmkekro
+    [LITEX-TERM] Received firmware download request from the device.
+    [LITEX-TERM] Uploading demo.bin to 0x40000000 (9264 bytes)...
+    [LITEX-TERM] Upload complete (9.8KB/s).
+    [LITEX-TERM] Booting the device.
+    [LITEX-TERM] Done.
+    Executing booted program at 0x40000000
+
+    --============= Liftoff! ===============--
+
+    LiteX minimal demo app built Dec 10 2020 17:13:02
+
+    Available commands:
+    help               - Show this command
+    reboot             - Reboot CPU
+    led                - Led demo
+    donut              - Spinning Donut demo
+    litex-demo-app> led
+    Led demo...
+    Counter mode...
+    Shift mode...
+    Dance mode...
+    litex-demo-app> donut
+    Donut demo...
+
+                                          $$$$$@@@@@
+                                      $##########$$$$$$$$
+                                   ###*!!!!!!!!!***##$$$$$$
+                                 ***!!====;;;;===!!**###$$$$#
+                                **!===;;;:::::;:===!!**####$##
+                              !*!!==;;:~-,,.,-~::;;=!!**#######!
+                              !!!!=;:~-,.......-~::==!!***#####*
+                             !!!!==;~~-.........,-:;==!!***###**!
+                             !**!!=;:~-...     ..-:;=!!!********!
+                            ;!*#####*!!;.       ~:;==!!!******!!=
+                            :!*###$$$$#*!      :;==!!!!!****!!!=;
+                            ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=;
+                             ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~
+                             -;!*###$$$$$$$###******!!!!!!!===;~
+                              -;!!*####$#####******!!!!!!==;;:-
+                               ,:=!!!!**#**#***!!!!!!!====;:~,
+                                 -:==!!!*!!*!!!!!!!===;;;:~-
+                                   .~:;;========;=;;:::~-,
+                                      .--~~::::~:~~--,.
+    litex-demo-app>
+
+[> Replace the LiteX BIOS with the Demo App
+-------------------------------------------
+In some cases, we'll just want to replace the LiteX BIOS with our custom app. This demo can be used as a basis to create a such custom app.
+
+The demo will be recompiled to target the ROM of the SoC:
+```
+litex_bare_metal_demo --build-path=build/arty/ --mem=rom
+```
+
+The SoC can then be re-compiled to integrate the demo app in the ROM with:
+```
+python3 -m litex_boards.targets.digilent_arty --integrated-rom-init=demo.bin --build --load
+```
+
+When loading the bitstream, you should then directly see the demo app executed:
+```
+    LiteX minimal demo app built Dec 10 2020 17:13:02
+
+    Available commands:
+    help               - Show this command
+    reboot             - Reboot CPU
+    led                - Led demo
+    donut              - Spinning Donut demo
+    litex-demo-app>
+```
+
+
+[> Going further
+----------------
+To create more complex apps, feel free to explore the source code of the BIOS or other open source projects build with LiteX at https://github.com/enjoy-digital/litex/wiki/Projects.

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo.py

@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import sys
+import argparse
+
+from litex.build.tools import replace_in_file
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.")
+    parser.add_argument("--build-path",                      help="Target's build path (ex build/board_name).", required=True)
+    parser.add_argument("--with-cxx",   action="store_true", help="Enable CXX support.")
+    parser.add_argument("--mem",        default="main_ram",  help="Memory Region where code will be loaded/executed.")
+    args = parser.parse_args()
+
+    # Create demo directory
+    os.makedirs("demo", exist_ok=True)
+
+    # Copy contents to demo directory
+    os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo")
+    os.system("chmod -R u+w demo") # Nix specific: Allow linker script to be modified.
+
+    # Update memory region.
+    replace_in_file("demo/linker.ld", "main_ram", args.mem)
+
+    # Compile demo
+    build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path)
+    os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make")
+
+    # Copy demo.bin
+    os.system("cp demo/demo.bin ./")
+
+    # Prepare flash boot image.
+    python3 = sys.executable or "python3" # Nix specific: Reuse current Python executable if available.
+    os.system(f"{python3} -m litex.soc.software.crcfbigen demo.bin -o demo.fbi --fbi --little") # FIXME: Endianness.
+
+if __name__ == "__main__":
+    main()
+

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/README.md

@@ -0,0 +1,102 @@
+[> Bare Metal Demo App
+----------------------
+
+This directory provides a minimal bare metal demo app that demonstrates how to easily create a bare metal C application and load it/run it on the CPU of a SoC.
+
+[> Build and Load over LiteX-Term
+---------------------------------
+
+To build a LiteX SoC for the Arty board (available in LiteX-Boards) and build the demo app for it, execute the following commands:
+```
+python3 -m litex_boards.targets.digilent_arty --build --load
+litex_bare_metal_demo --build-path=build/digilent_arty
+```
+Where `--build-path` is the build path to the Arty build directory. The Arty board is used here but almost any another board supported in LiteX-Boards could be used. When no external RAM is provided directly by the board, `--integrated-main-ram-size` argument could be used to add some integrated RAM in the SoC and be able to execute the demo from it. (ex `--integrated-main-ram-size=0x8000` will add 32KB of integrated RAM).
+
+Loading the compiled demo app can be done in different ways as explain in LiteX's wiki:
+https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU
+
+Since our app is small and for simplicity we'll just load it over serial here:
+ `$ litex_term /dev/ttyUSBX --kernel=demo.bin`
+
+You should see the minimal demo app running and should be able to interact with it:
+
+    --============== Boot ==================--
+    Booting from serial...
+    Press Q or ESC to abort boot completely.
+    sL5DdSMmkekro
+    [LITEX-TERM] Received firmware download request from the device.
+    [LITEX-TERM] Uploading demo.bin to 0x40000000 (9264 bytes)...
+    [LITEX-TERM] Upload complete (9.8KB/s).
+    [LITEX-TERM] Booting the device.
+    [LITEX-TERM] Done.
+    Executing booted program at 0x40000000
+
+    --============= Liftoff! ===============--
+
+    LiteX minimal demo app built Dec 10 2020 17:13:02
+
+    Available commands:
+    help               - Show this command
+    reboot             - Reboot CPU
+    led                - Led demo
+    donut              - Spinning Donut demo
+    litex-demo-app> led
+    Led demo...
+    Counter mode...
+    Shift mode...
+    Dance mode...
+    litex-demo-app> donut
+    Donut demo...
+
+                                          $$$$$@@@@@
+                                      $##########$$$$$$$$
+                                   ###*!!!!!!!!!***##$$$$$$
+                                 ***!!====;;;;===!!**###$$$$#
+                                **!===;;;:::::;:===!!**####$##
+                              !*!!==;;:~-,,.,-~::;;=!!**#######!
+                              !!!!=;:~-,.......-~::==!!***#####*
+                             !!!!==;~~-.........,-:;==!!***###**!
+                             !**!!=;:~-...     ..-:;=!!!********!
+                            ;!*#####*!!;.       ~:;==!!!******!!=
+                            :!*###$$$$#*!      :;==!!!!!****!!!=;
+                            ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=;
+                             ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~
+                             -;!*###$$$$$$$###******!!!!!!!===;~
+                              -;!!*####$#####******!!!!!!==;;:-
+                               ,:=!!!!**#**#***!!!!!!!====;:~,
+                                 -:==!!!*!!*!!!!!!!===;;;:~-
+                                   .~:;;========;=;;:::~-,
+                                      .--~~::::~:~~--,.
+    litex-demo-app>
+
+[> Replace the LiteX BIOS with the Demo App
+-------------------------------------------
+In some cases, we'll just want to replace the LiteX BIOS with our custom app. This demo can be used as a basis to create a such custom app.
+
+The demo will be recompiled to target the ROM of the SoC:
+```
+litex_bare_metal_demo --build-path=build/arty/ --mem=rom
+```
+
+The SoC can then be re-compiled to integrate the demo app in the ROM with:
+```
+python3 -m litex_boards.targets.digilent_arty --integrated-rom-init=demo.bin --build --load
+```
+
+When loading the bitstream, you should then directly see the demo app executed:
+```
+    LiteX minimal demo app built Dec 10 2020 17:13:02
+
+    Available commands:
+    help               - Show this command
+    reboot             - Reboot CPU
+    led                - Led demo
+    donut              - Spinning Donut demo
+    litex-demo-app>
+```
+
+
+[> Going further
+----------------
+To create more complex apps, feel free to explore the source code of the BIOS or other open source projects build with LiteX at https://github.com/enjoy-digital/litex/wiki/Projects.

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/demo.py

@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2020-2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import sys
+import argparse
+
+from litex.build.tools import replace_in_file
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.")
+    parser.add_argument("--build-path",                      help="Target's build path (ex build/board_name).", required=True)
+    parser.add_argument("--with-cxx",   action="store_true", help="Enable CXX support.")
+    parser.add_argument("--mem",        default="main_ram",  help="Memory Region where code will be loaded/executed.")
+    args = parser.parse_args()
+
+    # Create demo directory
+    os.makedirs("demo", exist_ok=True)
+
+    # Copy contents to demo directory
+    os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo")
+    os.system("chmod -R u+w demo") # Nix specific: Allow linker script to be modified.
+
+    # Update memory region.
+    replace_in_file("demo/linker.ld", "main_ram", args.mem)
+
+    # Compile demo
+    build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path)
+    os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make")
+
+    # Copy demo.bin
+    os.system("cp demo/demo.bin ./")
+
+    # Prepare flash boot image.
+    python3 = sys.executable or "python3" # Nix specific: Reuse current Python executable if available.
+    os.system(f"{python3} -m litex.soc.software.crcfbigen demo.bin -o demo.fbi --fbi --little") # FIXME: Endianness.
+
+if __name__ == "__main__":
+    main()
+

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/donut.c

@@ -0,0 +1,68 @@
+// The donut code with fixed-point arithmetic; no sines, cosines, square roots, or anything.
+// a1k0n 2020
+// Code from: https://gist.github.com/a1k0n/80f48aa8911fffd805316b8ba8f48e83
+// For more info:
+// - https://www.a1k0n.net/2011/07/20/donut-math.html
+// - https://www.youtube.com/watch?v=DEqXNfs_HhY
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <libbase/console.h>
+
+#define R(mul,shift,x,y) \
+  _=x; \
+  x -= mul*y>>shift; \
+  y += mul*_>>shift; \
+  _ = 3145728-x*x-y*y>>11; \
+  x = x*_>>10; \
+  y = y*_>>10;
+
+signed char b[1760], z[1760];
+
+void donut(void);
+void donut(void) {
+  int sA=1024,cA=0,sB=1024,cB=0,_;
+  for (;;) {
+    memset(b, 32, 1760);  // text buffer
+    memset(z, 127, 1760);   // z buffer
+    int sj=0, cj=1024;
+    for (int j = 0; j < 90; j++) {
+      int si = 0, ci = 1024;  // sine and cosine of angle i
+      for (int i = 0; i < 324; i++) {
+        int R1 = 1, R2 = 2048, K2 = 5120*1024;
+
+        int x0 = R1*cj + R2,
+            x1 = ci*x0 >> 10,
+            x2 = cA*sj >> 10,
+            x3 = si*x0 >> 10,
+            x4 = R1*x2 - (sA*x3 >> 10),
+            x5 = sA*sj >> 10,
+            x6 = K2 + R1*1024*x5 + cA*x3,
+            x7 = cj*si >> 10,
+            x = 40 + 30*(cB*x1 - sB*x4)/x6,
+            y = 12 + 15*(cB*x4 + sB*x1)/x6,
+            N = (-cA*x7 - cB*((-sA*x7>>10) + x2) - ci*(cj*sB >> 10) >> 10) - x5 >> 7;
+
+        int o = x + 80 * y;
+        signed char zz = (x6-K2)>>15;
+        if (22 > y && y > 0 && x > 0 && 80 > x && zz < z[o]) {
+          z[o] = zz;
+          b[o] = ".,-~:;=!*#$@"[N > 0 ? N : 0];
+        }
+        R(5, 8, ci, si)  // rotate i
+      }
+      R(9, 7, cj, sj)  // rotate j
+    }
+    for (int k = 0; 1761 > k; k++)
+      putchar(k % 80 ? b[k] : 10);
+    R(5, 7, cA, sA);
+    R(5, 8, cB, sB);
+  	if (readchar_nonblock()) {
+  		getchar();
+  		break;
+  	}
+    fputs("\x1b[23A", stdout);
+  }
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/helloc.c

@@ -0,0 +1,6 @@
+#include <stdio.h>
+
+void helloc(void);
+void helloc(void) {
+  printf("C: Hello, world!\n");
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/hellocpp.cpp

@@ -0,0 +1,7 @@
+#include <stdio.h>
+
+extern "C" void hellocpp(void);
+void hellocpp(void)
+{
+    printf("C++: Hello, world!\n");
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/main.c

@@ -0,0 +1,210 @@
+// This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+// License: BSD
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <irq.h>
+#include <libbase/uart.h>
+#include <libbase/console.h>
+#include <generated/csr.h>
+
+/*-----------------------------------------------------------------------*/
+/* Uart                                                                  */
+/*-----------------------------------------------------------------------*/
+
+static char *readstr(void)
+{
+	char c[2];
+	static char s[64];
+	static int ptr = 0;
+
+	if(readchar_nonblock()) {
+		c[0] = getchar();
+		c[1] = 0;
+		switch(c[0]) {
+			case 0x7f:
+			case 0x08:
+				if(ptr > 0) {
+					ptr--;
+					fputs("\x08 \x08", stdout);
+				}
+				break;
+			case 0x07:
+				break;
+			case '\r':
+			case '\n':
+				s[ptr] = 0x00;
+				fputs("\n", stdout);
+				ptr = 0;
+				return s;
+			default:
+				if(ptr >= (sizeof(s) - 1))
+					break;
+				fputs(c, stdout);
+				s[ptr] = c[0];
+				ptr++;
+				break;
+		}
+	}
+
+	return NULL;
+}
+
+static char *get_token(char **str)
+{
+	char *c, *d;
+
+	c = (char *)strchr(*str, ' ');
+	if(c == NULL) {
+		d = *str;
+		*str = *str+strlen(*str);
+		return d;
+	}
+	*c = 0;
+	d = *str;
+	*str = c+1;
+	return d;
+}
+
+static void prompt(void)
+{
+	printf("\e[92;1mlitex-demo-app\e[0m> ");
+}
+
+/*-----------------------------------------------------------------------*/
+/* Help                                                                  */
+/*-----------------------------------------------------------------------*/
+
+static void help(void)
+{
+	puts("\nLiteX minimal demo app built "__DATE__" "__TIME__"\n");
+	puts("Available commands:");
+	puts("help               - Show this command");
+	puts("reboot             - Reboot CPU");
+#ifdef CSR_LEDS_BASE
+	puts("led                - Led demo");
+#endif
+	puts("donut              - Spinning Donut demo");
+	puts("helloc             - Hello C");
+#ifdef WITH_CXX
+	puts("hellocpp           - Hello C++");
+#endif
+}
+
+/*-----------------------------------------------------------------------*/
+/* Commands                                                              */
+/*-----------------------------------------------------------------------*/
+
+static void reboot_cmd(void)
+{
+	ctrl_reset_write(1);
+}
+
+#ifdef CSR_LEDS_BASE
+static void led_cmd(void)
+{
+	int i;
+	printf("Led demo...\n");
+
+	printf("Counter mode...\n");
+	for(i=0; i<32; i++) {
+		leds_out_write(i);
+		busy_wait(100);
+	}
+
+	printf("Shift mode...\n");
+	for(i=0; i<4; i++) {
+		leds_out_write(1<<i);
+		busy_wait(200);
+	}
+	for(i=0; i<4; i++) {
+		leds_out_write(1<<(3-i));
+		busy_wait(200);
+	}
+
+	printf("Dance mode...\n");
+	for(i=0; i<4; i++) {
+		leds_out_write(0x55);
+		busy_wait(200);
+		leds_out_write(0xaa);
+		busy_wait(200);
+	}
+}
+#endif
+
+extern void donut(void);
+
+static void donut_cmd(void)
+{
+	printf("Donut demo...\n");
+	donut();
+}
+
+extern void helloc(void);
+
+static void helloc_cmd(void)
+{
+	printf("Hello C demo...\n");
+	helloc();
+}
+
+#ifdef WITH_CXX
+extern void hellocpp(void);
+
+static void hellocpp_cmd(void)
+{
+	printf("Hello C++ demo...\n");
+	hellocpp();
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Console service / Main                                                */
+/*-----------------------------------------------------------------------*/
+
+static void console_service(void)
+{
+	char *str;
+	char *token;
+
+	str = readstr();
+	if(str == NULL) return;
+	token = get_token(&str);
+	if(strcmp(token, "help") == 0)
+		help();
+	else if(strcmp(token, "reboot") == 0)
+		reboot_cmd();
+#ifdef CSR_LEDS_BASE
+	else if(strcmp(token, "led") == 0)
+		led_cmd();
+#endif
+	else if(strcmp(token, "donut") == 0)
+		donut_cmd();
+	else if(strcmp(token, "helloc") == 0)
+		helloc_cmd();
+#ifdef WITH_CXX
+	else if(strcmp(token, "hellocpp") == 0)
+		hellocpp_cmd();
+#endif
+	prompt();
+}
+
+int main(void)
+{
+#ifdef CONFIG_CPU_HAS_INTERRUPT
+	irq_setmask(0);
+	irq_setie(1);
+#endif
+	uart_init();
+
+	help();
+	prompt();
+
+	while(1) {
+		console_service();
+	}
+
+	return 0;
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/donut.c

@@ -0,0 +1,68 @@
+// The donut code with fixed-point arithmetic; no sines, cosines, square roots, or anything.
+// a1k0n 2020
+// Code from: https://gist.github.com/a1k0n/80f48aa8911fffd805316b8ba8f48e83
+// For more info:
+// - https://www.a1k0n.net/2011/07/20/donut-math.html
+// - https://www.youtube.com/watch?v=DEqXNfs_HhY
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <libbase/console.h>
+
+#define R(mul,shift,x,y) \
+  _=x; \
+  x -= mul*y>>shift; \
+  y += mul*_>>shift; \
+  _ = 3145728-x*x-y*y>>11; \
+  x = x*_>>10; \
+  y = y*_>>10;
+
+signed char b[1760], z[1760];
+
+void donut(void);
+void donut(void) {
+  int sA=1024,cA=0,sB=1024,cB=0,_;
+  for (;;) {
+    memset(b, 32, 1760);  // text buffer
+    memset(z, 127, 1760);   // z buffer
+    int sj=0, cj=1024;
+    for (int j = 0; j < 90; j++) {
+      int si = 0, ci = 1024;  // sine and cosine of angle i
+      for (int i = 0; i < 324; i++) {
+        int R1 = 1, R2 = 2048, K2 = 5120*1024;
+
+        int x0 = R1*cj + R2,
+            x1 = ci*x0 >> 10,
+            x2 = cA*sj >> 10,
+            x3 = si*x0 >> 10,
+            x4 = R1*x2 - (sA*x3 >> 10),
+            x5 = sA*sj >> 10,
+            x6 = K2 + R1*1024*x5 + cA*x3,
+            x7 = cj*si >> 10,
+            x = 40 + 30*(cB*x1 - sB*x4)/x6,
+            y = 12 + 15*(cB*x4 + sB*x1)/x6,
+            N = (-cA*x7 - cB*((-sA*x7>>10) + x2) - ci*(cj*sB >> 10) >> 10) - x5 >> 7;
+
+        int o = x + 80 * y;
+        signed char zz = (x6-K2)>>15;
+        if (22 > y && y > 0 && x > 0 && 80 > x && zz < z[o]) {
+          z[o] = zz;
+          b[o] = ".,-~:;=!*#$@"[N > 0 ? N : 0];
+        }
+        R(5, 8, ci, si)  // rotate i
+      }
+      R(9, 7, cj, sj)  // rotate j
+    }
+    for (int k = 0; 1761 > k; k++)
+      putchar(k % 80 ? b[k] : 10);
+    R(5, 7, cA, sA);
+    R(5, 8, cB, sB);
+  	if (readchar_nonblock()) {
+  		getchar();
+  		break;
+  	}
+    fputs("\x1b[23A", stdout);
+  }
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/helloc.c

@@ -0,0 +1,6 @@
+#include <stdio.h>
+
+void helloc(void);
+void helloc(void) {
+  printf("C: Hello, world!\n");
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/hellocpp.cpp

@@ -0,0 +1,7 @@
+#include <stdio.h>
+
+extern "C" void hellocpp(void);
+void hellocpp(void)
+{
+    printf("C++: Hello, world!\n");
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/main.c

@@ -0,0 +1,210 @@
+// This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+// License: BSD
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <irq.h>
+#include <libbase/uart.h>
+#include <libbase/console.h>
+#include <generated/csr.h>
+
+/*-----------------------------------------------------------------------*/
+/* Uart                                                                  */
+/*-----------------------------------------------------------------------*/
+
+static char *readstr(void)
+{
+	char c[2];
+	static char s[64];
+	static int ptr = 0;
+
+	if(readchar_nonblock()) {
+		c[0] = getchar();
+		c[1] = 0;
+		switch(c[0]) {
+			case 0x7f:
+			case 0x08:
+				if(ptr > 0) {
+					ptr--;
+					fputs("\x08 \x08", stdout);
+				}
+				break;
+			case 0x07:
+				break;
+			case '\r':
+			case '\n':
+				s[ptr] = 0x00;
+				fputs("\n", stdout);
+				ptr = 0;
+				return s;
+			default:
+				if(ptr >= (sizeof(s) - 1))
+					break;
+				fputs(c, stdout);
+				s[ptr] = c[0];
+				ptr++;
+				break;
+		}
+	}
+
+	return NULL;
+}
+
+static char *get_token(char **str)
+{
+	char *c, *d;
+
+	c = (char *)strchr(*str, ' ');
+	if(c == NULL) {
+		d = *str;
+		*str = *str+strlen(*str);
+		return d;
+	}
+	*c = 0;
+	d = *str;
+	*str = c+1;
+	return d;
+}
+
+static void prompt(void)
+{
+	printf("\e[92;1mlitex-demo-app\e[0m> ");
+}
+
+/*-----------------------------------------------------------------------*/
+/* Help                                                                  */
+/*-----------------------------------------------------------------------*/
+
+static void help(void)
+{
+	puts("\nLiteX minimal demo app built "__DATE__" "__TIME__"\n");
+	puts("Available commands:");
+	puts("help               - Show this command");
+	puts("reboot             - Reboot CPU");
+#ifdef CSR_LEDS_BASE
+	puts("led                - Led demo");
+#endif
+	puts("donut              - Spinning Donut demo");
+	puts("helloc             - Hello C");
+#ifdef WITH_CXX
+	puts("hellocpp           - Hello C++");
+#endif
+}
+
+/*-----------------------------------------------------------------------*/
+/* Commands                                                              */
+/*-----------------------------------------------------------------------*/
+
+static void reboot_cmd(void)
+{
+	ctrl_reset_write(1);
+}
+
+#ifdef CSR_LEDS_BASE
+static void led_cmd(void)
+{
+	int i;
+	printf("Led demo...\n");
+
+	printf("Counter mode...\n");
+	for(i=0; i<32; i++) {
+		leds_out_write(i);
+		busy_wait(100);
+	}
+
+	printf("Shift mode...\n");
+	for(i=0; i<4; i++) {
+		leds_out_write(1<<i);
+		busy_wait(200);
+	}
+	for(i=0; i<4; i++) {
+		leds_out_write(1<<(3-i));
+		busy_wait(200);
+	}
+
+	printf("Dance mode...\n");
+	for(i=0; i<4; i++) {
+		leds_out_write(0x55);
+		busy_wait(200);
+		leds_out_write(0xaa);
+		busy_wait(200);
+	}
+}
+#endif
+
+extern void donut(void);
+
+static void donut_cmd(void)
+{
+	printf("Donut demo...\n");
+	donut();
+}
+
+extern void helloc(void);
+
+static void helloc_cmd(void)
+{
+	printf("Hello C demo...\n");
+	helloc();
+}
+
+#ifdef WITH_CXX
+extern void hellocpp(void);
+
+static void hellocpp_cmd(void)
+{
+	printf("Hello C++ demo...\n");
+	hellocpp();
+}
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Console service / Main                                                */
+/*-----------------------------------------------------------------------*/
+
+static void console_service(void)
+{
+	char *str;
+	char *token;
+
+	str = readstr();
+	if(str == NULL) return;
+	token = get_token(&str);
+	if(strcmp(token, "help") == 0)
+		help();
+	else if(strcmp(token, "reboot") == 0)
+		reboot_cmd();
+#ifdef CSR_LEDS_BASE
+	else if(strcmp(token, "led") == 0)
+		led_cmd();
+#endif
+	else if(strcmp(token, "donut") == 0)
+		donut_cmd();
+	else if(strcmp(token, "helloc") == 0)
+		helloc_cmd();
+#ifdef WITH_CXX
+	else if(strcmp(token, "hellocpp") == 0)
+		hellocpp_cmd();
+#endif
+	prompt();
+}
+
+int main(void)
+{
+#ifdef CONFIG_CPU_HAS_INTERRUPT
+	irq_setmask(0);
+	irq_setie(1);
+#endif
+	uart_init();
+
+	help();
+	prompt();
+
+	while(1) {
+		console_service();
+	}
+
+	return 0;
+}

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/liteiclink/serdes/serdes_gm.py

@@ -0,0 +1,472 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex.gen import LiteXModule
+from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
+from litex.soc.interconnect import stream
+from litex.soc.cores.prbs import PRBSTX, PRBSRX
+from litex.soc.cores.code_8b10b import Encoder, Decoder
+
+class SerDesGM(LiteXModule):
+    def __init__(self, sys_clk_freq, refclk_freq=125e6, linerate=1.25e9,
+                 tx_polarity=0, rx_polarity=0,
+                 internal_loopback=False):
+        # We use a fixed 20-bit data path (two 10-bit 8b/10b words) at half the line rate.
+        data_width = 20
+        self.nwords = data_width // 10
+
+        self.tx_enable = Signal(reset=1)
+        self.rx_enable = Signal(reset=1)
+        self.tx_ready  = Signal()
+        self.rx_ready  = Signal()
+        self.tx_idle   = Signal()
+        self.loopback  = Signal(reset=1 if internal_loopback else 0)  # Loopback mode (fixed at init)
+
+        self.tx_prbs_config = Signal(2)    # PRBS pattern for TX (00: off, 01: PRBS7, 10: PRBS15, 11: PRBS31)
+        self.rx_prbs_config = Signal(2)    # PRBS pattern for RX (must match TX)
+        self.rx_prbs_pause  = Signal()
+        self.rx_prbs_errors = Signal(32)
+
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
+        self.cd_tx      = ClockDomain()
+        self.cd_tx_half = ClockDomain(reset_less=True)
+        self.cd_rx      = ClockDomain()
+
+        self.tx_clk_freq = linerate / data_width
+        self.rx_clk_freq = linerate / data_width
+
+        self.encoder  = ClockDomainsRenamer("tx")(Encoder(self.nwords, True))
+        self.decoders = [ClockDomainsRenamer("rx")(Decoder(True)) for _ in range(self.nwords)]
+
+        self.tx_prbs = ClockDomainsRenamer("tx")(PRBSTX(data_width, reverse=True))
+        self.rx_prbs = ClockDomainsRenamer("rx")(PRBSRX(data_width, reverse=True))
+
+        tx_data = Signal(data_width)
+        rx_data = Signal(data_width)
+        tx_bus  = Signal(24)
+        rx_bus  = Signal(24)
+        
+        
+        
+        _tx_prbs_config = Signal(2)
+        _rx_prbs_config = Signal(2)
+        _rx_prbs_pause  = Signal()
+        self.specials += [
+            MultiReg(self.tx_prbs_config, _tx_prbs_config, "tx"),
+            MultiReg(self.rx_prbs_config, _rx_prbs_config, "rx"),
+            MultiReg(self.rx_prbs_pause,  _rx_prbs_pause,  "rx")
+        ]
+
+        _prbs_errors = Signal(32)
+        self.specials += MultiReg(self.rx_prbs.errors, _prbs_errors, "sys")
+        self.comb += self.rx_prbs_errors.eq(_prbs_errors)
+
+        tx_reset      = Signal()
+        rx_reset      = Signal()
+        tx_reset_done = Signal()
+        rx_reset_done = Signal()
+        adpll_reset   = Signal(reset=1)
+        tx_detect_rx_done     = Signal()
+        tx_detect_rx_present  = Signal()
+        rx_buf_err            = Signal()
+        tx_buf_err            = Signal()
+        rx_prbs_err_flag      = Signal()    # you’ll have to OR–reduce your 32‑bit error count into 1 bit
+
+        tx_half_toggle = Signal(reset=0)
+        tx_half_clk    = Signal()
+        self.rx_reset_done_n        = rx_reset_done
+        self.tx_reset_done_n        = tx_reset_done
+        self.tx_detect_rx_done_n    = tx_detect_rx_done
+        self.tx_detect_rx_present_n = tx_detect_rx_present
+        self.rx_buf_err_n           = rx_buf_err
+        self.tx_buf_err_n           = tx_buf_err
+        self.comb += rx_prbs_err_flag.eq(self.rx_prbs_errors != 0)
+        self.rx_prbs_err_n = rx_prbs_err_flag
+        self.specials += [
+            Instance("CC_BUFG", i_I=self.txoutclk, o_O=self.cd_tx.clk),      # 125 MHz TX domain
+            Instance("CC_BUFG", i_I=self.rxoutclk, o_O=self.cd_rx.clk)       # 62.5 MHz RX domain
+        ]
+
+        # Generate 62.5 MHz TX half clock by dividing txoutclk by 2
+        self.sync.tx += tx_half_toggle.eq(~tx_half_toggle)
+        self.comb += tx_half_clk.eq(tx_half_toggle)
+        self.specials += Instance("CC_BUFG", i_I=tx_half_clk, o_O=self.cd_tx_half.clk)
+
+        self.comb += [
+            tx_reset.eq(~self.tx_enable | adpll_reset),  # hold TX in reset if disabled or PLL not ready
+            rx_reset.eq(~self.rx_enable)                 # hold RX in reset if disabled
+        ]
+        self.comb += [
+            self.tx_prbs.config.eq(_tx_prbs_config),
+            self.rx_prbs.config.eq(_rx_prbs_config),
+            self.rx_prbs.pause.eq(_rx_prbs_pause)
+        ]
+        # ** TX Data Path Selection **
+        # Feed 8b/10b encoder output into PRBS generator (the PRBS block will pass data through if PRBS is disabled)
+        self.comb += self.tx_prbs.i.eq(Cat(*[self.encoder.output[i] for i in range(self.nwords)]))
+        # Select transmitted data: PRBS output if PRBS mode is enabled, otherwise 8b/10b encoded data
+        self.comb += If(self.tx_prbs_config != 0,
+                        tx_data.eq(self.tx_prbs.o)
+                    ).Else(
+                        tx_data.eq(Cat(*[self.encoder.output[i] for i in range(self.nwords)]))
+                    )
+        # Map 20-bit tx_data into SERDES TX bus (16 data bits + 4 control bits for disparity/K)
+        # Lower 10-bit word: data[0:8] -> TX_DATA bits 0-7, tx_data[8] -> dispval, tx_data[9] -> dispmode
+        # Upper 10-bit word: data[10:18] -> TX_DATA bits 8-15, tx_data[18] -> dispval, tx_data[19] -> dispmode
+        self.comb += [
+            tx_bus[0:8].eq(tx_data[0:8]),     # lower byte of data
+            tx_bus[8].eq(0), tx_bus[9].eq(0), # we set all K/disp bits to 0 by default (assuming data already disparity-corrected)
+            tx_bus[10:18].eq(tx_data[10:18]), # upper byte of data
+            tx_bus[18:24].eq(0)               # upper word K/disp bits also 0
+        ]
+        # ** RX Data Path **
+        # Map SERDES RX bus back to 20-bit data (inverse of TX mapping)
+        self.comb += [
+            rx_data[0:8].eq(rx_bus[0:8]),     # lower 8 data bits
+            rx_data[8].eq(rx_bus[8]),         # (not used in fabric, would indicate K or disparity error)
+            rx_data[9].eq(rx_bus[9]),         # (not used in fabric)
+            rx_data[10:18].eq(rx_bus[10:18]), # upper 8 data bits
+            rx_data[18].eq(rx_bus[18]),
+            rx_data[19].eq(rx_bus[19])
+        ]
+        # Feed RX data into PRBS checker
+        self.comb += self.rx_prbs.i.eq(rx_data)
+        # Feed RX data into 8b/10b decoders (each decoder handles one 10-bit word)
+        for i in range(self.nwords):
+            self.sync.rx += self.decoders[i].input.eq(rx_data[10*i:10*(i+1)])
+        # ** Reset and Initialization Sequencing **
+        pll_reset_cycles = int((30000 * sys_clk_freq) // 1e9)  # ~30 µs at sys_clk_freq
+        if pll_reset_cycles < 1: pll_reset_cycles = 1
+        reset_counter = Signal(max=pll_reset_cycles+1, reset=0)
+        cdr_lock_time = int((sys_clk_freq * 50e3) // linerate)  # ~50,000 UI (bit periods) at sys_clk
+        if cdr_lock_time < 1: cdr_lock_time = 1
+        cdr_lock_counter = Signal(max=int(cdr_lock_time)+1, reset=0)
+        cdr_locked = Signal(reset=0)
+        # System clock domain FSM for resets
+        self.sync += [
+            # ADPLL reset release after `pll_reset_cycles` ticks
+            If(reset_counter < pll_reset_cycles,
+               reset_counter.eq(reset_counter + 1),
+               adpll_reset.eq(1)
+            ).Else(
+               adpll_reset.eq(0)
+            ),
+            # CDR lock timer (starts when RX reset is not asserted and PLL is running)
+            If(rx_reset | adpll_reset,
+               cdr_locked.eq(0),
+               cdr_lock_counter.eq(0)
+            ).Elif(cdr_lock_counter < cdr_lock_time,
+               cdr_lock_counter.eq(cdr_lock_counter + 1)
+            ).Else(
+               cdr_locked.eq(1)
+            )
+        ]
+        self.comb += [
+            self.rx_ready.eq(cdr_locked),
+            self.tx_ready.eq(tx_reset_done & cdr_locked)
+        ]
+        self.specials += AsyncResetSynchronizer(self.cd_rx, ~cdr_locked)
+        self.specials += AsyncResetSynchronizer(self.cd_tx, ~tx_reset_done)
+
+        # Select ADPLL parameters for the given reference clock frequency
+        adpll_config = {
+            100e6: {'fcntrl': 0x0A, 'main_divsel': 0x1B, 'out_divsel': 3},  # for 100 MHz ref
+            125e6: {'fcntrl': 0x1A, 'main_divsel': 0x1A, 'out_divsel': 3}   # for 125 MHz ref
+        }
+        assert refclk_freq in adpll_config, "Unsupported refclk_freq (use 100e6 or 125e6)."
+        cfg = adpll_config[refclk_freq]
+
+        serdes_params = dict(
+            # Global SERDES configuration
+            p_SERDES_ENABLE    = 1,
+            p_SERDES_AUTO_INIT = 0,
+            p_SERDES_TESTMODE  = 1,
+            # ADPLL (PLL) configuration
+            p_PLL_EN_ADPLL_CTRL = 1,
+            p_PLL_CONFIG_SEL    = 1, #0 :internal, 1: regfile
+            p_PLL_REF_SEL       = 1,   # 1 = LVDS reference (expects diff ref clock, or internal calibration if none)
+            p_PLL_REF_BYPASS    = 0,
+            p_PLL_REF_RTERM     = 1,
+            p_PLL_FCNTRL        = cfg['fcntrl'],
+            p_PLL_MAIN_DIVSEL   = cfg['main_divsel'],
+            p_PLL_OUT_DIVSEL    = cfg['out_divsel'],
+            p_PLL_CI            = 3,
+            p_PLL_CP            = 80,
+            p_PLL_AO            = 0,
+            p_PLL_SCAP          = 0,
+            p_PLL_FILTER_SHIFT  = 2,
+            p_PLL_SAR_LIMIT     = 2,
+            p_PLL_FT            = 512,
+            p_PLL_OPEN_LOOP     = 0,
+            p_PLL_SCAP_AUTO_CAL = 1,
+            p_PLL_SET_OP_LOCK  = 0,
+            p_PLL_ENFORCE_LOCK  = 0,
+            p_PLL_DISABLE_LOCK  = 0,
+            p_PLL_LOCK_WINDOW   = 1, 
+            p_PLL_FAST_LOCK     = 1, 
+            p_PLL_SYNC_BYPASS   = 0,
+            p_PLL_PFD_SELECT    = 0,
+            p_PLL_REF_RTERM     = 1,
+            #TX
+            p_TX_SEL_PRE = 0,
+            p_TX_SEL_POST = 0,
+            p_TX_AMP = 0XF,
+
+            p_TX_BRANCH_EN_PRE  = 0,
+            p_TX_BRANCH_EN_MAIN = 0x3F,
+            p_TX_BRANCH_EN_POST = 0,
+            p_TX_TAIL_CASCODE   = 0x4,
+            p_TX_DC_ENABLE      = 0x3F,
+            p_TX_DC_OFFSET      = 0x8, # note: set to 8
+            p_TX_CM_RAISE       = 0x0,
+            p_TX_CM_THRESHOLD_0 = 0xE,
+            p_TX_CM_THRESHOLD_1 = 0x10,
+            p_TX_SEL_PRE_EI     = 0x0,
+            p_TX_SEL_POST_EI    = 0x0,
+            p_TX_AMP_EI         = 0xF,
+            p_TX_BRANCH_EN_PRE_EI  = 0x0,
+            p_TX_BRANCH_EN_MAIN_EI = 0x3F,
+            p_TX_BRANCH_EN_POST_EI = 0x0,
+            p_TX_TAIL_CASCODE_EI   = 0x4,
+            p_TX_DC_ENABLE_EI      = 0x3F,
+            p_TX_DC_OFFSET_EI      = 0x0,
+            p_TX_CM_RAISE_EI       = 0x0,
+            p_TX_CM_THRESHOLD_0_EI = 0xE,
+            p_TX_CM_THRESHOLD_1_EI = 0x10,
+            p_TX_SEL_PRE_RXDET     = 0x0,
+            p_TX_SEL_POST_RXDET    = 0x0,
+            p_TX_AMP_RXDET         = 0xF,
+            p_TX_BRANCH_EN_PRE_RXDET = 0x0,
+            p_TX_BRANCH_EN_MAIN_RXDET = 0x3F,
+            p_TX_BRANCH_EN_POST_RXDET = 0x0,
+            p_TX_TAIL_CASCODE_RXDET   = 0x4,
+            p_TX_DC_ENABLE_RXDET      =0x3F,
+            p_TX_DC_OFFSET_RXDET      = 0x0,
+            p_TX_CM_RAISE_RXDET       = 0x0,
+            p_TX_CM_THRESHOLD_0_RXDET = 0xE,
+            p_TX_CM_THRESHOLD_1_RXDET = 0x10,
+            p_TX_CALIB_EN  = 0x0,
+            p_TX_CALIB_OVR = 0x0,
+            p_TX_CALIB_VAL = 0x0,
+            p_TX_CM_REG_KI = 0x80,
+            p_TX_CM_SAR_EN = 0x0,
+            p_TX_CM_REG_EN = 0x1,
+
+            p_TX_PCS_RESET_OVR=0x0,
+            p_TX_PCS_RESET=0x0,
+            p_TX_PMA_RESET_OVR=0x0,
+            p_TX_PMA_RESET=0x0,
+            p_TX_RESET_OVR=0x0,
+            p_TX_RESET=0x0,
+            p_TX_LOOPBACK_OVR=0x0,
+            p_TX_DETECT_RX_OVR=0x0,
+            p_TX_DETECT_RX=0x0,
+            p_TX_DATA_OVR=0x0,
+            p_TX_DATA_CNT=0x0,
+            p_TX_DATA_VALID=0x0,
+            # ADPLL BISC (Background calibration for PLL)
+            p_PLL_BISC_MODE         = 5,
+            p_PLL_BISC_TIMER_MAX    = 15,
+            p_PLL_BISC_OPT_DET_IND  = 0,
+            p_PLL_BISC_PFD_SEL      = 0,
+            p_PLL_BISC_DLY_DIR      = 0,
+            p_PLL_BISC_COR_DLY      = 1,
+            p_PLL_BISC_CAL_SIGN     = 0,
+            p_PLL_BISC_CAL_AUTO     = 1,
+            p_PLL_BISC_CP_MIN       = 6,
+            p_PLL_BISC_CP_MAX       = 30,
+            p_PLL_BISC_CP_START     = 6,
+            p_PLL_BISC_DLY_PFD_MON_REF = 0,
+            p_PLL_BISC_DLY_PFD_MON_DIV = 2,
+            # 8b/10b settings (bypass internal encoder/decoder)
+            p_TX_8B10B_EN_OVR = 0, p_TX_8B10B_EN = 0,
+            p_RX_8B10B_EN_OVR = 0, p_RX_8B10B_EN = 0,
+            p_RX_8B10B_BYPASS = 0x00,
+            # Data path width selection: 0 = 20-bit (1:2 gearbox)
+            p_TX_DATAPATH_SEL = 0,
+            p_RX_DATAPATH_SEL = 0,
+            # Reset timings
+            p_TX_PMA_RESET_TIME = 3, p_TX_PCS_RESET_TIME = 3,
+            p_RX_PMA_RESET_TIME = 3, p_RX_PCS_RESET_TIME = 3,
+            p_RX_RESET_TIMER_PRESC = 0, p_RX_RESET_DONE_GATE = 0,
+            # Electrical idle / power-down (TX/RX always on in this test)
+            p_TX_POWER_DOWN_OVR = 0, p_TX_POWER_DOWN_N = 1,
+            p_RX_POWER_DOWN_OVR = 0, p_RX_POWER_DOWN_N = 1,
+            p_TX_ELEC_IDLE_OVR  = 0, p_TX_ELEC_IDLE = 0,
+            # Polarity control
+            p_TX_POLARITY_OVR = 0, p_TX_POLARITY = 0,
+            p_RX_POLARITY_OVR = 0, p_RX_POLARITY = 0,
+            # Comma alignment
+            p_RX_COMMA_DETECT_EN_OVR = 0,
+            p_RX_COMMA_DETECT_EN     = 0,
+            p_RX_ALIGN_COMMA_WORD    = 3,
+            p_RX_ALIGN_COMMA_ENABLE  = 0x3FF,
+            p_RX_ALIGN_MCOMMA_VALUE  = 0x283,
+            p_RX_ALIGN_PCOMMA_VALUE  = 0x17C,
+            p_RX_MCOMMA_ALIGN_OVR    = 0, p_RX_MCOMMA_ALIGN = 0,
+            p_RX_PCOMMA_ALIGN_OVR    = 0, p_RX_PCOMMA_ALIGN = 0,
+            p_RX_SLIDE_MODE = 0, p_RX_SLIDE = 0,
+            p_RX_BYTE_REALIGN = 1,
+            # Clock correction
+            p_RX_CLKCOR_USE    = 0,
+            p_RX_CLKCOR_MIN_LAT= 32, p_RX_CLKCOR_MAX_LAT = 39,
+            p_RX_CLKCOR_SEQ_1_0= 0x1F7, p_RX_CLKCOR_SEQ_1_1=0x1F7,
+            p_RX_CLKCOR_SEQ_1_2= 0x1F7, p_RX_CLKCOR_SEQ_1_3=0x1F7,
+            # CDR configuration
+            p_RX_WAIT_CDR_LOCK = 0,
+            p_RX_CDR_FORCE_LOCK= 1,
+            p_RX_CDR_RESET_TIME= 3,
+            p_RX_CDR_CKP       = 0xF8,
+            p_RX_CDR_CKI       = 0x00,
+            p_RX_CDR_TRANS_TH  = 128,
+            p_RX_CDR_LOCK_CFG  = 0x0B,
+            p_RX_CDR_FREQ_ACC  = 0,
+            p_RX_CDR_PHASE_ACC = 0,
+            p_RX_CDR_SET_ACC_CONFIG = 0,
+            p_RX_CDR_RESET_OVR = 0, p_RX_CDR_RESET = 0,
+            # RX Equalizer
+            p_RX_EN_EI_DETECTOR_OVR = 0, p_RX_EN_EI_DETECTOR = 0,
+            p_RX_EI_BIAS = 4, p_RX_EI_BW_SEL = 4,
+            p_RX_AFE_PEAK = 0xF, p_RX_AFE_GAIN = 0x8, p_RX_AFE_VCMSEL = 0x4,
+            p_RX_CALIB_EN = 1, p_RX_CALIB_OVR = 0, p_RX_CALIB_VAL = 0,
+            p_RX_RTERM_VCMSEL = 4, p_RX_RTERM_PD = 0,
+            p_RX_EQA_RESET_TIME = 3, p_RX_EQA_RESET_OVR = 0, p_RX_EQA_RESET = 0,
+            p_RX_EQA_CKP_LF = 0xA3, p_RX_EQA_CKP_HF = 0xA3,
+            p_RX_EQA_CKP_OFFSET = 0x01,
+            p_RX_EN_EQA = 0, p_RX_EQA_LOCK_CFG = 0,
+            p_RX_TH_MON1 = 8, p_RX_TH_MON2 = 8,
+            p_RX_TAPW = 8, p_RX_AFE_OFFSET = 8,
+            p_RX_EQA_CONFIG = 0x01C0, p_RX_MON_PH_OFFSET = 0,
+            # PRBS
+            p_TX_PRBS_OVR = 0, p_TX_PRBS_SEL = 0, p_TX_PRBS_FORCE_ERR = 0,
+            p_RX_PRBS_OVR = 0, p_RX_PRBS_SEL = 0, p_RX_PRBS_CNT_RESET = 0,
+            # Loopback configuration
+            p_TX_PMA_LOOPBACK = 0, p_TX_PCS_LOOPBACK = 0,
+            p_RX_PMA_LOOPBACK = 0, p_RX_PCS_LOOPBACK = 0,
+            p_RX_BUF_RESET_TIME = 0x3,
+            p_RX_EN_EQA_EXT_VALUE = 0x0,
+            p_RX_EYE_MEAS_EN =0x0,
+            p_RX_EYE_MEAS_CFG = 0,    
+            p_RX_DATA_SEL =  0x0,
+            p_RX_BUF_BYPASS = 0x0,        
+            p_RX_LOOPBACK_OVR= 0x0,        
+            p_RX_RESET_OVR= 0x0,
+            p_RX_RESET= 0x0,
+            p_RX_PMA_RESET_OVR= 0x0,
+            p_RX_PMA_RESET= 0x0,
+            p_RX_PCS_RESET_OVR=0x0,
+            p_RX_PCS_RESET= 0x0,
+            p_RX_BUF_RESET_OVR= 0x0,
+            p_RX_BUF_RESET= 0x0,
+        )
+        # SERDES I/O port connections
+        serdes_params.update(
+            # Clocks & loopback
+            i_TX_CLK_I               = ClockSignal("tx_half"),
+            i_RX_CLK_I               = ClockSignal("rx"),
+            o_PLL_CLK_O              = self.txoutclk,
+            o_RX_CLK_O               = self.rxoutclk,
+            i_LOOPBACK_I             = 0b010 if internal_loopback else 0b000,
+
+            # Resets
+            i_TX_RESET_I             = tx_reset,
+            i_RX_RESET_I             = rx_reset,
+            i_RX_PMA_RESET_I         = 0,
+            i_RX_EQA_RESET_I         = 0,
+            i_RX_CDR_RESET_I         = 0,
+            i_RX_PCS_RESET_I         = 0,
+            i_RX_BUF_RESET_I         = 0,
+            i_TX_PCS_RESET_I         = 0,
+            i_TX_PMA_RESET_I         = 0,
+            i_PLL_RESET_I            = pll_reset,
+
+            # TX data & controls
+            i_TX_DATA_I              = Cat(tx_bus[0:8], tx_bus[10:18]),
+            i_TX_CHAR_IS_K_I         = 0,
+            i_TX_CHAR_DISPMODE_I     = Cat(tx_bus[9], tx_bus[23]),
+            i_TX_CHAR_DISPVAL_I      = Cat(tx_bus[8], tx_bus[22]),
+            i_TX_POWER_DOWN_N_I      = 1,
+            i_TX_POLARITY_I          = tx_polarity,
+            i_TX_ELEC_IDLE_I         = 0,
+            i_TX_DETECT_RX_I         = 1,
+            i_TX_PRBS_SEL_I          = _tx_prbs_config,
+            i_TX_PRBS_FORCE_ERR_I    = _tx_prbs_force_err,
+
+            o_TX_RESET_DONE_O        = tx_reset_done,
+            o_TX_BUF_ERR_O           = tx_buf_err,
+            o_TX_DETECT_RX_DONE_O    = tx_detect_rx_done,
+            o_TX_DETECT_RX_PRESENT_O = tx_detect_rx_present,
+
+             # RX data & controls
+            i_RX_POWER_DOWN_N_I      = 1,
+            i_RX_POLARITY_I          = rx_polarity,
+            i_RX_EN_EI_DETECTOR_I    = 0,
+            i_RX_COMMA_DETECT_EN_I   = rx_comma_detect_en,
+            i_RX_SLIDE_I             = 0,
+            i_RX_MCOMMA_ALIGN_I      = rx_comma_detect_en,
+            i_RX_PCOMMA_ALIGN_I      = rx_comma_detect_en,
+            i_RX_PRBS_SEL_I          = _rx_prbs_config,
+            i_RX_PRBS_CNT_RESET_I    = _rx_prbs_pause,
+    
+            o_RX_DATA_O              = Cat(rx_bus[0:8], rx_bus[10:18]),
+            o_RX_PRBS_ERR_O          = rx_prbs_err,
+            o_RX_BUF_ERR_O           = rx_buf_err,
+            o_RX_RESET_DONE_O        = rx_reset_done,
+
+            # register file
+            i_REGFILE_CLK_I          = 0,
+            i_REGFILE_WE_I           = 0,
+            i_REGFILE_EN_I           = 0,
+            i_REGFILE_ADDR_I         = 0,
+            i_REGFILE_DI_I           = 0,
+            i_REGFILE_MASK_I         = 0,
+            o_REGFILE_DO_O           = regfile_do,
+            o_REGFILE_RDY_O          = regfile_rdy,
+        )
+
+        # Connect SERDES to physical I/O pads if provided
+        if tx_pads is not None and hasattr(tx_pads, "p"):
+            serdes_params.update({o_TXP: tx_pads.p, o_TXN: tx_pads.n})
+        if rx_pads is not None and hasattr(rx_pads, "p"):
+            serdes_params.update({i_RXP: rx_pads.p, i_RXN: rx_pads.n})
+        # Instantiate the CC_SERDES primitive with all parameters
+        self.specials += Instance("CC_SERDES", **serdes_params)
+    def add_stream_endpoints(self):
+
+        # Create stream endpoints for data (each with nwords*8 data bits and nwords control bits for K)
+        self.sink   = stream.Endpoint([("data", 8*self.nwords), ("ctrl", self.nwords)])
+        self.source = stream.Endpoint([("data", 8*self.nwords), ("ctrl", self.nwords)])
+
+        self.comb += self.sink.ready.eq(1)
+        self.comb += self.source.valid.eq(1)
+        for i in range(self.nwords):
+            self.comb += [
+                self.encoder.d[i].eq(self.sink.data[8*i:8*(i+1)]),
+                self.encoder.k[i].eq(self.sink.ctrl[i])
+            ]
+            self.sync.rx += [
+                self.source.data[8*i:8*(i+1)].eq(self.decoders[i].d),
+                self.source.ctrl[i].eq(self.decoders[i].k)
+            ]
+    def add_controls(self, auto_enable=True):
+        self._tx_enable = CSRStorage(fields=[CSRField("enable", size=1, reset=int(auto_enable), description="TX Enable")])
+        self._rx_enable = CSRStorage(fields=[CSRField("enable", size=1, reset=int(auto_enable), description="RX Enable")])
+        self._tx_ready  = CSRStatus(fields=[CSRField("ready", size=1, description="TX Ready (PLL/SerDes locked)")])
+        self._rx_ready  = CSRStatus(fields=[CSRField("ready", size=1, description="RX Ready (CDR locked)")])
+        self._tx_prbs_config = CSRStorage(size=2, description="TX PRBS Configuration (0: PRBS off)")
+        self._rx_prbs_config = CSRStorage(size=2, description="RX PRBS Configuration (must match TX)")
+        self._rx_prbs_pause  = CSRStorage(size=1, description="Pause RX PRBS Checker")
+        self._rx_prbs_errors = CSRStatus(32, description="RX PRBS Error Count")
+        self.comb += [
+            self.tx_enable.eq(self._tx_enable.fields.enable),
+            self.rx_enable.eq(self._rx_enable.fields.enable),
+            self._tx_ready.fields.ready.eq(self.tx_ready),
+            self._rx_ready.fields.ready.eq(self.rx_ready),
+            self.tx_prbs_config.eq(self._tx_prbs_config.storage),
+            self.rx_prbs_config.eq(self._rx_prbs_config.storage),
+            self.rx_prbs_pause.eq(self._rx_prbs_pause.storage),
+            self._rx_prbs_errors.status.eq(self.rx_prbs_errors)
+        ]

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms/colognechip_gatemate_evb.py

@@ -0,0 +1,141 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
+# SPDX-License-Identifier: BSD-2-Clause
+
+# Board documentation/schematics:
+# https://colognechip.com/docs/ds1003-gatemate1-evalboard-3v1-latest.pdf
+
+from litex.build.generic_platform import *
+from litex.build.colognechip.platform import CologneChipPlatform
+from litex.build.openfpgaloader import OpenFPGALoader
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst
+    ("clk10",    0, Pins("IO_SB_A8"), Misc("SCHMITT_TRIGGER=true")),
+
+    # Leds
+    ("user_led_n", 0, Pins("IO_EB_B1")),
+    ("user_led_n", 1, Pins("IO_EB_B2")),
+    ("user_led_n", 2, Pins("IO_EB_B3")),
+    ("user_led_n", 3, Pins("IO_EB_B4")),
+    ("user_led_n", 4, Pins("IO_EB_B5")),
+    ("user_led_n", 5, Pins("IO_EB_B6")),
+    ("user_led_n", 6, Pins("IO_EB_B7")),
+    ("user_led_n", 7, Pins("IO_EB_B8")),
+
+    # Button
+    ("user_btn_n", 0, Pins("IO_EB_B0")),
+
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("IO_WA_A8")),
+        Subsignal("clk",  Pins("IO_WA_B8")),
+        Subsignal("miso", Pins("IO_WA_B7")),
+        Subsignal("mosi", Pins("IO_WA_A7")),
+        Subsignal("wp",   Pins("IO_WA_B6")),
+        Subsignal("hold", Pins("IO_WA_B6")),
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("IO_WA_A8")),
+        Subsignal("clk",  Pins("IO_WA_B8")),
+        Subsignal("dq",   Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_B6")),
+    ),
+
+    # HyperRAM
+    ("hyperram", 0,
+        Subsignal("dq", Pins("IO_WB_A5 IO_WB_B5 IO_WB_A6 IO_WB_B6 IO_WB_A7 IO_WB_B7 IO_WB_A8 IO_WB_B8")),
+        Subsignal("rwds", Pins("IO_WB_B4")),
+        Subsignal("cs_n", Pins("IO_WB_B0")),
+        Subsignal("rst_n", Pins("IO_WB_A2")),
+        Subsignal("clk_p", Pins("IO_WB_A3")),
+        Subsignal("clk_n", Pins("IO_WB_B3")),
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = [
+    ("PMODA", "IO_NB_A0 IO_NB_A1 IO_NB_A2 IO_NB_A3 IO_NB_B0 IO_NB_B1 IO_NB_B2 IO_NB_B3"),
+    ("PMODB", "IO_NB_A4 IO_NB_A5 IO_NB_A6 IO_NB_A7 IO_NB_B4 IO_NB_B5 IO_NB_B6 IO_NB_B7"),
+    ("io_na", "IO_NA_A0 IO_NA_B0",
+              "IO_NA_A1 IO_NA_B1",
+              "IO_NA_A2 IO_NA_B2",
+              "IO_NA_A3 IO_NA_B3",
+              "IO_NA_A4 IO_NA_B4",
+              "IO_NA_A5 IO_NA_B5",
+              "IO_NA_A6 IO_NA_B6",
+              "IO_NA_A7 IO_NA_B7",
+              "IO_NA_A8 IO_NA_B8"),
+    ("io_nb", "IO_NB_A4 IO_NB_A5",
+              "IO_NB_A6 IO_NB_A7",
+              "IO_NB_B4 IO_NB_B5",
+              "IO_NB_B6 IO_NB_B7"),
+    ("io_ea", "IO_EA_A0 IO_EA_B0",
+              "IO_EA_A1 IO_EA_B1",
+              "IO_EA_A2 IO_EA_B2",
+              "IO_EA_A3 IO_EA_B3",
+              "IO_EA_A4 IO_EA_B4",
+              "IO_EA_A5 IO_EA_B5",
+              "IO_EA_A6 IO_EA_B6",
+              "IO_EA_A7 IO_EA_B7",
+              "IO_EA_A8 IO_EA_B8"),
+    ("io_sa", "IO_SA_A0 IO_SA_B0",
+              "IO_SA_A1 IO_SA_B1",
+              "IO_SA_A2 IO_SA_B2",
+              "IO_SA_A3 IO_SA_B3",
+              "IO_SA_A4 IO_SA_B4",
+              "IO_SA_A5 IO_SA_B5",
+              "IO_SA_A6 IO_SA_B6",
+              "IO_SA_A7 IO_SA_B7",
+              "IO_SA_A8 IO_SA_B8"),
+    ("io_sb", "IO_SB_A0 IO_SB_B0",
+              "IO_SB_A1 IO_SB_B1",
+              "IO_SB_A2 IO_SB_B2",
+              "IO_SB_A3 IO_SB_B3",
+              "IO_SB_A4 IO_SB_B4",
+              "IO_SB_A5 IO_SB_B5",
+              "IO_SB_A6 IO_SB_B6",
+              "IO_SB_A7 IO_SB_B7",
+              "IO_SB_A8 IO_SB_B8"),
+
+    ("io_wc", "IO_WC_A0 IO_WC_B0",
+              "IO_WC_A1 IO_WC_B1",
+              "IO_WC_A2 IO_WC_B2",
+              "IO_WC_A3 IO_WC_B3",
+              "IO_WC_A4 IO_WC_B4",
+              "IO_WC_A5 IO_WC_B5",
+              "IO_WC_A6 IO_WC_B6",
+              "IO_WC_A7 IO_WC_B7",
+              "IO_WC_A8 IO_WC_B8"),
+]
+
+# PMODS --------------------------------------------------------------------------------------------
+
+def usb_pmod_io(pmod):
+    return [
+        # USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
+        ("usb_uart", 0,
+            Subsignal("tx", Pins(f"{pmod}:1")),
+            Subsignal("rx", Pins(f"{pmod}:2")),
+        ),
+    ]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(CologneChipPlatform):
+    default_clk_name   = "clk10"
+    default_clk_period = 1e9/10e6
+
+    def __init__(self, toolchain="colognechip"):
+        CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain)
+
+    def create_programmer(self):
+        return OpenFPGALoader("gatemate_evb_jtag")
+
+    def do_finalize(self, fragment):
+        CologneChipPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk10", loose=True), 1e9/10e6)

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets/colognechip_gatemate_evb.py

@@ -0,0 +1,123 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+
+from litex.gen import *
+
+from litex_boards.platforms import colognechip_gatemate_evb
+
+from litex.build.io import CRG
+
+from litex.soc.cores.clock.colognechip import GateMatePLL
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from litex.build.generic_platform import Pins
+
+from litex.soc.cores.led import LedChaser
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(LiteXModule):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst    = Signal()
+        rst_n       = Signal()
+        self.cd_sys = ClockDomain()
+
+        # # #
+
+        # Clk / Rst
+        clk10 = platform.request("clk10")
+        self.rst = ~platform.request("user_btn_n", 0)
+
+        self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n)
+
+        # PLL
+        self.pll = pll = GateMatePLL(perf_mode="economy")
+        self.comb += pll.reset.eq(~rst_n | self.rst)
+        pll.register_clkin(clk10, 10e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=48e6,
+        # with_led_chaser = False,
+        with_serdes=False,
+        **kwargs):
+        platform = colognechip_gatemate_evb.Platform()
+
+        # USBUART PMOD as Serial--------------------------------------------------------------------
+        platform.add_extension(colognechip_gatemate_evb.usb_pmod_io("PMODB"))
+        kwargs["uart_name"] = "usb_uart"
+
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs)
+
+        # Leds -------------------------------------------------------------------------------------
+        # if with_led_chaser:
+        #     self.leds = LedChaser(
+        #         pads         = platform.request_all("user_led_n"),
+        #         sys_clk_freq = sys_clk_freq)
+
+        if with_serdes:
+            from liteiclink.serdes.serdes_gm import SerDesGM
+            serdes = SerDesGM(sys_clk_freq=sys_clk_freq,
+                               refclk_freq=125e6,
+                               linerate=1.25e9,
+                               internal_loopback=False)
+            self.submodules += serdes
+            serdes.add_stream_endpoints()
+            serdes.add_controls()
+            leds = platform.request_all("user_led_n")
+            self.comb += [
+                leds[0].eq(serdes.rx_reset_done_n),        # LED0 ← RX_RESET_DONE_O_N
+                leds[1].eq(serdes.tx_reset_done_n),        # LED1 ← TX_RESET_DONE_O_N
+                leds[2].eq(serdes.tx_detect_rx_done_n),    # LED2 ← TX_DETECT_RX_DONE_O_N
+                leds[3].eq(serdes.tx_detect_rx_present_n), # LED3 ← TX_DETECT_RX_PRESENT_O_N
+                leds[4].eq(serdes.rx_prbs_err_n),          # LED4 ← RX_PRBS_ERR_O_N
+                leds[5].eq(serdes.rx_buf_err_n),           # LED5 ← RX_BUF_ERR_O_N
+                leds[6].eq(serdes.tx_buf_err_n),           # LED6 ← TX_BUF_ERR_O_N
+                leds[7].eq(~serdes.tx_ready)               # LED7 ← “ADPLL locked” indicator
+            ]
+
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.build.parser import LiteXArgumentParser
+    parser = LiteXArgumentParser(platform=colognechip_gatemate_evb.Platform, description="LiteX SoC on Gatemate EVB")
+    parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
+    parser.add_target_argument("--flash",        action="store_true",      help="Flash bitstream.")
+    parser.add_target_argument("--with-serdes", action="store_true",       help="Enable SERDES (1.25 Gbps transceiver loopback test).")
+    args = parser.parse_args()
+
+
+    soc = BaseSoC(
+        sys_clk_freq = args.sys_clk_freq,
+        with_serdes  = args.with_serdes,
+        **parser.soc_argdict)
+    builder = Builder(soc, **parser.builder_argdict)
+    if args.build:
+        builder.build(**parser.toolchain_argdict)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
+
+    if args.flash:
+        from litex.build.openfpgaloader import OpenFPGALoader
+        prog = OpenFPGALoader("gatemate_evb_spi")
+        prog.flash(0, builder.get_bitstream_filename(mode="flash"))
+
+if __name__ == "__main__":
+    main()

chili-chips-ba_openCologne/7.SerDes/2.liteiclink/README.md

@@ -0,0 +1,148 @@
+# Lite IC Link
+## Block Diagram
+
+```
+                           ┌────────────────────────────────────────────────────────────────────────────┐
+                           │                                sys_clk Domain                              │
+                           │────────────────────────────────────────────────────────────────────────────│
+                           │ • Inputs:                                                                  │
+                           │     – sys_clk                                                              │
+                           │     – CSR writes: _tx_enable(1), _rx_enable(1),                            │
+                           │       _tx_prbs_config(2), _rx_prbs_config(2), _rx_prbs_pause(1)            │
+                           │ • CSRStatus reads: _tx_ready(1), _rx_ready(1), _rx_prbs_errors(32)         │
+                           │ • MultiReg synchronizers → “tx” and “rx” clock domains                     │
+                           │ • Reset & Lock FSM:                                                        │
+                           │     - reset_cnt → adpll_reset                                              │
+                           │     - lock_cnt → cdr_locked                                                │
+                           │     - drives tx_reset_done → tx_ready, rx_reset_done → rx_ready            │
+                           └──────────────────────────────────┬─────────────────────────────────────────┘
+                                                              |
+                       ┌───────────────────────────┐          |                 ┌───────────────────────────┐
+                       │      Clock Buffering      |          |                 │      Clock Buffering      | 
+                       │───────────────────────────|          |                 │───────────────────────────|            
+                       │ • Instance CC_BUFG:       |◀────────┘───────────────▶│ • Instance CC_BUFG:       |
+                       |    - txoutclk → cd_tx.clk │                            |    - rxoutclk → cd_rx.clk │                      
+                       └────────────┬──────────────┘                            └─────────────┬─────────────┘
+                                    |                                                         |
+┌───────────────────────────────────▼──────────────────────┐     ┌────────────────────────────▼─────────────────────────────┐
+│                   cd_tx Domain                           |     │                       cd_rx Domain                       |       
+│──────────────────────────────────────────────────────────|     │──────────────────────────────────────────────────────────|
+│ 1) 8b/10b Encoder (ClockDomainsRenamer “tx”)             |     │ 1) Bus Unpacking                                         │
+│     – Inputs: sink.data[8·nbytes], sink.ctrl[nbytes]     │     │     – rx_data[8*i:8*(i+1)] ← rx_bus[8*i:8*(i+1)]         |
+│     – Outputs: encoder.output (10-bit symbols + K flags) │     │     – disp_flags (K bits)                                |
+│                                                          │     │                                                          │
+│ 2) PRBSTX                                                │     │ 2) PRBSRX                                                │
+│     – i ← encoder.output                                 │     │     – i ← rx_data                                        │
+│     – config ← synced tx_prbs_config                     │     │     – config ← synced rx_prbs_config                     │
+│     – o → PRBS bit-stream                                │     │     – errors → MultiReg → sys_clk (rx_prbs_errors)       │
+│                                                          │     │                                                          │
+│ 3) Datapath MUX                                          │     │ 3) 8b/10b Decoders                                       │
+│     – If prbs_config ≠ 0: tx_data ← PRBS.o               │     │     – d,i ← rx_data, disp_flags                          │
+│       Else:            tx_data ← encoder.output          |     │     – outputs: decoder.d → source.data,                  |
+|                                                          |     |                decoder.k → source.ctrl                   │
+|                                                          │     │ 4) source.valid = 1                                      │
+│ 4) Bus Packin                                            │     └─────────────────────────┬────────────────────────────────┘
+│     – tx_bus[8*i:8*(i+1)] ← tx_data[8*i:8*(i+1)          │                               |
+│                                                          │                               |
+│ 5) sink.ready = 1                                        |                               |
+└─────────────────────────┬────────────────────────────────┘                               | 
+                          |                                                                |
+                          |                                                                |
+                          |                                                                |
+                          |                                                                |
+              ┌───────────▼────────────────────────────────────────────────────────────────▼───────────────┐ 
+              │                                     CC_SERDES Primitive                                    │
+              │────────────────────────────────────────────────────────────────────────────────────────────│
+              │ • Params p_PLL_…, p_TX_…, p_RX_…, loopback, 8b/10b enable, comma align…                    │
+              │                                                                                            │
+              │ • Clocks & resets:                                                                         │
+              │     – i_TX_CLK_I = cd_tx.clk                                                               │
+              │     – i_TX_RESET_I = tx_reset (from FSM)                                                   │
+              │     – o_TX_RESET_DONE_O → tx_reset_done                                                    │
+              │     – o_PLL_CLK_O → txoutclk                                                               │
+              │     – i_RX_CLK_I = cd_rx.clk                                                               │
+              │     – i_RX_RESET_I = rx_reset                                                              │
+              │     – o_RX_RESET_DONE_O → rx_reset_done                                                    │
+              │     – o_RX_CLK_O → rxoutclk                                                                │
+              │                                                                                            │
+              │ • Data I/O:                                                                                │
+              │     – i_TX_DATA_I  = tx_bus                                                                │
+              │     – o_RX_DATA_O  = rx_bus                                                                │
+              │     – i_LOOPBACK_I = internal_loopback ? 0b010 : 0b000                                     │
+              │                                                                                            │
+              │ • Physical pads (optional):                                                                │
+              │     – o_TXP/o_TXN                                                                          │
+              │     – i_RXP/i_RXN                                                                          │
+              └────────────────────────────────────────────────────────────────────────────────────────────┘
+                                                           
+
+   ┌─────────────────────────────────────────────────────────────────────────────────────────────────────────┐
+   │                                               Stream Interface                                          │
+   │─────────────────────────────────────────────────────────────────────────────────────────────────────────│
+   │ • sink Endpoint (sys_clk):                                                                              │
+   │     – data[8·nbytes] → cd_tx.encoder.d                                                                  │
+   │     – ctrl[nbytes]  → cd_tx.encoder.k                                                                   │
+   │     – ready = 1                                                                                         │
+   │ • source Endpoint (cd_rx):                                                                              │
+   │     – data[8·nbytes] ← cd_rx.decoder.d                                                                  │
+   │     – ctrl[nbytes]  ← cd_rx.decoder.k                                                                   │
+   │     – valid = 1                                                                                         │
+   └─────────────────────────────────────────────────────────────────────────────────────────────────────────┘
+
+```
+
+
+## Workflow Overview
+First, let’s dive into the 2.liteiclink folder and walk through its structure so you can see how each component fits together and how the overall build process comes together
+
+### 2.sw
+
+In the [2.sw](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/2.sw) is a modified version of the [LiteX Demo Application](https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/demo) that will include generated CSR from the migen target file in the `main.c` function. There lie the control function for the datapath in the bare-metal C.
+The UART console is built upon the official demo application. 
+
+### 3.build
+
+Here in the [3.build](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/3.build) folder we have the [Makefile](https://github.com/chili-chips-ba/openCologne/blob/main/7.SerDes/2.liteiclink/3.build/Makefile) that divides the LiteX workflow into different parts. Running `make help` gives self-exmplanatory commands:
+
+```
+$ make help
+Usage:
+  make open-target     file=<name>
+  make open-example    file=<proj>
+  make build-board     [FREQ=..] [OPTIONS='..']
+  make load            [FREQ=..] [OPTIONS='..']
+  make term            [PORT=..]
+  make build-sw        [DEMO_FLAGS='..']
+  make sim
+  make view-sim
+  make clean-sim
+  make setup-ethernet  [ETH_IFACE=..] [STATIC_IP=..]
+  make start-server
+  make stop-server
+  make litescope
+  make clean
+  make copy-migen
+```
+
+The most important ones are:
+
+* `make build-board` which runs the build process using Vivado (openXC7 might also be used later on). The command has parameters `FREQ` and `OPTIONS` which can be overloaded.
+
+* `make build-sw` which compiles the bare-metal C application. The imporant note to add is to run the command after the build finishes because the compiler depends of the generated files in the `3.build/build` folder.
+
+* `make load` simply loads the bitstream onto the FPGA via the JTAG programmer
+  
+* `make term` opens up the serial console in the terminal to control the datapth signals. The default port is `/dev/ttyUSB0` while that can be simply changed with `PORT`.
+
+**NOTE**: Run `make term` in a seperate terminal before running `make load`
+
+### 4.migen
+The [4.migen](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen) folder contains two subfolders:
+
+* [liteiclink](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/liteiclink/serdes) which has the file that should be copied in the liteiclink litex folder
+  
+* [litex_boards](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards) which has:
+  [platforms](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms) which has the specific platform file that specifies the pins of the board
+  [targets](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets) has the target file that specifies all of the important parts of the CPU design and instantiates the SoC.
+
+**NOTE**: Right now you need to copy these subfolders with the files manually in your LiteX installation folder in `litex/litex_board/litex-boards`.

chili-chips-ba_openCologne/7.SerDes/README.md

@@ -0,0 +1,57 @@
+# SerDes App for GateMate
+
+Design a high-speed serial, **memory-mapped Chip-to-Chip (C2C) Interconnect**. The goal of such IP is to set the stage for creating compute clusters and Hyper Cubes made of GateMate FPGAs, all physically interconnected with SerDes, with this C2C on top of it, serving as logical and transport layer.
+
+## References:
+- CologneChip [SerDes example design](https://github.com/pu-cc/gm_serdes_lb) and latest [datasheet](https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf)
+- Xilinx PG046 - [Aurora 8B/10B](https://docs.amd.com/r/en-US/pg046-aurora-8b10b/Introduction?tocId=Tqe8wtK9r1zAUq13hUnVEw)
+    - Xilinx SP002 - [Aurora 8B/10B Protocol Spec](https://docs.amd.com/v/u/en-US/aurora_8b10b_protocol_spec_sp002)
+- BerkeleyLab [ChitChat](https://berkeleylab.github.io/Bedrock/_gen_md/serial_io/chitchat/README_md.html) protocol
+- LiteX [IC Link](https://github.com/enjoy-digital/liteiclink)
+- [MesaBusProtocol](https://github.com/blackmesalabs/MesaBusProtocol)
+- [Transputer](http://www.bitsavers.org/components/inmos/transputer/C011_Link_Adaptor.pdf)
+- [LiteX 1000basex](https://github.com/pu-cc/liteeth/tree/gatemate1000basex)
+- [Seding Data Structures from chip to chip](https://www.reddit.com/r/FPGA/comments/1m8gl5o/how_to_send_a_struct_from_one_dev_board_to_another)
+  
+- Timing-aware/better PNR for this high-speed design:
+    - [Project Peppercorn](https://github.com/YosysHQ/prjpeppercorn)
+    - [nextpnr for GateMate](https://github.com/YosysHQ/nextpnr/tree/gatemate)
+
+- Primer on [Eye Diagrams](https://incompliancemag.com/eye-diagram-part1) and [Equivalent Time Sampling](https://www.tek.com/en/documents/application-note/real-time-versus-equivalent-time-sampling) (vs. real-time)
+
+<p align="center" width="100%">
+    <img width="65%" src="0.doc/Eye-Diagrams.png">
+</p>
+
+- Gowin primer on SerDes Signal Integrity ([SI](https://www.gowinsemi.com/en/market/market_detail/48)) measurements 
+
+- Altera [Serial Link Analyzer](https://www.altera.com/products/development-tools/quartus-prime/advanced-link-analyzer)
+
+- Xilinx UG908 - In-System [IBERT](https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Using-Vivado-Serial-I/O-Analyzer-to-Debug-the-Design)
+
+    
+## Plan of Record
+Having thoroughly studied all options, the developers presented them in a project meeting on _July 11, 2025_, where team unanimously decided for the GateMate Chip2Chip SerDes:
+- not to mimic the semi-proprietary _Xilinx/AMD Aurora_
+- not to be based on _BerkeleyLab ChitChat_ 
+- not to be based on _MesaBusProtocol_
+- not to invent _our own scheme_ (which was the original plan of Chili.CHIPS*ba developers)
+- but rather to port `LiteX IC Link`, thus honoring CologneChip guidance and strong preference **<== WINNER!**
+
+The _IC Link_ comes with a worked out interface to the CPU. Its interface to SerDes will leverage from Patrick's _1000basex Ethernet MAC_ project. The best part of the _IC Link_ is that it opens the full power of LiteX integration, making it available for CologneChip customers almosts instantly, and so with minimal coding burden. As such, the _IC Link_ is the Chip2Chip interconnect that CologneChip would benefit the most from for their SerDes. 
+
+Given that GateMate proprietary (aka "legacy") PnR is rather unreliable and insensitive to timing constraints, while the new opensource PnR (Project Peppercorn) has already saved the day for our WP9-[BetrustedSOC](https://github.com/chili-chips-ba/openCologne/tree/main/9.BetrustedSOC), the _Chip2Chip SerDes_ will be delivered solely and exclusively for the _nextpnr_.
+
+
+For details on the work completed so far and the planned next steps, please refer to the [4.liteiclink](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/4.liteiclink) section of the repository.
+
+## Implementation
+We strongly recommend to start with standalone [SerDes loopback test](1.serdestool_by_gm/README.md) to get used to the hardware platform, SerDes settings, cabling and work with RF-class signaling in general. 
+
+Then move onto our [Lite IC Link](2.liteiclink/README.md) port for GateMate SerDes. You will find more detail in the respective project folders.
+
+### Public Announcements
+- [2025-08-10](https://www.linkedin.com/feed/update/urn:li:activity:7359764905572376577?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7359764905572376577%2C7360217016948985856%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287360217016948985856%2Curn%3Ali%3Aactivity%3A7359764905572376577%29)
+- [2025-02-21](https://www.linkedin.com/posts/patrick-urban-086177251_gatemate-fpga-colognechip-activity-7298662301677551616-4sw0?utm_source=share&utm_medium=member_desktop&rcm=ACoAAAJv-TcBSi_5ff0VNMrInrT-xg44YF3jnyU)
+
+### End of Document

chili-chips-ba_openCologne/8.StressTest/0.doc/Gowin-Arora/README.md

@@ -0,0 +1,4 @@
+## Gowin Documentation
+
+This directory contains documentation for the Gowin-Arora family of FPGAs.  They are direct competitors of the GateMate FPGAs. 
+First you may want to read this [Introductory User Guide by Mouser](https://device.report/manual/4181959). 

chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/README.md

@@ -0,0 +1,98 @@
+# CORESCORE - how many Servs can a FPGA serv?
+## * WORK IN PROGRESS * UNDER CONSTRUCTION *
+> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN'
+
+This is a popular metric, determining FPGA's logic capacity, routing algortihm and architectural ability to use all of the FPGA. We were able to achieve **54** cores with Fmax of **22.93 MHz**, when using `-tm 3` PnR "worst" timing setting. For comparison GW2AR-18C C8/I7 (20K LUT4) implemented **50** cores at **58 MHz** for worst timing PnR settings, bare in mind that this is a higher speed grade chip **C8/I7**.  
+
+## Results and analysis
+### Tools disclosure
+Obviously, comparing results obtained pushing the test sources through open-source yosys and propriatary synth isn't an apples to apples comparison. In an attempt to address this difference, and find the real potential of the GateMate's architecture, we conducted a reference yosys benchmark. Results of yosys synthesis are then compared to the "golden standard" propriatary syntehsis tool (Gowin). Later, all results can potentially be adjusted to account for the defficiencies in yosys. We didn't test the PnR tools since usually there are no alternatives. 
+Through testing, we obtained utilization figures for `1 <= core_count <= 50` for the **Gowin GW2AR-18C FPGA (20k LUT4)**. 
+
+Graphs are indicating a melting lead of propriatary tools, especially percentage-wise, but they still remain superior. The number of DFFs though, is steadily favoring the propriatary synthesis. Coming to an understanding of these results is possible only when we consider also the number of LUTRAM elements used in both implementations. Proprietary synthesis tools optimize resource usage by leveraging LUTRAM, reducing DFF consumption at the cost of additional LUTs. In contrast, Yosys relies on a basic approach using DFFs and LUTs exclusively. This results in higher LUT and DFF utilization in Yosys, as it emulates LUTRAM behavior with standard logic elements. The number of block RAMs remains unchanged and is therefore not shown. In relative perspective, yosys is far worse off for small designs, but the playing field evens out at higher utilization numbers. 
+
+### Takeaway - not so obvious
+Propriatary Gowin PnR topped out at 50 cores, utilizing only <td>11930 / 15750</td> of avaliable DFFs before reporting "fail to place 64 REGs". Taking this into account, yosys-based design would fail at 41 cores, or even earlier since the LUT usage is also increased. 
+
+Here we face a tough decision, **how to take yosys into account?** On one hand it's just 5% more LUTs and 18% more DFFs, but on the other hand it's prone to failing PnR with 20% less total logic instatiated. Since we're dealing with GateMate in our analysis, whose PnR isn't directly yosys netlist [compatible](https://github.com/chili-chips-ba/openCologne/issues/28#issuecomment-2353907213), from now on we use a 25% correction when assessing results. That would bring 41 yosys cores to 50 propriatary in Gowin.
+
+![figure1](absutil.png)
+![figure1](relutil.png)
+### Test results
+These tests have been verified on the real system.
+```
+Utilization Report
+
+ CPEs                  20037 /  20480  ( 97.8 %)
+ -----------------------------------------------
+   CPE Registers       13921 /  40960  ( 34.0 %)
+     Flip-flops        13921
+     Latches               0
+
+ GPIOs                     3 /    144  (  2.1 %)
+ -----------------------------------------------
+   Single-ended            3 /    144  (  2.1 %)
+     IBF                   2
+     OBF                   1
+     TOBF                  0
+     IOBF                  0
+
+
+ Block RAMs             26.0 /     32  ( 81.3 %)
+ -----------------------------------------------
+   BRAM_20K                1 /     64  (  1.6 %)
+   BRAM_40K               25 /     32  ( 78.1 %)
+   FIFO_40K                0 /     32  (  0.0 %)
+
+ PLLs                      1 /      4  ( 25.0 %)
+ GLBs                      1 /      4  ( 25.0 %)
+ SerDes                    0 /      1  (  0.0 %)
+```
+
+Considering that only 34% of sequential logic is utilized, but all Cologne Programmable Elements (CPEs) are fully utilized, it can be concluded that nearly all combinatorial elements are consumed. This positions the 20.5k CPE CologneChip GateMate FPGA alongside other FPGAs with similar capacities. 
+
+
+Notably, the GateMate's architecture, with 20.5k CPEs, effectively provides 41k LUT4 equivalents, as each CPE comprises an 8-input LUT-tree, which can be configured as two 4-input L2T4 primitives. Due to the reduced number of configuration bits required by this architecture, we can compute the normalized metric of **configuration bits per core** (the lower, the better). Throughput is computed by this formula: `core_count/technology`
+
+| FPGA Model         | Core Count | Configuration Bits per Core | LUT4 Count | Technology | Throughput |
+|--------------------|-----------|-----------------------------|------------|------------|-------------|
+| 10CL025YU256C8G   | 60        | 6666                        | 25k          | LP 20nm    | 3        |
+| CCGM1A1-BGA324    | 54        | 9102                        | 41k        | LP 28nm    |    1.964     |
+| LFE5U-25F-6BG256C | 61        | 7069                        | 24.3k      | LP 40nm    | 1.525        |
+| EP4CE10F17I7N     | 54        | 5770                        | 22k       | 60nm       | 0.9        |
+| GW2AR-18C C8/I7   | 50        | 6635                        | 20.7k       | 55nm HS | 0.9         |
+
+
+This indicates that the CCGM1A1 has a lower effective logic density per area unit, as measured by configuration bits per core. Conversely, CCGM1A1 shines in throughput per dollar, holding strong against the competition.
+
+## Build steps
+Put Yosys and GateMate p_r in PATH, and make sure you have FuseSoC installed:
+```
+pip install fusesoc
+```
+Navigate to 1.corescore_cc
+```
+cd 8.StressTest/1.corescore_cc/
+```
+Build FuseSoC target cc_gatemate
+```
+fusesoc run --target=cc_gatemate corescore
+```
+
+At this point your design should've successfully generated a bitstream. Uploading the bitstream to your board:
+```
+cd 8.StressTest/1.corescore_cc/
+make program
+```
+Listen to serial port at **57600 baud rate 8b no parity, 1 stop bit**, your output should be something like this, with xx ranging from `00` to `number_of_cores-1`:
+```
+core xx says hello
+```
+
+If for any reason you want to change the number of cores instantated, simply go to `fusesoc_libraries/corescore/corescore.core`, under targets find `cc_gatemate`, and change the count in the following line to a desired number of cores
+```
+generate: [corescorecore: {count: 55}]
+```
+**RTL functional simulation**:
+If for any reason you need debugging, there's a `sim` target provided, requiring Verilator. Waveform visualisation is left to the user.
+

chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0.eda.yml

@@ -0,0 +1,138 @@
+version: 0.2.1
+name: corescore_0
+toplevel: corescore_gatemate
+dependencies:
+  ::serv:1.0.2: []
+  ::verilog-axis:0-r3: []
+  ::serving:1.0.2:
+  - ::serv:1.0.2
+  ::corescore:0:
+  - ::serv:1.0.2
+  - ::serving:1.0.2
+  - ::verilog-axis:0-r3
+  - ::corescore-corescorecore:0
+  ::corescore-corescorecore:0: []
+parameters:
+  RISCV_FORMAL:
+    datatype: bool
+    paramtype: vlogdefine
+  SERV_CLEAR_RAM:
+    datatype: bool
+    paramtype: vlogdefine
+tool_options:
+  gatemate:
+    device: CCGM1A1
+    yosys_synth_options:
+    - -nomx8
+    p_r_options:
+    - -cCP
+    - --verbose
+    - -tm 1
+filters: []
+flow_options: {}
+hooks: {}
+files:
+- file_type: verilogSource
+  is_include_file: true
+  name: src/serv_1.0.2/rtl/serv_params.vh
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_shift.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_bufreg.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_alu.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_csr.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_ctrl.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_decode.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_mem_if.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_rf_if.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_rf_ram_if.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_rf_ram.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_state.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_top.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/serv_1.0.2/rtl/serv_rf_top.v
+  core: ::serv:1.0.2
+- file_type: verilogSource
+  name: src/verilog-axis_0-r3/rtl/arbiter.v
+  core: ::verilog-axis:0-r3
+- file_type: verilogSource
+  name: src/verilog-axis_0-r3/rtl/priority_encoder.v
+  core: ::verilog-axis:0-r3
+- file_type: verilogSource
+  name: src/verilog-axis_0-r3/rtl/axis_arb_mux.v
+  core: ::verilog-axis:0-r3
+- file_type: verilogSource
+  name: src/verilog-axis_0-r3/rtl/axis_async_fifo.v
+  core: ::verilog-axis:0-r3
+- file_type: verilogSource
+  name: src/serving_1.0.2/serving/serving_arbiter.v
+  core: ::serving:1.0.2
+- file_type: verilogSource
+  name: src/serving_1.0.2/serving/serving_mux.v
+  core: ::serving:1.0.2
+- file_type: verilogSource
+  name: src/serving_1.0.2/serving/serving_ram.v
+  core: ::serving:1.0.2
+- file_type: verilogSource
+  name: src/serving_1.0.2/serving/serving.v
+  core: ::serving:1.0.2
+- file_type: verilogSource
+  name: src/corescore_0/rtl/wb2axis.v
+  core: ::corescore:0
+- file_type: verilogSource
+  name: src/corescore_0/rtl/base.v
+  core: ::corescore:0
+- file_type: verilogSource
+  name: src/corescore_0/rtl/emitter_uart.v
+  core: ::corescore:0
+- file_type: CCF
+  name: src/corescore_0/data/cc_gatemate.ccf
+  core: ::corescore:0
+- file_type: verilogSource
+  name: src/corescore_0/rtl/cc_gatemate_clock_gen.v
+  core: ::corescore:0
+- file_type: verilogSource
+  name: src/corescore_0/rtl/corescore_gatemate.v
+  core: ::corescore:0
+- file_type: verilogSource
+  name: src/corescore-corescorecore_0/corescorecore.v
+  core: ::corescore-corescorecore:0
+- file_type: user
+  name: core_0.hex
+  core: ::corescore-corescorecore:0
+- file_type: user
+  name: core_1.hex
+  core: ::corescore-corescorecore:0
+- file_type: user
+  name: core_2.hex
+  core: ::corescore-corescorecore:0
+- file_type: user
+  name: core_3.hex
+  core: ::corescore-corescorecore:0
+- file_type: user
+  name: core_4.hex
+  core: ::corescore-corescorecore:0
+vpi: []

chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/edalize_yosys_procs.tcl

@@ -0,0 +1,51 @@
+proc read_files {} {
+read_verilog {src/serv_1.0.2/rtl/serv_shift.v}
+read_verilog {src/serv_1.0.2/rtl/serv_bufreg.v}
+read_verilog {src/serv_1.0.2/rtl/serv_alu.v}
+read_verilog {src/serv_1.0.2/rtl/serv_csr.v}
+read_verilog {src/serv_1.0.2/rtl/serv_ctrl.v}
+read_verilog {src/serv_1.0.2/rtl/serv_decode.v}
+read_verilog {src/serv_1.0.2/rtl/serv_mem_if.v}
+read_verilog {src/serv_1.0.2/rtl/serv_rf_if.v}
+read_verilog {src/serv_1.0.2/rtl/serv_rf_ram_if.v}
+read_verilog {src/serv_1.0.2/rtl/serv_rf_ram.v}
+read_verilog {src/serv_1.0.2/rtl/serv_state.v}
+read_verilog {src/serv_1.0.2/rtl/serv_top.v}
+read_verilog {src/serv_1.0.2/rtl/serv_rf_top.v}
+read_verilog {src/verilog-axis_0-r3/rtl/arbiter.v}
+read_verilog {src/verilog-axis_0-r3/rtl/priority_encoder.v}
+read_verilog {src/verilog-axis_0-r3/rtl/axis_arb_mux.v}
+read_verilog {src/verilog-axis_0-r3/rtl/axis_async_fifo.v}
+read_verilog {src/serving_1.0.2/serving/serving_arbiter.v}
+read_verilog {src/serving_1.0.2/serving/serving_mux.v}
+read_verilog {src/serving_1.0.2/serving/serving_ram.v}
+read_verilog {src/serving_1.0.2/serving/serving.v}
+read_verilog {src/corescore_0/rtl/wb2axis.v}
+read_verilog {src/corescore_0/rtl/base.v}
+read_verilog {src/corescore_0/rtl/emitter_uart.v}
+read_verilog {src/corescore_0/rtl/cc_gatemate_clock_gen.v}
+read_verilog {src/corescore_0/rtl/corescore_gatemate.v}
+read_verilog {src/corescore-corescorecore_0/corescorecore.v}
+}
+
+proc set_defines {} {
+set defines {{CCGM 1}}
+
+foreach d ${defines} {
+  set key [lindex $d 0]
+  set val [lindex $d 1]
+  verilog_defines "-D$key=$val"
+}}
+
+proc set_incdirs {} {
+verilog_defaults -add -Isrc/serv_1.0.2/rtl}
+
+proc set_params {} {
+}
+
+proc synth {top} {
+synth_gatemate -nomx8 -top $top
+}
+
+set top corescore_gatemate
+set name corescore_0

chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore.v

@@ -0,0 +1,105 @@
+// THIS FILE IS AUTOGENERATED BY corescorecore_gen
+// ANY MANUAL CHANGES WILL BE LOST
+`default_nettype none
+module corescorecore
+   (input  wire       i_clk,
+    input  wire       i_rst,
+    output wire [7:0] o_tdata,
+    output wire       o_tlast,
+    output wire       o_tvalid,
+    input  wire       i_tready);
+
+wire [39:0] tdata;
+wire  [4:0] tlast;
+wire  [4:0] tvalid;
+wire  [4:0] tready;
+
+base
+  #(.memfile ("core_0.hex"),
+    .memsize (256))
+ core_0
+   (.i_clk    (i_clk),
+    .i_rst    (i_rst),
+    .o_tdata  (tdata[7:0]),
+    .o_tlast  (tlast[0]),
+    .o_tvalid (tvalid[0]),
+    .i_tready (tready[0]));
+
+base
+  #(.memfile ("core_1.hex"),
+    .memsize (256))
+ core_1
+   (.i_clk    (i_clk),
+    .i_rst    (i_rst),
+    .o_tdata  (tdata[15:8]),
+    .o_tlast  (tlast[1]),
+    .o_tvalid (tvalid[1]),
+    .i_tready (tready[1]));
+
+base
+  #(.memfile ("core_2.hex"),
+    .memsize (256))
+ core_2
+   (.i_clk    (i_clk),
+    .i_rst    (i_rst),
+    .o_tdata  (tdata[23:16]),
+    .o_tlast  (tlast[2]),
+    .o_tvalid (tvalid[2]),
+    .i_tready (tready[2]));
+
+base
+  #(.memfile ("core_3.hex"),
+    .memsize (256))
+ core_3
+   (.i_clk    (i_clk),
+    .i_rst    (i_rst),
+    .o_tdata  (tdata[31:24]),
+    .o_tlast  (tlast[3]),
+    .o_tvalid (tvalid[3]),
+    .i_tready (tready[3]));
+
+base
+  #(.memfile ("core_4.hex"),
+    .memsize (256))
+ core_4
+   (.i_clk    (i_clk),
+    .i_rst    (i_rst),
+    .o_tdata  (tdata[39:32]),
+    .o_tlast  (tlast[4]),
+    .o_tvalid (tvalid[4]),
+    .i_tready (tready[4]));
+
+axis_arb_mux
+  #(.S_COUNT      (5),
+    .DATA_WIDTH   (8),
+    .KEEP_ENABLE  (0),
+    .KEEP_WIDTH   (1),
+    .ID_ENABLE    (0),
+    .ID_WIDTH     (8),
+    .DEST_ENABLE  (0),
+    .DEST_WIDTH   (8),
+    .USER_ENABLE  (0),
+    .USER_WIDTH   (1),
+    .ARB_TYPE     ("ROUND_ROBIN"),
+    .LSB_PRIORITY ("HIGH"))
+ axis_mux
+   (.clk           (i_clk),
+    .rst           (i_rst),
+    .s_axis_tdata  (tdata),
+    .s_axis_tkeep  (5'd0),
+    .s_axis_tvalid (tvalid),
+    .s_axis_tready (tready),
+    .s_axis_tlast  (tlast),
+    .s_axis_tid    (40'd0),
+    .s_axis_tdest  (40'd0),
+    .s_axis_tuser  (5'd0),
+    .m_axis_tdata  (o_tdata),
+    .m_axis_tkeep  (),
+    .m_axis_tvalid (o_tvalid),
+    .m_axis_tready (i_tready),
+    .m_axis_tlast  (o_tlast),
+    .m_axis_tid    (),
+    .m_axis_tdest  (),
+    .m_axis_tuser  ());
+
+endmodule