Add Repo: compsec-snu_difuzz-rtl (part 3)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle16ff_v.h

@@ -0,0 +1,2 @@
+// vle16ff.v and vlseg[2-8]e16ff.v
+VI_LDST_FF(int16);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle32_v.h

@@ -0,0 +1,2 @@
+// vle32.v and vlseg[2-8]e32.v
+VI_LD(0, (i * nf + fn), int32);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle32ff_v.h

@@ -0,0 +1,2 @@
+// vle32ff.v and vlseg[2-8]e32ff.v
+VI_LDST_FF(int32);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle64_v.h

@@ -0,0 +1,2 @@
+// vle64.v and vlseg[2-8]e64.v
+VI_LD(0, (i * nf + fn), int64);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle64ff_v.h

@@ -0,0 +1,2 @@
+// vle64ff.v and vlseg[2-8]e64ff.v
+VI_LDST_FF(int64);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle8_v.h

@@ -0,0 +1,2 @@
+// vle8.v and vlseg[2-8]e8.v
+VI_LD(0, (i * nf + fn), int8);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vle8ff_v.h

@@ -0,0 +1,2 @@
+// vle8ff.v and vlseg[2-8]e8ff.v
+VI_LDST_FF(int8);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlse16_v.h

@@ -0,0 +1,2 @@
+// vlse16.v and vlsseg[2-8]e16.v
+VI_LD(i * RS2, fn, int16);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlse32_v.h

@@ -0,0 +1,2 @@
+// vlse32.v and vlsseg[2-8]e32.v
+VI_LD(i * RS2, fn, int32);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlse64_v.h

@@ -0,0 +1,2 @@
+// vlse64.v and vlsseg[2-8]e64.v
+VI_LD(i * RS2, fn, int64);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlse8_v.h

@@ -0,0 +1,2 @@
+// vlse8.v and vlsseg[2-8]e8.v
+VI_LD(i * RS2, fn, int8);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlxei16_v.h

@@ -0,0 +1,2 @@
+// vlxei16.v and vlxseg[2-8]e16.v
+VI_LD_INDEX(e16, true);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlxei32_v.h

@@ -0,0 +1,2 @@
+// vlxe32.v and vlxseg[2-8]ei32.v
+VI_LD_INDEX(e32, true);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlxei64_v.h

@@ -0,0 +1,3 @@
+// vlxei64.v and vlxseg[2-8]ei64.v
+VI_LD_INDEX(e64, true);
+

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vlxei8_v.h

@@ -0,0 +1,2 @@
+// vlxei8.v and vlxseg[2-8]ei8.v
+VI_LD_INDEX(e8, true);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmacc_vv.h

@@ -0,0 +1,5 @@
+// vmacc.vv: vd[i] = +(vs1[i] * vs2[i]) + vd[i]
+VI_VV_LOOP
+({
+  vd = vs1 * vs2 + vd;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmacc_vx.h

@@ -0,0 +1,5 @@
+// vmacc.vx: vd[i] = +(x[rs1] * vs2[i]) + vd[i]
+VI_VX_LOOP
+({
+  vd = rs1 * vs2 + vd;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmadc_vim.h

@@ -0,0 +1,13 @@
+// vmadc.vim vd, vs2, simm5
+VI_XI_LOOP_CARRY
+({
+  auto v0 = P.VU.elt<uint64_t>(0, midx);
+  const uint64_t mmask = UINT64_C(1) << mpos; \
+  const uint128_t op_mask = (UINT64_MAX >> (64 - sew));
+  uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0;
+
+  uint128_t res = (op_mask & simm5) + (op_mask & vs2) + carry;
+
+  carry = (res >> sew) & 0x1u;
+  vd = (vd & ~mmask) | ((carry << mpos) & mmask);
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmadc_vvm.h

@@ -0,0 +1,13 @@
+// vmadc.vvm vd, vs2, rs1
+VI_VV_LOOP_CARRY
+({
+  auto v0 = P.VU.elt<uint64_t>(0, midx);
+  const uint64_t mmask = UINT64_C(1) << mpos; \
+  const uint128_t op_mask = (UINT64_MAX >> (64 - sew));
+  uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0;
+
+  uint128_t res = (op_mask & vs1) + (op_mask & vs2) + carry;
+
+  carry = (res >> sew) & 0x1u;
+  vd = (vd & ~mmask) | ((carry << mpos) & mmask);
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmadc_vxm.h

@@ -0,0 +1,13 @@
+// vadc.vx vd, vs2, rs1
+VI_XI_LOOP_CARRY
+({
+  auto v0 = P.VU.elt<uint64_t>(0, midx);
+  const uint64_t mmask = UINT64_C(1) << mpos; \
+  const uint128_t op_mask = (UINT64_MAX >> (64 - sew));
+  uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0;
+
+  uint128_t res = (op_mask & rs1) + (op_mask & vs2) + carry;
+
+  carry = (res >> sew) & 0x1u;
+  vd = (vd & ~mmask) | ((carry << mpos) & mmask);
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmadd_vv.h

@@ -0,0 +1,5 @@
+// vmadd: vd[i] = (vd[i] * vs1[i]) + vs2[i]
+VI_VV_LOOP
+({
+  vd = vd * vs1 + vs2;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmadd_vx.h

@@ -0,0 +1,5 @@
+// vmadd: vd[i] = (vd[i] * x[rs1]) + vs2[i]
+VI_VX_LOOP
+({
+  vd = vd * rs1 + vs2;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmand_mm.h

@@ -0,0 +1,2 @@
+// vmand.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 & vs1);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmandnot_mm.h

@@ -0,0 +1,2 @@
+// vmandnot.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 & ~vs1);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmax_vv.h

@@ -0,0 +1,10 @@
+// vmax.vv vd, vs2, vs1, vm   # Vector-vector
+VI_VV_LOOP
+({
+  if (vs1 >= vs2) {
+    vd = vs1;
+  } else {
+    vd = vs2;
+  }
+
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmax_vx.h

@@ -0,0 +1,10 @@
+// vmax.vx vd, vs2, rs1, vm   # vector-scalar
+VI_VX_LOOP
+({
+  if (rs1 >= vs2) {
+    vd = rs1;
+  } else {
+    vd = vs2;
+  }
+
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmaxu_vv.h

@@ -0,0 +1,9 @@
+// vmaxu.vv vd, vs2, vs1, vm   # Vector-vector
+VI_VV_ULOOP
+({
+  if (vs1 >= vs2) {
+    vd = vs1;
+  } else {
+    vd = vs2;
+  }
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmaxu_vx.h

@@ -0,0 +1,9 @@
+// vmaxu.vx vd, vs2, rs1, vm   # vector-scalar
+VI_VX_ULOOP
+({
+  if (rs1 >= vs2) {
+    vd = rs1;
+  } else {
+    vd = vs2;
+  }
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmerge_vim.h

@@ -0,0 +1,11 @@
+// vmerge.vim vd, vs2, simm5
+require_vector(true);
+VI_CHECK_SSS(false);
+VI_VVXI_MERGE_LOOP
+({
+  int midx = i / 64;
+  int mpos = i % 64;
+  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
+
+  vd = use_first ? simm5 : vs2;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmerge_vvm.h

@@ -0,0 +1,11 @@
+// vmerge.vvm vd, vs2, vs1
+require_vector(true);
+VI_CHECK_SSS(true);
+VI_VVXI_MERGE_LOOP
+({
+  int midx = i / 64;
+  int mpos = i % 64;
+  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
+
+  vd = use_first ? vs1 : vs2;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmerge_vxm.h

@@ -0,0 +1,11 @@
+// vmerge.vxm vd, vs2, rs1
+require_vector(true);
+VI_CHECK_SSS(false);
+VI_VVXI_MERGE_LOOP
+({
+  int midx = i / 64;
+  int mpos = i % 64;
+  bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
+
+  vd = use_first ? rs1 : vs2;
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfeq_vf.h

@@ -0,0 +1,12 @@
+// vmfeq.vf vd, vs2, fs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_eq(vs2, rs1);
+},
+{
+  res = f32_eq(vs2, rs1);
+},
+{
+  res = f64_eq(vs2, rs1);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfeq_vv.h

@@ -0,0 +1,12 @@
+// vmfeq.vv vd, vs2, vs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_eq(vs2, vs1);
+},
+{
+  res = f32_eq(vs2, vs1);
+},
+{
+  res = f64_eq(vs2, vs1);
+},
+true)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfge_vf.h

@@ -0,0 +1,12 @@
+// vmfge.vf vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_le(rs1, vs2);
+},
+{
+  res = f32_le(rs1, vs2);
+},
+{
+  res = f64_le(rs1, vs2);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfgt_vf.h

@@ -0,0 +1,12 @@
+// vmfgt.vf vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_lt(rs1, vs2);
+},
+{
+  res = f32_lt(rs1, vs2);
+},
+{
+  res = f64_lt(rs1, vs2);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfle_vf.h

@@ -0,0 +1,12 @@
+// vmfle.vf vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_le(vs2, rs1);
+},
+{
+  res = f32_le(vs2, rs1);
+},
+{
+  res = f64_le(vs2, rs1);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfle_vv.h

@@ -0,0 +1,12 @@
+// vmfle.vv vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_le(vs2, vs1);
+},
+{
+  res = f32_le(vs2, vs1);
+},
+{
+  res = f64_le(vs2, vs1);
+},
+true)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmflt_vf.h

@@ -0,0 +1,12 @@
+// vmflt.vf vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_lt(vs2, rs1);
+},
+{
+  res = f32_lt(vs2, rs1);
+},
+{
+  res = f64_lt(vs2, rs1);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmflt_vv.h

@@ -0,0 +1,12 @@
+// vmflt.vv vd, vs2, vs1
+VI_VFP_LOOP_CMP
+({
+  res = f16_lt(vs2, vs1);
+},
+{
+  res = f32_lt(vs2, vs1);
+},
+{
+  res = f64_lt(vs2, vs1);
+},
+true)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfne_vf.h

@@ -0,0 +1,12 @@
+// vmfne.vf vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = !f16_eq(vs2, rs1);
+},
+{
+  res = !f32_eq(vs2, rs1);
+},
+{
+  res = !f64_eq(vs2, rs1);
+},
+false)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmfne_vv.h

@@ -0,0 +1,12 @@
+// vmfne.vv vd, vs2, rs1
+VI_VFP_LOOP_CMP
+({
+  res = !f16_eq(vs2, vs1);
+},
+{
+  res = !f32_eq(vs2, vs1);
+},
+{
+  res = !f64_eq(vs2, vs1);
+},
+true)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmin_vv.h

@@ -0,0 +1,11 @@
+// vmin.vv vd, vs2, vs1, vm   # Vector-vector
+VI_VV_LOOP
+({
+  if (vs1 <= vs2) {
+    vd = vs1;
+  } else {
+    vd = vs2;
+  }
+
+
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmin_vx.h

@@ -0,0 +1,11 @@
+// vminx.vx vd, vs2, rs1, vm   # vector-scalar
+VI_VX_LOOP
+({
+  if (rs1 <= vs2) {
+    vd = rs1;
+  } else {
+    vd = vs2;
+  }
+
+
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vminu_vv.h

@@ -0,0 +1,9 @@
+// vminu.vv vd, vs2, vs1, vm   # Vector-vector
+VI_VV_ULOOP
+({
+  if (vs1 <= vs2) {
+    vd = vs1;
+  } else {
+    vd = vs2;
+  }
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vminu_vx.h

@@ -0,0 +1,10 @@
+// vminu.vx vd, vs2, rs1, vm   # vector-scalar
+VI_VX_ULOOP
+({
+  if (rs1 <= vs2) {
+    vd = rs1;
+  } else {
+    vd = vs2;
+  }
+
+})

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmnand_mm.h

@@ -0,0 +1,2 @@
+// vmnand.mm vd, vs2, vs1
+VI_LOOP_MASK(~(vs2 & vs1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmnor_mm.h

@@ -0,0 +1,2 @@
+// vmnor.mm vd, vs2, vs1
+VI_LOOP_MASK(~(vs2 | vs1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmor_mm.h

@@ -0,0 +1,2 @@
+// vmor.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 | vs1);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmornot_mm.h

@@ -0,0 +1,2 @@
+// vmornot.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 | ~vs1);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/vmsbc_vvm.h

@@ -0,0 +1,13 @@
+// vmsbc.vvm vd, vs2, rs1
+VI_VV_LOOP_CARRY
+({
+  auto v0 = P.VU.elt<uint64_t>(0, midx);
+  const uint64_t mmask = UINT64_C(1) << mpos;
+  const uint128_t op_mask = (UINT64_MAX >> (64 - sew));
+  uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0;
+
+  uint128_t res = (op_mask & vs2) - (op_mask & vs1) - carry;
+
+  carry = (res >> sew) & 0x1u;
+  vd = (vd & ~mmask) | ((carry << mpos) & mmask);
+})