Add Repo: compsec-snu_difuzz-rtl (part 2)

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsgnjx_q.h

@@ -0,0 +1,3 @@
+require_extension('Q');
+require_fp;
+WRITE_FRD(fsgnj128(FRS1, FRS2, false, true));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsgnjx_s.h

@@ -0,0 +1,3 @@
+require_extension('F');
+require_fp;
+WRITE_FRD(fsgnj32(FRS1, FRS2, false, true));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsh.h

@@ -0,0 +1,3 @@
+require_extension(EXT_ZFH);
+require_fp;
+MMU.store_uint16(RS1 + insn.s_imm(), FRS2.v[0]);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsq.h

@@ -0,0 +1,3 @@
+require_extension('Q');
+require_fp;
+MMU.store_float128(RS1 + insn.s_imm(), FRS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsqrt_d.h

@@ -0,0 +1,5 @@
+require_extension('D');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f64_sqrt(f64(FRS1)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsqrt_h.h

@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_sqrt(f16(FRS1)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsqrt_q.h

@@ -0,0 +1,5 @@
+require_extension('Q');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f128_sqrt(f128(FRS1)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsqrt_s.h

@@ -0,0 +1,5 @@
+require_extension('F');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f32_sqrt(f32(FRS1)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsub_d.h

@@ -0,0 +1,5 @@
+require_extension('D');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsub_h.h

@@ -0,0 +1,5 @@
+require_extension(EXT_ZFH);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsub_q.h

@@ -0,0 +1,5 @@
+require_extension('Q');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f128_sub(f128(FRS1), f128(FRS2)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsub_s.h

@@ -0,0 +1,5 @@
+require_extension('F');
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
+set_fp_exceptions;

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/fsw.h

@@ -0,0 +1,3 @@
+require_extension('F');
+require_fp;
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hfence_gvma.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(PRV_S);
+require_novirt();
+MMU.flush_tlb();

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hfence_vvma.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(PRV_S);
+require_novirt();
+MMU.flush_tlb();

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_b.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int8(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_bu.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint8(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_d.h

@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int64(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_h.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int16(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_hu.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint16(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_w.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_int32(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlv_wu.h

@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_uint32(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlvx_hu.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_x_uint16(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hlvx_wu.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+WRITE_RD(MMU.guest_load_x_uint32(RS1));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hsv_b.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint8(RS1, RS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hsv_d.h

@@ -0,0 +1,5 @@
+require_extension('H');
+require_rv64;
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint64(RS1, RS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hsv_h.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint16(RS1, RS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/hsv_w.h

@@ -0,0 +1,4 @@
+require_extension('H');
+require_privilege(get_field(STATE.hstatus, HSTATUS_HU) ? PRV_S : PRV_U);
+require_novirt();
+MMU.guest_store_uint32(RS1, RS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/jal.h

@@ -0,0 +1,3 @@
+reg_t tmp = npc;
+set_pc(JUMP_TARGET);
+WRITE_RD(tmp);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/jalr.h

@@ -0,0 +1,3 @@
+reg_t tmp = npc;
+set_pc((RS1 + insn.i_imm()) & ~reg_t(1));
+WRITE_RD(tmp);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lb.h

@@ -0,0 +1 @@
+WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lbu.h

@@ -0,0 +1 @@
+WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/ld.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.load_int64(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lh.h

@@ -0,0 +1 @@
+WRITE_RD(MMU.load_int16(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lhu.h

@@ -0,0 +1 @@
+WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lr_d.h

@@ -0,0 +1,5 @@
+require_extension('A');
+require_rv64;
+auto res = MMU.load_int64(RS1);
+MMU.acquire_load_reservation(RS1);
+WRITE_RD(res);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lr_w.h

@@ -0,0 +1,4 @@
+require_extension('A');
+auto res = MMU.load_int32(RS1);
+MMU.acquire_load_reservation(RS1);
+WRITE_RD(res);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lui.h

@@ -0,0 +1 @@
+WRITE_RD(insn.u_imm());

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lw.h

@@ -0,0 +1 @@
+WRITE_RD(MMU.load_int32(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/lwu.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm()));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mret.h

@@ -0,0 +1,11 @@
+require_privilege(PRV_M);
+set_pc_and_serialize(p->get_state()->mepc);
+reg_t s = STATE.mstatus;
+reg_t prev_prv = get_field(s, MSTATUS_MPP);
+reg_t prev_virt = get_field(s, MSTATUS_MPV);
+s = set_field(s, MSTATUS_MIE, get_field(s, MSTATUS_MPIE));
+s = set_field(s, MSTATUS_MPIE, 1);
+s = set_field(s, MSTATUS_MPP, PRV_U);
+p->set_csr(CSR_MSTATUS, s);
+p->set_privilege(prev_prv);
+p->set_virt(prev_virt);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mul.h

@@ -0,0 +1,2 @@
+require_extension('M');
+WRITE_RD(sext_xlen(RS1 * RS2));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mulh.h

@@ -0,0 +1,5 @@
+require_extension('M');
+if (xlen == 64)
+  WRITE_RD(mulh(RS1, RS2));
+else
+  WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mulhsu.h

@@ -0,0 +1,5 @@
+require_extension('M');
+if (xlen == 64)
+  WRITE_RD(mulhsu(RS1, RS2));
+else
+  WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mulhu.h

@@ -0,0 +1,5 @@
+require_extension('M');
+if (xlen == 64)
+  WRITE_RD(mulhu(RS1, RS2));
+else
+  WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/mulw.h

@@ -0,0 +1,3 @@
+require_extension('M');
+require_rv64;
+WRITE_RD(sext32(RS1 * RS2));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/or.h

@@ -0,0 +1 @@
+WRITE_RD(RS1 | RS2);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/ori.h

@@ -0,0 +1 @@
+WRITE_RD(insn.i_imm() | RS1);

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/rem.h

@@ -0,0 +1,9 @@
+require_extension('M');
+sreg_t lhs = sext_xlen(RS1);
+sreg_t rhs = sext_xlen(RS2);
+if(rhs == 0)
+  WRITE_RD(lhs);
+else if(lhs == INT64_MIN && rhs == -1)
+  WRITE_RD(0);
+else
+  WRITE_RD(sext_xlen(lhs % rhs));

compsec-snu_difuzz-rtl/Fuzzer/ISASim/riscv-isa-sim/riscv/insns/remu.h

@@ -0,0 +1,7 @@
+require_extension('M');
+reg_t lhs = zext_xlen(RS1);
+reg_t rhs = zext_xlen(RS2);
+if(rhs == 0)
+  WRITE_RD(sext_xlen(RS1));
+else
+  WRITE_RD(sext_xlen(lhs % rhs));