Add Repo: Floatkyun_Ultra-Vision

Floatkyun_Ultra-Vision/Algorithm/README.md

@@ -0,0 +1,15 @@
+# 算法代码已提交，文档还在写。。。。。。
+代码部分top为 `rgb_bicubic.v`。`bicubic_interpolation.v`是一个通道的算法。 
+可以看mian（划掉）文件夹里的算法细节
+
+
+## 2024.12.9更新
+1. 算法基于CrazyBingo的双线性缩放，借鉴了  [FPGA-Bicubic-interpolation](https://github.com/KevinHexin/FPGA-Bicubic-interpolation)
+的8个插值参数计算部分（不过大部分插拍都改掉了），修改完成了算法。目前支持双线性，双三次，最近临的缩放。
+
+2. `out_model`只在最后进行算法输出的选择，本质上三种算法都进行了计算。0为最近临，1为双线性，2为双三次。
+
+3. 算法的状态机还是基于 CrazyBingo 的缩放算法，进行了更改以兼容双三次算法设计。
+
+
+

Floatkyun_Ultra-Vision/Algorithm/matlab_test/create_grayimg.py

@@ -0,0 +1,20 @@
+from PIL import Image
+import random
+
+# 设置图片大小
+width, height = 80, 60
+
+# 创建一个新的灰度图片
+image = Image.new('L', (width, height))
+
+# 为图片的每个像素分配一个随机的灰度值
+for x in range(width):
+    for y in range(height):
+        pixel_value = random.randint(0, 255)
+        image.putpixel((x, y), pixel_value)
+
+# 保存图片
+image.save('img_gray.png')
+
+# 显示图片
+image.show()

Floatkyun_Ultra-Vision/Algorithm/matlab_test/rgb2gray.py

@@ -0,0 +1,16 @@
+from PIL import Image
+
+
+def rgb_to_grayscale(image_path, output_path):
+    # 打开图片
+    image = Image.open(image_path)
+
+    # 转换为灰度
+    grayscale_image = image.convert('L')
+
+    # 保存灰度图片
+    grayscale_image.save(output_path)
+
+
+# 使用示例
+rgb_to_grayscale('tip_line.png', 'tip_line_gray.png')

Floatkyun_Ultra-Vision/Algorithm/rtl/bicubic_interpolation.v

@@ -0,0 +1,1923 @@
+// *********************************************************************
+// this is gray pixel bicubic interpolation
+// *********************************************************************
+module bicubic_interpolation
+#(
+    parameter C_SRC_IMG_WIDTH  = 12'd640    ,
+    parameter C_SRC_IMG_HEIGHT = 12'd480   
+)
+(
+    input  wire                 clk_in1         ,
+    input  wire                 clk_in2         ,
+    input  wire                 rst_n           ,
+    input  wire     [1:0]       out_model       ,
+    
+    //  Image data prepared to be processed
+    input  wire                 per_img_vsync   ,       //  Prepared Image data vsync valid signal
+    input  wire                 per_img_href    ,       //  Prepared Image data href vaild  signal
+    input  wire     [7:0]       per_img_gray    ,       //  Prepared Image brightness input
+    
+    //  Image data has been processed
+    output reg                  post_img_vsync  ,       //  processed Image data vsync valid signal
+    output reg                  post_img_href   ,       //  processed Image data href vaild  signal
+    output reg      [7:0]       post_img_gray  ,         //  processed Image brightness output
+
+    input  wire         [16:0]              C_X_RATIO,
+    input  wire         [16:0]              C_Y_RATIO,
+    input  wire         [11:0]              C_DST_IMG_WIDTH,
+    input  wire         [11:0]              C_DST_IMG_HEIGHT,
+
+    input    wire            [33:0] coeff00_c11, coeff01_c11, coeff02_c11, coeff03_c11,
+    input    wire            [33:0] coeff10_c11, coeff11_c11, coeff12_c11, coeff13_c11,
+    input    wire            [33:0] coeff20_c11, coeff21_c11, coeff22_c11, coeff23_c11,
+    input    wire            [33:0] coeff30_c11, coeff31_c11, coeff32_c11, coeff33_c11,
+
+    input    wire            [33:0] frac_00_c2, frac_01_c2, frac_10_c2, frac_11_c2,
+
+    output   reg             [16:0]          x_fra_c1,
+    output   reg             [16:0]          y_fra_c1,
+    output   reg             [16:0]          inv_x_fra_c1,
+    output   reg             [16:0]          inv_y_fra_c1
+);
+//----------------------------------------------------------------------
+
+
+
+reg                             per_img_href_dly;
+
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        per_img_href_dly <= 1'b0;
+    else
+        per_img_href_dly <= per_img_href;
+end
+
+wire                            per_img_href_neg;
+
+assign per_img_href_neg = per_img_href_dly & ~per_img_href;
+
+reg             [10:0]          img_vs_cnt;                             //  from 0 to C_SRC_IMG_HEIGHT - 1
+
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        img_vs_cnt <= 11'b0;
+    else
+    begin
+        if(per_img_vsync == 1'b0)
+            img_vs_cnt <= 11'b0;
+        else
+        begin
+            if(per_img_href_neg == 1'b1)
+                img_vs_cnt <= img_vs_cnt + 1'b1;
+            else
+                img_vs_cnt <= img_vs_cnt;
+        end
+    end
+end
+
+reg             [10:0]          img_hs_cnt;                             //  from 0 to C_SRC_IMG_WIDTH - 1
+
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        img_hs_cnt <= 11'b0;
+    else
+    begin
+        if((per_img_vsync == 1'b1)&&(per_img_href == 1'b1))
+            img_hs_cnt <= img_hs_cnt + 1'b1;
+        else
+            img_hs_cnt <= 11'b0;
+    end
+end
+
+//----------------------------------------------------------------------
+reg             [7:0]           bram_wdata;
+
+always @(posedge clk_in1)
+begin
+    bram_wdata <= per_img_gray;
+end
+
+reg             [10:0]          bram_waddr;
+
+always @(posedge clk_in1)
+begin
+    bram_waddr <= {img_vs_cnt[2],10'b0} + img_hs_cnt;
+end
+
+//-------------------------------bram wirte control begin --------------------
+reg                             bram0_wenb;
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        bram0_wenb <= 1'b0;
+    else
+        bram0_wenb <= per_img_vsync & per_img_href & ~img_vs_cnt[1]& ~img_vs_cnt[0];
+end
+
+
+reg                             bram1_wenb;
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        bram1_wenb <= 1'b0;
+    else
+        bram1_wenb <= per_img_vsync & per_img_href & ~img_vs_cnt[1]& img_vs_cnt[0];
+end
+
+
+reg                             bram2_wenb;
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        bram2_wenb <= 1'b0;
+    else
+        bram2_wenb <= per_img_vsync & per_img_href & img_vs_cnt[1]& ~img_vs_cnt[0];
+end
+
+
+reg                             bram3_wenb;
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        bram3_wenb <= 1'b0;
+    else
+        bram3_wenb <= per_img_vsync & per_img_href & img_vs_cnt[1]& img_vs_cnt[0];
+end
+
+//-------------------------------bram wirte control end -----------------------
+
+reg             [10:0]          fifo_wdata;
+
+always @(posedge clk_in1)
+begin
+    fifo_wdata <= img_vs_cnt;
+end
+
+reg                             fifo_wenb;
+
+always @(posedge clk_in1)
+begin
+    if(rst_n == 1'b0)
+        fifo_wenb <= 1'b0;
+    else
+    begin
+        if((per_img_vsync == 1'b1)&&(per_img_href == 1'b1)&&(img_hs_cnt == C_SRC_IMG_WIDTH - 1'b1))
+            fifo_wenb <= 1'b1;
+        else
+            fifo_wenb <= 1'b0;
+    end
+end
+
+//----------------------------------------------------------------------
+//  bram & fifo rw
+reg             [10:0]          bram11_raddr,bram12_raddr,bram13_raddr,bram14_raddr;
+reg             [10:0]          bram21_raddr,bram22_raddr,bram23_raddr,bram24_raddr;
+reg             [10:0]          bram31_raddr,bram32_raddr,bram33_raddr,bram34_raddr;
+reg             [10:0]          bram41_raddr,bram42_raddr,bram43_raddr,bram44_raddr;
+
+wire            [ 7:0]          bram11_rdata,bram12_rdata,bram13_rdata,bram14_rdata;
+wire            [ 7:0]          bram21_rdata,bram22_rdata,bram23_rdata,bram24_rdata;
+wire            [ 7:0]          bram31_rdata,bram32_rdata,bram33_rdata,bram34_rdata;
+wire            [ 7:0]          bram41_rdata,bram42_rdata,bram43_rdata,bram44_rdata;
+
+
+
+
+
+my16bram u_my16bram (
+    .clk_in1(clk_in1),
+    .clk_in2(clk_in2), 
+
+    .bram0_wenb(bram0_wenb),
+    .bram1_wenb(bram1_wenb), 
+    .bram2_wenb(bram2_wenb),
+    .bram3_wenb(bram3_wenb), 
+    .bram_waddr(bram_waddr),
+    .bram_wdata(bram_wdata),
+
+    .bram11_raddr(bram11_raddr),
+    .bram12_raddr(bram12_raddr),
+    .bram13_raddr(bram13_raddr),
+    .bram14_raddr(bram14_raddr),
+
+    .bram21_raddr(bram21_raddr),
+    .bram22_raddr(bram22_raddr),
+    .bram23_raddr(bram23_raddr),
+    .bram24_raddr(bram24_raddr),
+
+    .bram31_raddr(bram31_raddr),
+    .bram32_raddr(bram32_raddr),
+    .bram33_raddr(bram33_raddr),
+    .bram34_raddr(bram34_raddr),
+
+    .bram41_raddr(bram41_raddr),
+    .bram42_raddr(bram42_raddr),
+    .bram43_raddr(bram43_raddr),
+    .bram44_raddr(bram44_raddr),
+    
+    .bram11_rdata(bram11_rdata),
+    .bram12_rdata(bram12_rdata),
+    .bram13_rdata(bram13_rdata),
+    .bram14_rdata(bram14_rdata),
+
+    .bram21_rdata(bram21_rdata),
+    .bram22_rdata(bram22_rdata),
+    .bram23_rdata(bram23_rdata),
+    .bram24_rdata(bram24_rdata),
+
+    .bram31_rdata(bram31_rdata),
+    .bram32_rdata(bram32_rdata),
+    .bram33_rdata(bram33_rdata),
+    .bram34_rdata(bram34_rdata),
+
+    .bram41_rdata(bram41_rdata),
+    .bram42_rdata(bram42_rdata),
+    .bram43_rdata(bram43_rdata),
+    .bram44_rdata(bram44_rdata)
+);
+
+wire                            fifo_renb;
+wire            [10:0]          fifo_rdata;
+wire                            fifo_empty;
+wire                            fifo_full;
+
+
+
+
+asyn_fifo  u_asyn_fifo(
+        .a_rst_i                           (   ~rst_n                       ), 
+        .wdata                             (    fifo_wdata                  ),
+        .rd_clk_i                          (     clk_in2                    ),
+        .rd_en_i                           (      fifo_renb                 ),
+        .wr_clk_i                          (       clk_in1                  ),
+        .wr_en_i                           (       fifo_wenb                ),
+        .rdata                             (       fifo_rdata               ),
+        .full_o                            (      fifo_full                ),
+        .empty_o                           (       fifo_empty                ),
+    .almost_full_o                     (        ),
+    .prog_full_o                       (        ),
+    .overflow_o                        (        ),
+    .wr_ack_o                          (        ),
+    .almost_empty_o                    (        ),
+    .underflow_o                       (        ),
+    .rd_valid_o                        (        ),
+    .wr_datacount_o                    (        ),
+    .rst_busy                          (        ),
+    .rd_datacount_o                    (        )
+);
+
+
+localparam S_IDLE      = 3'd0;
+localparam S_Y_LOAD    = 3'd1;
+localparam S_BRAM_ADDR = 3'd2;
+localparam S_Y_INC     = 3'd3;
+localparam S_RD_FIFO   = 3'd4;
+
+reg             [ 2:0]          state;
+reg             [26:0]          y_dec;
+reg             [26:0]          x_dec;
+reg             [11:0]          y_cnt;
+reg             [11:0]          x_cnt;
+
+
+
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+        state <= S_IDLE;
+    else
+    begin
+        case(state)
+            S_IDLE : 
+            begin
+                if(fifo_empty == 1'b0)
+                begin
+                    if((fifo_rdata != 11'b0)&&(y_cnt == C_DST_IMG_HEIGHT))
+                        state <= S_RD_FIFO;
+                    else
+                        state <= S_Y_LOAD;
+                end
+                else
+                    state <= S_IDLE;
+            end
+            S_Y_LOAD : 
+            begin
+                if((y_dec[26:16] + 2'd2 <= fifo_rdata)||
+                   (y_cnt == C_DST_IMG_HEIGHT - 2'd2)||
+                   (y_cnt == C_DST_IMG_HEIGHT - 1'b1)||
+                   ((y_cnt == C_DST_IMG_HEIGHT - 3'd3)&&(C_DST_IMG_HEIGHT>=1.5*C_SRC_IMG_HEIGHT))||
+                   ((y_cnt == C_DST_IMG_HEIGHT - 3'd4)&&(C_DST_IMG_HEIGHT>=2*C_SRC_IMG_HEIGHT))||
+                   ((y_cnt == C_DST_IMG_HEIGHT - 3'd5)&&(C_DST_IMG_HEIGHT>=2.5*C_SRC_IMG_HEIGHT)))
+                    state <= S_BRAM_ADDR;
+                else
+                    state <= S_RD_FIFO;
+            end
+            S_BRAM_ADDR : 
+            begin
+                if(x_cnt == C_DST_IMG_WIDTH - 1'b1)
+                    state <= S_Y_INC;
+                else
+                    state <= S_BRAM_ADDR;
+            end
+            S_Y_INC : 
+            begin
+                if(y_cnt == C_DST_IMG_HEIGHT - 1'b1)
+                    state <= S_RD_FIFO;
+                else
+                    state <= S_Y_LOAD;
+            end
+            S_RD_FIFO : 
+            begin
+                state <= S_IDLE;
+            end
+            default : 
+            begin
+                state <= S_IDLE;
+            end
+        endcase
+    end
+end
+
+assign fifo_renb = (state == S_RD_FIFO) ? 1'b1 : 1'b0;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+        y_dec <= 27'b0;
+    else
+    begin
+        if((state == S_IDLE)&&(fifo_empty == 1'b0)&&(fifo_rdata == 11'b0))
+            y_dec <= 27'b0;
+        else if(state == S_Y_INC)
+            y_dec <= y_dec + C_Y_RATIO;
+        else
+            y_dec <= y_dec;
+    end
+end
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+        y_cnt <= 11'b0;
+    else
+    begin
+        if((state == S_IDLE)&&(fifo_empty == 1'b0)&&(fifo_rdata == 11'b0))
+            y_cnt <= 11'b0;
+        else if(state == S_Y_INC)
+            y_cnt <= y_cnt + 1'b1;
+        else
+            y_cnt <= y_cnt;
+    end
+end
+
+always @(posedge clk_in2)
+begin
+    if(state == S_BRAM_ADDR)
+        x_dec <= x_dec + C_X_RATIO;
+    else
+        x_dec <= 27'b0;
+end
+
+always @(posedge clk_in2)
+begin
+    if(state == S_BRAM_ADDR)
+        x_cnt <= x_cnt + 1'b1;
+    else
+        x_cnt <= 11'b0;
+end
+
+//----------------------------------------------------------------------
+//  c1
+reg                             img_vs_c1;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c1 <= 1'b0;
+    end
+    else
+    begin
+        if((state == S_BRAM_ADDR)&&(x_cnt == 11'b0)&&(y_cnt == 11'b0))
+            img_vs_c1 <= 1'b1;
+        else if((state == S_Y_INC)&&(y_cnt == C_DST_IMG_HEIGHT - 1'b1))
+        begin
+            img_vs_c1 <= 1'b0;
+        end
+        else
+            img_vs_c1 <= img_vs_c1;
+    end
+end
+
+reg                             img_hs_c1;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+        img_hs_c1 <= 1'b0;
+    else
+    begin
+        if(state == S_BRAM_ADDR)
+            img_hs_c1 <= 1'b1;
+        else
+            img_hs_c1 <= 1'b0;
+    end
+end
+
+reg             [10:0]          x_int_c1;
+reg             [10:0]          y_int_c1;
+
+
+
+
+always @(posedge clk_in2)
+begin
+    x_int_c1     <= x_dec[25:16];
+    y_int_c1     <= y_dec[25:16];
+    x_fra_c1     <= {1'b0,x_dec[15:0]};
+    inv_x_fra_c1 <= 17'h10000 - {1'b0,x_dec[15:0]};
+    y_fra_c1     <= {1'b0,y_dec[15:0]};
+    inv_y_fra_c1 <= 17'h10000 - {1'b0,y_dec[15:0]};
+
+end
+
+//----------------------------------------------------------------------
+//  c2
+reg                             img_vs_c2;
+reg                             img_hs_c2;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c2 <= 1'b0;
+        img_hs_c2 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c2 <= img_vs_c1;
+        img_hs_c2 <= img_hs_c1;
+    end
+end
+
+reg             [10:0]          bram_addr_c2;
+reg             [ 1:0]          bram_mode_c2;
+
+always @(posedge clk_in2)
+begin
+    bram_addr_c2 <= {y_int_c1[2],10'b0} + x_int_c1;
+    bram_mode_c2 <= y_int_c1[1:0];
+end
+
+reg                             left_pixel_extand_flag_c2;
+reg                             right_pixel_extand_flag_1_c2;
+reg                             right_pixel_extand_flag_2_c2;
+reg                             top_pixel_extand_flag_c2;
+reg                             bottom_pixel_extand_flag_1_c2;
+reg                             bottom_pixel_extand_flag_2_c2;
+
+always @(posedge clk_in2)
+begin
+    if(x_int_c1 == 0)
+        left_pixel_extand_flag_c2 <= 1'b1;
+    else
+        left_pixel_extand_flag_c2 <= 1'b0;
+
+    if(x_int_c1 == C_SRC_IMG_WIDTH - 2'd2)
+        right_pixel_extand_flag_1_c2 <= 1'b1;
+    else
+        right_pixel_extand_flag_1_c2 <= 1'b0;
+    if(x_int_c1 == C_SRC_IMG_WIDTH - 2'd1)
+        right_pixel_extand_flag_2_c2 <= 1'b1;
+    else
+        right_pixel_extand_flag_2_c2 <= 1'b0;
+
+
+    if(y_int_c1 == 0)
+        top_pixel_extand_flag_c2 <= 1'b1;
+    else
+        top_pixel_extand_flag_c2 <= 1'b0;
+    if(y_int_c1 == C_SRC_IMG_HEIGHT - 2'd2)
+        bottom_pixel_extand_flag_1_c2 <= 1'b1;
+    else
+        bottom_pixel_extand_flag_1_c2 <= 1'b0;
+    if(y_int_c1 == C_SRC_IMG_HEIGHT - 2'd1)
+        bottom_pixel_extand_flag_2_c2 <= 1'b1;
+    else
+        bottom_pixel_extand_flag_2_c2 <= 1'b0;
+end
+
+reg                             xmax_c2;
+reg                             ymax_c2;
+
+always @(posedge clk_in2)
+begin
+    if(x_fra_c1<inv_x_fra_c1)
+        xmax_c2 <= 1'b0;
+    else
+        xmax_c2 <= 1'b1;
+    if(y_fra_c1<inv_y_fra_c1)
+        ymax_c2 <= 1'b0;
+    else
+        ymax_c2 <= 1'b1;
+end
+
+
+
+//----------------------------------------------------------------------
+//  c3
+reg                             img_vs_c3;
+reg                             img_hs_c3;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c3 <= 1'b0;
+        img_hs_c3 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c3 <= img_vs_c2;
+        img_hs_c3 <= img_hs_c2;
+    end
+end
+
+always @(posedge clk_in2)
+begin
+    case(bram_mode_c2)
+        2'b00 : 
+        begin
+            bram41_raddr <= bram_addr_c2+12'd1023;
+            bram42_raddr <= bram_addr_c2+12'd1024;
+            bram43_raddr <= bram_addr_c2+12'd1025;
+            bram44_raddr <= bram_addr_c2+12'd1026;
+
+            bram11_raddr <= bram_addr_c2- 1'd1;
+            bram12_raddr <= bram_addr_c2;
+            bram13_raddr <= bram_addr_c2+ 2'd1;
+            bram14_raddr <= bram_addr_c2+ 2'd2;
+
+            bram21_raddr <= bram_addr_c2- 1'd1;
+            bram22_raddr <= bram_addr_c2;
+            bram23_raddr <= bram_addr_c2+ 2'd1;
+            bram24_raddr <= bram_addr_c2+ 2'd2;
+
+            bram31_raddr <= bram_addr_c2- 1'd1;
+            bram32_raddr <= bram_addr_c2;
+            bram33_raddr <= bram_addr_c2+ 2'd1;
+            bram34_raddr <= bram_addr_c2+ 2'd2;
+        end
+        2'b01 : 
+        begin
+            bram11_raddr <= bram_addr_c2- 1'd1;
+            bram12_raddr <= bram_addr_c2;
+            bram13_raddr <= bram_addr_c2+ 2'd1;
+            bram14_raddr <= bram_addr_c2+ 2'd2;
+
+            bram21_raddr <= bram_addr_c2- 1'd1;
+            bram22_raddr <= bram_addr_c2;
+            bram23_raddr <= bram_addr_c2+ 2'd1;
+            bram24_raddr <= bram_addr_c2+ 2'd2;
+
+            bram31_raddr <= bram_addr_c2- 1'd1;
+            bram32_raddr <= bram_addr_c2;
+            bram33_raddr <= bram_addr_c2+ 2'd1;
+            bram34_raddr <= bram_addr_c2+ 2'd2;
+
+            bram41_raddr <= bram_addr_c2- 1'd1;
+            bram42_raddr <= bram_addr_c2;
+            bram43_raddr <= bram_addr_c2+ 2'd1;
+            bram44_raddr <= bram_addr_c2+ 2'd2;
+
+        end
+        2'b10 : 
+        begin
+            bram21_raddr <= bram_addr_c2- 1'd1;
+            bram22_raddr <= bram_addr_c2;
+            bram23_raddr <= bram_addr_c2+ 2'd1;
+            bram24_raddr <= bram_addr_c2+ 2'd2;
+
+            bram31_raddr <= bram_addr_c2- 1'd1;
+            bram32_raddr <= bram_addr_c2;
+            bram33_raddr <= bram_addr_c2+ 2'd1;
+            bram34_raddr <= bram_addr_c2+ 2'd2;
+
+            bram41_raddr <= bram_addr_c2- 1'd1;
+            bram42_raddr <= bram_addr_c2;
+            bram43_raddr <= bram_addr_c2+ 2'd1;
+            bram44_raddr <= bram_addr_c2+ 2'd2;
+
+            bram11_raddr <= bram_addr_c2+ 11'd1023;
+            bram12_raddr <= bram_addr_c2+ 11'd1024;
+            bram13_raddr <= bram_addr_c2+ 11'd1025;
+            bram14_raddr <= bram_addr_c2+ 11'd1026;
+
+        end
+        2'b11 : 
+        begin
+            bram31_raddr <= bram_addr_c2- 1'd1;
+            bram32_raddr <= bram_addr_c2;
+            bram33_raddr <= bram_addr_c2+ 2'd1;
+            bram34_raddr <= bram_addr_c2+ 2'd2;
+
+            bram41_raddr <= bram_addr_c2- 1'd1;
+            bram42_raddr <= bram_addr_c2;
+            bram43_raddr <= bram_addr_c2+ 2'd1;
+            bram44_raddr <= bram_addr_c2+ 2'd2;
+
+            bram11_raddr <= bram_addr_c2+ 11'd1023;
+            bram12_raddr <= bram_addr_c2+ 11'd1024;
+            bram13_raddr <= bram_addr_c2+ 11'd1025;
+            bram14_raddr <= bram_addr_c2+ 11'd1026;
+
+            bram21_raddr <= bram_addr_c2+ 11'd1023;
+            bram22_raddr <= bram_addr_c2+ 11'd1024;
+            bram23_raddr <= bram_addr_c2+ 11'd1025;
+            bram24_raddr <= bram_addr_c2+ 11'd1026;
+
+            
+        end
+    endcase
+end
+
+reg             [33:0]          frac_00_c3;
+reg             [33:0]          frac_01_c3;
+reg             [33:0]          frac_10_c3;
+reg             [33:0]          frac_11_c3;
+reg             [ 1:0]          bram_mode_c3;
+reg                             left_pixel_extand_flag_c3;
+reg                             right_pixel_extand_flag_1_c3;
+reg                             right_pixel_extand_flag_2_c3;
+reg                             top_pixel_extand_flag_c3;
+reg                             bottom_pixel_extand_flag_1_c3;
+reg                             bottom_pixel_extand_flag_2_c3;
+
+
+always @(posedge clk_in2)
+begin
+    frac_00_c3                  <= frac_00_c2;
+    frac_01_c3                  <= frac_01_c2;
+    frac_10_c3                  <= frac_10_c2;
+    frac_11_c3                  <= frac_11_c2;
+    bram_mode_c3                <= bram_mode_c2;
+    left_pixel_extand_flag_c3      <=left_pixel_extand_flag_c2;
+    right_pixel_extand_flag_1_c3   <=right_pixel_extand_flag_1_c2;
+    right_pixel_extand_flag_2_c3   <=right_pixel_extand_flag_2_c2;
+    top_pixel_extand_flag_c3       <=top_pixel_extand_flag_c2;
+    bottom_pixel_extand_flag_1_c3  <=bottom_pixel_extand_flag_1_c2;
+    bottom_pixel_extand_flag_2_c3  <=bottom_pixel_extand_flag_2_c2;   
+end
+
+reg                             xmax_c3;
+reg                             ymax_c3;
+always @(posedge clk_in2)
+begin
+    xmax_c3     <=xmax_c2;
+    ymax_c3     <=ymax_c2;
+end
+
+//----------------------------------------------------------------------
+//  c4
+reg                             img_vs_c4;
+reg                             img_hs_c4;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c4 <= 1'b0;
+        img_hs_c4 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c4 <= img_vs_c3;
+        img_hs_c4 <= img_hs_c3;
+    end
+end
+
+reg             [33:0]          frac_00_c4;
+reg             [33:0]          frac_01_c4;
+reg             [33:0]          frac_10_c4;
+reg             [33:0]          frac_11_c4;
+reg             [ 1:0]          bram_mode_c4;
+reg                             left_extand_flag_c4    ;
+reg                             right_extand_flag_1_c4 ;
+reg                             right_extand_flag_2_c4 ;
+reg                             top_extand_flag_c4     ;
+reg                             bottom_extand_flag_1_c4;
+reg                             bottom_extand_flag_2_c4;
+reg                             xmax_c4;
+reg                             ymax_c4;
+
+always @(posedge clk_in2)
+begin
+    frac_00_c4                  <= frac_00_c3;
+    frac_01_c4                  <= frac_01_c3;
+    frac_10_c4                  <= frac_10_c3;
+    frac_11_c4                  <= frac_11_c3;
+    bram_mode_c4                <= bram_mode_c3;
+    left_extand_flag_c4         <=left_pixel_extand_flag_c3   ;
+    right_extand_flag_1_c4      <=right_pixel_extand_flag_1_c3;
+    right_extand_flag_2_c4      <=right_pixel_extand_flag_2_c3;
+    top_extand_flag_c4          <=top_pixel_extand_flag_c3    ;
+    bottom_extand_flag_1_c4     <=bottom_pixel_extand_flag_1_c3;
+    bottom_extand_flag_2_c4     <=bottom_pixel_extand_flag_2_c3;
+    xmax_c4                     <=xmax_c3;
+    ymax_c4                     <=ymax_c3;
+end
+
+//----------------------------------------------------------------------
+//  c5
+reg                             img_vs_c5;
+reg                             img_hs_c5;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c5 <= 1'b0;
+        img_hs_c5 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c5 <= img_vs_c4;
+        img_hs_c5 <= img_hs_c4;
+    end
+end
+
+reg             [7:0]           pixel_data11_c5;
+reg             [7:0]           pixel_data12_c5;
+reg             [7:0]           pixel_data13_c5;
+reg             [7:0]           pixel_data14_c5;
+
+reg             [7:0]           pixel_data21_c5;
+reg             [7:0]           pixel_data22_c5;
+reg             [7:0]           pixel_data23_c5;
+reg             [7:0]           pixel_data24_c5;
+
+reg             [7:0]           pixel_data31_c5;
+reg             [7:0]           pixel_data32_c5;
+reg             [7:0]           pixel_data33_c5;
+reg             [7:0]           pixel_data34_c5;
+
+reg             [7:0]           pixel_data41_c5;
+reg             [7:0]           pixel_data42_c5;
+reg             [7:0]           pixel_data43_c5;
+reg             [7:0]           pixel_data44_c5;
+
+always @(posedge clk_in2)
+begin
+    case(bram_mode_c4)
+        2'b00 : 
+        begin
+            pixel_data11_c5 <= bram41_rdata;
+            pixel_data12_c5 <= bram42_rdata;
+            pixel_data13_c5 <= bram43_rdata;
+            pixel_data14_c5 <= bram44_rdata;
+
+            pixel_data21_c5 <= bram11_rdata;
+            pixel_data22_c5 <= bram12_rdata;
+            pixel_data23_c5 <= bram13_rdata;
+            pixel_data24_c5 <= bram14_rdata;
+
+            pixel_data31_c5 <= bram21_rdata;
+            pixel_data32_c5 <= bram22_rdata;
+            pixel_data33_c5 <= bram23_rdata;
+            pixel_data34_c5 <= bram24_rdata;
+
+            pixel_data41_c5 <= bram31_rdata;
+            pixel_data42_c5 <= bram32_rdata;
+            pixel_data43_c5 <= bram33_rdata;
+            pixel_data44_c5 <= bram34_rdata;
+        end
+        2'b01 : 
+        begin
+            pixel_data11_c5 <= bram11_rdata;
+            pixel_data12_c5 <= bram12_rdata;
+            pixel_data13_c5 <= bram13_rdata;
+            pixel_data14_c5 <= bram14_rdata;
+
+            pixel_data21_c5 <= bram21_rdata;
+            pixel_data22_c5 <= bram22_rdata;
+            pixel_data23_c5 <= bram23_rdata;
+            pixel_data24_c5 <= bram24_rdata;
+
+            pixel_data31_c5 <= bram31_rdata;
+            pixel_data32_c5 <= bram32_rdata;
+            pixel_data33_c5 <= bram33_rdata;
+            pixel_data34_c5 <= bram34_rdata;
+
+            pixel_data41_c5 <= bram41_rdata;
+            pixel_data42_c5 <= bram42_rdata;
+            pixel_data43_c5 <= bram43_rdata;
+            pixel_data44_c5 <= bram44_rdata;
+        end
+        2'b10 : 
+        begin
+            pixel_data11_c5 <= bram21_rdata;
+            pixel_data12_c5 <= bram22_rdata;
+            pixel_data13_c5 <= bram23_rdata;
+            pixel_data14_c5 <= bram24_rdata;
+
+            pixel_data21_c5 <= bram31_rdata;
+            pixel_data22_c5 <= bram32_rdata;
+            pixel_data23_c5 <= bram33_rdata;
+            pixel_data24_c5 <= bram34_rdata;
+
+            pixel_data31_c5 <= bram41_rdata;
+            pixel_data32_c5 <= bram42_rdata;
+            pixel_data33_c5 <= bram43_rdata;
+            pixel_data34_c5 <= bram44_rdata;
+
+            pixel_data41_c5 <= bram11_rdata;
+            pixel_data42_c5 <= bram12_rdata;
+            pixel_data43_c5 <= bram13_rdata;
+            pixel_data44_c5 <= bram14_rdata;
+        end
+        2'b11 : 
+        begin
+            pixel_data11_c5 <= bram31_rdata;
+            pixel_data12_c5 <= bram32_rdata;
+            pixel_data13_c5 <= bram33_rdata;
+            pixel_data14_c5 <= bram34_rdata;
+
+            pixel_data21_c5 <= bram41_rdata;
+            pixel_data22_c5 <= bram42_rdata;
+            pixel_data23_c5 <= bram43_rdata;
+            pixel_data24_c5 <= bram44_rdata;
+
+            pixel_data31_c5 <= bram11_rdata;
+            pixel_data32_c5 <= bram12_rdata;
+            pixel_data33_c5 <= bram13_rdata;
+            pixel_data34_c5 <= bram14_rdata;
+
+            pixel_data41_c5 <= bram21_rdata;
+            pixel_data42_c5 <= bram22_rdata;
+            pixel_data43_c5 <= bram23_rdata;
+            pixel_data44_c5 <= bram24_rdata; 
+        end
+    endcase
+end
+
+reg             [33:0]          frac_00_c5;
+reg             [33:0]          frac_01_c5;
+reg             [33:0]          frac_10_c5;
+reg             [33:0]          frac_11_c5;
+reg                             left_extand_flag_c5;
+reg                             right_extand_flag_1_c5;
+reg                             right_extand_flag_2_c5;
+reg                             top_extand_flag_c5;
+reg                             bottom_extand_flag_1_c5;
+reg                             bottom_extand_flag_2_c5;
+reg                             xmax_c5;
+reg                             ymax_c5;
+
+always @(posedge clk_in2)
+begin
+    frac_00_c5                  <= frac_00_c4;
+    frac_01_c5                  <= frac_01_c4;
+    frac_10_c5                  <= frac_10_c4;
+    frac_11_c5                  <= frac_11_c4;
+    left_extand_flag_c5           <=left_extand_flag_c4   ;
+    right_extand_flag_1_c5        <=right_extand_flag_1_c4;
+    right_extand_flag_2_c5        <=right_extand_flag_2_c4;
+    top_extand_flag_c5            <=top_extand_flag_c4    ;
+    bottom_extand_flag_1_c5       <=bottom_extand_flag_1_c4;
+    bottom_extand_flag_2_c5       <=bottom_extand_flag_2_c4;
+    xmax_c5                     <=xmax_c4;
+    ymax_c5                     <=ymax_c4;
+end
+
+//----------------------------------------------------------------------
+//  c6
+reg                             img_vs_c6;
+reg                             img_hs_c6;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c6 <= 1'b0;
+        img_hs_c6 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c6 <= img_vs_c5;
+        img_hs_c6 <= img_hs_c5;
+    end
+end
+
+reg             [7:0]           pixel_data11_c6, pixel_data12_c6, pixel_data13_c6, pixel_data14_c6; 
+reg             [7:0]           pixel_data21_c6, pixel_data22_c6, pixel_data23_c6, pixel_data24_c6;
+reg             [7:0]           pixel_data31_c6, pixel_data32_c6, pixel_data33_c6, pixel_data34_c6;
+reg             [7:0]           pixel_data41_c6, pixel_data42_c6, pixel_data43_c6, pixel_data44_c6;
+
+always @(posedge clk_in2)
+begin
+    case({left_extand_flag_c5,right_extand_flag_1_c5,right_extand_flag_2_c5,top_extand_flag_c5,bottom_extand_flag_1_c5,bottom_extand_flag_2_c5})
+        6'b000000 : //01
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data44_c5;
+        end
+        6'b000001 ://02
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data21_c5;
+            pixel_data32_c6 <= pixel_data22_c5;
+            pixel_data33_c6 <= pixel_data23_c5;
+            pixel_data34_c6 <= pixel_data24_c5;
+
+            pixel_data41_c6 <= pixel_data21_c5;
+            pixel_data42_c6 <= pixel_data22_c5;
+            pixel_data43_c6 <= pixel_data23_c5;
+            pixel_data44_c6 <= pixel_data24_c5;
+        end
+        6'b000010 ://03
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data31_c5;
+            pixel_data42_c6 <= pixel_data32_c5;
+            pixel_data43_c6 <= pixel_data33_c5;
+            pixel_data44_c6 <= pixel_data34_c5;
+        end
+        6'b000100 ://04
+        begin
+            pixel_data11_c6 <= pixel_data21_c5;
+            pixel_data12_c6 <= pixel_data22_c5;
+            pixel_data13_c6 <= pixel_data23_c5;
+            pixel_data14_c6 <= pixel_data24_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data44_c5;
+        end
+
+
+        6'b001000 : //11
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data12_c5;
+            pixel_data14_c6 <= pixel_data12_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data22_c5;
+            pixel_data24_c6 <= pixel_data22_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data32_c5;
+            pixel_data34_c6 <= pixel_data32_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data42_c5;
+            pixel_data44_c6 <= pixel_data42_c5;
+        end
+        6'b001001 ://12
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data12_c5;
+            pixel_data14_c6 <= pixel_data12_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data22_c5;
+            pixel_data24_c6 <= pixel_data22_c5;
+
+            pixel_data31_c6 <= pixel_data21_c5;
+            pixel_data32_c6 <= pixel_data22_c5;
+            pixel_data33_c6 <= pixel_data22_c5;
+            pixel_data34_c6 <= pixel_data22_c5;
+
+            pixel_data41_c6 <= pixel_data21_c5;
+            pixel_data42_c6 <= pixel_data22_c5;
+            pixel_data43_c6 <= pixel_data22_c5;
+            pixel_data44_c6 <= pixel_data22_c5;
+        end
+        6'b001010 ://13
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data12_c5;
+            pixel_data14_c6 <= pixel_data12_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data22_c5;
+            pixel_data24_c6 <= pixel_data22_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data32_c5;
+            pixel_data34_c6 <= pixel_data32_c5;
+
+            pixel_data41_c6 <= pixel_data31_c5;
+            pixel_data42_c6 <= pixel_data32_c5;
+            pixel_data43_c6 <= pixel_data32_c5;
+            pixel_data44_c6 <= pixel_data32_c5;
+        end
+        6'b001100 ://14
+        begin
+            pixel_data11_c6 <= pixel_data21_c5;
+            pixel_data12_c6 <= pixel_data22_c5;
+            pixel_data13_c6 <= pixel_data22_c5;
+            pixel_data14_c6 <= pixel_data22_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data22_c5;
+            pixel_data24_c6 <= pixel_data22_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data32_c5;
+            pixel_data34_c6 <= pixel_data32_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data42_c5;
+            pixel_data44_c6 <= pixel_data42_c5;
+        end
+
+        6'b010000 : //21
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data13_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data23_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data33_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data43_c5;
+        end
+        6'b010001 ://22
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data13_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data23_c5;
+
+            pixel_data31_c6 <= pixel_data21_c5;
+            pixel_data32_c6 <= pixel_data22_c5;
+            pixel_data33_c6 <= pixel_data23_c5;
+            pixel_data34_c6 <= pixel_data23_c5;
+
+            pixel_data41_c6 <= pixel_data21_c5;
+            pixel_data42_c6 <= pixel_data22_c5;
+            pixel_data43_c6 <= pixel_data23_c5;
+            pixel_data44_c6 <= pixel_data23_c5;
+        end
+        6'b010010 ://23
+        begin
+            pixel_data11_c6 <= pixel_data11_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data13_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data23_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data33_c5;
+
+            pixel_data41_c6 <= pixel_data31_c5;
+            pixel_data42_c6 <= pixel_data32_c5;
+            pixel_data43_c6 <= pixel_data33_c5;
+            pixel_data44_c6 <= pixel_data33_c5;
+        end
+        6'b010100 ://24
+        begin
+            pixel_data11_c6 <= pixel_data21_c5;
+            pixel_data12_c6 <= pixel_data22_c5;
+            pixel_data13_c6 <= pixel_data23_c5;
+            pixel_data14_c6 <= pixel_data23_c5;
+
+            pixel_data21_c6 <= pixel_data21_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data23_c5;
+
+            pixel_data31_c6 <= pixel_data31_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data33_c5;
+
+            pixel_data41_c6 <= pixel_data41_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data43_c5;
+        end
+
+        6'b100000 : //31
+        begin
+            pixel_data11_c6 <= pixel_data12_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data22_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data32_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data42_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data44_c5;
+        end
+        6'b100001 ://32
+        begin
+            pixel_data11_c6 <= pixel_data12_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data22_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data22_c5;
+            pixel_data32_c6 <= pixel_data22_c5;
+            pixel_data33_c6 <= pixel_data23_c5;
+            pixel_data34_c6 <= pixel_data24_c5;
+
+            pixel_data41_c6 <= pixel_data22_c5;
+            pixel_data42_c6 <= pixel_data22_c5;
+            pixel_data43_c6 <= pixel_data23_c5;
+            pixel_data44_c6 <= pixel_data24_c5;
+        end
+        6'b100010 ://33
+        begin
+            pixel_data11_c6 <= pixel_data12_c5;
+            pixel_data12_c6 <= pixel_data12_c5;
+            pixel_data13_c6 <= pixel_data13_c5;
+            pixel_data14_c6 <= pixel_data14_c5;
+
+            pixel_data21_c6 <= pixel_data22_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data32_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data32_c5;
+            pixel_data42_c6 <= pixel_data32_c5;
+            pixel_data43_c6 <= pixel_data33_c5;
+            pixel_data44_c6 <= pixel_data34_c5;
+        end
+        6'b100100 ://34
+        begin
+            pixel_data11_c6 <= pixel_data22_c5;
+            pixel_data12_c6 <= pixel_data22_c5;
+            pixel_data13_c6 <= pixel_data23_c5;
+            pixel_data14_c6 <= pixel_data24_c5;
+
+            pixel_data21_c6 <= pixel_data22_c5;
+            pixel_data22_c6 <= pixel_data22_c5;
+            pixel_data23_c6 <= pixel_data23_c5;
+            pixel_data24_c6 <= pixel_data24_c5;
+
+            pixel_data31_c6 <= pixel_data32_c5;
+            pixel_data32_c6 <= pixel_data32_c5;
+            pixel_data33_c6 <= pixel_data33_c5;
+            pixel_data34_c6 <= pixel_data34_c5;
+
+            pixel_data41_c6 <= pixel_data42_c5;
+            pixel_data42_c6 <= pixel_data42_c5;
+            pixel_data43_c6 <= pixel_data43_c5;
+            pixel_data44_c6 <= pixel_data44_c5;
+        end
+    endcase
+end
+
+reg             [33:0]          frac_00_c6;
+reg             [33:0]          frac_01_c6;
+reg             [33:0]          frac_10_c6;
+reg             [33:0]          frac_11_c6;
+reg                             xmax_c6;
+reg                             ymax_c6;
+
+always @(posedge clk_in2)
+begin
+    frac_00_c6 <= frac_00_c5;
+    frac_01_c6 <= frac_01_c5;
+    frac_10_c6 <= frac_10_c5;
+    frac_11_c6 <= frac_11_c5;
+    xmax_c6                     <=xmax_c5;
+    ymax_c6                     <=ymax_c5;
+end
+
+//----------------------------------------------------------------------
+//  c7
+reg                             img_vs_c7;
+reg                             img_hs_c7;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c7 <= 1'b0;
+        img_hs_c7 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c7 <= img_vs_c6;
+        img_hs_c7 <= img_hs_c6;
+    end
+end
+
+reg             [41:0]          gray_data00_c7;
+reg             [41:0]          gray_data01_c7;
+reg             [41:0]          gray_data10_c7;
+reg             [41:0]          gray_data11_c7;
+
+always @(posedge clk_in2)
+begin
+    gray_data00_c7 <= frac_00_c6 * pixel_data22_c6;
+    gray_data01_c7 <= frac_01_c6 * pixel_data23_c6;
+    gray_data10_c7 <= frac_10_c6 * pixel_data32_c6;
+    gray_data11_c7 <= frac_11_c6 * pixel_data33_c6;
+end
+
+reg             [7:0]          gray_data_max_c7;        
+
+always @(posedge clk_in2)
+begin
+    case({ymax_c6,xmax_c6})
+        2'b00 : 
+        begin
+            gray_data_max_c7 <= pixel_data22_c6;
+        end
+        2'b01 : 
+        begin
+            gray_data_max_c7 <= pixel_data23_c6;
+        end
+        2'b10 : 
+        begin
+            gray_data_max_c7 <= pixel_data32_c6;
+        end
+        2'b11 : 
+        begin
+            gray_data_max_c7 <= pixel_data33_c6;
+        end
+    endcase
+end
+
+reg             [7:0]           pixel_data11_c7, pixel_data12_c7, pixel_data13_c7, pixel_data14_c7;
+reg             [7:0]           pixel_data21_c7, pixel_data22_c7, pixel_data23_c7, pixel_data24_c7;
+reg             [7:0]           pixel_data31_c7, pixel_data32_c7, pixel_data33_c7, pixel_data34_c7;
+reg             [7:0]           pixel_data41_c7, pixel_data42_c7, pixel_data43_c7, pixel_data44_c7;
+always @(posedge clk_in2)
+begin
+    pixel_data11_c7 <= pixel_data11_c6;
+    pixel_data12_c7 <= pixel_data12_c6;
+    pixel_data13_c7 <= pixel_data13_c6;
+    pixel_data14_c7 <= pixel_data14_c6;
+    pixel_data21_c7 <= pixel_data21_c6;
+    pixel_data22_c7 <= pixel_data22_c6;
+    pixel_data23_c7 <= pixel_data23_c6;
+    pixel_data24_c7 <= pixel_data24_c6;
+    pixel_data31_c7 <= pixel_data31_c6;
+    pixel_data32_c7 <= pixel_data32_c6;
+    pixel_data33_c7 <= pixel_data33_c6;
+    pixel_data34_c7 <= pixel_data34_c6;
+    pixel_data41_c7 <= pixel_data41_c6;
+    pixel_data42_c7 <= pixel_data42_c6;
+    pixel_data43_c7 <= pixel_data43_c6;
+    pixel_data44_c7 <= pixel_data44_c6;
+end
+
+//----------------------------------------------------------------------
+//  c8
+reg                             img_vs_c8;
+reg                             img_hs_c8;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c8 <= 1'b0;
+        img_hs_c8 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c8 <= img_vs_c7;
+        img_hs_c8 <= img_hs_c7;
+    end
+end
+
+reg             [42:0]          gray_data_tmp1_c8;
+reg             [42:0]          gray_data_tmp2_c8;
+
+always @(posedge clk_in2)
+begin
+    gray_data_tmp1_c8 <= gray_data00_c7 + gray_data01_c7;
+    gray_data_tmp2_c8 <= gray_data10_c7 + gray_data11_c7;
+end
+
+reg             [7:0]          gray_data_max_c8;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c8 <= gray_data_max_c7;
+end
+
+
+
+
+reg             [7:0]           pixel_data11_c8, pixel_data12_c8, pixel_data13_c8, pixel_data14_c8;
+reg             [7:0]           pixel_data21_c8, pixel_data22_c8, pixel_data23_c8, pixel_data24_c8;
+reg             [7:0]           pixel_data31_c8, pixel_data32_c8, pixel_data33_c8, pixel_data34_c8;
+reg             [7:0]           pixel_data41_c8, pixel_data42_c8, pixel_data43_c8, pixel_data44_c8;
+always @(posedge clk_in2)
+begin
+    pixel_data11_c8 <= pixel_data11_c7;
+    pixel_data12_c8 <= pixel_data12_c7;
+    pixel_data13_c8 <= pixel_data13_c7;
+    pixel_data14_c8 <= pixel_data14_c7;
+    pixel_data21_c8 <= pixel_data21_c7;
+    pixel_data22_c8 <= pixel_data22_c7;
+    pixel_data23_c8 <= pixel_data23_c7;
+    pixel_data24_c8 <= pixel_data24_c7;
+    pixel_data31_c8 <= pixel_data31_c7;
+    pixel_data32_c8 <= pixel_data32_c7;
+    pixel_data33_c8 <= pixel_data33_c7;
+    pixel_data34_c8 <= pixel_data34_c7;
+    pixel_data41_c8 <= pixel_data41_c7;
+    pixel_data42_c8 <= pixel_data42_c7;
+    pixel_data43_c8 <= pixel_data43_c7;
+    pixel_data44_c8 <= pixel_data44_c7;
+end
+
+//----------------------------------------------------------------------
+//  c9
+reg                             img_vs_c9;
+reg                             img_hs_c9;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c9 <= 1'b0;
+        img_hs_c9 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c9 <= img_vs_c8;
+        img_hs_c9 <= img_hs_c8;
+    end
+end
+
+reg             [43:0]          gray_data_c9;
+
+always @(posedge clk_in2)
+begin
+    gray_data_c9 <= gray_data_tmp1_c8 + gray_data_tmp2_c8;
+end
+
+reg             [7:0]          gray_data_max_c9;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c9 <= gray_data_max_c8;
+end
+
+reg             [7:0]           pixel_data11_c9, pixel_data12_c9, pixel_data13_c9, pixel_data14_c9;
+reg             [7:0]           pixel_data21_c9, pixel_data22_c9, pixel_data23_c9, pixel_data24_c9;
+reg             [7:0]           pixel_data31_c9, pixel_data32_c9, pixel_data33_c9, pixel_data34_c9;
+reg             [7:0]           pixel_data41_c9, pixel_data42_c9, pixel_data43_c9, pixel_data44_c9;
+always @(posedge clk_in2)
+begin
+    pixel_data11_c9 <= pixel_data11_c8;
+    pixel_data12_c9 <= pixel_data12_c8;
+    pixel_data13_c9 <= pixel_data13_c8;
+    pixel_data14_c9 <= pixel_data14_c8;
+    pixel_data21_c9 <= pixel_data21_c8;
+    pixel_data22_c9 <= pixel_data22_c8;
+    pixel_data23_c9 <= pixel_data23_c8;
+    pixel_data24_c9 <= pixel_data24_c8;
+    pixel_data31_c9 <= pixel_data31_c8;
+    pixel_data32_c9 <= pixel_data32_c8;
+    pixel_data33_c9 <= pixel_data33_c8;
+    pixel_data34_c9 <= pixel_data34_c8;
+    pixel_data41_c9 <= pixel_data41_c8;
+    pixel_data42_c9 <= pixel_data42_c8;
+    pixel_data43_c9 <= pixel_data43_c8;
+    pixel_data44_c9 <= pixel_data44_c8;
+end
+
+//----------------------------------------------------------------------
+//  c10
+reg                             img_vs_c10;
+reg                             img_hs_c10;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c10 <= 1'b0;
+        img_hs_c10 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c10 <= img_vs_c9;
+        img_hs_c10 <= img_hs_c9;
+    end
+end
+
+reg             [11:0]          gray_data_c10;
+
+always @(posedge clk_in2)
+begin
+    gray_data_c10 <= gray_data_c9[43:32] + gray_data_c9[31];
+end
+
+reg             [7:0]          gray_data_max_c10;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c10 <= gray_data_max_c9;
+end
+
+reg             [7:0]           pixel_data11_c10, pixel_data12_c10, pixel_data13_c10, pixel_data14_c10;
+reg             [7:0]           pixel_data21_c10, pixel_data22_c10, pixel_data23_c10, pixel_data24_c10;
+reg             [7:0]           pixel_data31_c10, pixel_data32_c10, pixel_data33_c10, pixel_data34_c10;
+reg             [7:0]           pixel_data41_c10, pixel_data42_c10, pixel_data43_c10, pixel_data44_c10;
+always @(posedge clk_in2)
+begin
+    pixel_data11_c10 <= pixel_data11_c9;
+    pixel_data12_c10 <= pixel_data12_c9;
+    pixel_data13_c10 <= pixel_data13_c9;
+    pixel_data14_c10 <= pixel_data14_c9;
+    pixel_data21_c10 <= pixel_data21_c9;
+    pixel_data22_c10 <= pixel_data22_c9;
+    pixel_data23_c10 <= pixel_data23_c9;
+    pixel_data24_c10 <= pixel_data24_c9;
+    pixel_data31_c10 <= pixel_data31_c9;
+    pixel_data32_c10 <= pixel_data32_c9;
+    pixel_data33_c10 <= pixel_data33_c9;
+    pixel_data34_c10 <= pixel_data34_c9;
+    pixel_data41_c10 <= pixel_data41_c9;
+    pixel_data42_c10 <= pixel_data42_c9;
+    pixel_data43_c10 <= pixel_data43_c9;
+    pixel_data44_c10 <= pixel_data44_c9;
+end
+
+//----------------------------------------------------------------------
+//  c11
+reg                             img_vs_c11;
+reg                             img_hs_c11;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c11 <= 1'b0;
+        img_hs_c11 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c11 <= img_vs_c10;
+        img_hs_c11 <= img_hs_c10;
+    end
+end
+
+reg             [7:0]          gray_data_c11;
+
+always @(posedge clk_in2)
+begin
+    gray_data_c11 <= gray_data_c10[7:0];
+end
+
+reg             [7:0]          gray_data_max_c11;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c11 <= gray_data_max_c10;
+end
+
+reg             [7:0]           pixel_data11_c11, pixel_data12_c11, pixel_data13_c11, pixel_data14_c11;
+reg             [7:0]           pixel_data21_c11, pixel_data22_c11, pixel_data23_c11, pixel_data24_c11;
+reg             [7:0]           pixel_data31_c11, pixel_data32_c11, pixel_data33_c11, pixel_data34_c11;
+reg             [7:0]           pixel_data41_c11, pixel_data42_c11, pixel_data43_c11, pixel_data44_c11;
+always @(posedge clk_in2)
+begin
+    pixel_data11_c11 <= pixel_data11_c10;
+    pixel_data12_c11 <= pixel_data12_c10;
+    pixel_data13_c11 <= pixel_data13_c10;
+    pixel_data14_c11 <= pixel_data14_c10;
+    pixel_data21_c11 <= pixel_data21_c10;
+    pixel_data22_c11 <= pixel_data22_c10;
+    pixel_data23_c11 <= pixel_data23_c10;
+    pixel_data24_c11 <= pixel_data24_c10;
+    pixel_data31_c11 <= pixel_data31_c10;
+    pixel_data32_c11 <= pixel_data32_c10;
+    pixel_data33_c11 <= pixel_data33_c10;
+    pixel_data34_c11 <= pixel_data34_c10;
+    pixel_data41_c11 <= pixel_data41_c10;
+    pixel_data42_c11 <= pixel_data42_c10;
+    pixel_data43_c11 <= pixel_data43_c10;
+    pixel_data44_c11 <= pixel_data44_c10;
+end
+
+
+//----------------------------------------------------------------------
+//  c12
+reg                             img_vs_c12;
+reg                             img_hs_c12;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c12 <= 1'b0;
+        img_hs_c12 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c12 <= img_vs_c11;
+        img_hs_c12 <= img_hs_c11;
+    end
+end
+
+reg             [7:0]          gray_data_c12;
+
+always @(posedge clk_in2)
+begin
+    gray_data_c12 <= gray_data_c11;
+end
+
+reg             [7:0]          gray_data_max_c12;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c12 <= gray_data_max_c11;
+end
+
+
+localparam NUM_FLT = 16;
+reg [(NUM_FLT+8+1):0] weight_data00_c12, weight_data01_c12, weight_data02_c12, weight_data03_c12;// (33,24)
+reg [(NUM_FLT+8+1):0] weight_data10_c12, weight_data11_c12, weight_data12_c12, weight_data13_c12;
+reg [(NUM_FLT+8+1):0] weight_data20_c12, weight_data21_c12, weight_data22_c12, weight_data23_c12;
+reg [(NUM_FLT+8+1):0] weight_data30_c12, weight_data31_c12, weight_data32_c12, weight_data33_c12;
+always @(posedge clk_in2)
+begin
+    weight_data00_c12 <=coeff00_c11[33:(32-NUM_FLT)] *pixel_data11_c11;
+    weight_data01_c12 <=coeff01_c11[33:(32-NUM_FLT)] *pixel_data12_c11;
+    weight_data02_c12 <=coeff02_c11[33:(32-NUM_FLT)] *pixel_data13_c11;
+    weight_data03_c12 <=coeff03_c11[33:(32-NUM_FLT)] *pixel_data14_c11;
+
+    weight_data10_c12 <=coeff10_c11[33:(32-NUM_FLT)] *pixel_data21_c11;
+    weight_data11_c12 <=coeff11_c11[33:(32-NUM_FLT)] *pixel_data22_c11;
+    weight_data12_c12 <=coeff12_c11[33:(32-NUM_FLT)] *pixel_data23_c11;
+    weight_data13_c12 <=coeff13_c11[33:(32-NUM_FLT)] *pixel_data24_c11;
+
+    weight_data20_c12 <=coeff20_c11[33:(32-NUM_FLT)] *pixel_data31_c11;
+    weight_data21_c12 <=coeff21_c11[33:(32-NUM_FLT)] *pixel_data32_c11;
+    weight_data22_c12 <=coeff22_c11[33:(32-NUM_FLT)] *pixel_data33_c11;
+    weight_data23_c12 <=coeff23_c11[33:(32-NUM_FLT)] *pixel_data34_c11;
+
+    weight_data30_c12 <=coeff30_c11[33:(32-NUM_FLT)] *pixel_data41_c11;
+    weight_data31_c12 <=coeff31_c11[33:(32-NUM_FLT)] *pixel_data42_c11;
+    weight_data32_c12 <=coeff32_c11[33:(32-NUM_FLT)] *pixel_data43_c11;
+    weight_data33_c12 <=coeff33_c11[33:(32-NUM_FLT)] *pixel_data44_c11;
+end
+
+//----------------------------------------------------------------------
+//  c13
+
+reg                             img_vs_c13;
+reg                             img_hs_c13;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c13 <= 1'b0;
+        img_hs_c13 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c13 <= img_vs_c12;
+        img_hs_c13 <= img_hs_c12;
+    end
+end
+
+reg             [7:0]          gray_data_max_c13;
+reg             [7:0]          gray_data_c13;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c13 <= gray_data_max_c12;
+    gray_data_c13 <= gray_data_c12;
+end
+
+reg [(NUM_FLT+8+2):0] weight_data_temp1_c13,weight_data_temp2_c13;
+reg [(NUM_FLT+8+2):0] weight_data_temp3_c13,weight_data_temp4_c13;
+reg [(NUM_FLT+8+2):0] weight_data_temp5_c13,weight_data_temp6_c13;
+reg [(NUM_FLT+8+2):0] weight_data_temp7_c13,weight_data_temp8_c13;
+
+always @(posedge clk_in2)
+begin
+    weight_data_temp1_c13 <= weight_data00_c12+weight_data03_c12;
+    weight_data_temp2_c13 <= weight_data11_c12+weight_data12_c12;
+    weight_data_temp3_c13 <= weight_data21_c12+weight_data22_c12;
+    weight_data_temp4_c13 <= weight_data30_c12+weight_data33_c12;
+
+    weight_data_temp5_c13 <= weight_data01_c12+weight_data02_c12;
+    weight_data_temp6_c13 <= weight_data10_c12+weight_data13_c12;
+    weight_data_temp7_c13 <= weight_data20_c12+weight_data23_c12;
+    weight_data_temp8_c13 <= weight_data31_c12+weight_data32_c12;
+
+end
+
+//----------------------------------------------------------------------
+//  c14
+
+reg                             img_vs_c14;
+reg                             img_hs_c14;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c14 <= 1'b0;
+        img_hs_c14 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c14 <= img_vs_c13;
+        img_hs_c14 <= img_hs_c13;
+    end
+end
+
+reg             [7:0]          gray_data_max_c14;
+reg             [7:0]          gray_data_c14;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c14   <= gray_data_max_c13;
+    gray_data_c14       <= gray_data_c13;
+end
+
+reg [(NUM_FLT+8+3):0] weight_data_temp21_c14,weight_data_temp22_c14;
+reg [(NUM_FLT+8+3):0] weight_data_temp23_c14,weight_data_temp24_c14;
+
+always @(posedge clk_in2)
+begin
+    weight_data_temp21_c14 <= weight_data_temp1_c13+weight_data_temp2_c13;
+    weight_data_temp22_c14 <= weight_data_temp3_c13+weight_data_temp4_c13;
+
+    weight_data_temp23_c14 <= weight_data_temp5_c13+weight_data_temp6_c13;
+    weight_data_temp24_c14 <= weight_data_temp7_c13+weight_data_temp8_c13;
+end
+
+//----------------------------------------------------------------------
+//  c15
+
+reg                             img_vs_c15;
+reg                             img_hs_c15;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c15 <= 1'b0;
+        img_hs_c15 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c15 <= img_vs_c14;
+        img_hs_c15 <= img_hs_c14;
+    end
+end
+
+reg             [7:0]          gray_data_max_c15;
+reg             [7:0]          gray_data_c15;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c15   <= gray_data_max_c14;
+    gray_data_c15       <= gray_data_c14;
+end
+
+reg [(NUM_FLT+8+4):0] weight_data_temp31_c15,weight_data_temp32_c15;
+
+always @(posedge clk_in2)
+begin
+    weight_data_temp31_c15 <= weight_data_temp21_c14+weight_data_temp22_c14;
+    weight_data_temp32_c15 <= weight_data_temp23_c14+weight_data_temp24_c14;
+end
+
+//----------------------------------------------------------------------
+//  c16
+
+reg                             img_vs_c16;
+reg                             img_hs_c16;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c16 <= 1'b0;
+        img_hs_c16 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c16 <= img_vs_c15;
+        img_hs_c16 <= img_hs_c15;
+    end
+end
+
+reg             [7:0]          gray_data_max_c16;
+reg             [7:0]          gray_data_c16;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c16   <= gray_data_max_c15;
+        gray_data_c16       <= gray_data_c15;
+end
+
+reg [(NUM_FLT+8+5):0] weight_data_temp41_c16;
+
+always @(posedge clk_in2)
+begin
+    if(weight_data_temp31_c15 >= weight_data_temp32_c15)
+    begin
+        weight_data_temp41_c16 <= weight_data_temp31_c15 - weight_data_temp32_c15;
+    end
+    else
+    begin
+        weight_data_temp41_c16 <= 0;
+    end
+    
+end
+
+//----------------------------------------------------------------------
+//  c17
+
+reg                             img_vs_c17;
+reg                             img_hs_c17;
+
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        img_vs_c17 <= 1'b0;
+        img_hs_c17 <= 1'b0;
+    end
+    else
+    begin
+        img_vs_c17 <= img_vs_c16;
+        img_hs_c17 <= img_hs_c16;
+    end
+end
+
+reg             [7:0]          gray_data_max_c17;
+reg             [7:0]              gray_data_c17;
+always @(posedge clk_in2)
+begin
+    gray_data_max_c17   <= gray_data_max_c16;
+        gray_data_c17       <= gray_data_c16;
+end
+
+reg [13:0] weight_data_temp51_c17;
+
+always @(posedge clk_in2)
+begin
+    weight_data_temp51_c17 <= weight_data_temp41_c16[(NUM_FLT+8+5):NUM_FLT] + weight_data_temp41_c16[NUM_FLT-1];
+end
+
+//----------------------------------------------------------------------
+//  signals output
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+    begin
+        post_img_vsync <= 1'b0;
+        post_img_href  <= 1'b0;
+    end
+    else
+    begin
+        post_img_vsync <= img_vs_c17;
+        post_img_href  <= img_hs_c17;
+    end
+end
+
+always @(posedge clk_in2)
+begin
+
+    case({out_model})
+        2'b00 : 
+        begin
+            if(gray_data_max_c17 > 12'd255)
+                post_img_gray <= 8'd255;
+            else
+                post_img_gray <= gray_data_max_c17;
+        end
+        2'b01 : 
+        begin
+            if(gray_data_c17 > 12'd255)
+                post_img_gray <= 8'd255;
+            else
+                post_img_gray <= gray_data_c17;
+        end
+        2'b10 : 
+        begin
+            if(weight_data_temp51_c17 > 14'd255)
+                post_img_gray <= 8'd255;
+            else
+                post_img_gray <= weight_data_temp51_c17[7:0];
+        end
+        2'b11 : 
+        begin
+            if(gray_data_c17 > 12'd255)
+                post_img_gray <= 8'd255;
+            else
+                post_img_gray <= gray_data_c17;
+        end
+    endcase
+end
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/my16bram.v

@@ -0,0 +1,258 @@
+module my16bram (
+    input  wire             clk_in1 ,
+    input  wire             clk_in2,
+
+    input  wire                             bram0_wenb,
+    input  wire                             bram1_wenb, 
+    input  wire                             bram2_wenb,
+    input  wire                             bram3_wenb, 
+    input  wire             [10:0]          bram_waddr,
+    input  wire             [ 7:0]          bram_wdata,
+
+    input  wire            [10:0]          bram11_raddr,
+    input  wire            [10:0]          bram12_raddr,
+    input  wire            [10:0]          bram13_raddr,
+    input  wire            [10:0]          bram14_raddr,
+
+    input  wire            [10:0]          bram21_raddr,
+    input  wire            [10:0]          bram22_raddr,
+    input  wire            [10:0]          bram23_raddr,
+    input  wire            [10:0]          bram24_raddr,
+
+    input  wire            [10:0]          bram31_raddr,
+    input  wire            [10:0]          bram32_raddr,
+    input  wire            [10:0]          bram33_raddr,
+    input  wire            [10:0]          bram34_raddr,
+
+    input  wire            [10:0]          bram41_raddr,
+    input  wire            [10:0]          bram42_raddr,
+    input  wire            [10:0]          bram43_raddr,
+    input  wire            [10:0]          bram44_raddr,
+    
+
+    output              [ 7:0]          bram11_rdata,
+    output              [ 7:0]          bram12_rdata,
+    output              [ 7:0]          bram13_rdata,
+    output              [ 7:0]          bram14_rdata,
+
+    output              [ 7:0]          bram21_rdata,
+    output              [ 7:0]          bram22_rdata,
+    output              [ 7:0]          bram23_rdata,
+    output              [ 7:0]          bram24_rdata,
+
+    output              [ 7:0]          bram31_rdata,
+    output              [ 7:0]          bram32_rdata,
+    output              [ 7:0]          bram33_rdata,
+    output              [ 7:0]          bram34_rdata,
+
+    output              [ 7:0]          bram41_rdata,
+    output              [ 7:0]          bram42_rdata,
+    output              [ 7:0]          bram43_rdata,
+    output              [ 7:0]          bram44_rdata
+
+);
+
+// *******************************1line*******************************
+my_bram_ip  u11_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram0_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram11_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram11_rdata )
+);
+my_bram_ip  u12_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram0_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram12_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram12_rdata )
+);
+my_bram_ip  u13_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram0_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram13_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram13_rdata )
+);
+my_bram_ip  u14_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram0_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram14_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram14_rdata )
+);
+
+// *******************************2line*******************************
+my_bram_ip  u21_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram1_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram21_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram21_rdata )
+);
+my_bram_ip  u22_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram1_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram22_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram22_rdata )
+);
+my_bram_ip  u23_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram1_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram23_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram23_rdata )
+);
+my_bram_ip  u24_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram1_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram24_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram24_rdata )
+);
+
+// *******************************3line*******************************
+my_bram_ip  u31_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram2_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram31_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram31_rdata )
+);
+my_bram_ip  u32_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram2_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram32_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram32_rdata )
+);
+my_bram_ip  u33_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram2_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram33_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram33_rdata )
+);
+my_bram_ip  u34_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram2_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram34_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram34_rdata )
+);
+
+// *******************************4line*******************************
+my_bram_ip  u41_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram3_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram41_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram41_rdata )
+);
+my_bram_ip  u42_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram3_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram42_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram42_rdata )
+);
+my_bram_ip  u43_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram3_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram43_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram43_rdata )
+);
+my_bram_ip  u44_my_bram_ip(
+    .clk_a                             (    clk_in1      ),
+    .we_a                              (    bram3_wenb   ),
+    .addr_a                            (    bram_waddr   ),
+    .wdata_a                           (    bram_wdata   ),
+    .rdata_a                           (                 ),
+    .clk_b                             (    clk_in2      ), 
+    .we_b                              (    1'b0         ),
+    .addr_b                            (    bram44_raddr ),
+    .wdata_b                           (    8'b0         ),
+    .rdata_b                           (    bram44_rdata )
+);
+
+
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic.v

@@ -0,0 +1,90 @@
+module BiCubic(
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  yBlend,bi_a,xBlend,
+	output [16:0]  bi_y0,bi_y1,bi_y2,bi_y3,bi_x0,bi_x1,bi_x2,bi_x3
+);
+
+BiCubic_y3 BiCubic_y3_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.yBlend    (yBlend),
+	.bi_a      (bi_a),
+	.bi_y3     (bi_y3)
+);
+
+BiCubic_y2 BiCubic_y2_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.yBlend    (yBlend),
+	.bi_a      (bi_a),
+	.bi_y2     (bi_y2)
+);
+
+BiCubic_y1 BiCubic_y1_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffHalf (coeffHalf),
+	.yBlend    (yBlend),
+	.bi_a      (bi_a),
+	.bi_y1     (bi_y1)
+);
+
+BiCubic_y0 BiCubic_y0_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.yBlend    (yBlend),
+	.bi_a      (bi_a),
+	.bi_y0     (bi_y0)
+);
+
+///////////////////////////////////////////////
+
+BiCubic_x3 BiCubic_x3_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.xBlend    (xBlend),
+	.bi_a      (bi_a),
+	.bi_x3     (bi_x3)
+);
+
+BiCubic_x2 BiCubic_x2_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.xBlend    (xBlend),
+	.bi_a      (bi_a),
+	.bi_x2     (bi_x2)
+);
+
+BiCubic_x1 BiCubic_x1_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffHalf (coeffHalf),
+	.xBlend    (xBlend),
+	.bi_a      (bi_a),
+	.bi_x1     (bi_x1)
+);
+
+BiCubic_x0 BiCubic_x0_inst(
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.coeffOne  (coeffOne),
+	.coeffHalf (coeffHalf),
+	.xBlend    (xBlend),
+	.bi_a      (bi_a),
+	.bi_x0     (bi_x0)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_x0.v

@@ -0,0 +1,75 @@
+module BiCubic_x0 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  xBlend,bi_a,
+	output  [16:0]  bi_x0
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [17:0] mul_3_a,mul_add_2_d,mul_2_a;
+
+always@(posedge clk  )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=18'd0;
+		mul_2_a<=18'd0;
+		mul_add_2_d<=18'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<={1'd0,bi_a};
+		mul_3_a<=9'd5*bi_a;
+		mul_2_a<=9'd8*bi_a;
+		mul_add_2_d<=9'd4*bi_a;
+		
+		mul_x<=coeffOne + xBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_x0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_x0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_3_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+wire [27:0] BiCubic_1_2;
+mul_2 mul_2_x0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_x),
+	.b       (mul_2_a),
+	.result  (BiCubic_1_2)
+);
+
+
+mul_add_2 mul_add_2_x0_inst( 
+	.clk       (clk),
+	.rst_n     (rst_n),
+	.a         (BiCubic_1_4),
+	.b         (BiCubic_1_3),
+	.c         (BiCubic_1_2),
+	.d         (mul_add_2_d),
+	.coeffHalf (coeffHalf),
+	.result    (bi_x0)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_x1.v

@@ -0,0 +1,58 @@
+module BiCubic_x1 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  xBlend,bi_a,
+	output [16:0]  bi_x1
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [9:0] mul_3_a;
+always@(posedge clk  )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=10'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<=(2<<8)-bi_a;
+		mul_3_a<=(3<<8)-bi_a;
+		
+		mul_x<={1'd0,xBlend};
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_x1_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_x1_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       ({8'd0,mul_3_a}),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+mul_add_1 mul_add_1_x1_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (1'b1),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_x1)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_x2.v

@@ -0,0 +1,59 @@
+module BiCubic_x2 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  xBlend,bi_a,
+	output [16:0]   bi_x2
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [9:0] mul_3_a;
+always@(posedge clk  )
+begin
+	if(!rst_n) begin
+		mul_4_a<=9'd0;
+		mul_3_a<=10'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<=(2<<8)-bi_a;
+		mul_3_a<=(3<<8)-bi_a;
+		
+		mul_x<=coeffOne - xBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_x2_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_x2_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       ({8'd0,mul_3_a}),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+mul_add_1 mul_add_1_x2_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (1'b1),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_x2)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_x3.v

@@ -0,0 +1,75 @@
+module BiCubic_x3 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  xBlend,bi_a,
+	output [16:0]   bi_x3
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [17:0] mul_3_a,mul_add_2_d;
+reg [17:0] mul_2_a;
+always@(posedge clk  )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=18'd0;
+		mul_2_a<=18'd0;
+		mul_add_2_d<=18'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<={1'd0,bi_a};
+		mul_3_a<=9'd5*bi_a;
+		mul_2_a<=9'd8*bi_a;
+		mul_add_2_d<=9'd4*bi_a;
+		
+		mul_x<=(coeffOne << 1) - xBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_x3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_x3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_3_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+wire [27:0] BiCubic_1_2;
+mul_2 mul_2_x3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_x),
+	.b       (mul_2_a),
+	.result  (BiCubic_1_2)
+);
+
+
+mul_add_2 mul_add_2_x3_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (BiCubic_1_2),
+	.d          (mul_add_2_d),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_x3)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_y0.v

@@ -0,0 +1,74 @@
+module BiCubic_y0 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  yBlend,bi_a,
+	output [16:0]   bi_y0
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [17:0] mul_3_a,mul_add_2_d;
+reg [17:0] mul_2_a;
+always@(posedge clk  )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=18'd0;
+		mul_2_a<=18'd0;
+		mul_add_2_d<=18'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<={1'd0,bi_a};
+		mul_3_a<=9'd5*bi_a;
+		mul_2_a<=9'd8*bi_a;
+		mul_add_2_d<=9'd4*bi_a;
+		
+		mul_x<=coeffOne + yBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_y0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_y0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_3_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+wire [27:0] BiCubic_1_2;
+mul_2 mul_2_y0_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_x),
+	.b       (mul_2_a),
+	.result  (BiCubic_1_2)
+);
+
+mul_add_2 mul_add_2_y0_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (BiCubic_1_2),
+	.d          (mul_add_2_d),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_y0)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_y1.v

@@ -0,0 +1,58 @@
+module BiCubic_y1 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  yBlend,bi_a,
+	input  [8:0]  coeffHalf,
+	output [16:0]   bi_y1
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [9:0] mul_3_a;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=10'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<=(2<<8)-bi_a;
+		mul_3_a<=(3<<8)-bi_a;
+		
+		mul_x<={1'd0,yBlend};
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_y1_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_y1_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       ({8'd0,mul_3_a}),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+mul_add_1 mul_add_1_y1_inst(
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (1'b1),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_y1)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_y2.v

@@ -0,0 +1,59 @@
+module BiCubic_y2 (
+	input        clk,
+	input        rst_n,
+	input  [8:0] coeffOne,
+	input  [8:0] coeffHalf,
+	input  [8:0] yBlend,bi_a,
+	output [16:0]  bi_y2
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [9:0] mul_3_a;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=10'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<=(2<<8)-bi_a;
+		mul_3_a<=(3<<8)-bi_a;
+		
+		mul_x<=coeffOne - yBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_y2_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_y2_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       ({8'd0,mul_3_a}),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+mul_add_1 mul_add_1_y2_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (1'b1),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_y2)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/BiCubic_y3.v

@@ -0,0 +1,74 @@
+module BiCubic_y3 (
+	input         clk,
+	input         rst_n,
+	input  [8:0]  coeffOne,
+	input  [8:0]  coeffHalf,
+	input  [8:0]  yBlend,bi_a,
+	output [16:0]   bi_y3
+);
+
+reg [9:0] mul_x,mul_4_a;
+reg [17:0] mul_3_a,mul_add_2_d;
+reg [17:0] mul_2_a;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		mul_4_a<=10'd0;
+		mul_3_a<=18'd0;
+		mul_2_a<=18'd0;
+		mul_add_2_d<=18'd0;
+		
+		mul_x<=10'd0;
+	end
+	else begin
+		mul_4_a<={1'd0,bi_a};
+		mul_3_a<=9'd5*bi_a;
+		mul_2_a<=9'd8*bi_a;
+		mul_add_2_d<=9'd4*bi_a;
+		
+		mul_x<=(coeffOne << 1) - yBlend;
+	end
+end
+
+wire [39:0] BiCubic_1_4;
+mul_4 mul_4_y3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_4_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.d       (mul_x),
+	.result  (BiCubic_1_4)
+);
+
+wire [37:0] BiCubic_1_3;
+mul_3 mul_3_y3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_3_a),
+	.b       (mul_x),
+	.c       (mul_x),
+	.result  (BiCubic_1_3)
+);
+
+wire [27:0] BiCubic_1_2;
+mul_2 mul_2_y3_inst(
+	.clk     (clk),
+	.rst_n   (rst_n),
+	.a       (mul_x),
+	.b       (mul_2_a),
+	.result  (BiCubic_1_2)
+);
+
+mul_add_2 mul_add_2_y3_inst( 
+	.clk        (clk),
+	.rst_n      (rst_n),
+	.a          (BiCubic_1_4),
+	.b          (BiCubic_1_3),
+	.c          (BiCubic_1_2),
+	.d          (mul_add_2_d),
+	.coeffHalf  (coeffHalf),
+	.result     (bi_y3)
+);
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/mul_2.v

@@ -0,0 +1,33 @@
+module mul_2(
+	input          clk,
+	input          rst_n,
+	input  [9:0]   a,
+	input  [17:0]  b,
+	output reg [27:0]  result
+);
+
+
+//---------------------c1----------------------
+reg [27:0] result0;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result0<=28'd0;
+	end
+	else begin
+		result0<=a*b;
+	end
+end
+
+//----------------c2,c3,out------------------
+reg [27:0] result1,result2;
+//寄存延时
+always@(posedge clk)
+begin
+	result1<=result0;
+	result2<=result1;
+	result<=result2;
+end
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/mul_3.v

@@ -0,0 +1,61 @@
+module mul_3(
+	input clk,
+	input rst_n,
+	input [17:0] a,
+	input [9:0] b,c,
+	output reg [37:0] result
+);
+
+//------------c1----------------------
+reg [19:0] result0;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result0<=20'd0;
+	end
+	else begin
+		result0<=c*b;
+	end
+end
+
+reg [17:0] a_reg;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		a_reg<=18'd0;
+	end
+	else begin
+		a_reg<=a;
+	end
+end
+
+//------------c2----------------------
+reg [19:0] result1;
+reg [17:0] a_reg0;
+//寄存延时
+always@(posedge clk)
+begin
+	result1<=result0;
+	a_reg0<=a_reg;
+end
+
+//------------c3----------------------
+reg [37:0] result2;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result2<=38'd0;
+	end
+	else begin
+		result2<=result1*a_reg0;
+	end
+end
+//------------out----------------------
+//寄存延时
+always@(posedge clk)
+begin
+	result<=result2;
+end
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/mul_4.v

@@ -0,0 +1,104 @@
+module mul_4(
+    input clk,
+    input rst_n,
+    input [9:0] a,b,c,d,
+    output reg [39:0] result
+);
+
+//-------------------c1---------------------
+reg [19:0] result0;
+always@(posedge clk )
+begin
+    if(!rst_n) begin
+        result0<=20'd0;
+    end
+    else begin
+        result0<=a*b;
+    end
+end
+
+reg [19:0] result1;
+always@(posedge clk )
+begin
+    if(!rst_n) begin
+        result1<=20'd0;
+    end
+    else begin
+        result1<=c*d;
+    end
+end
+
+// reg [ 9:0] c_c1,d_c1;
+// always@(posedge clk)
+// begin
+//     c_c1<=c;
+//     d_c1<=d;
+// end
+
+//-------------------c2---------------------
+
+// reg [19:0] result1_c2;
+// always@(posedge clk )
+// begin
+//     if(!rst_n) begin
+//         result1_c2<=20'd0;
+//     end
+//     else begin
+//         result1_c2<=c_c1*d_c1;
+//     end
+// end
+
+// reg [19:0] result0_c2;
+// always@(posedge clk)
+// begin
+//     result0_c2<=result0;
+// end
+reg [19:0]result_low, result_mid1, result_mid2, result_high;
+always@(posedge clk )
+begin
+    if(!rst_n) begin
+        result_low<=20'd0;
+        result_mid1<=20'd0;
+        result_mid2<=20'd0;
+        result_high<=20'd0;
+    end
+    else begin
+        result_low <= result0[9:0] * result1[9:0];
+        result_mid1 <= result0[19:10] * result1[9:0];
+        result_mid2 <= result0[9:0] * result1[19:10];
+        result_high <= result0[19:10] * result1[19:10]; 
+    end
+end
+//------------------------c3----------------------
+
+// reg [39:0] result4_c3;
+// always@(posedge clk )
+// begin
+//     if(!rst_n) begin
+//         result4_c3<=40'd0;
+//     end
+//     else begin
+//         result4_c3<=result0_c2*result1_c2;
+//     end
+// end
+
+reg [39:0] result4;
+always@(posedge clk )
+begin
+    if(!rst_n) begin
+        result4<=40'd0;
+    end
+    else begin
+        result4<=(result_high << 20) + ((result_mid1 + result_mid2) << 10) + (result_low) ;
+    end
+end
+
+//---------------out--------------------
+always@(posedge clk)
+begin
+    result<=result4;
+end
+
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/mul_add_1.v

@@ -0,0 +1,57 @@
+module mul_add_1(
+	input        clk,
+	input        rst_n,
+	input [39:0] a,
+	input [37:0] b,
+	input        c,
+	input [8:0]  coeffHalf,
+	output reg [16:0]  result
+);
+
+
+//-----------------c1-----------------------
+reg [45:0] result0_c1;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result0_c1<=46'd0;
+	end
+	else begin
+		result0_c1<=a+(c<<32);
+	end
+end
+
+reg [45:0] b_c1;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		b_c1 <= 46'd0;
+	end
+	else begin
+		b_c1 <= b << 8;
+	end
+end
+
+//-----------------c2-----------------------
+reg [45:0] result1_c2;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result1_c2<=46'd0;
+	end
+	else begin
+		result1_c2<=result0_c1 - b_c1;
+	end
+end
+
+
+//---------------out--------------------
+//寄存延时
+always@(posedge clk)
+begin
+	result <= result1_c2[32:16];
+end
+
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/parameter/mul_add_2.v

@@ -0,0 +1,56 @@
+module mul_add_2(
+	input        clk,
+	input        rst_n,
+	input [39:0] a,
+	input [37:0] b,
+	input [27:0] c,
+	input [17:0] d,
+	input [8:0]  coeffHalf,
+	output  reg [16:0] result
+);
+//--------------------c1---------------------
+reg [45:0] result0_c1;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result0_c1<=46'd0;
+	end
+	else begin
+		result0_c1<=a+(c<<16);
+	end
+end
+
+reg [45:0] result1_c1;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result1_c1<=46'd0;
+	end
+	else begin
+		result1_c1<=(b<<8)+(d<<24);
+	end
+end
+
+//--------------------c2---------------------
+reg [45:0] result2_c2;
+always@(posedge clk )
+begin
+	if(!rst_n) begin
+		result2_c2<=46'd0;
+	end
+	else begin
+		result2_c2<=result0_c1 - result1_c1;
+	end
+end
+
+
+//---------------out--------------------
+always@(posedge clk )
+begin
+	result <= result2_c2[32:16];
+end
+
+
+
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/rtl/rgb_bicubic.v

@@ -0,0 +1,434 @@
+module rgb_bicubic
+#(
+    parameter C_SRC_IMG_WIDTH  = 12'd640,
+    parameter C_SRC_IMG_HEIGHT = 12'd480
+)
+(
+    input  wire                 clk_in1,
+    input  wire                 clk_in2,
+    input  wire                 rst_n,
+    input  wire        [1:0]     out_model,
+    
+    //  输入图像数据
+    input  wire                     per_img_vsync,
+    input  wire                     per_img_href,
+    input  wire     [ 7:0]          per_img_red,
+    input  wire     [ 7:0]          per_img_green,
+    input  wire     [ 7:0]          per_img_blue,
+    input  wire     [11:0]          c_dst_img_width,     
+    input  wire     [11:0]          c_dst_img_height,  
+    input  wire     [ 8:0]          bi_a,
+    
+    //  输出图像数据
+    output reg                  post_img_vsync,
+    output reg                  post_img_href,
+    output reg      [31:0]      post_img_data // 32位输出
+);
+
+// 内部信号
+wire [7:0] post_red, post_green, post_blue;
+wire red_vsync, red_href, green_vsync, green_href, blue_vsync, blue_href;
+
+wire [16:0]  x_fra_c1,y_fra_c1,inv_x_fra_c1,inv_y_fra_c1;
+wire [16:0]  bi_y0,bi_y1,bi_y2,bi_y3,bi_x0,bi_x1,bi_x2,bi_x3;
+
+reg [33:0]    frac_00_c2, frac_01_c2, frac_10_c2, frac_11_c2;
+reg [33:0] coeff00_c11, coeff01_c11, coeff02_c11, coeff03_c11;//(34,32)
+reg [33:0] coeff10_c11, coeff11_c11, coeff12_c11, coeff13_c11;
+reg [33:0] coeff20_c11, coeff21_c11, coeff22_c11, coeff23_c11;
+reg [33:0] coeff30_c11, coeff31_c11, coeff32_c11, coeff33_c11;
+
+reg         [16:0]              C_X_RATIO;
+reg         [16:0]              C_Y_RATIO;
+reg         [11:0]              C_DST_IMG_WIDTH;
+reg         [11:0]              C_DST_IMG_HEIGHT;
+
+// 实例化三个双线性插值模块
+bicubic_interpolation #(
+    .C_SRC_IMG_WIDTH(C_SRC_IMG_WIDTH),
+    .C_SRC_IMG_HEIGHT(C_SRC_IMG_HEIGHT)
+) red_interp (
+    .clk_in1(clk_in1),
+    .clk_in2(clk_in2),
+    .rst_n(rst_n),
+    .out_model(out_model),
+    .per_img_vsync(per_img_vsync),
+    .per_img_href(per_img_href),
+    .per_img_gray(per_img_red),
+    .post_img_vsync(red_vsync),
+    .post_img_href(red_href),
+    .post_img_gray(post_red),
+    .C_X_RATIO(C_X_RATIO),
+    .C_Y_RATIO(C_Y_RATIO),
+    .C_DST_IMG_HEIGHT(C_DST_IMG_HEIGHT),
+    .C_DST_IMG_WIDTH(C_DST_IMG_WIDTH),
+
+    .coeff00_c11(coeff00_c11),
+    .coeff01_c11(coeff01_c11),
+    .coeff02_c11(coeff02_c11),
+    .coeff03_c11(coeff03_c11),
+    .coeff10_c11(coeff10_c11),
+    .coeff11_c11(coeff11_c11),
+    .coeff12_c11(coeff12_c11),
+    .coeff13_c11(coeff13_c11),
+    .coeff20_c11(coeff20_c11),
+    .coeff21_c11(coeff21_c11),
+    .coeff22_c11(coeff22_c11),
+    .coeff23_c11(coeff23_c11),
+    .coeff30_c11(coeff30_c11),
+    .coeff31_c11(coeff31_c11),
+    .coeff32_c11(coeff32_c11),
+    .coeff33_c11(coeff33_c11),
+
+    .frac_00_c2(frac_00_c2),
+    .frac_01_c2(frac_01_c2),
+    .frac_10_c2(frac_10_c2),
+    .frac_11_c2(frac_11_c2),
+    .x_fra_c1(x_fra_c1),
+    .y_fra_c1(y_fra_c1),
+    .inv_x_fra_c1(inv_x_fra_c1),
+    .inv_y_fra_c1(inv_y_fra_c1)
+);
+
+bicubic_interpolation #(
+    .C_SRC_IMG_WIDTH(C_SRC_IMG_WIDTH),
+    .C_SRC_IMG_HEIGHT(C_SRC_IMG_HEIGHT)
+) green_interp (
+    .clk_in1(clk_in1),
+    .clk_in2(clk_in2),
+    .rst_n(rst_n),
+    .out_model(out_model),
+    .per_img_vsync(per_img_vsync),
+    .per_img_href(per_img_href),
+    .per_img_gray(per_img_green),
+    .post_img_vsync(green_vsync),
+    .post_img_href(green_href),
+    .post_img_gray(post_green),
+    .C_X_RATIO(C_X_RATIO),
+    .C_Y_RATIO(C_Y_RATIO),
+    .C_DST_IMG_HEIGHT(C_DST_IMG_HEIGHT),
+    .C_DST_IMG_WIDTH(C_DST_IMG_WIDTH),
+
+    .coeff00_c11(coeff00_c11),
+    .coeff01_c11(coeff01_c11),
+    .coeff02_c11(coeff02_c11),
+    .coeff03_c11(coeff03_c11),
+    .coeff10_c11(coeff10_c11),
+    .coeff11_c11(coeff11_c11),
+    .coeff12_c11(coeff12_c11),
+    .coeff13_c11(coeff13_c11),
+    .coeff20_c11(coeff20_c11),
+    .coeff21_c11(coeff21_c11),
+    .coeff22_c11(coeff22_c11),
+    .coeff23_c11(coeff23_c11),
+    .coeff30_c11(coeff30_c11),
+    .coeff31_c11(coeff31_c11),
+    .coeff32_c11(coeff32_c11),
+    .coeff33_c11(coeff33_c11),
+    
+    .frac_00_c2(frac_00_c2),
+    .frac_01_c2(frac_01_c2),
+    .frac_10_c2(frac_10_c2),
+    .frac_11_c2(frac_11_c2),
+    .x_fra_c1(),
+    .y_fra_c1(),
+    .inv_x_fra_c1(),
+    .inv_y_fra_c1()
+);
+
+bicubic_interpolation #(
+    .C_SRC_IMG_WIDTH(C_SRC_IMG_WIDTH),
+    .C_SRC_IMG_HEIGHT(C_SRC_IMG_HEIGHT)
+) blue_interp (
+    .clk_in1(clk_in1),
+    .clk_in2(clk_in2),
+    .rst_n(rst_n),
+    .out_model(out_model),
+    .per_img_vsync(per_img_vsync),
+    .per_img_href(per_img_href),
+    .per_img_gray(per_img_blue),
+    .post_img_vsync(blue_vsync),
+    .post_img_href(blue_href),
+    .post_img_gray(post_blue),
+    .C_X_RATIO(C_X_RATIO),
+    .C_Y_RATIO(C_Y_RATIO),
+    .C_DST_IMG_HEIGHT(C_DST_IMG_HEIGHT),
+    .C_DST_IMG_WIDTH(C_DST_IMG_WIDTH),
+
+    .coeff00_c11(coeff00_c11),
+    .coeff01_c11(coeff01_c11),
+    .coeff02_c11(coeff02_c11),
+    .coeff03_c11(coeff03_c11),
+    .coeff10_c11(coeff10_c11),
+    .coeff11_c11(coeff11_c11),
+    .coeff12_c11(coeff12_c11),
+    .coeff13_c11(coeff13_c11),
+    .coeff20_c11(coeff20_c11),
+    .coeff21_c11(coeff21_c11),
+    .coeff22_c11(coeff22_c11),
+    .coeff23_c11(coeff23_c11),
+    .coeff30_c11(coeff30_c11),
+    .coeff31_c11(coeff31_c11),
+    .coeff32_c11(coeff32_c11),
+    .coeff33_c11(coeff33_c11),
+
+    .frac_00_c2(frac_00_c2),
+    .frac_01_c2(frac_01_c2),
+    .frac_10_c2(frac_10_c2),
+    .frac_11_c2(frac_11_c2),
+    .x_fra_c1(),
+    .y_fra_c1(),
+    .inv_x_fra_c1(),
+    .inv_y_fra_c1()
+);
+
+// 合并输出
+always @(posedge clk_in2) begin
+    if (rst_n==0) begin
+        post_img_vsync <= 0;
+        post_img_href <= 0;
+        post_img_data <= 32'h0;
+    end else begin
+        // 确保行场信号同步
+        post_img_vsync <= red_vsync ;
+        post_img_href <= red_href ;
+
+        // 输出数据
+        post_img_data <= {8'h0, post_red, post_green, post_blue};
+    end
+end
+
+
+//----------------------caulacute  parameters in 7 pai--------begin in 2 get in 8-----------
+
+localparam COFFEEONE = { 1'b1, {8{1'b0}}};
+localparam COFFEEHALF ={2'b01, {7{1'b0}}}; //uesless
+
+BiCubic u_BiCubic (
+	.clk       (clk_in2),
+	.rst_n     (rst_n),
+	.coeffOne  (COFFEEONE),
+	.coeffHalf (COFFEEHALF),
+	.yBlend    (y_fra_c1[16:8]),
+	.bi_a      (bi_a),
+	.xBlend    (x_fra_c1[16:8]),
+	.bi_y0     (bi_y0),
+	.bi_y1     (bi_y1),
+	.bi_y2     (bi_y2),
+	.bi_y3     (bi_y3),
+	.bi_x0     (bi_x0),
+	.bi_x1     (bi_x1),
+	.bi_x2     (bi_x2),
+	.bi_x3     (bi_x3)
+);
+
+//------------------------------------------------------
+//c8
+reg [16:0] bi_y0_c10, bi_y1_c10, bi_y2_c10, bi_y3_c10, bi_x0_c10, bi_x1_c10, bi_x2_c10, bi_x3_c10;
+
+always  @(posedge clk_in2)
+begin
+    bi_y0_c10 <= bi_y0;
+    bi_y1_c10 <= bi_y1;
+    bi_y2_c10 <= bi_y2;
+    bi_y3_c10 <= bi_y3;
+    bi_x0_c10 <= bi_x0;
+    bi_x1_c10 <= bi_x1;
+    bi_x2_c10 <= bi_x2;
+    bi_x3_c10 <= bi_x3;
+end
+
+//------------------------------------------------------
+//c9
+
+always @(posedge clk_in2)
+begin
+    coeff00_c11 <=bi_y0_c10 *bi_x0_c10;
+    coeff01_c11 <=bi_y0_c10 *bi_x1_c10;
+    coeff02_c11 <=bi_y0_c10 *bi_x2_c10;
+    coeff03_c11 <=bi_y0_c10 *bi_x3_c10;
+
+    coeff10_c11 <=bi_y1_c10 *bi_x0_c10;
+    coeff11_c11 <=bi_y1_c10 *bi_x1_c10;
+    coeff12_c11 <=bi_y1_c10 *bi_x2_c10;
+    coeff13_c11 <=bi_y1_c10 *bi_x3_c10;
+
+    coeff20_c11 <=bi_y2_c10 *bi_x0_c10;
+    coeff21_c11 <=bi_y2_c10 *bi_x1_c10;
+    coeff22_c11 <=bi_y2_c10 *bi_x2_c10;
+    coeff23_c11 <=bi_y2_c10 *bi_x3_c10;
+
+    coeff30_c11 <=bi_y3_c10 *bi_x0_c10;
+    coeff31_c11 <=bi_y3_c10 *bi_x1_c10;
+    coeff32_c11 <=bi_y3_c10 *bi_x2_c10;
+    coeff33_c11 <=bi_y3_c10 *bi_x3_c10;
+end
+
+
+always @(posedge clk_in2) begin
+    frac_00_c2   <= inv_x_fra_c1 * inv_y_fra_c1;
+    frac_01_c2   <= x_fra_c1 * inv_y_fra_c1;
+    frac_10_c2   <= inv_x_fra_c1 * y_fra_c1;
+    frac_11_c2   <= x_fra_c1 * y_fra_c1;
+end
+
+
+//--------------------------------begin divider my own--------------------------------------
+
+reg                             post_img_vsync_dly;
+wire                            post_img_vsync_neg;
+always @(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)
+        post_img_vsync_dly <= 1'b0;
+    else
+        post_img_vsync_dly <= red_vsync;
+end
+assign post_img_vsync_neg = post_img_vsync_dly & ~red_vsync;
+
+
+
+
+// c1-----
+
+reg                             post_img_vsync_neg_c1;
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        post_img_vsync_neg_c1 =0;
+    end
+    else begin
+        post_img_vsync_neg_c1 <=post_img_vsync_neg;
+    end
+end
+
+//c1.5
+reg                             post_img_vsync_neg_c1_5;
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        post_img_vsync_neg_c1_5 =0;
+    end
+    else begin
+        post_img_vsync_neg_c1_5 <=post_img_vsync_neg_c1;
+    end
+end
+
+
+// c2-----
+
+reg                             post_img_vsync_neg_c2;
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        C_DST_IMG_WIDTH  <= 640;
+        C_DST_IMG_HEIGHT <= 480;
+    end
+    else begin
+        if(post_img_vsync_neg_c1_5 == 1) 
+        begin
+            C_DST_IMG_WIDTH  <= c_dst_img_width;
+            C_DST_IMG_HEIGHT <= c_dst_img_height;
+            post_img_vsync_neg_c2 <= 1;
+        end
+        else
+        begin
+            C_DST_IMG_WIDTH  <= C_DST_IMG_WIDTH;
+            C_DST_IMG_HEIGHT <= C_DST_IMG_HEIGHT;
+            post_img_vsync_neg_c2 <= 0;
+        end
+    end
+end
+
+
+//c3-----
+reg             [26:0]          multi_tmp1_c2;
+reg             [26:0]          multi_tmp2_c2;
+reg                             post_img_vsync_neg_c3;
+
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        multi_tmp1_c2  <= 0;
+        multi_tmp2_c2  <= 0;
+    end
+    else begin
+        if(post_img_vsync_neg_c2 ==1) begin
+            multi_tmp1_c2 <=(C_SRC_IMG_WIDTH <<16) ;// C_DST_IMG_WIDTH ;//  floor(C_SRC_IMG_WIDTH/C_DST_IMG_WIDTH*2^16)
+            multi_tmp2_c2 <=(C_SRC_IMG_HEIGHT <<16) ;// C_DST_IMG_HEIGHT ;//  floor(C_SRC_IMG_HEIGHT/C_DST_IMG_HEIGHT*2^16)
+            post_img_vsync_neg_c3 <=1;
+        end
+        else begin
+            multi_tmp1_c2 <=multi_tmp1_c2;
+            multi_tmp2_c2 <=multi_tmp2_c2;
+            post_img_vsync_neg_c3 <=0;
+        end
+    end
+end
+
+//c4-------
+
+reg    divide_clken;
+wire    rfd;
+wire    rfd1;
+wire   [26:0]   c_x_ratio_divide;
+wire   [26:0]   c_y_ratio_divide;
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        divide_clken  <= 0; 
+    end
+    else begin
+        if(post_img_vsync_neg_c3 ==1 && rfd ==0) begin
+            divide_clken <= 1;
+        end
+        else if(post_img_vsync_neg_c3 ==0 && rfd ==1) begin
+            divide_clken <= 0;
+        end else
+            divide_clken <= divide_clken;
+    end
+end
+
+divider_ip ux_divider_ip(  
+    .numer(multi_tmp1_c2), //  floor(C_SRC_IMG_WIDTH/C_DST_IMG_WIDTH*2^16)
+    .denom(C_DST_IMG_WIDTH),
+    .clken(divide_clken),
+    .clk(clk_in2),
+    .reset(1'b0),
+    .quotient(c_x_ratio_divide),
+    .remain(),
+    .rfd(rfd1)
+
+);
+divider_ip uy_divider_ip(
+    .numer(multi_tmp2_c2),
+    .denom(C_DST_IMG_HEIGHT),
+    .clken(divide_clken),
+    .clk(clk_in2),
+    .reset(1'b0),
+    .quotient(c_y_ratio_divide),
+    .remain(),
+    .rfd(rfd)
+
+);
+always@(posedge clk_in2)
+begin
+    if(rst_n == 1'b0)begin
+        C_X_RATIO  <= 65536; 
+        C_Y_RATIO  <= 65536; 
+    end
+    else begin
+        if (rfd ==1) begin
+            C_X_RATIO  <= c_x_ratio_divide; 
+            C_Y_RATIO  <= c_y_ratio_divide; 
+        end else begin
+            C_X_RATIO  <= C_X_RATIO; 
+            C_Y_RATIO  <= C_Y_RATIO; 
+        end
+    end
+end
+
+
+//---------------------------end divider my own---------------------------------------------------
+
+endmodule

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_add.v

@@ -0,0 +1,95 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix full-adder
+//
+// This is a simple full-adder
+// Both data inputs have programmable invert
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_ADD #
+(
+ parameter I0_POLARITY   = 1'b1,  // 0 invert
+ parameter I1_POLARITY   = 1'b1  // 0 invert
+)
+(
+ input 	I0,  // data input
+ input 	I1,  // data input
+ input 	CI,  // carry input
+ output	O,  // data output
+ output CO  // carry output
+);
+   // Create nets for optional data inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     I0_net;
+   wire     I1_net;
+   wire     CI_net;
+
+   // Default values for optional data signals
+   // Can be inverted by polarity parameter
+   assign (weak0, weak1) I0_net = I0_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) I1_net = I1_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) CI_net = 1'b0;
+
+   // Now assign the input
+   assign I0_net = I0;
+   assign I1_net = I1;
+   assign CI_net = CI;
+
+   // Internal signals
+   wire i0_int;
+   wire i1_int;
+
+   // Check datas polarity
+   assign i0_int = I0_POLARITY ? I0_net : ~I0_net;
+   assign i1_int = I1_POLARITY ? I1_net : ~I1_net;
+   
+   assign {CO, O} = i0_int + i1_int + CI_net;
+   
+endmodule // EFX_ADD
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_comb4.v

@@ -0,0 +1,170 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix 4-input combinational logic cell:
+//
+// This is a WYSIWYG cell representing the full functionality
+// of the Titanium logic cell.
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_COMB4 #
+(
+ parameter LUTMASK  = 16'h0000, // Content of Lookup table RAM
+ parameter MODE = "LOGIC"       // LOGIC or ARITH
+)
+(
+ input 	I0, // data input
+ input 	I1, // data input
+ input 	I2, // data input
+ input 	I3, // data input
+ input 	CI, // carry input
+ output O,  // data output
+ output CO, // carry out
+ output FCO, // flexibl carry out
+ output P   // Propagate output
+);
+
+   reg 		finish_error = 0;
+   initial begin
+	  if (MODE != "LOGIC" && MODE != "ARITH") begin
+		 $display("ERROR: Illegal MODE setting %s", MODE);
+		 finish_error = 1;
+	  end
+
+	  if (finish_error == 1)
+		#1 $finish();
+   end
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     I0_net;
+   wire     I1_net;
+   wire     I2_net;
+   wire     I3_net;
+   wire 	CI_net;
+   
+   // Default values for unused inputs
+   assign (weak0, weak1) I0_net = 1'b0;
+   assign (weak0, weak1) I1_net = 1'b0;
+   assign (weak0, weak1) I2_net = 1'b0;
+   assign (weak0, weak1) I3_net = 1'b0;
+   assign (weak0, weak1) CI_net = 1'b0;
+
+   // Now assign the input
+   assign I0_net = I0;
+   assign I1_net = I1;
+   assign I2_net = (MODE === "LOGIC") ? I2 : CI;
+   assign I3_net = (MODE === "LOGIC") ? I3 : 1'b0;
+   assign CI_net = CI;
+
+   // internal variables
+   wire [15:0] lutrom;
+   reg 	       lut = 1'b0;
+   reg 		   prop = 1'b0;
+   reg 		   gen = 1'b0;
+   
+   // assign LUT ROM
+   assign lutrom = LUTMASK;
+   
+   always @(I0_net or I1_net or I2_net or I3_net) begin
+      lut = get_lut_value(3, {I3_net, I2_net, I1_net, I0_net});
+      prop = get_lut_value(1, {1'b1, 1'b0, I1_net, I0_net});
+      gen = get_lut_value(1, {1'b1, 1'b1, I1_net, I0_net});
+   end
+
+   assign O = lut;
+   assign P = prop;
+   wire carry;
+   assign carry = (MODE === "ARITH") ? (prop ? CI_net : gen) : 1'bx;
+   
+   assign CO = ~carry;
+   assign FCO = carry;
+
+   function automatic [0:0] get_lut_value;
+	  input integer index;
+	  input [3:0] I;
+	  reg 		  hi_value, lo_value;
+	  
+	  // Check for an X value
+	  if (I[index] === 1'bx) begin
+		 // Need to test if both sub-trees return the same value
+		 case (index)
+		   3: begin
+			  hi_value = get_lut_value(2, {1'b1, I[2:0]});
+			  lo_value = get_lut_value(2, {1'b0, I[2:0]});
+		   end
+		   2: begin
+			  hi_value = get_lut_value(1, {I[3], 1'b1, I[1:0]});
+			  lo_value = get_lut_value(1, {I[3], 1'b0, I[1:0]});
+		   end
+		   1: begin
+			  hi_value = get_lut_value(0, {I[3:2], 1'b1, I[0]});
+			  lo_value = get_lut_value(0, {I[3:2], 1'b0, I[0]});
+		   end
+		   0: begin
+			  hi_value = lutrom[{I[3:1], 1'b1}];
+			  lo_value = lutrom[{I[3:1], 1'b0}];
+		   end
+		 endcase // case (index)
+
+		 //  If the same value return it, otherwise X
+		 get_lut_value = (hi_value === lo_value) ? hi_value : 1'bx;
+		 
+	  end
+	  else
+		// If last index return the value
+		if (index == 0)
+		  get_lut_value = lutrom[I];
+		else
+		  get_lut_value = get_lut_value(index-1, I);
+		  
+   endfunction //
+   
+   
+endmodule // EFX_LUT4
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_dpram10.v

@@ -0,0 +1,571 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix Dual-Port Block RAM (BRAM):
+//
+// This is a 10K true dual-port RAM
+//
+// The A & B ports can
+// Be in any of the following WIDTHs:
+//   8  --> 1024x8
+//   4  --> 2048x4
+//   2  --> 4096x2
+//   1  --> 8192x1
+//   10 --> 1024x10
+//   5  --> 2048x5
+// Reading and Writing can be in different WIDTHs
+//
+// Writing can be done in one of three WRITE MODEs
+//   READ_FIRST
+//   WRITE_FIRST
+//   NO_CHANGE
+//
+// Behavior is undefined when
+// reading / writing the same address
+// TODO: Need to add address collision checking!
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+module EFX_DPRAM10
+(
+   CLKA, WEA, CLKEA, RSTA, ADDRENA, WDATAA, ADDRA, RDATAA,
+   CLKB, WEB, CLKEB, RSTB, ADDRENB, WDATAB, ADDRB, RDATAB
+);
+   
+
+   parameter [0:0] CLKA_POLARITY    = 1'b1;
+   parameter [0:0] CLKEA_POLARITY   = 1'b1;
+   parameter [0:0] WEA_POLARITY     = 1'b1;
+   parameter [0:0] ADDRENA_POLARITY = 1'b1;
+   parameter [0:0] RSTA_POLARITY    = 1'b1;
+   parameter [0:0] CLKB_POLARITY    = 1'b1;
+   parameter [0:0] CLKEB_POLARITY   = 1'b1;
+   parameter [0:0] WEB_POLARITY     = 1'b1;
+   parameter [0:0] ADDRENB_POLARITY = 1'b1;
+   parameter [0:0] RSTB_POLARITY    = 1'b1;
+   // Need to add all the data & address input  polarity inversion parameters
+   parameter READ_WIDTH_A = 8;
+   parameter WRITE_WIDTH_A = 8;
+   parameter READ_WIDTH_B = 8;
+   parameter WRITE_WIDTH_B = 8;
+   parameter OUTPUT_REG_A = 1'b0;
+   parameter OUTPUT_REG_B = 1'b0;
+   parameter WRITE_MODE_A = "READ_FIRST";
+   parameter WRITE_MODE_B = "READ_FIRST";
+   parameter RESET_RAM_A = "ASYNC";
+   parameter RESET_OUTREG_A = "ASYNC";
+   parameter RESET_RAM_B = "ASYNC";
+   parameter RESET_OUTREG_B = "ASYNC";
+   parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_AWIDTH_A = 
+			    (READ_WIDTH_A == 1) ? 13 :
+			    (READ_WIDTH_A == 2) ? 12 :
+			    (READ_WIDTH_A == 4) ? 11 :
+			    (READ_WIDTH_A == 5) ? 11 :
+			    (READ_WIDTH_A == 8) ? 10 :
+			    (READ_WIDTH_A == 10) ? 10 :-1;
+   
+   localparam WRITE_AWIDTH_A = 
+			    (WRITE_WIDTH_A == 1) ? 13 :
+			    (WRITE_WIDTH_A == 2) ? 12 :
+			    (WRITE_WIDTH_A == 4) ? 11 :
+			    (WRITE_WIDTH_A == 5) ? 11 :
+			    (WRITE_WIDTH_A == 8) ? 10 :
+			    (WRITE_WIDTH_A == 10) ? 10 :-1;
+
+   // Greater of Read and Write widths defines input size
+   localparam AWIDTH_A = (READ_AWIDTH_A > WRITE_AWIDTH_A) ? READ_AWIDTH_A : WRITE_AWIDTH_A;
+   localparam DWIDTH_A = (READ_WIDTH_A > WRITE_WIDTH_A) ? WRITE_WIDTH_A : READ_WIDTH_A;
+   
+   localparam READ_AWIDTH_B = 
+			    (READ_WIDTH_B == 1) ? 13 :
+			    (READ_WIDTH_B == 2) ? 12 :
+			    (READ_WIDTH_B == 4) ? 11 :
+			    (READ_WIDTH_B == 5) ? 11 :
+			    (READ_WIDTH_B == 8) ? 10 :
+			    (READ_WIDTH_B == 10) ? 10 :-1;
+   
+   localparam WRITE_AWIDTH_B = 
+			    (WRITE_WIDTH_B == 1) ? 13 :
+			    (WRITE_WIDTH_B == 2) ? 12 :
+			    (WRITE_WIDTH_B == 4) ? 11 :
+			    (WRITE_WIDTH_B == 5) ? 11 :
+			    (WRITE_WIDTH_B == 8) ? 10 :
+			    (WRITE_WIDTH_B == 10) ? 10 :-1;
+   
+   // Greater of Read and Write widths defines input size
+   localparam AWIDTH_B = (READ_AWIDTH_B > WRITE_AWIDTH_B) ? READ_AWIDTH_B : WRITE_AWIDTH_B;
+   localparam DWIDTH_B = (READ_WIDTH_B > WRITE_WIDTH_B) ? WRITE_WIDTH_B : READ_WIDTH_B;
+
+   
+   localparam MEMORY_SIZE = 512*20;
+
+   localparam READ_FIRST = 0;
+   localparam WRITE_FIRST = 1;
+   localparam WRITE_NOT_READ = 2;
+   
+   input 			CLKA, WEA, CLKEA, RSTA, ADDRENA;
+   input 			CLKB, WEB, CLKEB, RSTB, ADDRENB;
+   input [WRITE_WIDTH_A-1:0] WDATAA;
+   input [AWIDTH_A-1:0] 	 ADDRA;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_early, RDATAA_late;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_out = 0;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_reg = 0;
+   output [READ_WIDTH_A-1:0] RDATAA;
+   input [WRITE_WIDTH_B-1:0] WDATAB;
+   input [AWIDTH_B-1:0] 	 ADDRB;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_early, RDATAB_late;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_out = 0;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_reg = 0;
+   output [READ_WIDTH_B-1:0] RDATAB;
+
+   // Local variables
+   reg mem [MEMORY_SIZE-1:0];
+   integer i;
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     WEA_net;
+   wire     CLKEA_net;
+   wire     RSTA_net;
+   wire     ADDRENA_net;
+   wire     WEB_net;
+   wire     CLKEB_net;
+   wire     RSTB_net;
+   wire     ADDRENB_net;
+
+   // Pull unused address lines low, to mirror EFX synthesis behavior.
+   wire [AWIDTH_A-1:0] ADDRA_net;
+   wire [AWIDTH_B-1:0] ADDRB_net;
+   reg [AWIDTH_A-1:0] ADDRA_r;
+   reg [AWIDTH_B-1:0] ADDRB_r;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) WEA_net     = ~WEA_POLARITY;
+   assign (weak0, weak1) CLKEA_net   = CLKEA_POLARITY;
+   assign (weak0, weak1) RSTA_net    = ~RSTA_POLARITY;
+   assign (weak0, weak1) ADDRENA_net = ADDRENA_POLARITY;
+   assign (weak0, weak1) WEB_net     = ~WEB_POLARITY;
+   assign (weak0, weak1) CLKEB_net   = CLKEB_POLARITY;
+   assign (weak0, weak1) RSTB_net    = ~RSTB_POLARITY;
+   assign (weak0, weak1) ADDRENB_net = ADDRENB_POLARITY;
+
+   assign (weak0, weak1) ADDRA_net = {AWIDTH_A{1'b0}};
+   assign (weak0, weak1) ADDRB_net = {AWIDTH_B{1'b0}};
+
+   // Now assign the input
+   assign WEA_net     = WEA;
+   assign CLKEA_net   = CLKEA;
+   assign RSTA_net    = RSTA;
+   assign ADDRENA_net = ADDRENA;
+   assign WEB_net     = WEB;
+   assign CLKEB_net   = CLKEB;
+   assign RSTB_net    = RSTB;
+   assign ADDRENB_net = ADDRENB;
+
+   assign ADDRA_net = ADDRA;
+   assign ADDRB_net = ADDRB;
+
+   function COMPATIBLE_WIDTH;
+	  input integer 	w1, w2;
+	  COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8))&&((w2==1)||(w2==2)||(w2==4)||(w2==8))) ||
+					(((w1==5)||(w1==10))&&((w2==5)||(w2==10))));
+   endfunction
+
+   
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal modes, address width will be -1
+	  if (READ_AWIDTH_A == -1) begin
+		 $display("ERROR:Illegal READ WIDTH Port A %d", READ_WIDTH_A);
+		 finish_error = 1;
+	  end
+	  if (WRITE_AWIDTH_A == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH Port A %d", WRITE_WIDTH_A);
+		 finish_error = 1;
+	  end
+	  if (READ_AWIDTH_B == -1) begin
+		 $display("ERROR:Illegal READ WIDTH Port B %d", READ_WIDTH_B);
+		 finish_error = 1;
+	  end
+	  if (WRITE_AWIDTH_B == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH Port B %d", WRITE_WIDTH_B);
+		 finish_error = 1;
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_A,WRITE_WIDTH_A)) begin
+		 $display("ERROR: Port A READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_A, WRITE_WIDTH_A);
+		 finish_error = 1;
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_B,WRITE_WIDTH_B)) begin
+		 $display("ERROR: Port B READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_B, WRITE_WIDTH_B);
+		 finish_error = 1;
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_A,READ_WIDTH_B)||~COMPATIBLE_WIDTH(WRITE_WIDTH_A,WRITE_WIDTH_B)) begin
+		 $display("ERROR: Port A READ/WRITE WIDTHS %d/%d cannot be used with Port B READ/WRITE WIDTHs %d/%d", 
+				  READ_WIDTH_A, WRITE_WIDTH_A, READ_WIDTH_B, WRITE_WIDTH_B);
+		 finish_error = 1;
+	  end
+	  // Check for illegal write modes
+	  if (WRITE_MODE_A != "READ_FIRST" && WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE") begin
+		 $display("ERROR:Illegal WRITE_MODE A %s", WRITE_MODE_A);
+		 finish_error = 1;
+	  end
+	  if (WRITE_MODE_B != "READ_FIRST" && WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE") begin
+		 $display("ERROR:Illegal WRITE_MODE B %s", WRITE_MODE_B);
+		 finish_error = 1;
+	  end
+	  if (RESET_RAM_A != "ASYNC" && RESET_RAM_A != "SYNC" && RESET_RAM_A != "NONE") begin
+		 $display("ERROR: Illegal RESET_RAM_A setting %s", RESET_RAM_A);
+		 finish_error = 1;
+	  end
+	  if (RESET_RAM_B != "ASYNC" && RESET_RAM_B != "SYNC" && RESET_RAM_B != "NONE") begin
+		 $display("ERROR: Illegal RESET_RAM_B setting %s", RESET_RAM_B);
+		 finish_error = 1;
+	  end
+	  if (RESET_OUTREG_A != "ASYNC" && RESET_OUTREG_A != "NONE") begin
+		 $display("ERROR: Illegal RESET_OUTREG_A setting %s", RESET_OUTREG_A);
+		 finish_error = 1;
+	  end
+	  if (RESET_OUTREG_B != "ASYNC" && RESET_OUTREG_B != "NONE") begin
+		 $display("ERROR: Illegal RESET_OUTREG_B setting %s", RESET_OUTREG_B);
+		 finish_error = 1;
+	  end
+
+	  if (finish_error == 1)
+		#1 $finish();
+
+	  // Initialize memory
+      for (i=0; i < 256; i=i+1) begin
+		 mem[256*0+i] = INIT_0[i];
+		 mem[256*1+i] = INIT_1[i];
+		 mem[256*2+i] = INIT_2[i];
+		 mem[256*3+i] = INIT_3[i];
+		 mem[256*4+i] = INIT_4[i];
+		 mem[256*5+i] = INIT_5[i];
+		 mem[256*6+i] = INIT_6[i];
+		 mem[256*7+i] = INIT_7[i];
+		 mem[256*8+i] = INIT_8[i];
+		 mem[256*9+i] = INIT_9[i];
+		 mem[256*10+i] = INIT_A[i];
+		 mem[256*11+i] = INIT_B[i];
+		 mem[256*12+i] = INIT_C[i];
+		 mem[256*13+i] = INIT_D[i];
+		 mem[256*14+i] = INIT_E[i];
+		 mem[256*15+i] = INIT_F[i];
+		 mem[256*16+i] = INIT_10[i];
+		 mem[256*17+i] = INIT_11[i];
+		 mem[256*18+i] = INIT_12[i];
+		 mem[256*19+i] = INIT_13[i];
+		 mem[256*20+i] = INIT_14[i];
+		 mem[256*21+i] = INIT_15[i];
+		 mem[256*22+i] = INIT_16[i];
+		 mem[256*23+i] = INIT_17[i];
+		 mem[256*24+i] = INIT_18[i];
+		 mem[256*25+i] = INIT_19[i];
+		 mem[256*26+i] = INIT_1A[i];
+		 mem[256*27+i] = INIT_1B[i];
+		 mem[256*28+i] = INIT_1C[i];
+		 mem[256*29+i] = INIT_1D[i];
+		 mem[256*30+i] = INIT_1E[i];
+		 mem[256*31+i] = INIT_1F[i];
+		 mem[256*32+i] = INIT_20[i];
+		 mem[256*33+i] = INIT_21[i];
+		 mem[256*34+i] = INIT_22[i];
+		 mem[256*35+i] = INIT_23[i];
+		 mem[256*36+i] = INIT_24[i];
+		 mem[256*37+i] = INIT_25[i];
+		 mem[256*38+i] = INIT_26[i];
+		 mem[256*39+i] = INIT_27[i];
+      end
+   end
+
+   // Wires for the polarity control.
+   // Only supporting clocks and enable for now
+   wire 			CLKA_i, WEA_i, CLKEA_i, RSTA_i, ADDRENA_i;
+   wire 			CLKB_i, WEB_i, CLKEB_i, RSTB_i, ADDRENB_i;
+
+   assign CLKA_i    = CLKA_POLARITY    ~^ CLKA;
+   assign CLKEA_i   = CLKEA_POLARITY   ~^ CLKEA_net;
+   assign RSTA_i    = RSTA_POLARITY    ~^ RSTA_net;
+   assign ADDRENA_i = ADDRENA_POLARITY ~^ ADDRENA_net;
+   assign WEA_i     = WEA_POLARITY     ~^ WEA_net;
+   assign CLKB_i    = CLKB_POLARITY    ~^ CLKB;
+   assign CLKEB_i   = CLKEB_POLARITY   ~^ CLKEB_net;
+   assign RSTB_i    = RSTB_POLARITY    ~^ RSTB_net;
+   assign ADDRENB_i = ADDRENB_POLARITY ~^ ADDRENB_net;
+   assign WEB_i     = WEB_POLARITY     ~^ WEB_net;
+
+   //////////////////////////////////////////////////////////////
+   // Port A
+   //////////////////////////////////////////////////////////////
+   // Wires for the configurable reset controls
+   wire 			ram_async_rsta, ram_sync_rsta, outreg_async_rsta;
+   assign ram_async_rsta    = (RESET_RAM_A == "ASYNC")    ? RSTA_i : 1'b0;
+   assign ram_sync_rsta     = (RESET_RAM_A == "SYNC")     ? RSTA_i : 1'b0;
+   assign outreg_async_rsta = (RESET_OUTREG_A == "ASYNC") ? RSTA_i : 1'b0;
+   
+   task read_rama;
+	  input [READ_AWIDTH_A-1:0] addr;
+	  output [READ_WIDTH_A-1:0] rdata;
+
+	  begin
+		
+		for (i=0; i < READ_WIDTH_A; i=i+1)
+		    rdata[i] = mem[addr*READ_WIDTH_A+i];
+	  end
+   endtask
+
+   task write_rama;
+	  input [WRITE_AWIDTH_A-1:0] addr;
+	  input [WRITE_WIDTH_A-1:0] wdata;
+	  input we;
+	  
+	  begin
+		if (we)
+		   for (i=0; i < WRITE_WIDTH_A; i=i+1)
+			 mem[addr*WRITE_WIDTH_A+i] = wdata[i];
+	  end
+   endtask
+
+   always@(posedge CLKA_i) begin
+     if (CLKEA_i) begin
+		// Only update the address latch if not stalled
+		ADDRA_r = ADDRENA_i ? ADDRA_net : ADDRA_r;
+
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		read_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - WRITE_AWIDTH_A], WDATAA, WEA_i);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		read_rama(ADDRA_r[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_late);
+		#0;
+	 end
+   end 
+
+   // Decide which data to output
+   always@(posedge CLKA_i or posedge ram_async_rsta) begin
+	  if (ram_async_rsta) begin
+		 RDATAA_out <= {READ_WIDTH_A{1'b0}};
+      end 
+	  else begin
+		 // Delay for the read/write/read to happen
+		 #0; #0; #0;
+		 if (CLKEA_i) begin
+			// Check for sync reset
+			if (ram_sync_rsta) begin 
+			   RDATAA_out <= {READ_WIDTH_A{1'b0}};
+	        end 
+			else begin
+			   // Based on the write mode decide which read data to use
+			   if (WRITE_MODE_A == "READ_FIRST") begin
+				  RDATAA_out <= RDATAA_early;
+			   end
+			   else if (WRITE_MODE_A == "WRITE_FIRST") begin
+				  if (WEA_i) RDATAA_out <= WDATAA;
+				  else RDATAA_out <= RDATAA_late;
+			   end
+			   else /* (WRITE_MODE_A == "NO_CHANGE") */ begin
+				  RDATAA_out <= WEA_i ? RDATAA_out : RDATAA_early;
+			   end
+			end
+		 end
+	  end
+   end
+
+   // Optional output register
+   generate if (OUTPUT_REG_A) 
+	 begin
+		always@(posedge CLKA_i or posedge outreg_async_rsta) begin
+		   if (outreg_async_rsta) RDATAA_reg <= {READ_WIDTH_A{1'b0}};
+		   else if (CLKEA_i) RDATAA_reg <= RDATAA_out;
+		end
+
+		assign RDATAA = RDATAA_reg;
+	 end
+   else
+	 begin
+		assign RDATAA = RDATAA_out;
+	 end
+   endgenerate
+
+   //////////////////////////////////////////////////////////////
+   // Port B
+   //////////////////////////////////////////////////////////////
+   // Wires for the configurable reset controls
+   wire 			ram_async_rstb, ram_sync_rstb, outreg_async_rstb;
+   assign ram_async_rstb    = (RESET_RAM_B == "ASYNC")    ? RSTB_i : 1'b0;
+   assign ram_sync_rstb     = (RESET_RAM_B == "SYNC")     ? RSTB_i : 1'b0;
+   assign outreg_async_rstb = (RESET_OUTREG_B == "ASYNC") ? RSTB_i : 1'b0;
+   
+   task read_ramb;
+	  input [READ_AWIDTH_B-1:0] addr;
+	  output [READ_WIDTH_B-1:0] rdata;
+
+	  begin
+		 for (i=0; i < READ_WIDTH_B; i=i+1)
+		   rdata[i] = mem[addr*READ_WIDTH_B+i];
+	  end
+   endtask
+
+   task write_ramb;
+	  input [WRITE_AWIDTH_B-1:0] addr;
+	  input [WRITE_WIDTH_B-1:0] wdata;
+	  input  we;
+
+	  begin
+		 if (we)
+		   for (i=0; i < WRITE_WIDTH_B; i=i+1)
+			 mem[addr*WRITE_WIDTH_B+i] = wdata[i];
+	  end
+   endtask
+
+   always@(posedge CLKB_i) begin
+     if (CLKEB_i) begin
+		// Only update the address latch if not stalled
+		ADDRB_r = ADDRENB_i ? ADDRB_net : ADDRB_r;
+
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		read_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - WRITE_AWIDTH_B], WDATAB, WEB_i);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		read_ramb(ADDRB_r[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_late);
+		#0;
+		
+	 end
+   end
+
+   // Choose the Read value to output
+   always@(posedge CLKB_i or posedge ram_async_rstb) begin
+	  if (ram_async_rstb) begin
+		 RDATAB_out <= {READ_WIDTH_B{1'b0}};
+      end
+	  else begin
+		 // Delay for the read/write/read to happen
+		 #0; #0; #0;
+		 if (CLKEB_i) begin
+			if (ram_sync_rstb) begin
+			   RDATAB_out <= {READ_WIDTH_B{1'b0}};
+	        end 
+			else begin
+			   // Based on the write mode decide which read data to use
+			   if (WRITE_MODE_B == "READ_FIRST") begin
+				  RDATAB_out <= RDATAB_early;
+			   end
+			   else if (WRITE_MODE_B == "WRITE_FIRST") begin
+				  if (WEB_i) RDATAB_out <= WDATAB;
+				  else RDATAB_out <= RDATAB_late;
+			   end
+			   else /* (WRITE_MODE_B == "NO_CHANGE") */ begin
+				  RDATAB_out <= WEB_i ? RDATAB_out : RDATAB_early;
+			   end
+			end
+		 end
+	  end
+   end
+   
+   // Optional output register
+   generate if (OUTPUT_REG_B) 
+	 begin
+		always@(posedge CLKB_i or posedge outreg_async_rstb) begin
+		   if (outreg_async_rstb) RDATAB_reg <= {READ_WIDTH_B{1'b0}};
+		   else if (CLKEB_i)RDATAB_reg <= RDATAB_out;
+		end
+
+		assign RDATAB = RDATAB_reg;
+	 end
+   else
+	 begin
+		assign RDATAB = RDATAB_out;
+	 end
+   endgenerate
+
+endmodule // EFX_DPRAM10
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_dpram_5k.v

@@ -0,0 +1,420 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix Dual-Port Block RAM (BRAM):
+//
+// This is a 5K true dual-port RAM
+//
+// The A & B ports can
+// Be in any of the following WIDTHs:
+//   8  --> 512x8
+//   4  --> 1024x4
+//   2  --> 2048x2
+//   1  --> 4096x1
+//   10 --> 512x10
+//   5  --> 1024x5
+// Reading and Writing can be in different WIDTHs
+//
+// Writing can be done in one of three WRITE MODEs
+//   READ_FIRST
+//   WRITE_FIRST
+//   NO_CHANGE
+//
+// Behavior is undefined when
+// reading / writing the same address
+// TODO: Need to add address collision checking!
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_DPRAM_5K
+(
+   CLKA, WEA, CLKEA, WDATAA, ADDRA, RDATAA,
+   CLKB, WEB, CLKEB, WDATAB, ADDRB, RDATAB
+);
+   
+
+   parameter CLKA_POLARITY  = 1'b1;
+   parameter CLKEA_POLARITY = 1'b1;
+   parameter WEA_POLARITY   = 1'b1;
+   parameter CLKB_POLARITY  = 1'b1;
+   parameter CLKEB_POLARITY = 1'b1;
+   parameter WEB_POLARITY   = 1'b1;
+   // Need to add all the data & address input  polarity inversion parameters
+   parameter READ_WIDTH_A = 8;
+   parameter WRITE_WIDTH_A = 8;
+   parameter READ_WIDTH_B = 8;
+   parameter WRITE_WIDTH_B = 8;
+   parameter OUTPUT_REG_A = 1'b0;
+   parameter OUTPUT_REG_B = 1'b0;
+   parameter WRITE_MODE_A = "READ_FIRST";
+   parameter WRITE_MODE_B = "READ_FIRST";
+   parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_AWIDTH_A = 
+			    (READ_WIDTH_A == 1) ? 12 :
+			    (READ_WIDTH_A == 2) ? 11 :
+			    (READ_WIDTH_A == 4) ? 10 :
+			    (READ_WIDTH_A == 5) ? 10 :
+			    (READ_WIDTH_A == 8) ? 9 :
+			    (READ_WIDTH_A == 10) ? 9 :-1;
+   
+   localparam WRITE_AWIDTH_A = 
+			    (WRITE_WIDTH_A == 1) ? 12 :
+			    (WRITE_WIDTH_A == 2) ? 11 :
+			    (WRITE_WIDTH_A == 4) ? 10 :
+			    (WRITE_WIDTH_A == 5) ? 10 :
+			    (WRITE_WIDTH_A == 8) ? 9 :
+			    (WRITE_WIDTH_A == 10) ? 9 :-1;
+
+   // Greater of Read and Write widths defines input size
+   localparam AWIDTH_A = (READ_AWIDTH_A > WRITE_AWIDTH_A) ? READ_AWIDTH_A : WRITE_AWIDTH_A;
+   localparam DWIDTH_A = (READ_WIDTH_A > WRITE_WIDTH_A) ? WRITE_WIDTH_A : READ_WIDTH_A;
+   
+   localparam READ_AWIDTH_B = 
+			    (READ_WIDTH_B == 1) ? 12 :
+			    (READ_WIDTH_B == 2) ? 11 :
+			    (READ_WIDTH_B == 4) ? 10 :
+			    (READ_WIDTH_B == 5) ? 10 :
+			    (READ_WIDTH_B == 8) ? 9 :
+			    (READ_WIDTH_B == 10) ? 9 :-1;
+   
+   localparam WRITE_AWIDTH_B = 
+			    (WRITE_WIDTH_B == 1) ? 12 :
+			    (WRITE_WIDTH_B == 2) ? 11 :
+			    (WRITE_WIDTH_B == 4) ? 10 :
+			    (WRITE_WIDTH_B == 5) ? 10 :
+			    (WRITE_WIDTH_B == 8) ? 9 :
+			    (WRITE_WIDTH_B == 10) ? 9 :-1;
+   
+   // Greater of Read and Write widths defines input size
+   localparam AWIDTH_B = (READ_AWIDTH_B > WRITE_AWIDTH_B) ? READ_AWIDTH_B : WRITE_AWIDTH_B;
+   localparam DWIDTH_B = (READ_WIDTH_B > WRITE_WIDTH_B) ? WRITE_WIDTH_B : READ_WIDTH_B;
+
+   
+   localparam MEMORY_SIZE = 256*20;
+
+   localparam READ_FIRST = 0;
+   localparam WRITE_FIRST = 1;
+   localparam WRITE_NOT_READ = 2;
+   
+   input 			CLKA, WEA, CLKEA;
+   input 			CLKB, WEB, CLKEB;
+   input [WRITE_WIDTH_A-1:0] WDATAA;
+   input [AWIDTH_A-1:0] 	 ADDRA;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_early, RDATAA_late;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_out = 0;
+   reg [READ_WIDTH_A-1:0] 	 RDATAA_reg = 0;
+   output [READ_WIDTH_A-1:0] RDATAA;
+   input [WRITE_WIDTH_B-1:0] WDATAB;
+   input [AWIDTH_B-1:0] 	 ADDRB;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_early, RDATAB_late;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_out = 0;
+   reg [READ_WIDTH_B-1:0] 	 RDATAB_reg = 0;
+   output [READ_WIDTH_B-1:0] RDATAB;
+
+   // Local variables
+   reg mem [MEMORY_SIZE-1:0];
+   integer i;
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     WEA_net;
+   wire     CLKEA_net;
+   wire     WEB_net;
+   wire     CLKEB_net;
+
+   // Pull unused address lines low, to mirror EFX synthesis behavior.
+   wire [AWIDTH_A-1:0] ADDRA_net;
+   wire [AWIDTH_B-1:0] ADDRB_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) WEA_net = WEA_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) CLKEA_net = CLKEA_POLARITY ? 1'b1 : 1'b0;
+   assign (weak0, weak1) WEB_net = WEB_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) CLKEB_net = CLKEB_POLARITY ? 1'b1 : 1'b0;
+
+   assign (weak0, weak1) ADDRA_net = {AWIDTH_A{1'b0}};
+   assign (weak0, weak1) ADDRB_net = {AWIDTH_B{1'b0}};
+
+   // Now assign the input
+   assign WEA_net = WEA;
+   assign CLKEA_net = CLKEA;
+   assign WEB_net = WEB;
+   assign CLKEB_net = CLKEB;
+
+   assign ADDRA_net = ADDRA;
+   assign ADDRB_net = ADDRB;
+
+   function COMPATIBLE_WIDTH;
+	  input integer 	w1, w2;
+	  COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8))&&((w2==1)||(w2==2)||(w2==4)||(w2==8))) ||
+					(((w1==5)||(w1==10))&&((w2==5)||(w2==10))));
+   endfunction
+
+   
+   initial begin
+	  // Check for illegal modes, address width will be -1
+	  if (READ_AWIDTH_A == -1) begin
+		 $display("ERROR:Illegal READ WIDTH Port A %d", READ_WIDTH_A);
+		 $finish();
+	  end
+	  if (WRITE_AWIDTH_A == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH Port A %d", WRITE_WIDTH_A);
+		 $finish();
+	  end
+	  if (READ_AWIDTH_B == -1) begin
+		 $display("ERROR:Illegal READ WIDTH Port B %d", READ_WIDTH_B);
+		 $finish();
+	  end
+	  if (WRITE_AWIDTH_B == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH Port B %d", WRITE_WIDTH_B);
+		 $finish();
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_A,WRITE_WIDTH_A)) begin
+		 $display("ERROR: Port A READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_A, WRITE_WIDTH_A);
+		 $finish();
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_B,WRITE_WIDTH_B)) begin
+		 $display("ERROR: Port B READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH_B, WRITE_WIDTH_B);
+		 $finish();
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH_A,READ_WIDTH_B)||~COMPATIBLE_WIDTH(WRITE_WIDTH_A,WRITE_WIDTH_B)) begin
+		 $display("ERROR: Port A READ/WRITE WIDTHS %d/%d cannot be used with Port B READ/WRITE WIDTHs %d/%d", 
+				  READ_WIDTH_A, WRITE_WIDTH_A, READ_WIDTH_B, WRITE_WIDTH_B);
+		 $finish();
+	  end
+	  // Check for illegal write modes
+	  if (WRITE_MODE_A != "READ_FIRST" && WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE") begin
+		 $display("ERROR:Illegal WRITE_MODE A %s", WRITE_MODE_A);
+		 $finish();
+	  end
+	  if (WRITE_MODE_B != "READ_FIRST" && WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE") begin
+		 $display("ERROR:Illegal WRITE_MODE B %s", WRITE_MODE_B);
+		 $finish();
+	  end
+	  // Initialize memory
+      for (i=0; i < 256; i=i+1) begin
+		 mem[256*0+i] = INIT_0[i];
+		 mem[256*1+i] = INIT_1[i];
+		 mem[256*2+i] = INIT_2[i];
+		 mem[256*3+i] = INIT_3[i];
+		 mem[256*4+i] = INIT_4[i];
+		 mem[256*5+i] = INIT_5[i];
+		 mem[256*6+i] = INIT_6[i];
+		 mem[256*7+i] = INIT_7[i];
+		 mem[256*8+i] = INIT_8[i];
+		 mem[256*9+i] = INIT_9[i];
+		 mem[256*10+i] = INIT_A[i];
+		 mem[256*11+i] = INIT_B[i];
+		 mem[256*12+i] = INIT_C[i];
+		 mem[256*13+i] = INIT_D[i];
+		 mem[256*14+i] = INIT_E[i];
+		 mem[256*15+i] = INIT_F[i];
+		 mem[256*16+i] = INIT_10[i];
+		 mem[256*17+i] = INIT_11[i];
+		 mem[256*18+i] = INIT_12[i];
+		 mem[256*19+i] = INIT_13[i];
+      end
+   end
+
+   // Wires for the polarity control.
+   // Only supporting clocks and enable for now
+   wire 			CLKA_i, WEA_i, CLKEA_i;
+   wire 			CLKB_i, WEB_i, CLKEB_i;
+
+   assign CLKA_i  = CLKA_POLARITY  ? CLKA : ~CLKA;
+   assign CLKEA_i = CLKEA_POLARITY ? CLKEA_net : ~CLKEA_net;
+   assign WEA_i   = WEA_POLARITY   ? WEA_net : ~WEA_net;
+   assign CLKB_i  = CLKB_POLARITY  ? CLKB : ~CLKB;
+   assign CLKEB_i = CLKEB_POLARITY ? CLKEB_net : ~CLKEB_net;
+   assign WEB_i   = WEB_POLARITY   ? WEB_net : ~WEB_net;
+
+   //////////////////////////////////////////////////////////////
+   // Port A
+   //////////////////////////////////////////////////////////////
+   task read_rama;
+	  input [READ_AWIDTH_A-1:0] addr;
+	  output [READ_WIDTH_A-1:0] rdata;
+
+	  
+	  begin
+		
+		for (i=0; i < READ_WIDTH_A; i=i+1)
+		    rdata[i] = mem[addr*READ_WIDTH_A+i];
+	  end
+   endtask
+
+   task write_rama;
+	  input [WRITE_AWIDTH_A-1:0] addr;
+	  input [WRITE_WIDTH_A-1:0] wdata;
+	  input we;
+	  
+	  begin
+		if (we)
+		   for (i=0; i < WRITE_WIDTH_A; i=i+1)
+			 mem[addr*WRITE_WIDTH_A+i] = wdata[i];
+	  end
+   endtask
+
+   always@(posedge CLKA_i)
+     if (CLKEA_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		read_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - WRITE_AWIDTH_A], WDATAA, WEA_i);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		read_rama(ADDRA_net[AWIDTH_A-1:AWIDTH_A - READ_AWIDTH_A], RDATAA_late);
+		   
+		// Based on the write mode decide which read data to use
+		if (WRITE_MODE_A == "READ_FIRST") begin
+		   RDATAA_out = RDATAA_early;
+		end
+		else if (WRITE_MODE_A == "WRITE_FIRST") begin
+		   RDATAA_out = RDATAA_late;
+		end
+		else /* (WRITE_MODE_A == "NO_CHANGE") */ begin
+		   RDATAA_out = WEA_i ? RDATAA_out : RDATAA_early;
+		end
+	 end
+   
+   // Optional output register
+   generate if (OUTPUT_REG_A) 
+	 begin
+		always@(posedge CLKA_i)
+			RDATAA_reg <= RDATAA_out;
+
+		assign RDATAA = RDATAA_reg;
+	 end
+   else
+	 begin
+		assign RDATAA = RDATAA_out;
+	 end
+   endgenerate
+
+   //////////////////////////////////////////////////////////////
+   // Port B
+   //////////////////////////////////////////////////////////////
+   task read_ramb;
+	  input [READ_AWIDTH_B-1:0] addr;
+	  output [READ_WIDTH_B-1:0] rdata;
+
+	  begin
+		 for (i=0; i < READ_WIDTH_B; i=i+1)
+		   rdata[i] = mem[addr*READ_WIDTH_B+i];
+	  end
+   endtask
+
+   task write_ramb;
+	  input [WRITE_AWIDTH_B-1:0] addr;
+	  input [WRITE_WIDTH_B-1:0] wdata;
+	  input  we;
+
+	  begin
+		 if (we)
+		   for (i=0; i < WRITE_WIDTH_B; i=i+1)
+			 mem[addr*WRITE_WIDTH_B+i] = wdata[i];
+	  end
+   endtask
+
+   always@(posedge CLKB_i)
+     if (CLKEB_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		read_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - WRITE_AWIDTH_B], WDATAB, WEB_i);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		read_ramb(ADDRB_net[AWIDTH_B-1:AWIDTH_B - READ_AWIDTH_B], RDATAB_late);
+		   
+		// Based on the write mode decide which read data to use
+		if (WRITE_MODE_B == "READ_FIRST") begin
+		   RDATAB_out = RDATAB_early;
+		end
+		else if (WRITE_MODE_B == "WRITE_FIRST") begin
+		   RDATAB_out = RDATAB_late;
+		end
+		else /* (WRITE_MODE_B == "NO_CHANGE") */ begin
+		   RDATAB_out = WEB_i ? RDATAB_out : RDATAB_early;
+		end
+	 end
+   
+   // Optional output register
+   generate if (OUTPUT_REG_B) 
+	 begin
+		always@(posedge CLKB_i)
+			RDATAB_reg <= RDATAB_out;
+
+		assign RDATAB = RDATAB_reg;
+	 end
+   else
+	 begin
+		assign RDATAB = RDATAB_out;
+	 end
+   endgenerate
+
+endmodule // EFX_DPRAM_5K
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_dsp12.v

@@ -0,0 +1,386 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix DSP12:
+//
+// This is a powerful DSP block that can perform multiplication
+// plus addition/subtraction/accumulation. The final output can 
+// be dynamically shifted 0-15 bits right.
+//
+// There are 6 optional pipe-line registers at key points. 
+//
+// The DSP can be signed or unsinged.
+// The DSP implements an 4x4 multiplier followed by an AddSub block
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_DSP12 (
+   A, B, C, CASCIN, OP, SHIFT_ENA, CLK, CE, RST, O, CASCOUT
+);
+   
+   parameter [0:0] A_REG     = 0;
+   parameter [0:0] B_REG     = 0;
+   parameter [0:0] C_REG     = 0;
+   parameter [0:0] P_REG     = 0;
+   parameter [0:0] OP_REG    = 0;
+   parameter [0:0] W_REG     = 0;
+   parameter [0:0] O_REG     = 0;
+   parameter [0:0] SHIFTER   = 0;
+   parameter [0:0] RST_SYNC  = 0;
+   parameter [0:0] SIGNED    = 1;
+   parameter P_EXT           = "ALIGN_RIGHT";
+   parameter C_EXT           = "ALIGN_RIGHT";
+   parameter M_SEL           = "P";
+   parameter N_SEL           = "C";
+   parameter W_SEL           = "X";
+   parameter CASCOUT_SEL     = "W";
+   parameter [0:0] CLK_POLARITY       = 1;
+   parameter [0:0] CE_POLARITY        = 1;
+   parameter [0:0] RST_POLARITY       = 1;
+   parameter [0:0] SHIFT_ENA_POLARITY = 1;
+   parameter [0:0] A_REG_USE_CE   = 1;
+   parameter [0:0] B_REG_USE_CE   = 1;
+   parameter [0:0] C_REG_USE_CE   = 1;
+   parameter [0:0] OP_REG_USE_CE  = 1;
+   parameter [0:0] P_REG_USE_CE   = 1;
+   parameter [0:0] W_REG_USE_CE   = 1;
+   parameter [0:0] O_REG_USE_CE   = 1;
+   parameter [0:0] A_REG_USE_RST  = 1;
+   parameter [0:0] B_REG_USE_RST  = 1;
+   parameter [0:0] C_REG_USE_RST  = 1;
+   parameter [0:0] OP_REG_USE_RST = 1;
+   parameter [0:0] P_REG_USE_RST  = 1;
+   parameter [0:0] W_REG_USE_RST  = 1;
+   parameter [0:0] O_REG_USE_RST  = 1;
+   
+   input [3:0]  A;
+   input [3:0]  B;
+   input [3:0]  C;
+   input [11:0]  CASCIN;
+   input [1:0] 	 OP;
+   input 		 SHIFT_ENA, CLK, CE, RST;
+   output [11:0] O;
+   output [11:0] CASCOUT;
+   
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal extension
+	  case(P_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal P_EXT %s", P_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(C_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal C_EXT %s", C_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  // Check for illegal mux selection
+	  case(M_SEL)
+		"P","C" : ;
+		default: begin
+		 $display("ERROR: Illegal M_SEL %s", M_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(N_SEL)
+		"CONST0", "CONST1", "C", "P", "CASCIN", "W","O" : ;
+		default: begin
+		 $display("ERROR: Illegal N_SEL %s", N_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(W_SEL)
+		"P","X" : ;
+		default: begin
+		 $display("ERROR: Illegal W_SEL %s", W_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(CASCOUT_SEL)
+		"C", "P","W", "ABC" : ;
+		default: begin
+		 $display("ERROR: Illegal CASCOUT_SEL %s", CASCOUT_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+
+	  if (finish_error == 1)
+		#1 $finish();
+   end
+
+   wire [3:0] 	 A_p, B_p, C_p;
+   wire [1:0] 	 OP_p;
+   wire [7:0] 	 P, P_p;
+   wire [11:0] 	 C_a, P_a, M, N, X, W, W_p, S, O_p;
+   wire [3:0] 	 shift;
+
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire 		 CE_net;
+   wire 		 RST_net;
+   wire 		 SHIFT_ENA_net;
+   
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY;
+   assign (weak0, weak1) RST_net = ~RST_POLARITY;
+   assign (weak0, weak1) SHIFT_ENA_net = ~SHIFT_ENA_POLARITY;
+
+   // Now assign the input
+   assign CE_net = CE;
+   assign RST_net = RST;
+   assign SHIFT_ENA_net = SHIFT_ENA;
+
+   // Wires for polarity control
+   wire 		 CLK_i, CE_i, RST_i, SHIFT_ENA_i;
+   
+   assign CLK_i       = CLK_POLARITY       ~^ CLK;
+   assign CE_i        = CE_POLARITY        ~^ CE_net;
+   assign RST_i       = RST_POLARITY       ~^ RST_net;
+   assign SHIFT_ENA_i = SHIFT_ENA_POLARITY ~^ SHIFT_ENA_net;
+
+   // Individual pipeline stages can ignore the CE & RST pins
+   wire 		 CE_a, CE_b, CE_c, CE_op, CE_p, CE_w, CE_o;
+   wire 		 RST_a, RST_b, RST_c, RST_op, RST_p, RST_w, RST_o;
+
+   assign CE_a   = CE_i | ~A_REG_USE_CE;
+   assign CE_b   = CE_i | ~B_REG_USE_CE;
+   assign CE_c   = CE_i | ~C_REG_USE_CE;
+   assign CE_op  = CE_i | ~OP_REG_USE_CE;
+   assign CE_p   = CE_i | ~P_REG_USE_CE;
+   assign CE_w   = CE_i | ~W_REG_USE_CE;
+   assign CE_o   = CE_i | ~O_REG_USE_CE;
+   assign RST_a  = RST_i & A_REG_USE_RST;
+   assign RST_b  = RST_i & B_REG_USE_RST;
+   assign RST_c  = RST_i & C_REG_USE_RST;
+   assign RST_op = RST_i & OP_REG_USE_RST;
+   assign RST_p  = RST_i & P_REG_USE_RST;
+   assign RST_w  = RST_i & W_REG_USE_RST;
+   assign RST_o  = RST_i & O_REG_USE_RST;
+
+   // Mult Operator
+   EFX_DSP12_pipe #(.W(4), .REG(A_REG), .SYNC(RST_SYNC)) A_pipe(.I(A), .CLK(CLK_i), .CE(CE_a), .RST(RST_a), .O(A_p));
+   EFX_DSP12_pipe #(.W(4), .REG(B_REG), .SYNC(RST_SYNC)) B_pipe(.I(B), .CLK(CLK_i), .CE(CE_b), .RST(RST_b), .O(B_p));
+   EFX_DSP12_mult #(.A_W(4), .B_W(4), .O_W(8), .SIGNED(SIGNED)) mult(.A(A_p), .B(B_p), .O(P));
+   EFX_DSP12_pipe #(.W(8), .REG(P_REG), .SYNC(RST_SYNC)) P_pipe(.I(P), .CLK(CLK_i), .CE(CE_p), .RST(RST_p), .O(P_p));
+
+   // Mult Extender
+   EFX_DSP12_extender #(.W_I(8),.W_O(12),.SIGNED(SIGNED),.EXT(P_EXT)) ext_P(.I(P_p),  .O(P_a));
+
+   // C input and extender
+   EFX_DSP12_pipe #(.W(4), .REG(C_REG), .SYNC(RST_SYNC)) C_pipe(.I(C), .CLK(CLK_i), .CE(CE_c), .RST(RST_c), .O(C_p));
+   EFX_DSP12_extender #(.W_I(4), .W_O(12),.SIGNED(SIGNED),.EXT(C_EXT)) ext_C(.I(C_p), .O(C_a));
+
+   // Choose Add/Sub Operator Inputs
+   assign M = (M_SEL == "P") ? P_a : 
+			  (M_SEL == "C") ? C_a : -1;
+   
+
+   assign N = (N_SEL == "CONST0") ? 12'd0 :
+			  (N_SEL == "CONST1") ? 12'd1 :
+			  (N_SEL == "C") ? C_a :
+			  (N_SEL == "P") ? P_a :
+			  (N_SEL == "CASCIN") ? CASCIN :
+			  (N_SEL == "W") ? W_p :
+			  (N_SEL == "O") ? O_p : -1;
+
+   // Add/Sub Operator
+   EFX_DSP12_pipe #(.W(2), .REG(OP_REG), .SYNC(RST_SYNC)) OP_pipe(.I(OP), .CLK(CLK_i), .CE(CE_op), .RST(RST_op), .O(OP_p));
+   EFX_DSP12_add_sub #(.W(12), .SIGNED(SIGNED)) add_sub(.A(M), .B(N), .OP(OP_p), .O(X), .OVFL());
+   EFX_DSP12_pipe #(.W(12), .REG(W_REG), .SYNC(RST_SYNC)) W_pipe(.I(X), .CLK(CLK_i), .CE(CE_w), .RST(RST_w), .O(W_p));
+
+   // Choose the shifter input W register or aligned multiplier
+   assign W = (W_SEL == "P") ? P_a : W_p;
+   EFX_DSP12_pipe #(.W(4), .REG(1)) shift_val(.I(C[3:0]), .CLK(CLK_i), .CE(SHIFT_ENA_i), .RST(RST_i), .O(shift));
+   EFX_DSP12_shifter #(.W(12), .SIGNED(SIGNED)) shifter(.I(W),  .S(shift), .O(S));
+
+   // Output pipeline
+   EFX_DSP12_pipe #(.W(12), .REG(O_REG|(W_REG && W_SEL=="P")), .SYNC(RST_SYNC)) O_pipe(.I(S), .CLK(CLK_i), .CE(CE_o), .RST(RST_o), .O(O_p));
+   assign O = O_p;
+
+   // Choose Cascade Output
+   assign CASCOUT = (CASCOUT_SEL == "C") ? C_a :
+					(CASCOUT_SEL == "P") ? P_a :
+					(CASCOUT_SEL == "W") ? W_p : 
+					(CASCOUT_SEL == "ABC") ? {A_p,B_p,C_p} : -1;
+endmodule
+
+module EFX_DSP12_pipe (I, CLK, CE, RST, O);
+   parameter W    = 48;
+   parameter REG  = 0;
+   parameter SYNC = 0;
+
+   input [W-1:0] I;
+   input 		 CLK, CE, RST;
+   output [W-1:0] O;
+
+   wire 		  s_RST, a_RST;
+   assign s_RST = SYNC ? RST : 0;
+   assign a_RST = SYNC ? 0 : RST;
+   
+   reg [W-1:0] O_r = 0;
+   
+   always @(posedge CLK or posedge a_RST) begin
+	  if (a_RST || s_RST) begin
+		 O_r <= 0;
+	  end
+	  else begin
+		if (CE) O_r <= I;
+	  end
+   end
+
+   assign O = REG ? O_r : I;
+   
+endmodule
+
+module EFX_DSP12_mult (A, B, O);
+   parameter A_W = 8;
+   parameter B_W = 8;
+   parameter O_W = 16;
+   parameter SIGNED = 1;
+
+   input [A_W-1:0] A;
+   input [B_W-1:0] B;
+   output [O_W-1:0] O;
+
+   reg [O_W-1:0] O_r;
+   
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(A) * $signed(B);
+	  else O_r = A * B;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP12_extender (I, O);
+   parameter W_I = 48;
+   parameter W_O = 48;
+   parameter SIGNED = 1;
+   parameter EXT = "ALIGN_RIGHT";
+
+   input [W_I-1:0] I;
+   output [W_O-1:0] O;
+
+   reg [W_O-1:0] O_r;
+	  
+   always @(*) begin
+	  if (EXT == "ALIGN_RIGHT")
+		if (SIGNED) O_r = $signed(I);
+	  	else O_r = {{W_O-W_I{1'b0}}, I};
+	  else O_r = {I, {W_O-W_I{1'b0}}};
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP12_shifter (I, S, O);
+   parameter W = 48;
+   parameter WS = 4;
+   parameter SIGNED = 1;
+
+   input [W-1:0] I;
+   input [WS-1:0] 	 S;
+   output [W-1:0] O;
+
+   reg [W-1:0] O_r;
+	  
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(I) >>> S;
+	  else O_r = I >>> S;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP12_add_sub (A, B, OP, O, OVFL);
+   parameter W = 12;
+   parameter SIGNED = 1;
+
+   input [W-1:0] A;
+   input [W-1:0] B;
+   input [1:0] 	 OP;
+   output [W-1:0] O;
+   output 		  OVFL;
+
+   localparam signed [W+1:0] MAX = (1<<(W-1))-1;
+   localparam signed [W+1:0] MIN = -(1<<(W-1));
+   reg signed [W+1:0] 	  O_r;
+   reg signed [W:0] 	  A_r, B_r;
+   
+   always @(*) begin
+	  // Add/sub is done in signed arith and converted back to unsigned
+	  if (SIGNED) begin
+		 A_r = $signed(A);
+		 B_r = $signed(B);
+	  end
+	  else begin
+		 A_r = $unsigned(A);
+		 B_r = $unsigned(B);
+	  end
+	  
+	  case(OP)
+		2'b00: O_r = A_r+B_r;
+		2'b01: O_r = A_r-B_r;
+		2'b10: O_r = -A_r+B_r;
+		2'b11: O_r = -A_r-B_r-1;
+	  endcase
+   end
+
+   assign O = O_r[W-1:0];
+   // Only overflow if data is lost. 
+   assign OVFL = (SIGNED || OP != 2'b00) ? ((O_r > MAX) || (O_r < MIN)) : O_r[W];
+      
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_dsp24.v

@@ -0,0 +1,386 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix DSP24:
+//
+// This is a powerful DSP block that can perform multiplication
+// plus addition/subtraction/accumulation. The final output can 
+// be dynamically shifted 0-15 bits right.
+//
+// There are 6 optional pipe-line registers at key points. 
+//
+// The DSP can be signed or unsinged.
+// The DSP implements an 8x8 multiplier followed by an AddSub block
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_DSP24 (
+   A, B, C, CASCIN, OP, SHIFT_ENA, CLK, CE, RST, O, CASCOUT
+);
+   
+   parameter [0:0] A_REG     = 0;
+   parameter [0:0] B_REG     = 0;
+   parameter [0:0] C_REG     = 0;
+   parameter [0:0] P_REG     = 0;
+   parameter [0:0] OP_REG    = 0;
+   parameter [0:0] W_REG     = 0;
+   parameter [0:0] O_REG     = 0;
+   parameter [0:0] SHIFTER   = 0;
+   parameter [0:0] RST_SYNC  = 0;
+   parameter [0:0] SIGNED    = 1;
+   parameter P_EXT           = "ALIGN_RIGHT";
+   parameter C_EXT           = "ALIGN_RIGHT";
+   parameter M_SEL           = "P";
+   parameter N_SEL           = "C";
+   parameter W_SEL           = "X";
+   parameter CASCOUT_SEL     = "W";
+   parameter [0:0] CLK_POLARITY       = 1;
+   parameter [0:0] CE_POLARITY        = 1;
+   parameter [0:0] RST_POLARITY       = 1;
+   parameter [0:0] SHIFT_ENA_POLARITY = 1;
+   parameter [0:0] A_REG_USE_CE   = 1;
+   parameter [0:0] B_REG_USE_CE   = 1;
+   parameter [0:0] C_REG_USE_CE   = 1;
+   parameter [0:0] OP_REG_USE_CE  = 1;
+   parameter [0:0] P_REG_USE_CE   = 1;
+   parameter [0:0] W_REG_USE_CE   = 1;
+   parameter [0:0] O_REG_USE_CE   = 1;
+   parameter [0:0] A_REG_USE_RST  = 1;
+   parameter [0:0] B_REG_USE_RST  = 1;
+   parameter [0:0] C_REG_USE_RST  = 1;
+   parameter [0:0] OP_REG_USE_RST = 1;
+   parameter [0:0] P_REG_USE_RST  = 1;
+   parameter [0:0] W_REG_USE_RST  = 1;
+   parameter [0:0] O_REG_USE_RST  = 1;
+   
+   input [7:0]  A;
+   input [7:0]  B;
+   input [7:0]  C;
+   input [23:0]  CASCIN;
+   input [1:0] 	 OP;
+   input 		 SHIFT_ENA, CLK, CE, RST;
+   output [23:0] O;
+   output [23:0] CASCOUT;
+   
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal extension
+	  case(P_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal P_EXT %s", P_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(C_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal C_EXT %s", C_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  // Check for illegal mux selection
+	  case(M_SEL)
+		"P","C" : ;
+		default: begin
+		 $display("ERROR: Illegal M_SEL %s", M_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(N_SEL)
+		"CONST0", "CONST1", "C", "P", "CASCIN", "W","O" : ;
+		default: begin
+		 $display("ERROR: Illegal N_SEL %s", N_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(W_SEL)
+		"P","X" : ;
+		default: begin
+		 $display("ERROR: Illegal W_SEL %s", W_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(CASCOUT_SEL)
+		"C", "P","W", "ABC" : ;
+		default: begin
+		 $display("ERROR: Illegal CASCOUT_SEL %s", CASCOUT_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+
+	  if (finish_error == 1)
+		#1 $finish();
+   end
+
+   wire [7:0] 	 A_p, B_p, C_p;
+   wire [1:0] 	 OP_p;
+   wire [15:0] 	 P, P_p;
+   wire [23:0] 	 C_a, P_a, M, N, X, W, W_p, S, O_p;
+   wire [3:0] 	 shift;
+
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire 		 CE_net;
+   wire 		 RST_net;
+   wire 		 SHIFT_ENA_net;
+   
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY;
+   assign (weak0, weak1) RST_net = ~RST_POLARITY;
+   assign (weak0, weak1) SHIFT_ENA_net = ~SHIFT_ENA_POLARITY;
+
+   // Now assign the input
+   assign CE_net = CE;
+   assign RST_net = RST;
+   assign SHIFT_ENA_net = SHIFT_ENA;
+
+   // Wires for polarity control
+   wire 		 CLK_i, CE_i, RST_i, SHIFT_ENA_i;
+   
+   assign CLK_i       = CLK_POLARITY       ~^ CLK;
+   assign CE_i        = CE_POLARITY        ~^ CE_net;
+   assign RST_i       = RST_POLARITY       ~^ RST_net;
+   assign SHIFT_ENA_i = SHIFT_ENA_POLARITY ~^ SHIFT_ENA_net;
+
+   // Individual pipeline stages can ignore the CE & RST pins
+   wire 		 CE_a, CE_b, CE_c, CE_op, CE_p, CE_w, CE_o;
+   wire 		 RST_a, RST_b, RST_c, RST_op, RST_p, RST_w, RST_o;
+
+   assign CE_a   = CE_i | ~A_REG_USE_CE;
+   assign CE_b   = CE_i | ~B_REG_USE_CE;
+   assign CE_c   = CE_i | ~C_REG_USE_CE;
+   assign CE_op  = CE_i | ~OP_REG_USE_CE;
+   assign CE_p   = CE_i | ~P_REG_USE_CE;
+   assign CE_w   = CE_i | ~W_REG_USE_CE;
+   assign CE_o   = CE_i | ~O_REG_USE_CE;
+   assign RST_a  = RST_i & A_REG_USE_RST;
+   assign RST_b  = RST_i & B_REG_USE_RST;
+   assign RST_c  = RST_i & C_REG_USE_RST;
+   assign RST_op = RST_i & OP_REG_USE_RST;
+   assign RST_p  = RST_i & P_REG_USE_RST;
+   assign RST_w  = RST_i & W_REG_USE_RST;
+   assign RST_o  = RST_i & O_REG_USE_RST;
+
+   // Mult Operator
+   EFX_DSP24_pipe #(.W(8), .REG(A_REG), .SYNC(RST_SYNC)) A_pipe(.I(A), .CLK(CLK_i), .CE(CE_a), .RST(RST_a), .O(A_p));
+   EFX_DSP24_pipe #(.W(8), .REG(B_REG), .SYNC(RST_SYNC)) B_pipe(.I(B), .CLK(CLK_i), .CE(CE_b), .RST(RST_b), .O(B_p));
+   EFX_DSP24_mult #(.A_W(8), .B_W(8), .O_W(16), .SIGNED(SIGNED)) mult(.A(A_p), .B(B_p), .O(P));
+   EFX_DSP24_pipe #(.W(16), .REG(P_REG), .SYNC(RST_SYNC)) P_pipe(.I(P), .CLK(CLK_i), .CE(CE_p), .RST(RST_p), .O(P_p));
+
+   // Mult Extender
+   EFX_DSP24_extender #(.W_I(16),.W_O(24),.SIGNED(SIGNED),.EXT(P_EXT)) ext_P(.I(P_p),  .O(P_a));
+
+   // C input and extender
+   EFX_DSP24_pipe #(.W(8), .REG(C_REG), .SYNC(RST_SYNC)) C_pipe(.I(C), .CLK(CLK_i), .CE(CE_c), .RST(RST_c), .O(C_p));
+   EFX_DSP24_extender #(.W_I(8), .W_O(24),.SIGNED(SIGNED),.EXT(C_EXT)) ext_C(.I(C_p), .O(C_a));
+
+   // Choose Add/Sub Operator Inputs
+   assign M = (M_SEL == "P") ? P_a : 
+			  (M_SEL == "C") ? C_a : -1;
+   
+
+   assign N = (N_SEL == "CONST0") ? 24'd0 :
+			  (N_SEL == "CONST1") ? 24'd1 :
+			  (N_SEL == "C") ? C_a :
+			  (N_SEL == "P") ? P_a :
+			  (N_SEL == "CASCIN") ? CASCIN :
+			  (N_SEL == "W") ? W_p :
+			  (N_SEL == "O") ? O_p : -1;
+
+   // Add/Sub Operator
+   EFX_DSP24_pipe #(.W(2), .REG(OP_REG), .SYNC(RST_SYNC)) OP_pipe(.I(OP), .CLK(CLK_i), .CE(CE_op), .RST(RST_op), .O(OP_p));
+   EFX_DSP24_add_sub #(.W(24), .SIGNED(SIGNED)) add_sub(.A(M), .B(N), .OP(OP_p), .O(X), .OVFL());
+   EFX_DSP24_pipe #(.W(24), .REG(W_REG), .SYNC(RST_SYNC)) W_pipe(.I(X), .CLK(CLK_i), .CE(CE_w), .RST(RST_w), .O(W_p));
+
+   // Choose the shifter input W register or aligned multiplier
+   assign W = (W_SEL == "P") ? P_a : W_p;
+   EFX_DSP24_pipe #(.W(4), .REG(1)) shift_val(.I(C[3:0]), .CLK(CLK_i), .CE(SHIFT_ENA_i), .RST(RST_i), .O(shift));
+   EFX_DSP24_shifter #(.W(24), .SIGNED(SIGNED)) shifter(.I(W),  .S(shift), .O(S));
+
+   // Output pipeline
+   EFX_DSP24_pipe #(.W(24), .REG(O_REG|(W_REG && W_SEL=="P")), .SYNC(RST_SYNC)) O_pipe(.I(S), .CLK(CLK_i), .CE(CE_o), .RST(RST_o), .O(O_p));
+   assign O = O_p;
+
+   // Choose Cascade Output
+   assign CASCOUT = (CASCOUT_SEL == "C") ? C_a :
+					(CASCOUT_SEL == "P") ? P_a :
+					(CASCOUT_SEL == "W") ? W_p : 
+					(CASCOUT_SEL == "ABC") ? {A_p,B_p,C_p} : -1;
+endmodule
+
+module EFX_DSP24_pipe (I, CLK, CE, RST, O);
+   parameter W    = 48;
+   parameter REG  = 0;
+   parameter SYNC = 0;
+
+   input [W-1:0] I;
+   input 		 CLK, CE, RST;
+   output [W-1:0] O;
+
+   wire 		  s_RST, a_RST;
+   assign s_RST = SYNC ? RST : 0;
+   assign a_RST = SYNC ? 0 : RST;
+   
+   reg [W-1:0] O_r = 0;
+
+   always @(posedge CLK or posedge a_RST) begin
+	  if (a_RST || s_RST) begin
+		 O_r <= 0;
+	  end
+	  else begin
+		if (CE) O_r <= I;
+	  end
+   end
+
+   assign O = REG ? O_r : I;
+   
+endmodule
+
+module EFX_DSP24_mult (A, B, O);
+   parameter A_W = 8;
+   parameter B_W = 8;
+   parameter O_W = 16;
+   parameter SIGNED = 1;
+
+   input [A_W-1:0] A;
+   input [B_W-1:0] B;
+   output [O_W-1:0] O;
+
+   reg [O_W-1:0] O_r;
+   
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(A) * $signed(B);
+	  else O_r = A * B;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP24_extender (I, O);
+   parameter W_I = 48;
+   parameter W_O = 48;
+   parameter SIGNED = 1;
+   parameter EXT = "ALIGN_RIGHT";
+
+   input [W_I-1:0] I;
+   output [W_O-1:0] O;
+
+   reg [W_O-1:0] O_r;
+	  
+   always @(*) begin
+	  if (EXT == "ALIGN_RIGHT")
+		if (SIGNED) O_r = $signed(I);
+	  	else O_r = {{W_O-W_I{1'b0}}, I};
+	  else O_r = {I, {W_O-W_I{1'b0}}};
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP24_shifter (I, S, O);
+   parameter W = 48;
+   parameter WS = 4;
+   parameter SIGNED = 1;
+
+   input [W-1:0] I;
+   input [WS-1:0] 	 S;
+   output [W-1:0] O;
+
+   reg [W-1:0] O_r;
+	  
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(I) >>> S;
+	  else O_r = I >>> S;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP24_add_sub (A, B, OP, O, OVFL);
+   parameter W = 24;
+   parameter SIGNED = 1;
+
+   input [W-1:0] A;
+   input [W-1:0] B;
+   input [1:0] 	 OP;
+   output [W-1:0] O;
+   output 		  OVFL;
+
+   localparam signed [W+1:0] MAX = (1<<(W-1))-1;
+   localparam signed [W+1:0] MIN = -(1<<(W-1));
+   reg signed [W+1:0] 	  O_r;
+   reg signed [W:0] 	  A_r, B_r;
+   
+   always @(*) begin
+	  // Add/sub is done in signed arith and converted back to unsigned
+	  if (SIGNED) begin
+		 A_r = $signed(A);
+		 B_r = $signed(B);
+	  end
+	  else begin
+		 A_r = $unsigned(A);
+		 B_r = $unsigned(B);
+	  end
+	  
+	  case(OP)
+		2'b00: O_r = A_r+B_r;
+		2'b01: O_r = A_r-B_r;
+		2'b10: O_r = -A_r+B_r;
+		2'b11: O_r = -A_r-B_r-1;
+	  endcase
+   end
+
+   assign O = O_r[W-1:0];
+   // Only overflow if data is lost. 
+   assign OVFL = (SIGNED || OP != 2'b00) ? ((O_r > MAX) || (O_r < MIN)) : O_r[W];
+      
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_dsp48.v

@@ -0,0 +1,1550 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix DSP48:
+//
+// This is a powerful DSP block that can perform multiplication
+// plus addition/subtraction/accumulation. The final output can 
+// be dynamically shifted 0-15 bits right.
+//
+// There are 6 optional pipe-line registers at key points. 
+//
+// The DSP can be signed or unsinged. 
+// The DSP can be in the following MODES:
+//   NORMAL   --> 19x18
+//   DUAL     --> 11x10 & 8x8
+//   QUAD     --> 7x6 & (3) 4x4
+//   BFLOAT    --> A,B,C BFLOAT16, CASCIN, CASCOUT, O FP32
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_DSP48 (
+   A, B, C, CASCIN, OP, SHIFT_ENA, CLK, CE, RST, O, CASCOUT, OVFL
+);
+   
+   parameter MODE            = "NORMAL";
+   parameter [0:0] A_REG     = 0;
+   parameter [0:0] B_REG     = 0;
+   parameter [0:0] C_REG     = 0;
+   parameter [0:0] P_REG     = 0;
+   parameter [0:0] OP_REG    = 0;
+   parameter [0:0] W_REG     = 0;
+   parameter [0:0] O_REG     = 0;
+   parameter [0:0] SHIFTER   = 0;
+   parameter [0:0] RST_SYNC  = 0;
+   parameter [0:0] SIGNED    = 1;
+   parameter P_EXT           = "ALIGN_RIGHT";
+   parameter C_EXT           = "ALIGN_RIGHT";
+   parameter M_SEL           = "P";
+   parameter N_SEL           = "C";
+   parameter W_SEL           = "X";
+   parameter CASCOUT_SEL     = "W";
+   parameter [0:0] CLK_POLARITY       = 1;
+   parameter [0:0] CE_POLARITY        = 1;
+   parameter [0:0] RST_POLARITY       = 1;
+   parameter [0:0] SHIFT_ENA_POLARITY = 1;
+   parameter ROUNDING        = "RNE";
+   parameter [0:0] A_REG_USE_CE   = 1;
+   parameter [0:0] B_REG_USE_CE   = 1;
+   parameter [0:0] C_REG_USE_CE   = 1;
+   parameter [0:0] OP_REG_USE_CE  = 1;
+   parameter [0:0] P_REG_USE_CE   = 1;
+   parameter [0:0] W_REG_USE_CE   = 1;
+   parameter [0:0] O_REG_USE_CE   = 1;
+   parameter [0:0] A_REG_USE_RST  = 1;
+   parameter [0:0] B_REG_USE_RST  = 1;
+   parameter [0:0] C_REG_USE_RST  = 1;
+   parameter [0:0] OP_REG_USE_RST = 1;
+   parameter [0:0] P_REG_USE_RST  = 1;
+   parameter [0:0] W_REG_USE_RST  = 1;
+   parameter [0:0] O_REG_USE_RST  = 1;
+   
+   input [18:0]  A;
+   input [17:0]  B;
+   input [17:0]  C;
+   input [47:0]  CASCIN;
+   input [1:0] 	 OP;
+   input 		 SHIFT_ENA, CLK, CE, RST;
+   output [47:0] O;
+   output [47:0] CASCOUT;
+   output 		 OVFL;
+   
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal modes
+	  case(MODE)
+		"NORMAL","DUAL","QUAD","BFLOAT" : ;
+		default: begin
+		 $display("ERROR: Illegal MODE %s", MODE);
+		 finish_error = 1;
+		end
+	  endcase
+	  // Check for illegal extension
+	  case(P_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal P_EXT %s", P_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(C_EXT)
+		"ALIGN_LEFT","ALIGN_RIGHT","TEST" : ;
+		default: begin
+		 $display("ERROR: Illegal C_EXT %s", C_EXT);
+		 finish_error = 1;
+		end
+	  endcase
+	  // Check for illegal mux selection
+	  case(M_SEL)
+		"P","C","ABC" : ;
+		default: begin
+		 $display("ERROR: Illegal M_SEL %s", M_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(N_SEL)
+		"CONST0", "CONST1", "C", "P", "CASCIN", "CASCIN_ASR18", "CASCIN_LSR18", "W","O" : ;
+		default: begin
+		 $display("ERROR: Illegal N_SEL %s", N_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(W_SEL)
+		"P","X" : ;
+		default: begin
+		 $display("ERROR: Illegal W_SEL %s", W_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(CASCOUT_SEL)
+		"C", "P","W", "ABC" : ;
+		default: begin
+		 $display("ERROR: Illegal CASCOUT_SEL %s", CASCOUT_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(ROUNDING)
+		"RTZ", "RDOWN","RUP", "RTI", "RTO", "RNE" : ;
+		default: begin
+		 $display("ERROR: Illegal ROUNDING %s", ROUNDING);
+		 finish_error = 1;
+		end
+	  endcase
+
+	  if (finish_error == 1)
+		#1 $finish();
+   end
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire 		 CE_net;
+   wire 		 RST_net;
+   wire 		 SHIFT_ENA_net;
+   
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY;
+   assign (weak0, weak1) RST_net = ~RST_POLARITY;
+   assign (weak0, weak1) SHIFT_ENA_net = ~SHIFT_ENA_POLARITY;
+
+   // Now assign the input
+   assign CE_net = CE;
+   assign RST_net = RST;
+   assign SHIFT_ENA_net = SHIFT_ENA;
+
+   // Wires for polarity control
+   wire 		 CLK_w, CE_w, RST_w, SHIFT_ENA_w;
+   
+   assign CLK_w       = CLK_POLARITY       ~^ CLK;
+   assign CE_w        = CE_POLARITY        ~^ CE_net;
+   assign RST_w       = RST_POLARITY       ~^ RST_net;
+   assign SHIFT_ENA_w = SHIFT_ENA_POLARITY ~^ SHIFT_ENA_net;
+
+   // Choose integer or floating point
+   generate
+	  if (MODE == "BFLOAT") begin
+		 EFX_DSP48_float bf_DSP48 (.A(A),.B(B),.C(C),.CASCIN(CASCIN),.OP(OP),.SHIFT_ENA(SHIFT_ENA_w),.CLK(CLK_w),.CE(CE_w),.RST(RST_w),.O(O),.CASCOUT(CASCOUT),.OVFL(OVFL));
+		 defparam bf_DSP48.MODE        = MODE;
+		 defparam bf_DSP48.A_REG       = A_REG;
+		 defparam bf_DSP48.B_REG       = B_REG;
+		 defparam bf_DSP48.C_REG       = C_REG;
+		 defparam bf_DSP48.P_REG       = P_REG;
+		 defparam bf_DSP48.OP_REG      = OP_REG;
+		 defparam bf_DSP48.W_REG       = W_REG;
+		 defparam bf_DSP48.O_REG       = O_REG;
+		 defparam bf_DSP48.RST_SYNC    = RST_SYNC;
+		 defparam bf_DSP48.SIGNED      = SIGNED;
+		 defparam bf_DSP48.P_EXT       = P_EXT;
+		 defparam bf_DSP48.C_EXT       = C_EXT;
+		 defparam bf_DSP48.M_SEL       = M_SEL;
+		 defparam bf_DSP48.N_SEL       = N_SEL;
+		 defparam bf_DSP48.W_SEL       = W_SEL;
+		 defparam bf_DSP48.CASCOUT_SEL = CASCOUT_SEL;
+		 defparam bf_DSP48.ROUNDING    = ROUNDING;
+		 defparam bf_DSP48.A_REG_USE_CE   = A_REG_USE_CE;
+		 defparam bf_DSP48.B_REG_USE_CE   = B_REG_USE_CE;
+		 defparam bf_DSP48.C_REG_USE_CE   = C_REG_USE_CE;
+		 defparam bf_DSP48.OP_REG_USE_CE  = OP_REG_USE_CE;
+		 defparam bf_DSP48.P_REG_USE_CE   = P_REG_USE_CE;
+		 defparam bf_DSP48.W_REG_USE_CE   = W_REG_USE_CE;
+		 defparam bf_DSP48.O_REG_USE_CE   = O_REG_USE_CE;
+		 defparam bf_DSP48.A_REG_USE_RST  = A_REG_USE_RST;
+		 defparam bf_DSP48.B_REG_USE_RST  = B_REG_USE_RST;
+		 defparam bf_DSP48.C_REG_USE_RST  = C_REG_USE_RST;
+		 defparam bf_DSP48.OP_REG_USE_RST = OP_REG_USE_RST;
+		 defparam bf_DSP48.P_REG_USE_RST  = P_REG_USE_RST;
+		 defparam bf_DSP48.W_REG_USE_RST  = W_REG_USE_RST;
+		 defparam bf_DSP48.O_REG_USE_RST  = O_REG_USE_RST;
+	  end
+	  else begin
+		 EFX_DSP48_int i_DSP48 (.A(A),.B(B),.C(C),.CASCIN(CASCIN),.OP(OP),.SHIFT_ENA(SHIFT_ENA_w),.CLK(CLK_w),.CE(CE_w),.RST(RST_w),.O(O),.CASCOUT(CASCOUT),.OVFL(OVFL));
+		 defparam i_DSP48.MODE        = MODE;
+		 defparam i_DSP48.A_REG       = A_REG;
+		 defparam i_DSP48.B_REG       = B_REG;
+		 defparam i_DSP48.C_REG       = C_REG;
+		 defparam i_DSP48.P_REG       = P_REG;
+		 defparam i_DSP48.OP_REG      = OP_REG;
+		 defparam i_DSP48.W_REG       = W_REG;
+		 defparam i_DSP48.O_REG       = O_REG;
+		 defparam i_DSP48.RST_SYNC    = RST_SYNC;
+		 defparam i_DSP48.SIGNED      = SIGNED;
+		 defparam i_DSP48.P_EXT       = P_EXT;
+		 defparam i_DSP48.C_EXT       = C_EXT;
+		 defparam i_DSP48.M_SEL       = M_SEL;
+		 defparam i_DSP48.N_SEL       = N_SEL;
+		 defparam i_DSP48.W_SEL       = W_SEL;
+		 defparam i_DSP48.CASCOUT_SEL = CASCOUT_SEL;
+		 defparam i_DSP48.ROUNDING    = ROUNDING;
+		 defparam i_DSP48.A_REG_USE_CE   = A_REG_USE_CE;
+		 defparam i_DSP48.B_REG_USE_CE   = B_REG_USE_CE;
+		 defparam i_DSP48.C_REG_USE_CE   = C_REG_USE_CE;
+		 defparam i_DSP48.OP_REG_USE_CE  = OP_REG_USE_CE;
+		 defparam i_DSP48.P_REG_USE_CE   = P_REG_USE_CE;
+		 defparam i_DSP48.W_REG_USE_CE   = W_REG_USE_CE;
+		 defparam i_DSP48.O_REG_USE_CE   = O_REG_USE_CE;
+		 defparam i_DSP48.A_REG_USE_RST  = A_REG_USE_RST;
+		 defparam i_DSP48.B_REG_USE_RST  = B_REG_USE_RST;
+		 defparam i_DSP48.C_REG_USE_RST  = C_REG_USE_RST;
+		 defparam i_DSP48.OP_REG_USE_RST = OP_REG_USE_RST;
+		 defparam i_DSP48.P_REG_USE_RST  = P_REG_USE_RST;
+		 defparam i_DSP48.W_REG_USE_RST  = W_REG_USE_RST;
+		 defparam i_DSP48.O_REG_USE_RST  = O_REG_USE_RST;
+	  end
+   endgenerate
+endmodule
+
+module EFX_DSP48_int (
+   A, B, C, CASCIN, OP, SHIFT_ENA, CLK, CE, RST, O, CASCOUT, OVFL
+);
+   
+   parameter MODE            = "NORMAL";
+   parameter [0:0] A_REG     = 0;
+   parameter [0:0] B_REG     = 0;
+   parameter [0:0] C_REG     = 0;
+   parameter [0:0] P_REG     = 0;
+   parameter [0:0] OP_REG    = 0;
+   parameter [0:0] W_REG     = 0;
+   parameter [0:0] O_REG     = 0;
+   parameter [0:0] RST_SYNC  = 0;
+   parameter [0:0] SIGNED    = 1;
+   parameter P_EXT           = "ALIGN_RIGHT";
+   parameter C_EXT           = "ALIGN_RIGHT";
+   parameter M_SEL           = "P";
+   parameter N_SEL           = "C";
+   parameter W_SEL           = "P";
+   parameter CASCOUT_SEL     = "W";
+   parameter ROUNDING        = "RNE";
+   parameter [0:0] A_REG_USE_CE   = 1;
+   parameter [0:0] B_REG_USE_CE   = 1;
+   parameter [0:0] C_REG_USE_CE   = 1;
+   parameter [0:0] OP_REG_USE_CE  = 1;
+   parameter [0:0] P_REG_USE_CE   = 1;
+   parameter [0:0] W_REG_USE_CE   = 1;
+   parameter [0:0] O_REG_USE_CE   = 1;
+   parameter [0:0] A_REG_USE_RST  = 1;
+   parameter [0:0] B_REG_USE_RST  = 1;
+   parameter [0:0] C_REG_USE_RST  = 1;
+   parameter [0:0] OP_REG_USE_RST = 1;
+   parameter [0:0] P_REG_USE_RST  = 1;
+   parameter [0:0] W_REG_USE_RST  = 1;
+   parameter [0:0] O_REG_USE_RST  = 1;
+   
+   input [18:0]  A;
+   input [17:0]  B;
+   input [17:0]  C;
+   input [47:0]  CASCIN;
+   input [1:0] 	 OP;
+   input 		 SHIFT_ENA, CLK, CE, RST;
+   output [47:0] O;
+   output [47:0] CASCOUT;
+   output 		 OVFL;
+
+   wire [18:0] 	 A_p;
+   wire [17:0] 	 B_p, C_p;
+   wire [1:0] 	 OP_p;
+   wire [36:0] 	 P, P_p;
+   wire [47:0] 	 C_a, P_a, M, N, X, W, W_p, S, O_p, CASCIN_asr18, CASCIN_lsr18;
+   wire [15:0] 	 shift;
+   wire 		 OVFL_w, OVFL_wp, OVFL_p;
+
+   // Individual pipeline stages can ignore the CE & RST pins
+   wire 		 CE_a, CE_b, CE_c, CE_op, CE_p, CE_w, CE_o;
+   wire 		 RST_a, RST_b, RST_c, RST_op, RST_p, RST_w, RST_o;
+
+   assign CE_a   = CE | ~A_REG_USE_CE;
+   assign CE_b   = CE | ~B_REG_USE_CE;
+   assign CE_c   = CE | ~C_REG_USE_CE;
+   assign CE_op  = CE | ~OP_REG_USE_CE;
+   assign CE_p   = CE | ~P_REG_USE_CE;
+   assign CE_w   = CE | ~W_REG_USE_CE;
+   assign CE_o   = CE | ~O_REG_USE_CE;
+   assign RST_a  = RST & A_REG_USE_RST;
+   assign RST_b  = RST & B_REG_USE_RST;
+   assign RST_c  = RST & C_REG_USE_RST;
+   assign RST_op = RST & OP_REG_USE_RST;
+   assign RST_p  = RST & P_REG_USE_RST;
+   assign RST_w  = RST & W_REG_USE_RST;
+   assign RST_o  = RST & O_REG_USE_RST;
+
+   // Mult Operator
+   EFX_DSP48_pipe #(.W(19), .REG(A_REG), .SYNC(RST_SYNC)) A_pipe(.I(A), .CLK(CLK), .CE(CE_a), .RST(RST_a), .O(A_p));
+   EFX_DSP48_pipe #(.W(18), .REG(B_REG), .SYNC(RST_SYNC)) B_pipe(.I(B), .CLK(CLK), .CE(CE_b), .RST(RST_b), .O(B_p));
+   EFX_DSP48_mult_mode #(.MODE(MODE),.SIGNED(SIGNED)) mult(.A(A_p), .B(B_p), .O(P));
+   EFX_DSP48_pipe #(.W(37), .REG(P_REG), .SYNC(RST_SYNC)) P_pipe(.I(P), .CLK(CLK), .CE(CE_p), .RST(RST_p), .O(P_p));
+
+   // Mult Extender
+   EFX_DSP48_p_extender #(.MODE(MODE), .SIGNED(SIGNED), .EXT(P_EXT)) ext_P(.I(P_p), .O(P_a));
+
+   // C input and extender
+   EFX_DSP48_pipe #(.W(18), .REG(C_REG), .SYNC(RST_SYNC)) C_pipe(.I(C), .CLK(CLK), .CE(CE_c), .RST(RST_c), .O(C_p));
+   EFX_DSP48_c_extender #(.MODE(MODE), .SIGNED(SIGNED), .EXT(C_EXT)) ext_C(.I(C_p), .O(C_a));
+
+   // CASCIN 18-bit shifter
+   EFX_DSP48_shifter #(.W(48), .WS(5), .SIGNED(1)) ASR18_shifter(.I(CASCIN), .S(5'd18), .O(CASCIN_asr18));
+   EFX_DSP48_shifter #(.W(48), .WS(5), .SIGNED(0)) LSR18_shifter(.I(CASCIN), .S(5'd18), .O(CASCIN_lsr18));
+   
+   // Choose Add/Sub Operator Inputs
+   assign M = (M_SEL == "P") ? P_a : 
+			  (M_SEL == "C") ? C_a :
+			  (M_SEL == "ABC") ? {A_p[15:0],B_p[15:0],C_p[15:0]} : -1;
+   
+
+   wire [47:0] 	 CONST1;
+   assign CONST1 = (MODE == "QUAD") ? 48'h001_001_001_001 : (MODE == "DUAL") ? 48'h000001_000001 : 48'd1;
+   
+   assign N = (N_SEL == "CONST0") ? 48'd0 :
+			  (N_SEL == "CONST1") ? CONST1 :
+			  (N_SEL == "C") ? C_a :
+			  (N_SEL == "P") ? P_a :
+			  (N_SEL == "CASCIN") ? CASCIN :
+			  (N_SEL == "CASCIN_ASR18") ? CASCIN_asr18 :
+			  (N_SEL == "CASCIN_LSR18") ? CASCIN_lsr18 :
+			  (N_SEL == "W") ? W_p :
+			  (N_SEL == "O") ? O_p : -1;
+
+   // Add/Sub Operator
+   EFX_DSP48_pipe #(.W(2), .REG(OP_REG), .SYNC(RST_SYNC)) OP_pipe(.I(OP), .CLK(CLK), .CE(CE_op), .RST(RST_op), .O(OP_p));
+   EFX_DSP48_add_sub_mode #(.MODE(MODE), .SIGNED(SIGNED)) add_sub(.A(M), .B(N), .OP(OP_p), .O(X), .OVFL(OVFL_w));
+   EFX_DSP48_pipe #(.W(48), .REG(W_REG), .SYNC(RST_SYNC)) W_pipe(.I(X), .CLK(CLK), .CE(CE_w), .RST(RST_w), .O(W_p));
+   EFX_DSP48_pipe #(.W(1), .REG(W_REG), .SYNC(RST_SYNC)) OVFL_W_pipe(.I(OVFL_w), .CLK(CLK), .CE(CE_w), .RST(RST_w), .O(OVFL_wp));
+
+   // Choose the shifter input W register or aligned multiplier
+   assign W = (W_SEL == "P") ? P_a : W_p;
+   EFX_DSP48_pipe #(.W(16), .REG(1)) shift_val(.I(C[15:0]), .CLK(CLK), .CE(SHIFT_ENA), .RST(RST), .O(shift));
+   EFX_DSP48_shifter_mode #(.MODE(MODE), .SIGNED(SIGNED)) shifter(.I(W), .S(shift), .O(S));
+
+   // Output pipeline
+   EFX_DSP48_pipe #(.W(48), .REG(O_REG|(W_REG && W_SEL=="P")), .SYNC(RST_SYNC)) O_pipe(.I(S), .CLK(CLK), .CE(CE_o), .RST(RST_o), .O(O_p));
+   EFX_DSP48_pipe #(.W(1), .REG(O_REG), .SYNC(RST_SYNC)) OVFL_O_pipe(.I(OVFL_wp), .CLK(CLK), .CE(CE_o), .RST(RST_o), .O(OVFL_p));
+   assign O = O_p;
+   assign OVFL = OVFL_p;
+
+   // Choose Cascade Output
+   assign CASCOUT = (CASCOUT_SEL == "C") ? C_a :
+					(CASCOUT_SEL == "P") ? P_a :
+					(CASCOUT_SEL == "W") ? W_p : 
+					(CASCOUT_SEL == "ABC") ? {A_p[15:0],B_p[15:0],C_p[15:0]} : -1;
+      
+endmodule
+
+module EFX_DSP48_float (
+   A, B, C, CASCIN, OP, SHIFT_ENA, CLK, CE, RST, O, CASCOUT, OVFL
+);
+   
+   parameter MODE            = "BFLOAT";
+   parameter [0:0] A_REG     = 0;             // Ignored
+   parameter [0:0] B_REG     = 0;             // Ignored
+   parameter [0:0] C_REG     = 0;             // Ignored
+   parameter [0:0] P_REG     = 0;             // Ignored
+   parameter [0:0] OP_REG    = 0;             // Ignored
+   parameter [0:0] W_REG     = 0;             // Ignored
+   parameter [0:0] O_REG     = 0;
+   parameter [0:0] RST_SYNC  = 0;
+   parameter [0:0] SIGNED    = 1;             // Ignored
+   parameter P_EXT           = "ALIGN_RIGHT"; // Ignored
+   parameter C_EXT           = "ALIGN_RIGHT"; // Ignored
+   parameter M_SEL           = "P";           // Ignored
+   parameter N_SEL           = "C";
+   parameter W_SEL           = "P";           // Ignored
+   parameter CASCOUT_SEL     = "W";
+   parameter ROUNDING        = "RNE";
+   parameter [0:0] A_REG_USE_CE   = 1;
+   parameter [0:0] B_REG_USE_CE   = 1;
+   parameter [0:0] C_REG_USE_CE   = 1;
+   parameter [0:0] OP_REG_USE_CE  = 1;
+   parameter [0:0] P_REG_USE_CE   = 1;           // Ignored
+   parameter [0:0] W_REG_USE_CE   = 1;           // Ignored
+   parameter [0:0] O_REG_USE_CE   = 1;
+   parameter [0:0] A_REG_USE_RST  = 1;
+   parameter [0:0] B_REG_USE_RST  = 1;
+   parameter [0:0] C_REG_USE_RST  = 1;
+   parameter [0:0] OP_REG_USE_RST = 1;
+   parameter [0:0] P_REG_USE_RST  = 1;           // Ignored
+   parameter [0:0] W_REG_USE_RST  = 1;           // Ignored
+   parameter [0:0] O_REG_USE_RST  = 1;
+   
+   input [18:0]  A;
+   input [17:0]  B;
+   input [17:0]  C;
+   input [47:0]  CASCIN;
+   input [1:0] 	 OP;
+   input 		 SHIFT_ENA, CLK, CE, RST;
+   output [47:0] O;
+   output [47:0] CASCOUT;
+   output 		 OVFL;
+
+   // Special checking for BFLOAT mode
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal modes
+	  case(MODE)
+		"BFLOAT" : ;
+		default: begin
+		 $display("ERROR: Illegal MODE %s", MODE);
+		 finish_error = 1;
+		end
+	  endcase
+	  // Check for illegal mux selection
+	  case(N_SEL)
+		"CONST0", "C", "CASCIN", "W" : ;
+		default: begin
+		 $display("ERROR: Illegal N_SEL %s", N_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(CASCOUT_SEL)
+		"W", "ABC" : ;
+		default: begin
+		 $display("ERROR: Illegal CASCOUT_SEL %s", CASCOUT_SEL);
+		 finish_error = 1;
+		end
+	  endcase
+	  case(ROUNDING)
+		"RTZ", "RDOWN","RUP", "RTI", "RTO", "RNE" : ;
+		default: begin
+		 $display("ERROR: Illegal ROUNDING %s", ROUNDING);
+		 finish_error = 1;
+		end
+	  endcase
+
+	  if (finish_error == 1)
+		#1 $finish();
+   end
+
+   localparam BF16_W = 16;
+   localparam FP32_W = 32;
+   
+   wire [15:0] 	 A_p, B_p, C_p;
+   wire [15:0] 	 A_bf, B_bf, C_bf;
+   wire [1:0] 	 OP_p;
+   wire [31:0] 	 C_fp;
+   wire [47:0] 	 CASCIN_fp, N, R, R_p1, R_p2, R_p3, W_fp, W, O_p;
+   wire [2:0] 	 ROUNDING_w;
+
+   // Individual pipeline stages can ignore the CE & RST pins
+   wire 		 CE_a, CE_b, CE_c, CE_op, CE_o;
+   wire 		 RST_a, RST_b, RST_c, RST_op, RST_o;
+
+   assign CE_a   = CE | ~A_REG_USE_CE;
+   assign CE_b   = CE | ~B_REG_USE_CE;
+   assign CE_c   = CE | ~C_REG_USE_CE;
+   assign CE_op  = CE | ~OP_REG_USE_CE;
+   assign CE_o   = CE | ~O_REG_USE_CE;
+   assign RST_a  = RST & A_REG_USE_RST;
+   assign RST_b  = RST & B_REG_USE_RST;
+   assign RST_c  = RST & C_REG_USE_RST;
+   assign RST_op = RST & OP_REG_USE_RST;
+   assign RST_o  = RST & O_REG_USE_RST;
+
+   // Input Registers, expects BF16 (only use the 16 LSB)
+   EFX_DSP48_pipe #(.W(16), .REG(1'b1), .SYNC(RST_SYNC)) A_pipe(.I(A[15:0]), .CLK(CLK), .CE(CE_a), .RST(RST_a), .O(A_p));
+   EFX_DSP48_pipe #(.W(16), .REG(1'b1), .SYNC(RST_SYNC)) B_pipe(.I(B[15:0]), .CLK(CLK), .CE(CE_b), .RST(RST_b), .O(B_p));
+   EFX_DSP48_pipe #(.W(16), .REG(1'b1), .SYNC(RST_SYNC)) C_pipe(.I(C[15:0]), .CLK(CLK), .CE(CE_c), .RST(RST_c), .O(C_p));
+   EFX_DSP48_pipe #(.W(2), .REG(1'b1), .SYNC(RST_SYNC)) OP_pipe(.I(OP), .CLK(CLK), .CE(CE_op), .RST(RST_op), .O(OP_p));
+
+   // Subnormal numbers not supported
+   fp_fmt_conv #(.R_W(48)) fp_fmt();
+   assign A_bf = fp_fmt.adjust_bf_input(A_p);
+   assign B_bf = fp_fmt.adjust_bf_input(B_p);
+   assign C_bf = fp_fmt.adjust_bf_input(C_p);
+
+   // Convert C input to FP32 (zero extend the mantissa)
+   assign C_fp = {C_bf, 16'd0};
+
+   // Convert CASCIN input to FP32 from internal representation (includes error flags)
+   assign CASCIN_fp = fp_fmt.conv_rec_to_fp(CASCIN);
+
+   // Choose the C input to the FMA block
+   assign N = (N_SEL == "CONST0") ? 48'd0 :
+			  (N_SEL == "CONST1") ? 48'd1 :              // Illegal (behaves the same as CONST0)
+			  (N_SEL == "C") ? C_fp :
+			  (N_SEL == "P") ? -1 :                      // Illegal
+			  (N_SEL == "CASCIN") ? CASCIN_fp :
+			  (N_SEL == "CASCIN_ASR18") ? -1 :            // Illegal
+			  (N_SEL == "CASCIN_LSR18") ? -1 :            // Illegal
+			  (N_SEL == "W") ? W_fp :
+			  (N_SEL == "O") ? -1 : -1;                  // Illegal
+
+   // Set the ROUNDING value
+   assign ROUNDING_w = (ROUNDING == "RTZ") ? 3'b001 :        // Round to Zero
+					   (ROUNDING == "RDOWN") ? 3'b010 :      // Round Down
+					   (ROUNDING == "RUP") ? 3'b011 :        // Round Up
+					   (ROUNDING == "RTI") ? 3'b100 :        // Round to Nearest, ties to infinity
+					   (ROUNDING == "RTO") ? 3'b110 :        // Round to Odd
+					   (ROUNDING == "RNE") ? 3'b000 : -1;    // Round to Nearest, ties to even
+   
+
+   // FMA (Fused-Multiply-Add) Block
+   f_mulAdd fma (A_bf, B_bf, N[31:0], OP_p, ROUNDING_w, R);
+
+   // FMA pipe-line
+   EFX_DSP48_pipe #(.W(48), .REG(1), .SYNC(RST_SYNC)) R1_pipe(.I(R), .CLK(CLK), .CE(1'b1), .RST(RST), .O(R_p1));
+   EFX_DSP48_pipe #(.W(48), .REG(1), .SYNC(RST_SYNC)) R2_pipe(.I(R_p1), .CLK(CLK), .CE(1'b1), .RST(RST), .O(R_p2));
+   EFX_DSP48_pipe #(.W(48), .REG(1), .SYNC(RST_SYNC)) R3_pipe(.I(R_p2), .CLK(CLK), .CE(1'b1), .RST(RST), .O(R_p3));
+   EFX_DSP48_pipe #(.W(48), .REG(1'b1), .SYNC(RST_SYNC)) W_pipe(.I(R_p3), .CLK(CLK), .CE(1'b1), .RST(RST), .O(W_fp));
+   EFX_DSP48_pipe #(.W(48), .REG(O_REG), .SYNC(RST_SYNC)) O_pipe(.I(W_fp), .CLK(CLK), .CE(CE_o), .RST(RST_o), .O(O_p));
+   assign O = O_p;
+
+   // Overflow is always 0
+   assign OVFL = 1'b0;
+
+   // Cascade expects internal format
+   assign W = fp_fmt.conv_fp_to_rec(W_fp);
+   
+   // Choose Cascade Output
+   assign CASCOUT = (CASCOUT_SEL == "C") ? -1  :          // Illegal
+					(CASCOUT_SEL == "P") ? -1  :          // Illegal
+					(CASCOUT_SEL == "W") ? W   : 
+					(CASCOUT_SEL == "ABC") ? {A_p[15:0],B_p[15:0],C_p[15:0]} : -1;
+
+endmodule
+
+module EFX_DSP48_pipe (I, CLK, CE, RST, O);
+   parameter W    = 48;
+   parameter REG  = 0;
+   parameter SYNC = 0;
+
+   input [W-1:0] I;
+   input 		 CLK, CE, RST;
+   output [W-1:0] O;
+
+   wire 		  s_RST, a_RST;
+   assign s_RST = SYNC ? RST : 0;
+   assign a_RST = SYNC ? 0 : RST;
+   
+   reg [W-1:0] O_r = 0;
+ 
+   always @(posedge CLK or posedge a_RST) begin
+	  if (a_RST || s_RST) begin
+		 O_r <= 0;
+	  end
+	  else begin
+		if (CE) O_r <= I;
+	  end
+   end
+
+   assign O = REG ? O_r : I;
+   
+endmodule
+
+module EFX_DSP48_mult_mode (A, B, O);
+   parameter MODE = "NORMAL";
+   parameter SIGNED = 1;
+
+   input [18:0] A;
+   input [17:0] B;
+   output [36:0] O;
+
+   generate
+	  case(MODE) 
+		"NORMAL": begin
+		   EFX_DSP48_mult #(.A_W(19), .B_W(18), .O_W(37), .SIGNED(SIGNED)) mult(.A(A), .B(B), .O(O));
+		end
+		"DUAL": begin
+		   EFX_DSP48_mult #(.A_W(11), .B_W(10), .O_W(21), .SIGNED(SIGNED)) multA(.A(A[18:8]), .B(B[17:8]), .O(O[36:16]));
+		   EFX_DSP48_mult #(.A_W(8), .B_W(8), .O_W(16), .SIGNED(SIGNED)) multB(.A(A[7:0]), .B(B[7:0]), .O(O[15:0]));
+		end
+		"QUAD": begin
+		   EFX_DSP48_mult #(.A_W(7), .B_W(6), .O_W(13), .SIGNED(SIGNED)) multA(.A(A[18:12]), .B(B[17:12]), .O(O[36:24]));
+		   EFX_DSP48_mult #(.A_W(4), .B_W(4), .O_W(8), .SIGNED(SIGNED)) multB(.A(A[11:8]), .B(B[11:8]), .O(O[23:16]));
+		   EFX_DSP48_mult #(.A_W(4), .B_W(4), .O_W(8), .SIGNED(SIGNED)) multC(.A(A[7:4]), .B(B[7:4]), .O(O[15:8]));
+		   EFX_DSP48_mult #(.A_W(4), .B_W(4), .O_W(8), .SIGNED(SIGNED)) multD(.A(A[3:0]), .B(B[3:0]), .O(O[7:0]));
+		end
+	  endcase
+   endgenerate
+   
+endmodule
+
+module EFX_DSP48_mult (A, B, O);
+   parameter A_W = 19;
+   parameter B_W = 18;
+   parameter O_W = 37;
+   parameter SIGNED = 1;
+
+   input [A_W-1:0] A;
+   input [B_W-1:0] B;
+   output [O_W-1:0] O;
+
+   reg [O_W-1:0] O_r;
+   
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(A) * $signed(B);
+	  else O_r = A * B;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP48_p_extender (I, O);
+   parameter MODE = "NORMAL";
+   parameter SIGNED = 1;
+   parameter EXT = "ALIGN_RIGHT";
+
+   input [36:0] I;
+   output [47:0] O;
+
+   generate
+	  case (MODE)
+		"NORMAL": begin
+		   EFX_DSP48_extender #(.W_I(37),.W_O(48),.SIGNED(SIGNED),.EXT(EXT)) extA(.I(I), .O(O));
+		end
+		"DUAL": begin
+		   EFX_DSP48_extender #(.W_I(21),.W_O(24),.SIGNED(SIGNED),.EXT(EXT)) extA(.I(I[36:16]), .O(O[47:24]));
+		   EFX_DSP48_extender #(.W_I(16),.W_O(24),.SIGNED(SIGNED),.EXT(EXT)) extB(.I(I[15:0]),  .O(O[23:0]));
+		end
+		"QUAD": begin
+		   if (EXT == "TEST") begin
+			  // Only extend the MSB
+			  EFX_DSP48_extender #(.W_I(13),.W_O(24),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extA(.I(I[36:24]), .O(O[47:24]));
+			  EFX_DSP48_extender #(.W_I(8), .W_O(8),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extB(.I(I[23:16]), .O(O[23:16]));
+			  EFX_DSP48_extender #(.W_I(8), .W_O(8),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extC(.I(I[15:8]),  .O(O[15:8]));
+			  EFX_DSP48_extender #(.W_I(8), .W_O(8),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extD(.I(I[7:0]),   .O(O[7:0]));
+		   end
+		   else begin
+			  // Truncate the 13-bit result
+			  assign O[47:36] = (EXT === "ALIGN_RIGHT") ? I[35:24] : I[36:25];
+			  EFX_DSP48_extender #(.W_I(8), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extB(.I(I[23:16]), .O(O[35:24]));
+			  EFX_DSP48_extender #(.W_I(8), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extC(.I(I[15:8]),  .O(O[23:12]));
+			  EFX_DSP48_extender #(.W_I(8), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extD(.I(I[7:0]),   .O(O[11:0]));
+		   end
+		end
+	  endcase
+   endgenerate
+   
+endmodule
+
+module EFX_DSP48_c_extender (I, O);
+   parameter MODE = "NORMAL";
+   parameter SIGNED = 1;
+   parameter EXT = "ALIGN_RIGHT";
+
+   input [17:0] I;
+   output [47:0] O;
+
+   generate
+	  case (MODE)
+		"NORMAL": begin
+		   EFX_DSP48_extender #(.W_I(18),.W_O(48),.SIGNED(SIGNED),.EXT(EXT)) extA(.I(I), .O(O));
+		end
+		"DUAL": begin
+		   EFX_DSP48_extender #(.W_I(10),.W_O(24),.SIGNED(SIGNED),.EXT(EXT)) extA(.I(I[17:8]), .O(O[47:24]));
+		   EFX_DSP48_extender #(.W_I(8), .W_O(24),.SIGNED(SIGNED),.EXT(EXT)) extB(.I(I[7:0]), .O(O[23:0]));
+		end
+		"QUAD": begin
+		   if (EXT == "TEST") begin
+			  EFX_DSP48_extender #(.W_I(6), .W_O(36),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extA(.I(I[17:12]), .O(O[47:12]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(4),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extB(.I(I[11:8]), .O(O[11:8]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(4),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extC(.I(I[7:4]), .O(O[7:4]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(4),.SIGNED(SIGNED),.EXT("ALIGN_RIGHT")) extD(.I(I[3:0]), .O(O[3:0]));
+		   end
+		   else begin
+			  EFX_DSP48_extender #(.W_I(6), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extA(.I(I[17:12]), .O(O[47:36]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extB(.I(I[11:8]), .O(O[35:24]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extC(.I(I[7:4]), .O(O[23:12]));
+			  EFX_DSP48_extender #(.W_I(4), .W_O(12),.SIGNED(SIGNED),.EXT(EXT)) extD(.I(I[3:0]), .O(O[11:0]));
+		   end
+		end
+	  endcase
+   endgenerate
+   
+endmodule
+
+module EFX_DSP48_extender (I, O);
+   parameter W_I = 48;
+   parameter W_O = 48;
+   parameter SIGNED = 1;
+   parameter EXT = "ALIGN_RIGHT";
+
+   input [W_I-1:0] I;
+   output [W_O-1:0] O;
+
+   reg [W_O-1:0] O_r;
+	  
+   always @(*) begin
+	  if (EXT == "ALIGN_RIGHT")
+		if (SIGNED) O_r = $signed(I);
+	  	else O_r = {{W_O-W_I{1'b0}}, I};
+	  else O_r = {I, {W_O-W_I{1'b0}}};
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP48_shifter_mode (I, S, O);
+   parameter MODE = "NORMAL";
+   parameter SIGNED = 1;
+
+   input [47:0] I;
+   input [15:0] S;
+   output [47:0] O;
+	  
+   generate
+	  case(MODE) 
+		"NORMAL": begin
+		   EFX_DSP48_shifter #(.W(48), .SIGNED(SIGNED)) shiftA(.I(I), .S(S[3:0]), .O(O));
+		end
+		"DUAL": begin
+		   EFX_DSP48_shifter #(.W(24), .SIGNED(SIGNED)) shiftA(.I(I[47:24]), .S(S[7:4]), .O(O[47:24]));
+		   EFX_DSP48_shifter #(.W(24), .SIGNED(SIGNED)) shiftB(.I(I[23:0]),  .S(S[3:0]), .O(O[23:0]));
+		end
+		"QUAD": begin
+		   EFX_DSP48_shifter #(.W(12), .SIGNED(SIGNED)) shiftA(.I(I[47:36]), .S(S[15:12]), .O(O[47:36]));
+		   EFX_DSP48_shifter #(.W(12), .SIGNED(SIGNED)) shiftB(.I(I[35:24]), .S(S[11:8]),  .O(O[35:24]));
+		   EFX_DSP48_shifter #(.W(12), .SIGNED(SIGNED)) shiftC(.I(I[23:12]), .S(S[7:4]),   .O(O[23:12]));
+		   EFX_DSP48_shifter #(.W(12), .SIGNED(SIGNED)) shiftD(.I(I[11:0]),  .S(S[3:0]),   .O(O[11:0]));
+		end
+	  endcase
+   endgenerate
+   
+endmodule
+
+module EFX_DSP48_shifter (I, S, O);
+   parameter W = 48;
+   parameter WS = 4;
+   parameter SIGNED = 1;
+
+   input [W-1:0] I;
+   input [WS-1:0] 	 S;
+   output [W-1:0] O;
+
+   reg [W-1:0] O_r;
+	  
+   always @(*) begin
+	  if (SIGNED) O_r = $signed(I) >>> S;
+	  else O_r = I >>> S;
+   end
+
+   assign O = O_r;
+   
+endmodule
+
+module EFX_DSP48_add_sub_mode (A, B, OP, O, OVFL);
+   parameter MODE = "NORMAL";
+   parameter SIGNED = 1;
+
+   input [47:0] A;
+   input [47:0] B;
+   input [1:0] 	OP;
+   output [47:0] O;
+   output 		 OVFL;
+
+   wire [3:0] 	 OVFL_w;
+   
+   generate
+	  case(MODE) 
+		"NORMAL": begin
+		   EFX_DSP48_add_sub #(.W(48), .SIGNED(SIGNED)) add_sub(.A(A), .B(B), .OP(OP), .O(O), .OVFL(OVFL));
+		end
+		"DUAL": begin
+		   EFX_DSP48_add_sub #(.W(24), .SIGNED(SIGNED)) add_subA(.A(A[47:24]), .B(B[47:24]), .OP(OP), .O(O[47:24]), .OVFL(OVFL_w[1]));
+		   EFX_DSP48_add_sub #(.W(24), .SIGNED(SIGNED)) add_subB(.A(A[23:0]), .B(B[23:0]), .OP(OP), .O(O[23:0]), .OVFL(OVFL_w[0]));
+		   assign OVFL = OVFL_w[1] | OVFL_w[0];
+		end
+		"QUAD": begin
+		   EFX_DSP48_add_sub #(.W(12), .SIGNED(SIGNED)) add_subA(.A(A[47:36]), .B(B[47:36]), .OP(OP), .O(O[47:36]), .OVFL(OVFL_w[3]));
+		   EFX_DSP48_add_sub #(.W(12), .SIGNED(SIGNED)) add_subB(.A(A[35:24]), .B(B[35:24]), .OP(OP), .O(O[35:24]), .OVFL(OVFL_w[2]));
+		   EFX_DSP48_add_sub #(.W(12), .SIGNED(SIGNED)) add_subC(.A(A[23:12]), .B(B[23:12]), .OP(OP), .O(O[23:12]), .OVFL(OVFL_w[1]));
+		   EFX_DSP48_add_sub #(.W(12), .SIGNED(SIGNED)) add_subD(.A(A[11:0]),  .B(B[11:0]),  .OP(OP), .O(O[11:0]),  .OVFL(OVFL_w[0]));
+		   assign OVFL = |OVFL_w;
+		end
+	  endcase
+   endgenerate
+   
+endmodule
+
+module EFX_DSP48_add_sub (A, B, OP, O, OVFL);
+   parameter W = 48;
+   parameter SIGNED = 1;
+
+   input [W-1:0] A;
+   input [W-1:0] B;
+   input [1:0] 	 OP;
+   output [W-1:0] O;
+   output 		  OVFL;
+
+   localparam signed [W+1:0] MAX = (1<<(W-1))-1;
+   localparam signed [W+1:0] MIN = -(1<<(W-1));
+   reg signed [W+1:0] 	  O_r;
+   reg signed [W:0] 	  A_r, B_r;
+   
+   always @(*) begin
+	  // Add/sub is done in signed arith and converted back to unsigned
+	  if (SIGNED) begin
+		 A_r = $signed(A);
+		 B_r = $signed(B);
+	  end
+	  else begin
+		 A_r = $unsigned(A);
+		 B_r = $unsigned(B);
+	  end
+	  
+	  case(OP)
+		2'b00: O_r = A_r+B_r;
+		2'b01: O_r = A_r-B_r;
+		2'b10: O_r = -A_r+B_r;
+		2'b11: O_r = -A_r-B_r-1;
+	  endcase
+   end
+
+   assign O = O_r[W-1:0];
+   // Only overflow if data is lost. 
+   assign OVFL = (SIGNED || OP != 2'b00) ? ((O_r > MAX) || (O_r < MIN)) : O_r[W];
+endmodule
+
+module f_mulAdd(a, b, c, op, rounding_mode, r);
+    parameter A_W = 16;
+    parameter B_W = 16;
+    parameter C_W = 32;
+    parameter R_W = 48;
+
+    localparam BF16_W = 16;
+    localparam BF16_N_EXP = 8;
+    localparam BF16_N_FRAC = 7;
+
+    localparam FP32_W = 32;
+    localparam FP32_N_EXP = 8;
+    localparam FP32_N_FRAC = 23;
+
+    localparam defaultNaN_fp32 = 32'h7FC00000;
+
+    localparam inexactBit = 0;
+    localparam underflowBit = 1;
+    localparam overflowBit = 2;
+    localparam infBit = 3;
+    localparam invalidBit = 4;
+
+    localparam [4:0] inexactBitMask = (1'b1 << inexactBit);
+    localparam [4:0] underflowBitMask = (1'b1 << underflowBit);
+    localparam [4:0] overflowBitMask = (1'b1 << overflowBit);
+    localparam [4:0] infBitMaskMask = (1'b1 << infBit);
+    localparam [4:0] invalidBitMask = (1'b1 << invalidBit);
+
+    input [A_W-1:0] a;
+    input [B_W-1:0] b;
+    input [C_W-1:0] c;
+    input [1:0] op;
+    input [2:0] rounding_mode;
+    output [R_W-1:0] r;
+
+    task automatic isSpecialValue_bf16;
+        input [BF16_N_EXP-1:0] exp;
+        input [BF16_N_FRAC-1:0] frac;
+        output isNaN, isInf, isZero;
+
+        begin
+            // according to Wiki page
+            isNaN = (&exp) && (|frac);
+            isInf = (&exp) && ~(|frac);
+            isZero = ~(|exp) && ~(|frac);
+        end
+    endtask
+
+    task automatic decode_bf16_rep;
+        input [BF16_W-1:0] f;
+        output isNaN, isInf, isZero;
+        output f_sign;
+        output [BF16_N_EXP-1:0] f_exp;
+        output [BF16_N_FRAC-1:0] f_frac;
+
+        begin
+            f_sign = f[BF16_W-1];
+            f_exp = f[BF16_N_EXP+BF16_N_FRAC-1:BF16_N_FRAC];
+            f_frac = (f_exp == 'd0) ? {BF16_N_FRAC{1'b0}} : f[BF16_N_FRAC-1:0];
+
+            isSpecialValue_bf16(f_exp, f_frac, isNaN, isInf, isZero);
+        end
+    endtask
+
+    task automatic isSpecialValue_fp32;
+        input [FP32_N_EXP-1:0] exp;
+        input [FP32_N_FRAC-1:0] frac;
+        output isNaN, isInf, isZero;
+
+        begin
+            // according to Wiki page
+            isNaN = (&exp) && (|frac);
+            isInf = (&exp) && ~(|frac);
+            isZero = ~(|exp) && ~(|frac);
+        end
+    endtask
+
+    task automatic decode_fp32_rep;
+        input [FP32_W-1:0] f;
+        output isNaN, isInf, isZero;
+        output f_sign;
+        output [FP32_N_EXP-1:0] f_exp;
+        output [FP32_N_FRAC-1:0] f_frac;
+
+        begin
+            f_sign = f[FP32_W-1];
+            f_exp = f[FP32_N_EXP+FP32_N_FRAC-1:FP32_N_FRAC];
+            f_frac = (f_exp == 'd0) ? {FP32_N_FRAC{1'b0}} : f[FP32_N_FRAC-1:0];
+
+            isSpecialValue_fp32(f_exp, f_frac, isNaN, isInf, isZero);
+        end
+    endtask
+
+    function automatic isSignalNaN_fp32;
+        input [FP32_W-1:0] f;
+
+        begin
+            isSignalNaN_fp32 = (((f & 32'h7FC00000) == 32'h7F800000) && (f & 32'h003FFFFF));
+        end
+    endfunction
+
+    function automatic isNaN_fp32;
+        input [FP32_W-1:0] f;
+        begin
+            isNaN_fp32 =  (((~(f) & 32'h7F800000) == 0) && (f & 32'h007FFFFF));
+        end
+    endfunction
+
+    function automatic [4:0] raiseExceptionFlag;
+        input [4:0] currFlag;
+        input [4:0] flagToSet;
+
+        begin
+            raiseExceptionFlag = currFlag | flagToSet;
+        end
+    endfunction
+
+    task automatic propagateNaN_fp32;
+        input [FP32_W-1:0] fa;
+        input [FP32_W-1:0] fb;
+        input [4:0] f_currFlag;
+
+        output [FP32_W-1:0] fout;
+        output [4:0] fout_exptFlag;
+
+        begin : propagate
+            reg is_fa_signal;
+            reg is_fb_signal;
+            reg [4:0] f_expt_flag;
+
+            f_expt_flag = f_currFlag;
+
+            is_fa_signal = isSignalNaN_fp32(fa);
+            is_fb_signal = isSignalNaN_fp32(fb);
+
+            if (is_fa_signal || is_fb_signal) begin
+                f_expt_flag = raiseExceptionFlag(f_expt_flag, invalidBitMask);
+            end
+
+            fout = defaultNaN_fp32;
+            fout_exptFlag = f_expt_flag;
+        end
+    endtask
+
+    function automatic integer count_leading_zero;
+        input [30:0] val;
+
+        begin : cnt
+            integer i;
+            for (i=30; val[i]==0; i=i-1) begin
+            end
+            count_leading_zero = 30 - i;
+        end
+    endfunction
+
+    function automatic [31:0] adjust_radix_pt;
+        input [31:0] frac;
+        input integer exp_diff;
+
+        begin : adjust
+            reg [31:0] adj_frac;
+            reg [1:0] gr;
+            reg s;
+
+            if (exp_diff >= 2) begin
+                gr = (frac & ((1<<exp_diff) - 1)) >> (exp_diff - 2);
+            end
+            else begin
+                gr = {frac&exp_diff, 1'b0};
+            end
+
+            if (exp_diff >= 3) begin
+                s = |(frac & ((1<<(exp_diff-2)) - 1));
+            end
+            else begin
+                s = 1'b0;
+            end
+
+            adj_frac = {(frac >> exp_diff), gr, s};
+
+            adjust_radix_pt = adj_frac;
+        end
+    endfunction
+
+    function automatic find_rounding;
+        input f_sign;
+        input [31:0] f_frac;
+        input integer rbit;
+        input [2:0] rounding_mode;
+
+        begin : round_value
+            reg lsb, g, r, s;
+            reg ulp;
+
+            lsb = (rbit < 32) ? f_frac[rbit] : 1'b0;
+
+            if (rbit >= 2) begin
+                {g, r} = (f_frac & ((1<<rbit) - 1)) >> (rbit - 2);
+            end
+            else begin
+                {g, r} = {f_frac&rbit, 1'b0};
+            end
+
+            if (rbit >= 3) begin
+                s = |(f_frac & ((1<<(rbit-2)) - 1));
+            end
+            else begin
+                s = 1'b0;
+            end
+
+            case (rounding_mode)
+                3'b001: // rz
+                begin
+                    ulp = 1'b0;
+                end
+                3'b010: // rdown
+                begin
+                    ulp = (f_sign == 1 && ({g, r, s} != 3'b000))? 1'b1:1'b0;
+                end
+                3'b011: // rup
+                begin
+                    ulp = (f_sign == 0 && ({g, r, s} != 3'b000))? 1'b1:1'b0;
+                end
+                3'b100: // rnz
+                begin
+                    ulp = g;
+                end
+                3'b110: // rno
+                begin
+                    ulp = ({g, r, s} != 3'b000)? ~lsb : 1'b0;
+                end
+                default: //rne
+                begin
+                    if ({g, r, s} == 3'b100) begin
+                        ulp = lsb;
+                    end
+                    else begin
+                        ulp = g;
+                    end
+                end
+            endcase
+
+            find_rounding = ulp;
+        end
+    endfunction
+
+    task automatic round_and_pack_fp32;
+        input f_sign;
+        input [FP32_N_EXP*2-1:0] f_exp;
+        input [31:0] f_frac;
+        input [4:0] f_currFlag;
+        input [2:0] rounding_mode;
+
+        output [31:0] f_round;
+        output [4:0] f_exptFlag;
+
+        begin : rounding
+            // rounding 32 bits fraction to 23 bits
+            // assume there are 2 bits at MSB have special use,
+            // for example, the hidden bit "1" is at bit 30
+            // therefore, 32-23-2 = 7 and the new LSB is at bit 7
+            localparam integer RoundToBit = 7;
+
+            reg signed [FP32_N_EXP*2-1:0] f_exp_round;
+            reg [31:0] f_frac_round;
+            reg [4:0] f_expt_flag;
+            reg signed [FP32_N_EXP*2-1:0] exp_max, exp_min;
+
+            integer rbit;
+
+            reg lsb, g, r, s;
+            reg ulp;
+
+            rbit = RoundToBit;
+
+            exp_max = (1 << FP32_N_EXP) - 2;
+            exp_min = 'd1;
+
+            ulp = find_rounding(f_sign, f_frac, RoundToBit, rounding_mode);
+
+            f_exp_round = f_exp;
+            f_frac_round = (f_frac >> RoundToBit) + ulp;
+            f_expt_flag = f_currFlag;
+
+            if (f_frac_round[24] == 1'b1) begin
+                f_frac_round = f_frac_round >> 1;
+                f_exp_round = f_exp_round + 1;
+            end
+
+            if ((f_frac&((1<<RoundToBit)-1)) != 'd0) begin
+                f_expt_flag = raiseExceptionFlag(f_expt_flag, inexactBitMask);
+            end
+
+            if (f_exp_round > exp_max) begin
+                if (rounding_mode == 3'b010) begin
+                    f_round = (f_sign) ?
+                        {f_sign, {FP32_N_EXP{1'b1}}, {FP32_N_FRAC{1'b0}}} :
+                        {f_sign, {FP32_N_EXP-1{1'b1}}, 1'b0, {FP32_N_FRAC{1'b1}}};
+                end
+                else if (rounding_mode == 3'b011) begin
+                    f_round = (f_sign) ?
+                        {f_sign, {FP32_N_EXP-1{1'b1}}, 1'b0, {FP32_N_FRAC{1'b1}}} :
+                        {f_sign, {FP32_N_EXP{1'b1}}, {FP32_N_FRAC{1'b0}}};
+                end
+                else if (rounding_mode == 3'b001 || rounding_mode == 3'b110) begin
+                    f_round = {f_sign, {FP32_N_EXP-1{1'b1}}, 1'b0, {FP32_N_FRAC{1'b1}}};
+                end
+                else begin
+                    f_round = {f_sign, {FP32_N_EXP{1'b1}}, {FP32_N_FRAC{1'b0}}};
+                end
+
+                f_expt_flag = raiseExceptionFlag(f_expt_flag, (overflowBitMask | inexactBitMask));
+
+            end
+            else if (f_exp_round < exp_min) begin
+                // use original fraction
+                // calculate the new round-to-bit by adding the addition bits when exp <= 0
+                rbit = rbit + (-f_exp_round) + 1;
+
+                if ((f_frac&((1<<rbit)-1)) != 'd0) begin
+                    f_expt_flag = raiseExceptionFlag(f_expt_flag, (underflowBitMask | inexactBitMask));
+                end
+
+                // if bit 23 is 1 after round, exp + 1
+                ulp = find_rounding(f_sign, f_frac, rbit, rounding_mode);
+                f_frac_round = (f_frac >> rbit) + ulp;
+
+                // become subnormal, set to zero
+                f_round = (f_frac_round[23] == 1'b1) ?
+                    {f_sign, ({(FP32_N_EXP+FP32_N_FRAC){1'b0}} | f_frac_round[23:0])} :
+                    {f_sign, {(FP32_N_EXP+FP32_N_FRAC){1'b0}}};
+
+            end
+            else begin
+                f_round = {f_sign, f_exp_round[FP32_N_EXP-1:0], f_frac_round[FP32_N_FRAC-1:0]};
+            end
+
+            f_exptFlag = f_expt_flag;
+        end
+    endtask
+
+    task automatic muladd_fp32;
+        input [BF16_W-1:0] a, b;
+        input [FP32_W-1:0] c;
+        input [1:0] op_mode;
+        input [2:0] rounding_mode;
+        output [FP32_W-1:0] p;
+        output [4:0] exceptionFlag;
+
+        begin : muladd
+            reg a_sign;
+            reg [BF16_N_EXP-1:0] a_exp;
+            reg [BF16_N_FRAC-1:0] a_frac;
+            reg isNaN_a, isInf_a, isZero_a;
+
+            reg b_sign;
+            reg [BF16_N_EXP-1:0] b_exp;
+            reg [BF16_N_FRAC-1:0] b_frac;
+            reg isNaN_b, isInf_b, isZero_b;
+
+            reg c_sign;
+            reg [FP32_N_EXP-1:0] c_exp;
+            reg [FP32_N_FRAC-1:0] c_frac;
+            reg isNaN_c, isInf_c, isZero_c;
+
+            reg [FP32_N_EXP:0] exp_max, exp_min;
+            reg signed [FP32_N_EXP-1:0] exp_bias;
+
+            reg var_c_sign;
+
+            reg var_p_sign;
+            reg signed [FP32_N_EXP*2-1:0] var_p_exp;
+            reg [31:0] var_p_frac;
+
+            reg var_s_sign;
+            reg [FP32_N_EXP*2-1:0] var_s_exp;
+            // sign bit, carry,  hidden bit "1"
+            // -> reserve 3 bits at MSB
+            // save 3 bits when right-shift 
+            // -> reserve 3 bits at LSB
+            reg [31:0] var_c_frac;
+            reg [31:0] var_s_frac;
+            reg [FP32_W-1:0] var_s;
+            reg [4:0] var_s_flag;
+
+            integer exp_diff;
+            integer n_sl;
+
+            var_s = {(FP32_W-1){1'b0}};
+            var_s_flag = {5{1'b0}};
+
+            exp_bias = ((1 << FP32_N_EXP-1) - 1);
+            exp_max = (1 << FP32_N_EXP) - 2;
+            exp_min = 'd0;
+
+            decode_bf16_rep(a, isNaN_a, isInf_a, isZero_a, a_sign, a_exp, a_frac);
+            decode_bf16_rep(b, isNaN_b, isInf_b, isZero_b, b_sign, b_exp, b_frac);
+
+            decode_fp32_rep(c, isNaN_c, isInf_c, isZero_c, c_sign, c_exp, c_frac);
+
+            if (isNaN_a || isNaN_b) begin
+                propagateNaN_fp32((a<<16), (b<<16), var_s_flag, var_s, var_s_flag);
+                propagateNaN_fp32(var_s, c, var_s_flag, p, exceptionFlag);
+                disable muladd;
+            end
+
+            if ((isInf_a && isZero_b) || (isZero_a && isInf_b)) begin
+                p = defaultNaN_fp32;
+                exceptionFlag = raiseExceptionFlag(var_s_flag, invalidBitMask);
+                disable muladd;
+            end
+
+            var_c_sign = c_sign^op_mode[0];
+            var_p_sign = a_sign^b_sign^op_mode[1];
+
+            if (isInf_a || isInf_b) begin
+                var_s = {var_p_sign, {FP32_N_EXP{1'b1}}, {FP32_N_FRAC{1'b0}}};
+                if (isNaN_c) begin
+                    propagateNaN_fp32(var_s, c, var_s_flag, p, exceptionFlag);
+                end
+                else if (isInf_c && var_p_sign != var_c_sign) begin
+                    var_s = defaultNaN_fp32;
+                    var_s_flag = raiseExceptionFlag(var_s_flag, invalidBitMask);
+
+                    propagateNaN_fp32(var_s, c, var_s_flag, p, exceptionFlag);
+                end
+                else begin
+                    p = var_s;
+                    exceptionFlag = var_s_flag;
+                end
+
+                disable muladd;
+            end
+
+            if (isNaN_c) begin
+                //p = c;
+                propagateNaN_fp32('d0, c, var_s_flag, p, exceptionFlag);
+                disable muladd;
+            end
+
+            if (isInf_c) begin
+                //p = c;
+                p = {var_c_sign, c_exp, c_frac};
+                exceptionFlag = var_s_flag;
+                disable muladd;
+            end
+
+            if (isZero_a || isZero_b) begin
+                if (isZero_c && (var_p_sign^var_c_sign)) begin
+                    p = {((rounding_mode == 3'b010)? 1'b1 : 1'b0), {31{1'b0}}};
+                end
+                else begin
+                    //p = c;
+                    p = {var_c_sign, c_exp, c_frac};
+                end
+
+                exceptionFlag = var_s_flag;
+                disable muladd;
+            end
+
+            // mul part
+            var_p_exp = $signed(a_exp - exp_bias) + $signed(b_exp - exp_bias) + exp_bias;
+
+            // add back the hidden bit when multiply
+            var_p_frac = ({1'b1, a_frac} * {1'b1, b_frac});
+
+            // normalize product
+            if (var_p_frac[15] == 1'b1) begin
+                var_p_exp = var_p_exp + 1;
+            end
+            else begin
+                var_p_frac = var_p_frac << 1;
+            end
+
+            // add part
+            if (isZero_c) begin
+                // rounding and pack
+                round_and_pack_fp32(var_p_sign, var_p_exp,
+                    (var_p_frac[15:0] << 15), var_s_flag, rounding_mode,
+                    p, exceptionFlag);
+
+                disable muladd;
+            end
+
+            var_p_frac = var_p_frac[15:0] << (3 + 8);
+            var_c_frac = {1'b1, c_frac} << 3;
+
+            exp_diff = $signed(var_p_exp) - $signed({1'b0, c_exp});
+
+            if (exp_diff >= 0) begin
+                // 3 extra bits (g,r,s) may add at LSB after radix adjustment
+                var_p_frac = var_p_frac << 3;
+                var_c_frac = adjust_radix_pt(var_c_frac, exp_diff);
+
+                var_s_exp = var_p_exp;
+            end
+            else begin
+                // 3 extra bits (g,r,s) may add at LSB after radix adjustment
+                var_p_frac = adjust_radix_pt(var_p_frac, -exp_diff);
+                var_c_frac = var_c_frac << 3;
+
+                var_s_exp = c_exp;
+            end
+
+            var_p_frac = (var_p_sign)?-var_p_frac:var_p_frac;
+            var_c_frac = (var_c_sign)?-var_c_frac:var_c_frac;
+
+            var_s_frac = var_p_frac + var_c_frac;
+
+            if (exp_diff == 0 && (var_p_sign^var_c_sign) && ~(|var_s_frac)) begin
+                // complete cancel?
+                var_s = {((rounding_mode == 3'b010)? 1'b1 : 1'b0), {31{1'b0}}};
+
+            end
+            else begin
+                var_s_sign = var_s_frac[31];
+                var_s_frac = (var_s_frac[31])?-var_s_frac:var_s_frac;
+
+                // normalize sum
+                // now, consider the hidden '1' at bit 30, instead of bit 29
+                // -> will need to rounding the last 7 bits, instead of 6
+                if (var_s_frac[30] == 1'b1) begin
+                    var_s_exp = var_s_exp + 1;
+                end
+                else begin
+                    // make sure the hidden '1' is at bit 30
+                    var_s_frac = var_s_frac << 1;
+                end
+
+                n_sl = count_leading_zero(var_s_frac[30:0]);
+                var_s_exp = var_s_exp - n_sl;
+                var_s_frac = var_s_frac << n_sl;
+
+                // rounding and pack
+                round_and_pack_fp32(var_s_sign, var_s_exp, var_s_frac, var_s_flag, rounding_mode,
+                    var_s, var_s_flag);
+            end
+
+            p = var_s;
+            exceptionFlag = var_s_flag;
+        end
+    endtask
+
+    reg [FP32_W-1:0] w_r;
+    reg [4:0] w_r_expt_flag = {5{1'b0}};
+
+    assign r = {w_r_expt_flag, {(R_W-FP32_W-5){1'b0}}, w_r};
+
+    always @(*)
+    begin
+        muladd_fp32(a, b, c, op, rounding_mode, w_r, w_r_expt_flag);
+    end
+
+endmodule
+
+module fp_fmt_conv();
+    parameter R_W = 48;
+    parameter EXP_W = 8;
+    parameter FRAC_W = 23;
+    parameter BF_FRAC_W = 7;
+
+    localparam FP_W = EXP_W+FRAC_W+1;
+    localparam BF_W = EXP_W+BF_FRAC_W+1;
+
+    function automatic [FP_W-1:0] rec_to_fp;
+        input [FP_W:0] rec_in;
+
+        begin : convert_to_fp
+            reg sign;
+            reg signed [EXP_W+1:0] rec_exp;
+            reg [FRAC_W-1:0] rec_frac;
+
+            reg [EXP_W-1:0] fp_exp;
+            reg [FRAC_W-1:0] fp_frac;
+
+            reg signed [EXP_W:0] fp_exp_min;
+
+            reg isSpecial;
+            reg isNaN, isInf, isZero;
+            reg isSubnormal;
+
+            fp_exp_min = (1<<(EXP_W-1)) + 2;
+
+            sign = rec_in[FP_W];
+            rec_exp = rec_in[EXP_W+FRAC_W:FRAC_W];
+            rec_frac = rec_in[FRAC_W-1:0];
+
+            isSpecial = (rec_exp[EXP_W:EXP_W-1] == 2'b11);
+
+            isNaN = isSpecial && rec_exp[EXP_W-2];
+            isInf = isSpecial && !rec_exp[EXP_W-2];
+            isZero = (rec_exp[EXP_W:EXP_W-2] == 3'b000);
+            isSubnormal = (rec_exp < fp_exp_min);
+
+            fp_exp = (isSubnormal) ? {EXP_W{1'b0}} :
+                (isNaN || isInf) ? {EXP_W{1'b1}} : (rec_exp - fp_exp_min + 1);
+            fp_frac = (isSubnormal || isInf) ? {FRAC_W{1'b0}} : rec_frac;
+            rec_to_fp = {sign, fp_exp, fp_frac};
+        end
+    endfunction
+
+    function automatic [FP_W:0] fp_to_rec;
+        input [FP_W-1:0] fp_in;
+
+        begin : convert_to_rec
+            reg sign;
+            reg [EXP_W-1:0] fp_exp;
+            reg [FRAC_W-1:0] fp_frac;
+
+            reg [EXP_W:0] rec_exp;
+            reg [FRAC_W-1:0] rec_frac;
+
+            reg [EXP_W:0] adj_exp;
+
+            reg isSpecial, isExpZero;
+
+            sign = fp_in[FP_W-1];
+            fp_exp = fp_in[EXP_W+FRAC_W-1:FRAC_W];
+            fp_frac = fp_in[FRAC_W-1:0];
+
+            adj_exp = fp_exp + ((1 << (EXP_W-1)) | 1);
+
+            isExpZero = (fp_exp == 0);
+            isSpecial = (adj_exp[EXP_W:EXP_W-1]  == 2'b11);
+
+            rec_exp[EXP_W:EXP_W-2] = (isSpecial)? {2'b11, (|fp_frac)} : (isExpZero)? 3'b000 : adj_exp[EXP_W:EXP_W-2];
+            rec_exp[EXP_W-3:0] = adj_exp[EXP_W-3:0];
+
+            rec_frac = (isExpZero)? {FRAC_W{1'b0}} : fp_frac;
+            fp_to_rec = {sign, rec_exp, rec_frac};
+        end
+    endfunction
+
+    function automatic [R_W-1:0] conv_rec_to_fp;
+        input [R_W-1:0] in;
+
+        begin
+            conv_rec_to_fp = {in[R_W-1:R_W-5], {(R_W-FP_W-5){1'b0}}, rec_to_fp(in[FP_W:0])};
+        end
+    endfunction
+
+    function automatic [R_W-1:0] conv_fp_to_rec;
+        input [R_W-1:0] in;
+
+        begin
+            conv_fp_to_rec = {in[R_W-1:R_W-5], {(R_W-(FP_W+1)-5){1'b0}}, fp_to_rec(in[FP_W-1:0])};
+        end
+    endfunction
+
+    function automatic [BF_W-1:0] adjust_bf_input;
+        input [BF_W-1:0] bf_in;
+
+        begin : cast_to_zero_if_denormal
+            reg sign;
+            reg [EXP_W-1:0] bf_exp;
+            reg [BF_FRAC_W-1:0] bf_frac;
+
+            reg [BF_FRAC_W-1:0] bf_out_frac;
+
+            reg isExpZero;
+
+            sign = bf_in[BF_W-1];
+            bf_exp = bf_in[EXP_W+BF_FRAC_W-1:BF_FRAC_W];
+            bf_frac = bf_in[BF_FRAC_W-1:0];
+
+            isExpZero = (bf_exp == 0);
+
+            bf_out_frac = (isExpZero)? {BF_FRAC_W{1'b0}} : bf_frac;
+            adjust_bf_input = {sign, bf_exp, bf_out_frac};
+        end
+    endfunction
+
+endmodule
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_ff.v

@@ -0,0 +1,129 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix FF:
+//
+// This is a D-FF with clock-enable and programmable set/reset
+// All of the data and control inputs are invertable
+// the set/reset pin can be sync or async, set or reset
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_FF # 
+(
+ parameter CLK_POLARITY = 1'b1, // 0 falling edge, 1 rising edge
+ parameter CE_POLARITY  = 1'b1, // 0 negative, 1 positive
+ parameter SR_POLARITY  = 1'b1, // 0 negative, 1 positive
+ parameter SR_SYNC      = 1'b0, // 0 async, 1 sync
+ parameter SR_VALUE     = 1'b0, // 0 reset, 1 set
+ parameter SR_SYNC_PRIORITY = 1'b1, // 0 CE, 1 SR
+ parameter D_POLARITY   = 1'b1  // 0 invert
+)
+(
+ input 	    D, // data input
+ input 	    CE, // clock-enable
+ input 	    CLK, // clock
+ input 	    SR, // asyc/sync set/reset
+ output reg Q  = 0 // data output
+);
+
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     CE_net;
+   wire     SR_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY ? 1'b1 : 1'b0;
+   assign (weak0, weak1) SR_net = SR_POLARITY ? 1'b0 : 1'b1;
+
+   // Now assign the input
+   assign CE_net = CE;
+   assign SR_net = SR;
+   
+   // Internal signals
+   wire d_int;
+   wire ce_int;
+   wire clk_int;
+   wire sr_int;
+   wire sync_sr_int;
+   wire async_sr_int;
+   wire priority_ce_int;
+     
+   // Check parameters and set internal signals appropriately
+   
+   // Check clock polarity
+   assign clk_int = CLK_POLARITY ? CLK : ~CLK;
+   
+   // Check clock-enable polarity
+   assign ce_int = CE_POLARITY ? CE_net : ~CE_net;
+
+   // Check set/reset polarity
+   assign sr_int = SR_POLARITY ? SR_net : ~SR_net;
+
+   // Check datas polarity
+   assign d_int = D_POLARITY ? D : ~D;
+
+   // Decide if set/reset is sync or async
+   assign sync_sr_int = SR_SYNC ? sr_int : 1'b0;
+   assign async_sr_int = SR_SYNC ? 1'b0 : sr_int;
+
+   // Decide if CE or sync SR is a priority
+   assign priority_ce_int = SR_SYNC_PRIORITY ? 1'b1 : ce_int;
+
+   // Actual FF guts, everything is positive logic
+   always @(posedge async_sr_int or posedge clk_int)
+     // Only one of async/sync sr will be valid
+     if (async_sr_int)
+       Q <= SR_VALUE;
+     else if (priority_ce_int)
+       if (sync_sr_int)
+		 Q <= SR_VALUE;
+	   else if (ce_int)
+		 Q <= d_int;
+
+endmodule // EFX_FF
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_gbufce.v

@@ -0,0 +1,89 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix Global Buffer:
+//
+// This is a simple clock buffer with a glitch free
+// clock-enable
+// The clock-enable is invertable
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_GBUFCE #
+(
+ parameter CE_POLARITY  = 1'b1 // 0 active low, 1 active high
+)
+(
+ input 	CE, // clock-enable, active high
+ input 	I,  // data input
+ output O   // data outputclock
+);
+
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     CE_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY ? 1'b1 : 1'b0;
+
+   // Now assign the input
+   assign CE_net = CE;
+   
+   wire ce_int;
+   reg 	ce_sync;
+
+   // Insert inverter if active-low polarity
+   assign ce_int = CE_POLARITY ? CE_net : ~CE_net;
+
+   // Sync clock-enable to clock
+   always @(I or ce_int)
+     if (~I) ce_sync = ce_int;
+
+   assign O = I & ce_sync;
+
+endmodule // EFX_GBUFCE
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_lut4.v

@@ -0,0 +1,140 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix 4-input Lookup Table (LUT):
+//
+// This is a simple 4-input LUT
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_LUT4 #
+(
+ parameter LUTMASK  = 16'h0000 // Content of Lookup table RAM
+)
+(
+ input 	I0,  // data input
+ input 	I1,  // data input
+ input 	I2,  // data input
+ input 	I3,  // data input
+ output O    // data output
+);
+
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     I0_net;
+   wire     I1_net;
+   wire     I2_net;
+   wire     I3_net;
+
+   // Default values for unused inputs
+   assign (weak0, weak1) I0_net = 1'b0;
+   assign (weak0, weak1) I1_net = 1'b0;
+   assign (weak0, weak1) I2_net = 1'b0;
+   assign (weak0, weak1) I3_net = 1'b0;
+
+   // Now assign the input
+   assign I0_net = I0;
+   assign I1_net = I1;
+   assign I2_net = I2;
+   assign I3_net = I3;
+
+   // internal variables
+   wire [15:0] lutrom;
+   reg 	       lut = 1'b0;
+   
+   // assign LUT ROM
+   assign lutrom = LUTMASK;
+   
+   always @(I0_net or I1_net or I2_net or I3_net) begin
+      lut = get_lut_value(3, {I3_net, I2_net, I1_net, I0_net});
+   end
+
+   assign O = lut;
+
+   function automatic [0:0] get_lut_value;
+	  input integer index;
+	  input [3:0] I;
+	  reg 		  hi_value, lo_value;
+	  
+	  // Check for an X value
+	  if (I[index] === 1'bx) begin
+		 // Need to test if both sub-trees return the same value
+		 case (index)
+		   3: begin
+			  hi_value = get_lut_value(2, {1'b1, I[2:0]});
+			  lo_value = get_lut_value(2, {1'b0, I[2:0]});
+		   end
+		   2: begin
+			  hi_value = get_lut_value(1, {I[3], 1'b1, I[1:0]});
+			  lo_value = get_lut_value(1, {I[3], 1'b0, I[1:0]});
+		   end
+		   1: begin
+			  hi_value = get_lut_value(0, {I[3:2], 1'b1, I[0]});
+			  lo_value = get_lut_value(0, {I[3:2], 1'b0, I[0]});
+		   end
+		   0: begin
+			  hi_value = lutrom[{I[3:1], 1'b1}];
+			  lo_value = lutrom[{I[3:1], 1'b0}];
+		   end
+		 endcase // case (index)
+
+		 //  If the same value return it, otherwise X
+		 get_lut_value = (hi_value === lo_value) ? hi_value : 1'bx;
+		 
+	  end
+	  else
+		// If last index return the value
+		if (index == 0)
+		  get_lut_value = lutrom[I];
+		else
+		  get_lut_value = get_lut_value(index-1, I);
+		  
+   endfunction //
+   
+   
+endmodule // EFX_LUT4
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_mult.v

@@ -0,0 +1,207 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix Multipler:
+//
+// This is a simple signed multiplier
+// with optional registers on all data ports.
+//
+// The multiplier can be in the widths:
+//   16 --> 16x16
+//   18 --> 18x18
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+// Set the next line to 1 to enable checks that
+// the multiplier widths are legal for our architectures
+`define STRICT_MULT_CHECK 1
+
+module EFX_MULT
+(
+   A, B, O, CLK, CEA, RSTA, CEB, RSTB, CEO, RSTO
+);
+   
+   parameter WIDTH        = 18;
+   parameter A_REG        = 1'b0;
+   parameter B_REG        = 1'b0;
+   parameter O_REG        = 1'b0;
+   parameter CLK_POLARITY = 1'b1; // 0 falling edge, 1 rising edge
+   parameter CEA_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTA_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTA_SYNC     = 1'b0; // 0 async, 1 sync
+   parameter RSTA_VALUE    = 1'b0; // 0 reset, 1 set
+   parameter CEB_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTB_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTB_SYNC     = 1'b0; // 0 async, 1 sync
+   parameter RSTB_VALUE    = 1'b0; // 0 reset, 1 set
+   parameter CEO_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTO_POLARITY = 1'b1; // 0 negative, 1 positive
+   parameter RSTO_SYNC     = 1'b0; // 0 async, 1 sync
+   parameter RSTO_VALUE    = 1'b0; // 0 reset, 1 set
+   parameter SR_SYNC_PRIORITY = 1'b1; // 0 CE, 1 SR
+   
+   initial begin
+	  // Check for illegal width
+	  if (`STRICT_MULT_CHECK) begin
+		 if (WIDTH != 16 && WIDTH != 18 ) begin
+			$display("ERROR:Illegal WIDTH %d", WIDTH);
+			$finish();
+		 end
+	  end
+   end
+
+   localparam IN_DATA_WIDTH = WIDTH;
+   localparam OUT_DATA_WIDTH = WIDTH*2;
+
+   input  signed [IN_DATA_WIDTH-1:0] A, B;
+   output signed [OUT_DATA_WIDTH-1:0] O;
+   input CLK, CEA, RSTA, CEB, RSTB, CEO, RSTO;
+
+   wire  signed [IN_DATA_WIDTH-1:0] A_ff, B_ff, A_int, B_int;
+   wire  signed [OUT_DATA_WIDTH-1:0] O_ff, O_int;
+
+   // Optional input registers
+   genvar i;
+   generate for(i=0;i<IN_DATA_WIDTH;i=i+1) begin : inreg
+	  INIT_MULT_FF #(.CLK_POLARITY(CLK_POLARITY), .CE_POLARITY(CEA_POLARITY), .SR_POLARITY(RSTA_POLARITY), .SR_VALUE(RSTA_VALUE), .SR_SYNC(RSTA_SYNC), .SR_SYNC_PRIORITY(SR_SYNC_PRIORITY)) 
+	      ffa (.D(A[i]), .CLK(CLK), .CE(CEA), .SR(RSTA), .Q(A_ff[i]));
+	  
+	  INIT_MULT_FF #(.CLK_POLARITY(CLK_POLARITY), .CE_POLARITY(CEB_POLARITY), .SR_POLARITY(RSTB_POLARITY), .SR_VALUE(RSTB_VALUE), .SR_SYNC(RSTB_SYNC), .SR_SYNC_PRIORITY(SR_SYNC_PRIORITY)) 
+	      ffb(.D(B[i]), .CLK(CLK), .CE(CEB), .SR(RSTB), .Q(B_ff[i]));
+   end
+   endgenerate
+
+   assign A_int = (A_REG == 1) ? A_ff : A;
+   assign B_int = (B_REG == 1) ? B_ff : B;
+   
+   assign O_int = A_int * B_int;
+
+   // Optional output registers
+   genvar j;
+   generate for(j=0;j<OUT_DATA_WIDTH;j=j+1) begin : outreg
+	  INIT_MULT_FF #(.CLK_POLARITY(CLK_POLARITY), .CE_POLARITY(CEO_POLARITY), .SR_POLARITY(RSTO_POLARITY), .SR_VALUE(RSTO_VALUE), .SR_SYNC(RSTO_SYNC), .SR_SYNC_PRIORITY(SR_SYNC_PRIORITY)) 
+	      ffo(.D(O_int[j]), .CLK(CLK), .CE(CEO), .SR(RSTO), .Q(O_ff[j]));
+   end
+   endgenerate
+
+   assign O = (O_REG == 1) ? O_ff : O_int;
+
+endmodule // EFX_MULT
+
+module INIT_MULT_FF # 
+(
+ parameter CLK_POLARITY = 1'b1, // 0 falling edge, 1 rising edge
+ parameter CE_POLARITY  = 1'b1, // 0 negative, 1 positive
+ parameter SR_POLARITY  = 1'b1, // 0 negative, 1 positive
+ parameter SR_SYNC      = 1'b0, // 0 async, 1 sync
+ parameter SR_VALUE     = 1'b0, // 0 reset, 1 set
+ parameter SR_SYNC_PRIORITY = 1'b1, // 0 CE, 1 SR
+ parameter D_POLARITY   = 1'b1  // 0 invert
+)
+(
+ input 	    D, // data input
+ input 	    CE, // clock-enable
+ input 	    CLK, // clock
+ input 	    SR, // asyc/sync set/reset
+ output reg Q = 1'b0    // data output
+);
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     CE_net;
+   wire     SR_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) CE_net = CE_POLARITY ? 1'b1 : 1'b0;
+   assign (weak0, weak1) SR_net = SR_POLARITY ? 1'b0 : 1'b1;
+
+   // Now assign the input
+   assign CE_net = CE;
+   assign SR_net = SR;
+   
+   // Internal signals
+   wire d_int;
+   wire ce_int;
+   wire clk_int;
+   wire sr_int;
+   wire sync_sr_int;
+   wire async_sr_int;
+   wire priority_ce_int;
+     
+   // Check parameters and set internal signals appropriately
+   
+   // Check clock polarity
+   assign clk_int = CLK_POLARITY ? CLK : ~CLK;
+   
+   // Check clock-enable polarity
+   assign ce_int = CE_POLARITY ? CE_net : ~CE_net;
+
+   // Check set/reset polarity
+   assign sr_int = SR_POLARITY ? SR_net : ~SR_net;
+
+   // Check datas polarity
+   assign d_int = D_POLARITY ? D : ~D;
+
+   // Decide if set/reset is sync or async
+   assign sync_sr_int = SR_SYNC ? sr_int : 1'b0;
+   assign async_sr_int = SR_SYNC ? 1'b0 : sr_int;
+
+   // Decide if CE or sync SR is a priority
+   assign priority_ce_int = SR_SYNC_PRIORITY ? 1'b1 : ce_int;
+
+   // Actual FF guts, everything is positive logic
+   always @(posedge async_sr_int or posedge clk_int)
+     // Only one of async/sync sr will be valid
+     if (async_sr_int)
+       Q <= SR_VALUE;
+     else if (priority_ce_int)
+       if (sync_sr_int)
+		 Q <= SR_VALUE;
+	   else if (ce_int)
+		 Q <= d_int;
+
+endmodule // INIT_MULT_FF
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_ram10.v

@@ -0,0 +1,457 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2018 Efinix Inc. All rights reserved.
+//
+// Efinix Block RAM (BRAM):
+//
+// This is a 10K simple dual-port RAM
+// (one read & one write port)
+//
+// The read and write ports can
+// Be in any of the following WIDTHS
+//   16 --> 512x16
+//   8  --> 1024x8
+//   4  --> 2048x4
+//   2  --> 4096x2
+//   1  --> 8192x1
+//   20 --> 512x20
+//   10 --> 1024x10
+//   5  --> 2048x5
+//
+// Writing can be done in one of three WRITE MODEs
+//   READ_FIRST
+//   WRITE_FIRST
+//   READ_UNKNOWN
+//
+// Behavior is undefined when
+// reading / writing the same address
+// TODO: Need to add address collision checking!
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_RAM10
+(
+   WCLK, WE, WCLKE, WADDREN, WDATA, WADDR,
+   RCLK, RE, RST, RADDREN, RDATA, RADDR
+);
+   
+
+   parameter [0:0] WCLK_POLARITY  = 1'b1;
+   parameter [0:0] WCLKE_POLARITY = 1'b1;
+   parameter [0:0] WADDREN_POLARITY = 1'b1;
+   parameter [1:0] WE_POLARITY    = 2'b11;
+   parameter [0:0] RCLK_POLARITY  = 1'b1;
+   parameter [0:0] RE_POLARITY    = 1'b1;
+   parameter [0:0] RST_POLARITY    = 1'b1;
+   parameter [0:0] RADDREN_POLARITY = 1'b1;
+   // Need to add all the data & address input  polarity inversion parameters
+   parameter READ_WIDTH = 16;
+   parameter WRITE_WIDTH = 16;
+   parameter [0:0] OUTPUT_REG = 1'b0;
+   parameter WRITE_MODE = "READ_FIRST";
+   parameter RESET_RAM = "ASYNC";
+   parameter RESET_OUTREG = "ASYNC";
+   
+   parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_AWIDTH = 
+			    (READ_WIDTH == 1) ? 13 :
+			    (READ_WIDTH == 2) ? 12 :
+			    (READ_WIDTH == 4) ? 11 :
+			    (READ_WIDTH == 5) ? 11 :
+			    (READ_WIDTH == 8) ? 10 :
+			    (READ_WIDTH == 10) ? 10 :
+			    (READ_WIDTH == 16) ? 9 :
+			    (READ_WIDTH == 20) ? 9 :-1;
+   
+   localparam WRITE_AWIDTH = 
+			    (WRITE_WIDTH == 1) ? 13 :
+			    (WRITE_WIDTH == 2) ? 12 :
+			    (WRITE_WIDTH == 4) ? 11 :
+			    (WRITE_WIDTH == 5) ? 11 :
+			    (WRITE_WIDTH == 8) ? 10 :
+			    (WRITE_WIDTH == 10) ? 10 :
+			    (WRITE_WIDTH == 16) ? 9 :
+			    (WRITE_WIDTH == 20) ? 9 :-1;
+
+   localparam WRITE_BYTES = (WRITE_WIDTH == 16) || (WRITE_WIDTH == 20);
+   
+   localparam MEMORY_SIZE = 512*20;
+      
+   input 			WCLK, WCLKE, WADDREN;
+   input 			RCLK, RE, RST, RADDREN;
+   input [1:0] 		WE;
+   input [WRITE_WIDTH-1:0]  WDATA;
+   input [WRITE_AWIDTH-1:0] WADDR;
+   input [READ_AWIDTH-1:0] 	RADDR;
+   reg [READ_WIDTH-1:0] 	RDATA_early, RDATA_late;
+   reg [READ_WIDTH-1:0] 	RDATA_out = 0;
+   reg [READ_WIDTH-1:0] 	RDATA_reg = 0;
+   output [READ_WIDTH-1:0] 	RDATA;
+
+   // Local variables
+   reg mem [MEMORY_SIZE-1:0];
+   integer i;
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire [1:0] WE_net;
+   wire     WCLKE_net;
+   wire 	WADDREN_net;
+   wire     RE_net;
+   wire     RST_net;
+   wire 	RADDREN_net;
+
+   // Pull unused address lines low, to mirror EFX synthesis behavior.
+   wire [WRITE_AWIDTH-1:0] WADDR_net;
+   wire [READ_AWIDTH-1:0] RADDR_net;
+   reg [WRITE_AWIDTH-1:0] WADDR_r = 0;
+   reg [READ_AWIDTH-1:0] RADDR_r = 0;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) WE_net      = ~WE_POLARITY;
+   assign (weak0, weak1) WCLKE_net   = WCLKE_POLARITY;
+   assign (weak0, weak1) WADDREN_net = WADDREN_POLARITY;
+   assign (weak0, weak1) RE_net      = RE_POLARITY;
+   assign (weak0, weak1) RST_net     = ~RST_POLARITY;
+   assign (weak0, weak1) RADDREN_net = RADDREN_POLARITY;
+
+   assign (weak0, weak1) WADDR_net = {WRITE_AWIDTH{1'b0}};
+   assign (weak0, weak1) RADDR_net = {READ_AWIDTH{1'b0}};
+
+   // Now assign the input
+   assign WE_net      = WE;
+   assign WCLKE_net   = WCLKE;
+   assign WADDREN_net = WADDREN;
+   assign RE_net      = RE;
+   assign RST_net     = RST;
+   assign RADDREN_net = RADDREN;
+   
+   assign WADDR_net = WADDR;
+   assign RADDR_net = RADDR;
+
+   function COMPATIBLE_WIDTH;
+	  input integer 	w1, w2;
+	  COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8)||(w1==16))&&((w2==1)||(w2==2)||(w2==4)||(w2==8)||(w2==16))) ||
+					(((w1==5)||(w1==10)||(w1==20))&&((w2==5)||(w2==10)||(w2==20))));
+   endfunction
+
+   reg 		finish_error = 0;
+   initial begin
+	  // Check for illegal modes, address width will be -1
+	  if (READ_AWIDTH == -1) begin
+		 $display("ERROR: Illegal READ WIDTH %d", READ_WIDTH);
+		 finish_error = 1;
+	  end
+	  if (WRITE_AWIDTH == -1) begin
+		 $display("ERROR: Illegal WRITE WIDTH %d", WRITE_WIDTH);
+		 finish_error = 1;
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH,WRITE_WIDTH)) begin
+		 $display("ERROR: READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH, WRITE_WIDTH);
+		 finish_error = 1;
+	  end
+	  // Check for illegal write modes
+	  if (WRITE_MODE != "READ_FIRST" && WRITE_MODE != "WRITE_FIRST" && WRITE_MODE != "READ_UNKNOWN") begin
+		 $display("ERROR: Illegal WRITE_MODE %s", WRITE_MODE);
+		 finish_error = 1;
+	  end
+	  if (RESET_RAM != "ASYNC" && RESET_RAM != "SYNC" && RESET_RAM != "NONE") begin
+		 $display("ERROR: Illegal RESET_RAM setting %s", RESET_RAM);
+		 finish_error = 1;
+	  end
+	  if (RESET_OUTREG != "ASYNC" && RESET_OUTREG != "NONE") begin
+		 $display("ERROR: Illegal RESET_OUTREG setting %s", RESET_OUTREG);
+		 finish_error = 1;
+	  end
+	  if ((WRITE_MODE === "WRITE_FIRST") && (WRITE_WIDTH != READ_WIDTH)) begin
+		 $display("ERROR: WRITE_WIDTH %d must match READ_WIDTH %d in WRITE_FIRST WRITE_MODE", WRITE_WIDTH, READ_WIDTH);
+		 finish_error = 1;
+	  end
+
+	  if (finish_error == 1)
+		#1 $finish();
+
+	  // Initialize memory
+      for (i=0; i < 256; i=i+1) begin
+		 mem[256*0+i] = INIT_0[i];
+		 mem[256*1+i] = INIT_1[i];
+		 mem[256*2+i] = INIT_2[i];
+		 mem[256*3+i] = INIT_3[i];
+		 mem[256*4+i] = INIT_4[i];
+		 mem[256*5+i] = INIT_5[i];
+		 mem[256*6+i] = INIT_6[i];
+		 mem[256*7+i] = INIT_7[i];
+		 mem[256*8+i] = INIT_8[i];
+		 mem[256*9+i] = INIT_9[i];
+		 mem[256*10+i] = INIT_A[i];
+		 mem[256*11+i] = INIT_B[i];
+		 mem[256*12+i] = INIT_C[i];
+		 mem[256*13+i] = INIT_D[i];
+		 mem[256*14+i] = INIT_E[i];
+		 mem[256*15+i] = INIT_F[i];
+		 mem[256*16+i] = INIT_10[i];
+		 mem[256*17+i] = INIT_11[i];
+		 mem[256*18+i] = INIT_12[i];
+		 mem[256*19+i] = INIT_13[i];
+		 mem[256*20+i] = INIT_14[i];
+		 mem[256*21+i] = INIT_15[i];
+		 mem[256*22+i] = INIT_16[i];
+		 mem[256*23+i] = INIT_17[i];
+		 mem[256*24+i] = INIT_18[i];
+		 mem[256*25+i] = INIT_19[i];
+		 mem[256*26+i] = INIT_1A[i];
+		 mem[256*27+i] = INIT_1B[i];
+		 mem[256*28+i] = INIT_1C[i];
+		 mem[256*29+i] = INIT_1D[i];
+		 mem[256*30+i] = INIT_1E[i];
+		 mem[256*31+i] = INIT_1F[i];
+		 mem[256*32+i] = INIT_20[i];
+		 mem[256*33+i] = INIT_21[i];
+		 mem[256*34+i] = INIT_22[i];
+		 mem[256*35+i] = INIT_23[i];
+		 mem[256*36+i] = INIT_24[i];
+		 mem[256*37+i] = INIT_25[i];
+		 mem[256*38+i] = INIT_26[i];
+		 mem[256*39+i] = INIT_27[i];
+
+      end
+   end
+
+   // Wires for the polarity control.
+   // Only supporting clocks and enable for now
+   wire 			WCLK_i, WCLKE_i, WADDREN_i;
+   wire 			RCLK_i, RE_i, RCLKE_i, RST_i, RADDREN_i;
+   wire [1:0] 		WE_i;
+
+   assign WCLK_i    = WCLK_POLARITY    ~^ WCLK;
+   assign WCLKE_i   = WCLKE_POLARITY   ~^ WCLKE_net;
+   assign WE_i      = WE_POLARITY      ~^ WE_net;
+   assign WADDREN_i = WADDREN_POLARITY ~^ WADDREN_net;
+   assign RCLK_i    = RCLK_POLARITY    ~^ RCLK;
+   assign RE_i      = RE_POLARITY      ~^ RE_net;
+   assign RST_i     = RST_POLARITY     ~^ RST_net;
+   assign RADDREN_i = RADDREN_POLARITY ~^ RADDREN_net;
+
+   // Wires for the configurable reset controls
+   wire 			ram_async_rst, ram_sync_rst, outreg_async_rst;
+   assign ram_async_rst    = (RESET_RAM == "ASYNC")    ? RST_i : 1'b0;
+   assign ram_sync_rst     = (RESET_RAM == "SYNC")     ? RST_i : 1'b0;
+   assign outreg_async_rst = (RESET_OUTREG == "ASYNC") ? RST_i : 1'b0;
+   
+   //////////////////////////////////////////////////////////////
+   // Tasks for actual RAM reading & writing
+   //////////////////////////////////////////////////////////////
+   task read_ram;
+	  input [READ_AWIDTH-1:0] addr;
+	  output [READ_WIDTH-1:0] rdata;
+ 
+	  begin
+		 for (i=0; i < READ_WIDTH; i=i+1)
+		   rdata[i] = mem[addr*READ_WIDTH+i];
+	  end
+   endtask
+
+   task write_ram;
+	  input [WRITE_AWIDTH-1:0] addr;
+	  input [WRITE_WIDTH-1:0] wdata;
+	  
+	  begin
+		 for (i=0; i < WRITE_WIDTH; i=i+1)
+		   mem[addr*WRITE_WIDTH+i] = wdata[i];
+	  end
+   endtask   
+
+   task write_ram_lo;
+	  input [WRITE_AWIDTH-1:0] addr;
+	  input [WRITE_WIDTH-1:0] wdata;
+	  
+	  begin
+		 for (i=0; i < (WRITE_WIDTH/2); i=i+1)
+		   mem[addr*WRITE_WIDTH+i] = wdata[i];
+	  end
+   endtask   
+
+   task write_ram_hi;
+	  input [WRITE_AWIDTH-1:0] addr;
+	  input [WRITE_WIDTH-1:0] wdata;
+	  
+	  begin
+		 for (i=(WRITE_WIDTH/2); i < WRITE_WIDTH; i=i+1)
+		   mem[addr*WRITE_WIDTH+i] = wdata[i];
+	  end
+   endtask
+   
+
+   always@(posedge WCLK_i) begin
+	  if (WCLKE_i) begin
+		 // Only update the address latch if not stalled
+		 WADDR_r = WADDREN_i ? WADDR_net : WADDR_r;
+		 // #0 delay blocking assignments for coordinating cross port read/write
+		 #0; // Early read
+		 // Write
+		 // Decide if we are writing bytes or the whole data width
+		 if (WRITE_BYTES) begin
+			if (WE_i[0]) begin
+			   // Write low byte
+			   write_ram_lo(WADDR_r, WDATA);
+			end
+			if (WE_i[1]) begin
+			   // Write high byte
+			   write_ram_hi(WADDR_r, WDATA);
+			end
+		 end
+		 else begin
+			if (WE_i[0]) begin
+			   // Write full width
+			   write_ram(WADDR_r, WDATA);
+			end
+		 end
+		 #0; // Late read
+	  end
+   end
+
+   always@(posedge RCLK_i) begin
+	  if (RE_i) begin
+		 // Update the address latch if reading & not stalled
+		 RADDR_r = RADDREN_i ? RADDR_net : RADDR_r;
+		 
+		 // early read, write and late read
+		 read_ram(RADDR_r, RDATA_early);
+		 #0; // Use #0 delay blocking assignments to allow cross port read/write
+		 #0; // Use #0 delay blocking assignments to allow cross port read/write
+		 read_ram(RADDR_r, RDATA_late);
+		 #0;
+	  end
+   end
+
+   // Decide which data to output
+   always@(posedge RCLK_i or posedge ram_async_rst) begin
+	  // Check for async reset
+	  if (ram_async_rst) begin
+		 RDATA_out <= {READ_WIDTH{1'b0}};
+	  end
+	  else begin
+		 // Delay for the read/write/read to happen
+		 #0; #0; #0;
+		 if (RE_i) begin
+			// Check for sync reset
+			if (ram_sync_rst) begin
+			   RDATA_out <= {READ_WIDTH{1'b0}};
+		    end 
+			else begin
+			   // Based on the write mode decide which read data to use
+			   if (WRITE_MODE == "READ_FIRST") begin
+				  RDATA_out <= RDATA_early;
+			   end
+			   else if (WRITE_MODE == "WRITE_FIRST") begin
+				  RDATA_out <= RDATA_late;
+			   end
+			   else /* (WRITE_MODE == "READ_UNKNOWN") */ begin
+				  RDATA_out <= (RDATA_early === RDATA_late) ? RDATA_early : {READ_WIDTH{1'bx}};
+		       end
+			end
+		 end
+	  end
+   end
+   
+   // Optional output register
+   generate if (OUTPUT_REG) 
+	 begin
+		always@(posedge RCLK_i or posedge outreg_async_rst) begin
+		   if (outreg_async_rst) RDATA_reg <= {READ_WIDTH{1'b0}};
+		   else if (RE_i) RDATA_reg <= RDATA_out;
+		end
+
+		assign RDATA = RDATA_reg;
+	 end
+   else
+	 begin
+		assign RDATA = RDATA_out;
+	 end // else: !if(OUTPUT_REG)
+   endgenerate
+	       
+endmodule 
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2017 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_ram_10k.v

@@ -0,0 +1,344 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2018 Efinix Inc. All rights reserved.
+//
+// Efinix Block RAM (BRAM):
+//
+// This is a 10K simple dual-port RAM
+// (one read & one write port)
+//
+// The read and write ports can
+// Be in any of the following WIDTHS
+//   16 --> 512x16
+//   8  --> 1024x8
+//   4  --> 2048x4
+//   2  --> 4096x2
+//   1  --> 8192x1
+//   20 --> 512x20
+//   10 --> 1024x10
+//   5  --> 2048x5
+//
+// Writing can be done in one of three WRITE MODEs
+//   READ_FIRST
+//   WRITE_FIRST
+//   READ_UNKNOWN
+//
+// Behavior is undefined when
+// reading / writing the same address
+// TODO: Need to add address collision checking!
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_RAM_10K
+(
+   WCLK, WE, WCLKE, WDATA, WADDR,
+   RCLK, RE, RDATA, RADDR
+);
+   
+
+   parameter WCLK_POLARITY  = 1'b1;
+   parameter WCLKE_POLARITY = 1'b1;
+   parameter WE_POLARITY    = 1'b1;
+   parameter RCLK_POLARITY  = 1'b1;
+   parameter RE_POLARITY    = 1'b1;
+   // Need to add all the data & address input  polarity inversion parameters
+   parameter READ_WIDTH = 16;
+   parameter WRITE_WIDTH = 16;
+   parameter OUTPUT_REG = 1'b0;
+   parameter WRITE_MODE = "READ_UNKNOWN";
+   parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_AWIDTH = 
+			    (READ_WIDTH == 1) ? 13 :
+			    (READ_WIDTH == 2) ? 12 :
+			    (READ_WIDTH == 4) ? 11 :
+			    (READ_WIDTH == 5) ? 11 :
+			    (READ_WIDTH == 8) ? 10 :
+			    (READ_WIDTH == 10) ? 10 :
+			    (READ_WIDTH == 16) ? 9 :
+			    (READ_WIDTH == 20) ? 9 :-1;
+   
+   localparam WRITE_AWIDTH = 
+			    (WRITE_WIDTH == 1) ? 13 :
+			    (WRITE_WIDTH == 2) ? 12 :
+			    (WRITE_WIDTH == 4) ? 11 :
+			    (WRITE_WIDTH == 5) ? 11 :
+			    (WRITE_WIDTH == 8) ? 10 :
+			    (WRITE_WIDTH == 10) ? 10 :
+			    (WRITE_WIDTH == 16) ? 9 :
+			    (WRITE_WIDTH == 20) ? 9 :-1;
+
+   localparam MEMORY_SIZE = 512*20;
+      
+   input 			WCLK, WE, WCLKE;
+   input 			RCLK, RE;
+   input [WRITE_WIDTH-1:0]  WDATA;
+   input [WRITE_AWIDTH-1:0] WADDR;
+   input [READ_AWIDTH-1:0] 	RADDR;
+   reg [READ_WIDTH-1:0] 	RDATA_early, RDATA_late;
+   reg [READ_WIDTH-1:0] 	RDATA_out = 0;
+   reg [READ_WIDTH-1:0] 	RDATA_reg = 0;
+   output [READ_WIDTH-1:0] 	RDATA;
+
+   // Local variables
+   reg mem [MEMORY_SIZE-1:0];
+   integer i;
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     WE_net;
+   wire     WCLKE_net;
+   wire     RE_net;
+
+   // Pull unused address lines low, to mirror EFX synthesis behavior.
+   wire [WRITE_AWIDTH-1:0] WADDR_net;
+   wire [READ_AWIDTH-1:0] RADDR_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) WE_net = WE_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) WCLKE_net = WCLKE_POLARITY ? 1'b1 : 1'b0;
+   assign (weak0, weak1) RE_net = RE_POLARITY ? 1'b1 : 1'b0;
+
+   assign (weak0, weak1) WADDR_net = {WRITE_AWIDTH{1'b0}};
+   assign (weak0, weak1) RADDR_net = {READ_AWIDTH{1'b0}};
+
+   // Now assign the input
+   assign WE_net = WE;
+   assign WCLKE_net = WCLKE;
+   assign RE_net = RE;
+   
+   assign WADDR_net = WADDR;
+   assign RADDR_net = RADDR;
+
+   function COMPATIBLE_WIDTH;
+	  input integer 	w1, w2;
+	  COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8)||(w1==16))&&((w2==1)||(w2==2)||(w2==4)||(w2==8)||(w2==16))) ||
+					(((w1==5)||(w1==10)||(w1==20))&&((w2==5)||(w2==10)||(w2==20))));
+   endfunction
+
+   initial begin
+	  // Check for illegal modes, address width will be -1
+	  if (READ_AWIDTH == -1) begin
+		 $display("ERROR:Illegal READ WIDTH %d", READ_WIDTH);
+		 $finish();
+	  end
+	  if (WRITE_AWIDTH == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH %d", WRITE_WIDTH);
+		 $finish();
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH,WRITE_WIDTH)) begin
+		 $display("ERROR: READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH, WRITE_WIDTH);
+		 $finish();
+	  end
+	  // Check for illegal write modes
+	  if (WRITE_MODE != "READ_FIRST" && WRITE_MODE != "WRITE_FIRST" && WRITE_MODE != "READ_UNKNOWN") begin
+		 $display("ERROR:Illegal WRITE_MODE %s", WRITE_MODE);
+		 $finish();
+	  end
+	  // Initialize memory
+      for (i=0; i < 256; i=i+1) begin
+		 mem[256*0+i] = INIT_0[i];
+		 mem[256*1+i] = INIT_1[i];
+		 mem[256*2+i] = INIT_2[i];
+		 mem[256*3+i] = INIT_3[i];
+		 mem[256*4+i] = INIT_4[i];
+		 mem[256*5+i] = INIT_5[i];
+		 mem[256*6+i] = INIT_6[i];
+		 mem[256*7+i] = INIT_7[i];
+		 mem[256*8+i] = INIT_8[i];
+		 mem[256*9+i] = INIT_9[i];
+		 mem[256*10+i] = INIT_A[i];
+		 mem[256*11+i] = INIT_B[i];
+		 mem[256*12+i] = INIT_C[i];
+		 mem[256*13+i] = INIT_D[i];
+		 mem[256*14+i] = INIT_E[i];
+		 mem[256*15+i] = INIT_F[i];
+		 mem[256*16+i] = INIT_10[i];
+		 mem[256*17+i] = INIT_11[i];
+		 mem[256*18+i] = INIT_12[i];
+		 mem[256*19+i] = INIT_13[i];
+		 mem[256*20+i] = INIT_14[i];
+		 mem[256*21+i] = INIT_15[i];
+		 mem[256*22+i] = INIT_16[i];
+		 mem[256*23+i] = INIT_17[i];
+		 mem[256*24+i] = INIT_18[i];
+		 mem[256*25+i] = INIT_19[i];
+		 mem[256*26+i] = INIT_1A[i];
+		 mem[256*27+i] = INIT_1B[i];
+		 mem[256*28+i] = INIT_1C[i];
+		 mem[256*29+i] = INIT_1D[i];
+		 mem[256*30+i] = INIT_1E[i];
+		 mem[256*31+i] = INIT_1F[i];
+		 mem[256*32+i] = INIT_20[i];
+		 mem[256*33+i] = INIT_21[i];
+		 mem[256*34+i] = INIT_22[i];
+		 mem[256*35+i] = INIT_23[i];
+		 mem[256*36+i] = INIT_24[i];
+		 mem[256*37+i] = INIT_25[i];
+		 mem[256*38+i] = INIT_26[i];
+		 mem[256*39+i] = INIT_27[i];
+      end
+   end
+
+   // Wires for the polarity control.
+   // Only supporting clocks and enable for now
+   wire 			WCLK_i, WE_i, WCLKE_i;
+   wire 			RCLK_i, RE_i, RCLKE_i;
+
+   assign WCLK_i  = WCLK_POLARITY ? WCLK : ~WCLK;
+   assign WCLKE_i = WCLKE_POLARITY ? WCLKE_net : ~WCLKE_net;
+   assign WE_i    = WE_POLARITY ? WE_net : ~WE_net;
+   assign RCLK_i  = RCLK_POLARITY ? RCLK : ~RCLK;
+   assign RE_i    = RE_POLARITY ? RE_net : ~RE_net;
+
+   //////////////////////////////////////////////////////////////
+   // Tasks for actual RAM reading & writing
+   //////////////////////////////////////////////////////////////
+   task read_ram;
+	  input [READ_AWIDTH-1:0] addr;
+	  output [READ_WIDTH-1:0] rdata;
+ 
+	  begin
+		 for (i=0; i < READ_WIDTH; i=i+1)
+		   rdata[i] = mem[addr*READ_WIDTH+i];
+	  end
+   endtask
+
+   task write_ram;
+	  input [WRITE_AWIDTH-1:0] addr;
+	  input [WRITE_WIDTH-1:0] wdata;
+	  
+	  begin
+		 for (i=0; i < WRITE_WIDTH; i=i+1)
+		   mem[addr*WRITE_WIDTH+i] = wdata[i];
+	  end
+   endtask   
+
+   always@(posedge WCLK_i)
+     if (WE_i & WCLKE_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_ram(WADDR_net, WDATA);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+	 end
+   
+   always@(posedge RCLK_i)
+     if (RE_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+	   read_ram(RADDR_net, RDATA_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+	   read_ram(RADDR_net, RDATA_late);
+
+		// Based on the write mode decide which read data to use
+		if (WRITE_MODE == "READ_FIRST") begin
+		   RDATA_out = RDATA_early;
+		end
+		else if (WRITE_MODE == "WRITE_FIRST") begin
+		   RDATA_out = RDATA_late;
+		end
+		else /* (WRITE_MODE == "READ_UNKNOWN") */ begin
+		   RDATA_out = (RDATA_early === RDATA_late) ? RDATA_early : {READ_WIDTH{1'bx}};
+		end
+	 end
+
+   // Optional output register
+   generate if (OUTPUT_REG) 
+	 begin
+		always@(posedge RCLK_i)
+			RDATA_reg <= RDATA_out;
+
+		assign RDATA = RDATA_reg;
+	 end
+   else
+	 begin
+		assign RDATA = RDATA_out;
+	 end // else: !if(OUTPUT_REG)
+   endgenerate
+	       
+endmodule 
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2017 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_ram_5k.v

@@ -0,0 +1,304 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2013-2016 Efinix Inc. All rights reserved.
+//
+// Efinix Block RAM (BRAM):
+//
+// This is a 5K simple dual-port RAM
+// (one read & one write port)
+//
+// The read and write ports can
+// Be in any of the following WIDTHS
+//   16 --> 256x16
+//   8  --> 512x8
+//   4  --> 1024x4
+//   2  --> 2048x2
+//   1  --> 4096x1
+//   20 --> 256x20
+//   10 --> 512x10
+//   5  --> 1024x5
+//
+// Writing can be done in one of two READ DURING WRITE MODEs
+//   READ_FIRST
+//   WRITE_FIRST
+//   READ_UNKNOWN
+//
+// Behavior is undefined when
+// reading / writing the same address
+// TODO: Need to add address collision checking!
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_RAM_5K
+(
+   WCLK, WE, WCLKE, WDATA, WADDR,
+   RCLK, RE, RDATA, RADDR
+);
+   
+
+   parameter WCLK_POLARITY  = 1'b1;
+   parameter WCLKE_POLARITY = 1'b1;
+   parameter WE_POLARITY    = 1'b1;
+   parameter RCLK_POLARITY  = 1'b1;
+   parameter RE_POLARITY    = 1'b1;
+   // Need to add all the data & address input  polarity inversion parameters
+   parameter READ_WIDTH = 16;
+   parameter WRITE_WIDTH = 16;
+   parameter OUTPUT_REG = 1'b0;
+   parameter WRITE_MODE = "READ_FIRST";
+   parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_AWIDTH = 
+			    (READ_WIDTH == 1) ? 12 :
+			    (READ_WIDTH == 2) ? 11 :
+			    (READ_WIDTH == 4) ? 10 :
+			    (READ_WIDTH == 5) ? 10 :
+			    (READ_WIDTH == 8) ? 9 :
+			    (READ_WIDTH == 10) ? 9 :
+			    (READ_WIDTH == 16) ? 8 :
+			    (READ_WIDTH == 20) ? 8 :-1;
+   
+   localparam WRITE_AWIDTH = 
+			    (WRITE_WIDTH == 1) ? 12 :
+			    (WRITE_WIDTH == 2) ? 11 :
+			    (WRITE_WIDTH == 4) ? 10 :
+			    (WRITE_WIDTH == 5) ? 10 :
+			    (WRITE_WIDTH == 8) ? 9 :
+			    (WRITE_WIDTH == 10) ? 9 :
+			    (WRITE_WIDTH == 16) ? 8 :
+			    (WRITE_WIDTH == 20) ? 8 :-1;
+
+   localparam MEMORY_SIZE = 256*20;
+      
+   input 			WCLK, WE, WCLKE;
+   input 			RCLK, RE;
+   input [WRITE_WIDTH-1:0]  WDATA;
+   input [WRITE_AWIDTH-1:0] WADDR;
+   input [READ_AWIDTH-1:0] 	RADDR;
+   reg [READ_WIDTH-1:0] 	RDATA_early, RDATA_late;
+   reg [READ_WIDTH-1:0] 	RDATA_out = 0;
+   reg [READ_WIDTH-1:0] 	RDATA_reg = 0;
+   output [READ_WIDTH-1:0] 	RDATA;
+
+   // Local variables
+   reg mem [MEMORY_SIZE-1:0];
+   integer i;
+   
+   // Create nets for optional control inputs
+   // allows us to assign to them without getting warning
+   // for coercing input to inout
+   wire     WE_net;
+   wire     WCLKE_net;
+   wire     RE_net;
+
+   // Pull unused address lines low, to mirror EFX synthesis behavior.
+   wire [WRITE_AWIDTH-1:0] WADDR_net;
+   wire [READ_AWIDTH-1:0] RADDR_net;
+
+   // Default values for optional control signals
+   assign (weak0, weak1) WE_net = WE_POLARITY ? 1'b0 : 1'b1;
+   assign (weak0, weak1) WCLKE_net = WCLKE_POLARITY ? 1'b1 : 1'b0;
+   assign (weak0, weak1) RE_net = RE_POLARITY ? 1'b1 : 1'b0;
+
+   assign (weak0, weak1) WADDR_net = {WRITE_AWIDTH{1'b0}};
+   assign (weak0, weak1) RADDR_net = {READ_AWIDTH{1'b0}};
+
+   // Now assign the input
+   assign WE_net = WE;
+   assign WCLKE_net = WCLKE;
+   assign RE_net = RE;
+   
+   assign WADDR_net = WADDR;
+   assign RADDR_net = RADDR;
+
+   function COMPATIBLE_WIDTH;
+	  input integer 	w1, w2;
+	  COMPATIBLE_WIDTH = ((((w1==1)||(w1==2)||(w1==4)||(w1==8)||(w1==16))&&((w2==1)||(w2==2)||(w2==4)||(w2==8)||(w2==16))) ||
+					(((w1==5)||(w1==10)||(w1==20))&&((w2==5)||(w2==10)||(w2==20))));
+   endfunction
+
+   initial begin
+	  // Check for illegal modes, address width will be -1
+	  if (READ_AWIDTH == -1) begin
+		 $display("ERROR:Illegal READ WIDTH %d", READ_WIDTH);
+		 $finish();
+	  end
+	  if (WRITE_AWIDTH == -1) begin
+		 $display("ERROR:Illegal WRITE WIDTH %d", WRITE_WIDTH);
+		 $finish();
+	  end
+	  if (~COMPATIBLE_WIDTH(READ_WIDTH,WRITE_WIDTH)) begin
+		 $display("ERROR: READ WIDTH %d cannot be used with WRITE WIDTH %d", READ_WIDTH, WRITE_WIDTH);
+		 $finish();
+	  end
+	  // Check for illegal write modes
+	  if (WRITE_MODE != "READ_FIRST" && WRITE_MODE != "WRITE_FIRST" && WRITE_MODE != "READ_UNKNOWN") begin
+		 $display("ERROR:Illegal WRITE_MODE %s", WRITE_MODE);
+		 $finish();
+	  end
+	  // Initialize memory
+      for (i=0; i < 256; i=i+1) begin
+		 mem[256*0+i] = INIT_0[i];
+		 mem[256*1+i] = INIT_1[i];
+		 mem[256*2+i] = INIT_2[i];
+		 mem[256*3+i] = INIT_3[i];
+		 mem[256*4+i] = INIT_4[i];
+		 mem[256*5+i] = INIT_5[i];
+		 mem[256*6+i] = INIT_6[i];
+		 mem[256*7+i] = INIT_7[i];
+		 mem[256*8+i] = INIT_8[i];
+		 mem[256*9+i] = INIT_9[i];
+		 mem[256*10+i] = INIT_A[i];
+		 mem[256*11+i] = INIT_B[i];
+		 mem[256*12+i] = INIT_C[i];
+		 mem[256*13+i] = INIT_D[i];
+		 mem[256*14+i] = INIT_E[i];
+		 mem[256*15+i] = INIT_F[i];
+		 mem[256*16+i] = INIT_10[i];
+		 mem[256*17+i] = INIT_11[i];
+		 mem[256*18+i] = INIT_12[i];
+		 mem[256*19+i] = INIT_13[i];
+      end
+   end
+
+   // Wires for the polarity control.
+   // Only supporting clocks and enable for now
+   wire 			WCLK_i, WE_i, WCLKE_i;
+   wire 			RCLK_i, RE_i, RCLKE_i;
+
+   assign WCLK_i  = WCLK_POLARITY ? WCLK : ~WCLK;
+   assign WCLKE_i = WCLKE_POLARITY ? WCLKE_net : ~WCLKE_net;
+   assign WE_i    = WE_POLARITY ? WE_net : ~WE_net;
+   assign RCLK_i  = RCLK_POLARITY ? RCLK : ~RCLK;
+   assign RE_i    = RE_POLARITY ? RE_net : ~RE_net;
+
+   //////////////////////////////////////////////////////////////
+   // Tasks for actual RAM reading & writing
+   //////////////////////////////////////////////////////////////
+   task read_ram;
+	  input [READ_AWIDTH-1:0] addr;
+	  output [READ_WIDTH-1:0] rdata;
+ 
+	  begin
+		 for (i=0; i < READ_WIDTH; i=i+1)
+		   rdata[i] = mem[addr*READ_WIDTH+i];
+	  end
+   endtask
+
+   task write_ram;
+	  input [WRITE_AWIDTH-1:0] addr;
+	  input [WRITE_WIDTH-1:0] wdata;
+	  
+	  begin
+		 for (i=0; i < WRITE_WIDTH; i=i+1)
+		   mem[addr*WRITE_WIDTH+i] = wdata[i];
+	  end
+   endtask   
+
+   always@(posedge WCLK_i)
+     if (WE_i & WCLKE_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		write_ram(WADDR_net, WDATA);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+	 end
+   
+   always@(posedge RCLK_i)
+     if (RE_i) begin
+		// Do an early read, write and late read
+		// Then decide what do do with the read data
+	   read_ram(RADDR_net, RDATA_early);
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+		#0; // Use #0 delay blocking assignments to allow cross port read/write
+	   read_ram(RADDR_net, RDATA_late);
+
+		// Based on the write mode decide which read data to use
+		if (WRITE_MODE == "READ_FIRST") begin
+		   RDATA_out = RDATA_early;
+		end
+		else if (WRITE_MODE == "WRITE_FIRST") begin
+		   RDATA_out = RDATA_late;
+		end
+		else /* (WRITE_MODE == "READ_UNKNOWN") */ begin
+		   RDATA_out = (RDATA_early === RDATA_late) ? RDATA_early : {READ_WIDTH{1'bx}};
+		end
+	 end
+
+   // Optional output register
+   generate if (OUTPUT_REG) 
+	 begin
+		always@(posedge RCLK_i)
+			RDATA_reg <= RDATA_out;
+
+		assign RDATA = RDATA_reg;
+	 end
+   else
+	 begin
+		assign RDATA = RDATA_out;
+	 end // else: !if(OUTPUT_REG)
+   endgenerate
+	       
+endmodule // EFX_RAM_5K
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2017 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/Efinity_Origion/efx_srl8.v

@@ -0,0 +1,107 @@
+/////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// Efinix SRL8:
+//
+// This is an 8-bit shift-register with clock-enable
+// The bit output can be controlled by the address input
+// The clock and clock-enable inputs are invertable
+//
+// *******************************
+// Revisions:
+// 0.0 Initial rev
+// *******************************
+/////////////////////////////////////////////////////////////////////////////
+
+module EFX_SRL8(D, A, CLK, CE, Q, Q7);
+   parameter CLK_POLARITY = 1'b1; // 0 falling edge, 1 rising edge
+   parameter CE_POLARITY  = 1'b1; // 0 negative, 1 positive
+   parameter INIT = 8'h00;
+
+   input [2:0] A;
+   input 	   D, CLK, CE;
+   output 	   Q;
+   output 	   Q7;
+
+   // Create nets for unused inputs
+   wire [2:0] A_net;
+   wire 	  CE_net;
+
+   // Default values for unused inptus
+   assign (weak0, weak1) A_net = 3'b1;
+   assign (weak0, weak1) CE_net = CE_POLARITY ? 1'b1 : 1'b0;
+
+   // Now assign the input
+   assign A_net = A;
+   assign CE_net = CE;
+   
+   // Internal signals
+   wire ce_int;
+   wire clk_int;
+     
+   // Check parameters and set internal signals appropriately
+   assign clk_int = CLK_POLARITY ? CLK : ~CLK;
+   assign ce_int = CE_POLARITY ? CE_net : ~CE_net;
+
+   // Shift register data
+   reg [7:0] data;
+
+   initial begin
+	  data = INIT;
+   end
+   
+   always @(posedge clk_int) begin
+	  if (ce_int) begin
+		 data <= {data[6:0], D};
+	  end
+	  else begin
+		data <= data;
+	  end
+   end
+
+   // Q points the the selected data bit
+   assign Q  = ~data[~A_net];
+   // Q7 points to the last data bit
+   assign Q7 = data[7];
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2020 Efinix Inc. All rights reserved.
+//
+// This   document  contains  proprietary information  which   is
+// protected by  copyright. All rights  are reserved.  This notice
+// refers to original work by Efinix, Inc. which may be derivitive
+// of other work distributed under license of the authors.  In the
+// case of derivative work, nothing in this notice overrides the
+// original author's license agreement.  Where applicable, the 
+// original license agreement is included in it's original 
+// unmodified form immediately below this header.
+//
+// WARRANTY DISCLAIMER.  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
+//
+// LIMITATION OF LIABILITY.  
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
+//     APPLY TO LICENSEE.
+//
+/////////////////////////////////////////////////////////////////////////////

Floatkyun_Ultra-Vision/Algorithm/sim/tb_rgb_bicubic.sv

@@ -0,0 +1,260 @@
+`timescale 100ps/100ps
+module tb_rgb_biliner;
+
+localparam src_image_width  = 640;
+localparam src_image_height = 480;
+localparam image_width_grow  = 68;
+localparam image_height_grow = 38;
+localparam num_cishu = 2;
+
+//----------------------------------------------------------------------
+// Clock and reset signals
+reg                             clk_in1;
+reg                             clk_in2;
+reg                             rst_n;
+reg          [1:0]              out_model;
+reg            [ 8:0]          bi_a;
+initial
+begin
+    clk_in1 = 1'b0;
+    forever #20 clk_in1 = ~clk_in1; // Generate clock 1
+end
+
+initial
+begin
+    bi_a = 128;
+end
+
+initial
+begin
+    clk_in2 = 1'b0;
+    forever #2 clk_in2 = ~clk_in2; // Generate clock 2
+end
+
+initial
+begin
+    out_model = 2'd2;
+end
+
+initial
+begin
+    rst_n = 1'b0;
+    repeat(50) @(posedge clk_in1); // After 50 clock cycles, set reset to 1
+    rst_n = 1'b1;
+end
+
+
+//----------------------------------------------------------------------
+// Image data prepared to be processed
+reg                             per_img_vsync;
+reg                             per_img_href;
+reg             [7:0]           per_img_red;
+reg             [7:0]           per_img_green;
+reg             [7:0]           per_img_blue;
+
+// Processed image data
+wire                            post_img_vsync;
+wire                            post_img_href;
+wire            [31:0]          post_img_data;
+
+
+wire                            post_img_vsync_pos;
+wire                            post_img_vsync_neg;
+reg                             post_img_vsync_r;
+
+assign post_img_vsync_pos = ~post_img_vsync_r & post_img_vsync; // Edge detection
+assign post_img_vsync_neg = post_img_vsync_r & ~post_img_vsync;
+
+//------------------------Custom Section-------------------------
+reg  [11:0] c_dst_img_width;
+reg  [11:0] c_dst_img_height;
+
+always @(posedge clk_in2)
+begin
+    if (rst_n == 1'b0) begin
+        c_dst_img_width  <= 27'd640; // Initialize destination image width
+        c_dst_img_height <= 27'd480; // Initialize destination image height
+    end
+    else begin
+        if (post_img_vsync_neg == 1) begin
+            c_dst_img_width = c_dst_img_width + image_width_grow; // Update width at the end of each frame
+            c_dst_img_height = c_dst_img_height + image_height_grow; // Update height at the end of each frame
+        end
+    end
+end
+//-------------------------------Custom Section End---------------------------
+
+//----------------------------------------------------------------------
+// Task and function definitions
+task image_input(input string img_file_r,input string img_file_s,input string img_file_t);
+    bit             [31:0]      row_cnt;
+    bit             [31:0]      col_cnt;
+    bit             [7:0]       red_mem[src_image_width*src_image_height-1:0];
+    bit             [7:0]       green_mem[src_image_width*src_image_height-1:0];
+    bit             [7:0]       blue_mem[src_image_width*src_image_height-1:0];
+    
+    // Read image data from file
+    $readmemh(img_file_r, red_mem); // For red channel
+    $readmemh(img_file_s, green_mem); // For green channel
+    $readmemh(img_file_t, blue_mem); // For blue channel
+    
+    @(posedge clk_in1);
+    per_img_vsync = 1'b1;
+    for (row_cnt = 0; row_cnt < src_image_height; row_cnt++) begin
+        repeat(3) @(posedge clk_in1);
+        for (col_cnt = 0; col_cnt < src_image_width; col_cnt++) begin
+            per_img_href  = 1'b1;
+            per_img_red   = red_mem[row_cnt*src_image_width + col_cnt]; 
+            per_img_green = green_mem[row_cnt*src_image_width + col_cnt];
+            per_img_blue  = blue_mem[row_cnt*src_image_width + col_cnt];
+            @(posedge clk_in1);
+        end
+        per_img_href  = 1'b0;
+    end
+    repeat(5) @(posedge clk_in1);
+    per_img_vsync = 1'b0; // Image data transmission complete
+    @(posedge clk_in1);
+endtask : image_input
+
+always @(posedge clk_in2) begin
+    if (rst_n == 1'b0)
+        post_img_vsync_r <= 1'b0;
+    else
+        post_img_vsync_r <= post_img_vsync; // Record previous frame's vertical sync signal
+end
+integer dout_file;
+task image_result_check(input string ref_file,input string out_ref_file);
+    bit frame_flag;
+    bit [31:0] row_cnt;
+    bit [31:0] col_cnt;
+    bit [31:0] ref_mem[]; 
+    
+    ref_mem = new[c_dst_img_width * c_dst_img_height]; // Allocate memory for reference image
+    frame_flag = 0;
+    dout_file=$fopen(out_ref_file);  
+    // Read reference data from file
+    $readmemh(ref_file, ref_mem); 
+    $display(ref_file);
+    $display(out_ref_file);
+    $display(dout_file);
+    
+    // Wait for the start of each frame
+    @(post_img_vsync_pos);
+    if (post_img_vsync_pos == 1'b1) begin
+        frame_flag = 1;
+        row_cnt = 0;
+        col_cnt = 0;
+        $display("############## Image result check begin ##############");
+        $display ($time);
+    end
+
+    
+    while (frame_flag) begin
+        @(posedge clk_in2);
+        if (post_img_href == 1'b1) begin
+            $fwrite(dout_file,"%h ",post_img_data);
+            if ({{post_img_data[23:20]},{post_img_data[15:12]},{post_img_data[7:4]}} != {{ref_mem[row_cnt * c_dst_img_width + col_cnt][23:20]},{ref_mem[row_cnt * c_dst_img_width + col_cnt][15:12]},{ref_mem[row_cnt * c_dst_img_width + col_cnt][7:4]}}) begin
+                $display("Result error ---> Row: %0d; Col: %0d; Pixel data: %h; Reference data: %h", row_cnt + 1, col_cnt + 1, post_img_data, ref_mem[row_cnt * c_dst_img_width + col_cnt]);
+                //$display("%0d",{{ref_mem[row_cnt * c_dst_img_width + col_cnt][23:20]},{ref_mem[row_cnt * c_dst_img_width + col_cnt][15:12]},{ref_mem[row_cnt * c_dst_img_width + col_cnt][7:4]}});
+            end
+            col_cnt = col_cnt + 1;
+        end
+        
+        if (col_cnt == c_dst_img_width) begin
+            $fwrite(dout_file,"\n");
+            col_cnt = 0;
+            row_cnt = row_cnt + 1; // Move to the next row
+        end
+        
+        if (post_img_vsync_neg == 1'b1) begin
+            frame_flag = 0;
+            $display("############## Image result check end ##############");
+            $display ($time);
+            $fclose(dout_file);
+        end
+    end
+endtask : image_result_check
+
+//----------------------------------------------------------------------
+// Instantiate the rgb_biliner module
+rgb_bicubic
+#(
+    .C_SRC_IMG_WIDTH (src_image_width),
+    .C_SRC_IMG_HEIGHT(src_image_height)
+)
+u_rgb_bicubic
+(
+    .clk_in1        (clk_in1        ),
+    .clk_in2        (clk_in2        ),
+    .rst_n          (rst_n          ),
+    .out_model      (out_model      ),
+    
+    // Image data prepared to be processed
+    .per_img_vsync  (per_img_vsync  ),
+    .per_img_href   (per_img_href   ),
+    .per_img_red    (per_img_red    ),
+    .per_img_green  (per_img_green  ),
+    .per_img_blue   (per_img_blue   ),
+    
+    // Processed image data
+    .post_img_vsync (post_img_vsync ),
+    .post_img_href  (post_img_href  ),
+    .post_img_data  (post_img_data  ),
+    .c_dst_img_width(c_dst_img_width),
+    .c_dst_img_height(c_dst_img_height),
+    .bi_a(bi_a)
+);
+
+initial
+begin
+    per_img_vsync = 0;
+    per_img_href  = 0;
+    per_img_red   = 0;
+    per_img_green = 0;
+    per_img_blue  = 0;
+end
+
+initial 
+begin 
+    string img_file_r = "F:/FPAG_comp/bicube_test/rgb_bicubic4/matlab_test/bicubic_img_datas/img_640_r.dat";
+    string img_file_s = "F:/FPAG_comp/bicube_test/rgb_bicubic4/matlab_test/bicubic_img_datas/img_640_s.dat";
+    string img_file_t = "F:/FPAG_comp/bicube_test/rgb_bicubic4/matlab_test/bicubic_img_datas/img_640_t.dat";
+
+    wait(rst_n);
+    for (int i = 0; i < num_cishu; i++) begin
+        image_input(img_file_r,img_file_s,img_file_t); // Input the image
+       // repeat(400) @(posedge clk_in1); 
+    end
+end 
+
+
+initial 
+begin
+    string ref_file_prefix = "F:/FPAG_comp/bicube_test/rgb_bicubic4/matlab_test/bicubic_img_datas/img_"; // Reference file prefix
+    string ref_files[num_cishu]; // Assume a maximum of 11 reference files
+    int ref_file_count = 0;
+    string ref_file;
+    string out_ref_prefix = "F:/FPAG_comp/bicube_test/rgb_bicubic4/matlab_test/bicubic_img_datas/out_img_";
+    string out_ref_files[num_cishu];
+    string out_ref_file;
+    // Loop to read each .dat file in the folder as reference files
+    for (int i = 0; i < num_cishu; i++) begin
+        // Generate filename based on naming convention without spaces
+        ref_file = {ref_file_prefix, $sformatf("%0d_%0d.dat", i*image_width_grow+src_image_width,i*image_height_grow+src_image_height)}; 
+        out_ref_file ={out_ref_prefix ,$sformatf("%0d_%0d.dat", i*image_width_grow+src_image_width,i*image_height_grow+src_image_height)};
+        // Check if the file can be opened
+        if ($fopen(ref_file, "r") != 0&&$fopen(out_ref_file, "r") != 0) begin
+            ref_files[ref_file_count] = ref_file; // Store valid filenames
+            out_ref_files[ref_file_count]=out_ref_file;
+            ref_file_count++;
+        end
+    end
+
+    wait(rst_n);
+    for (int i = 0; i < num_cishu; i++) begin
+        image_result_check(ref_files[i],out_ref_files[i]); // Check results
+    end
+end
+
+
+endmodule

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/Ti60_Demo.pt.sdc

@@ -0,0 +1,356 @@
+
+# Auto-generated by Interface Designer
+#
+# WARNING: Any manual changes made to this file will be lost when generating constraints.
+
+# Efinity Interface Designer SDC
+# Version: 2023.2.307.5.10
+# Date: 2024-10-08 21:23
+
+# Copyright (C) 2013 - 2023 Efinix Inc. All rights reserved.
+
+# Device: Ti60F225
+# Project: Ti60_Demo
+# Timing Model: C4 (final)
+
+# PLL Constraints
+#################
+create_clock -period 2.3148 tdqss_clk
+create_clock -period 4.6296 core_clk
+create_clock -period 2.3148 tac_clk
+create_clock -waveform {0.5787 1.7361} -period 2.3148 twd_clk
+create_clock -period 5.2083 ddr_pll_CLKOUT4
+create_clock -period 40.0000 clk_sys
+create_clock -period 6.6667 clk_pixel_2x
+create_clock -period 5.0000 clk_pixel
+create_clock -waveform {0.3333 1.0000} -period 1.3333 clk_pixel_10x
+create_clock -period 10.4167 clk_96m
+create_clock -period 50.0000 clk_20m
+
+# GPIO Constraints
+####################
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_rxd_1}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_rxd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_txd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_txd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[0]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[0]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[1]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[1]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[2]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[2]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[3]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[3]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[4]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[4]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[5]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[5]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[6]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[6]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {led_o[7]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {led_o[7]}]
+
+# HSIO GPIO Constraints
+#########################
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_rxd_0}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_rxd_0}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[0]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[0]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[1]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[1]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[2]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[2]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[3]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[3]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[4]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[4]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[5]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[5]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[6]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[6]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[7]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[7]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[8]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[8]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[9]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[9]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[10]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[10]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[11]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[11]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[12]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[12]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[13]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[13]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[14]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[14]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[15]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[15]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[16]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[16]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[17]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[17]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[18]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[18]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[19]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[19]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[20]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[20]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[21]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[21]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[22]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[22]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_data_i[23]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_data_i[23]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_de_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_de_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_hs_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_hs_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_pclk_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_pclk_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_vs_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_vs_i}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~95}] -max 0.263 [get_ports {addr[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~95}] -min -0.140 [get_ports {addr[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~36}] -max 0.263 [get_ports {addr[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~36}] -min -0.140 [get_ports {addr[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~70}] -max 0.263 [get_ports {addr[2]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~70}] -min -0.140 [get_ports {addr[2]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~50~1}] -max 0.263 [get_ports {addr[3]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~50~1}] -min -0.140 [get_ports {addr[3]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~25}] -max 0.263 [get_ports {addr[4]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~25}] -min -0.140 [get_ports {addr[4]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~142~1}] -max 0.263 [get_ports {addr[5]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~142~1}] -min -0.140 [get_ports {addr[5]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~59}] -max 0.263 [get_ports {addr[6]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~59}] -min -0.140 [get_ports {addr[6]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~110}] -max 0.263 [get_ports {addr[7]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~110}] -min -0.140 [get_ports {addr[7]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~26}] -max 0.263 [get_ports {addr[8]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~26}] -min -0.140 [get_ports {addr[8]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~127}] -max 0.263 [get_ports {addr[9]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~127}] -min -0.140 [get_ports {addr[9]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~138}] -max 0.263 [get_ports {addr[10]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~138}] -min -0.140 [get_ports {addr[10]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~60}] -max 0.263 [get_ports {addr[11]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~60}] -min -0.140 [get_ports {addr[11]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~35}] -max 0.263 [get_ports {addr[12]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~35}] -min -0.140 [get_ports {addr[12]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~71}] -max 0.263 [get_ports {addr[13]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~71}] -min -0.140 [get_ports {addr[13]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~109}] -max 0.263 [get_ports {addr[14]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~109}] -min -0.140 [get_ports {addr[14]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~143~1}] -max 0.263 [get_ports {addr[15]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~143~1}] -min -0.140 [get_ports {addr[15]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {adv7611_rstn}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {adv7611_rstn}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~74~1}] -max 0.263 [get_ports {ba[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~74~1}] -min -0.140 [get_ports {ba[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~132~1}] -max 0.263 [get_ports {ba[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~132~1}] -min -0.140 [get_ports {ba[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~126}] -max 0.263 [get_ports {ba[2]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~126}] -min -0.140 [get_ports {ba[2]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~49}] -max 0.263 [get_ports {cas}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~49}] -min -0.140 [get_ports {cas}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~123~1}] -max 0.263 [get_ports {cke}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~123~1}] -min -0.140 [get_ports {cke}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~150}] -max 0.263 [get_ports {clk_n_lo clk_n_hi}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~150}] -min -0.140 [get_ports {clk_n_lo clk_n_hi}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~149}] -max 0.263 [get_ports {clk_p_lo clk_p_hi}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~149}] -min -0.140 [get_ports {clk_p_lo clk_p_hi}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~95~1}] -max 0.263 [get_ports {cs}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~95~1}] -min -0.140 [get_ports {cs}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~131~1}] -max 0.263 [get_ports {o_dm_lo[0] o_dm_hi[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~131~1}] -min -0.140 [get_ports {o_dm_lo[0] o_dm_hi[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~83~1}] -max 0.263 [get_ports {o_dm_lo[1] o_dm_hi[1]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~83~1}] -min -0.140 [get_ports {o_dm_lo[1] o_dm_hi[1]}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_txd_0}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_txd_0}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_scl_io}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_scl_io}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~73~1}] -max 0.263 [get_ports {odt}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~73~1}] -min -0.140 [get_ports {odt}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~48}] -max 0.263 [get_ports {ras}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~48}] -min -0.140 [get_ports {ras}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~139}] -max 0.263 [get_ports {reset}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~139}] -min -0.140 [get_ports {reset}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~94}] -max 0.263 [get_ports {we}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~218~94}] -min -0.140 [get_ports {we}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~148~1}] -max 0.414 [get_ports {i_dq_lo[0] i_dq_hi[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~148~1}] -min 0.276 [get_ports {i_dq_lo[0] i_dq_hi[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -max 0.263 [get_ports {o_dq_lo[0] o_dq_hi[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -min -0.140 [get_ports {o_dq_lo[0] o_dq_hi[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -max 0.263 [get_ports {o_dq_oe[0]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~150~1}] -min -0.140 [get_ports {o_dq_oe[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~157~1}] -max 0.414 [get_ports {i_dq_lo[1] i_dq_hi[1]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~157~1}] -min 0.276 [get_ports {i_dq_lo[1] i_dq_hi[1]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -max 0.263 [get_ports {o_dq_lo[1] o_dq_hi[1]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -min -0.140 [get_ports {o_dq_lo[1] o_dq_hi[1]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -max 0.263 [get_ports {o_dq_oe[1]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~159~1}] -min -0.140 [get_ports {o_dq_oe[1]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~164~1}] -max 0.414 [get_ports {i_dq_lo[2] i_dq_hi[2]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~164~1}] -min 0.276 [get_ports {i_dq_lo[2] i_dq_hi[2]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -max 0.263 [get_ports {o_dq_lo[2] o_dq_hi[2]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -min -0.140 [get_ports {o_dq_lo[2] o_dq_hi[2]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -max 0.263 [get_ports {o_dq_oe[2]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~166~1}] -min -0.140 [get_ports {o_dq_oe[2]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~149~1}] -max 0.414 [get_ports {i_dq_lo[3] i_dq_hi[3]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~149~1}] -min 0.276 [get_ports {i_dq_lo[3] i_dq_hi[3]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -max 0.263 [get_ports {o_dq_lo[3] o_dq_hi[3]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -min -0.140 [get_ports {o_dq_lo[3] o_dq_hi[3]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -max 0.263 [get_ports {o_dq_oe[3]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~151~1}] -min -0.140 [get_ports {o_dq_oe[3]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~189~1}] -max 0.414 [get_ports {i_dq_lo[4] i_dq_hi[4]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~189~1}] -min 0.276 [get_ports {i_dq_lo[4] i_dq_hi[4]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -max 0.263 [get_ports {o_dq_lo[4] o_dq_hi[4]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -min -0.140 [get_ports {o_dq_lo[4] o_dq_hi[4]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -max 0.263 [get_ports {o_dq_oe[4]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~191~1}] -min -0.140 [get_ports {o_dq_oe[4]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~156~1}] -max 0.414 [get_ports {i_dq_lo[5] i_dq_hi[5]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~156~1}] -min 0.276 [get_ports {i_dq_lo[5] i_dq_hi[5]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -max 0.263 [get_ports {o_dq_lo[5] o_dq_hi[5]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -min -0.140 [get_ports {o_dq_lo[5] o_dq_hi[5]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -max 0.263 [get_ports {o_dq_oe[5]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~158~1}] -min -0.140 [get_ports {o_dq_oe[5]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~165~1}] -max 0.414 [get_ports {i_dq_lo[6] i_dq_hi[6]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~165~1}] -min 0.276 [get_ports {i_dq_lo[6] i_dq_hi[6]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -max 0.263 [get_ports {o_dq_lo[6] o_dq_hi[6]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -min -0.140 [get_ports {o_dq_lo[6] o_dq_hi[6]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -max 0.263 [get_ports {o_dq_oe[6]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~167~1}] -min -0.140 [get_ports {o_dq_oe[6]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~188~1}] -max 0.414 [get_ports {i_dq_lo[7] i_dq_hi[7]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~188~1}] -min 0.276 [get_ports {i_dq_lo[7] i_dq_hi[7]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -max 0.263 [get_ports {o_dq_lo[7] o_dq_hi[7]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -min -0.140 [get_ports {o_dq_lo[7] o_dq_hi[7]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -max 0.263 [get_ports {o_dq_oe[7]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~190~1}] -min -0.140 [get_ports {o_dq_oe[7]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~82~1}] -max 0.414 [get_ports {i_dq_lo[8] i_dq_hi[8]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~82~1}] -min 0.276 [get_ports {i_dq_lo[8] i_dq_hi[8]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -max 0.263 [get_ports {o_dq_lo[8] o_dq_hi[8]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -min -0.140 [get_ports {o_dq_lo[8] o_dq_hi[8]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -max 0.263 [get_ports {o_dq_oe[8]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~84~1}] -min -0.140 [get_ports {o_dq_oe[8]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~39~1}] -max 0.414 [get_ports {i_dq_lo[9] i_dq_hi[9]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~39~1}] -min 0.276 [get_ports {i_dq_lo[9] i_dq_hi[9]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -max 0.263 [get_ports {o_dq_lo[9] o_dq_hi[9]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -min -0.140 [get_ports {o_dq_lo[9] o_dq_hi[9]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -max 0.263 [get_ports {o_dq_oe[9]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~41~1}] -min -0.140 [get_ports {o_dq_oe[9]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~22~1}] -max 0.414 [get_ports {i_dq_lo[10] i_dq_hi[10]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~22~1}] -min 0.276 [get_ports {i_dq_lo[10] i_dq_hi[10]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -max 0.263 [get_ports {o_dq_lo[10] o_dq_hi[10]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -min -0.140 [get_ports {o_dq_lo[10] o_dq_hi[10]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -max 0.263 [get_ports {o_dq_oe[10]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~24~1}] -min -0.140 [get_ports {o_dq_oe[10]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~92~1}] -max 0.414 [get_ports {i_dq_lo[11] i_dq_hi[11]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~92~1}] -min 0.276 [get_ports {i_dq_lo[11] i_dq_hi[11]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -max 0.263 [get_ports {o_dq_lo[11] o_dq_hi[11]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -min -0.140 [get_ports {o_dq_lo[11] o_dq_hi[11]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -max 0.263 [get_ports {o_dq_oe[11]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~94~1}] -min -0.140 [get_ports {o_dq_oe[11]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~23~1}] -max 0.414 [get_ports {i_dq_lo[12] i_dq_hi[12]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~23~1}] -min 0.276 [get_ports {i_dq_lo[12] i_dq_hi[12]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -max 0.263 [get_ports {o_dq_lo[12] o_dq_hi[12]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -min -0.140 [get_ports {o_dq_lo[12] o_dq_hi[12]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -max 0.263 [get_ports {o_dq_oe[12]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~25~1}] -min -0.140 [get_ports {o_dq_oe[12]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~38~1}] -max 0.414 [get_ports {i_dq_lo[13] i_dq_hi[13]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~38~1}] -min 0.276 [get_ports {i_dq_lo[13] i_dq_hi[13]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -max 0.263 [get_ports {o_dq_lo[13] o_dq_hi[13]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -min -0.140 [get_ports {o_dq_lo[13] o_dq_hi[13]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -max 0.263 [get_ports {o_dq_oe[13]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~40~1}] -min -0.140 [get_ports {o_dq_oe[13]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~11~1}] -max 0.414 [get_ports {i_dq_lo[14] i_dq_hi[14]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~11~1}] -min 0.276 [get_ports {i_dq_lo[14] i_dq_hi[14]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -max 0.263 [get_ports {o_dq_lo[14] o_dq_hi[14]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -min -0.140 [get_ports {o_dq_lo[14] o_dq_hi[14]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -max 0.263 [get_ports {o_dq_oe[14]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~13~1}] -min -0.140 [get_ports {o_dq_oe[14]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~12~1}] -max 0.414 [get_ports {i_dq_lo[15] i_dq_hi[15]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~12~1}] -min 0.276 [get_ports {i_dq_lo[15] i_dq_hi[15]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -max 0.263 [get_ports {o_dq_lo[15] o_dq_hi[15]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -min -0.140 [get_ports {o_dq_lo[15] o_dq_hi[15]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -max 0.263 [get_ports {o_dq_oe[15]}]
+set_output_delay -clock twd_clk -reference_pin [get_ports {twd_clk~CLKOUT~14~1}] -min -0.140 [get_ports {o_dq_oe[15]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~172~1}] -max 0.414 [get_ports {i_dqs_lo[0] i_dqs_hi[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~172~1}] -min 0.276 [get_ports {i_dqs_lo[0] i_dqs_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -max 0.263 [get_ports {o_dqs_lo[0] o_dqs_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -min -0.140 [get_ports {o_dqs_lo[0] o_dqs_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -max 0.263 [get_ports {o_dqs_oe[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~174~1}] -min -0.140 [get_ports {o_dqs_oe[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~30~1}] -max 0.414 [get_ports {i_dqs_lo[1] i_dqs_hi[1]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~30~1}] -min 0.276 [get_ports {i_dqs_lo[1] i_dqs_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -max 0.263 [get_ports {o_dqs_lo[1] o_dqs_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -min -0.140 [get_ports {o_dqs_lo[1] o_dqs_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -max 0.263 [get_ports {o_dqs_oe[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~32~1}] -min -0.140 [get_ports {o_dqs_oe[1]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~173~1}] -max 0.414 [get_ports {i_dqs_n_lo[0] i_dqs_n_hi[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~173~1}] -min 0.276 [get_ports {i_dqs_n_lo[0] i_dqs_n_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -max 0.263 [get_ports {o_dqs_n_lo[0] o_dqs_n_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -min -0.140 [get_ports {o_dqs_n_lo[0] o_dqs_n_hi[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -max 0.263 [get_ports {o_dqs_n_oe[0]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~175~1}] -min -0.140 [get_ports {o_dqs_n_oe[0]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~31~1}] -max 0.414 [get_ports {i_dqs_n_lo[1] i_dqs_n_hi[1]}]
+set_input_delay -clock tac_clk -reference_pin [get_ports {tac_clk~CLKOUT~31~1}] -min 0.276 [get_ports {i_dqs_n_lo[1] i_dqs_n_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -max 0.263 [get_ports {o_dqs_n_lo[1] o_dqs_n_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -min -0.140 [get_ports {o_dqs_n_lo[1] o_dqs_n_hi[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -max 0.263 [get_ports {o_dqs_n_oe[1]}]
+set_output_delay -clock tdqss_clk -reference_pin [get_ports {tdqss_clk~CLKOUT~33~1}] -min -0.140 [get_ports {o_dqs_n_oe[1]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_IN}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_IN}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_OUT}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_OUT}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_OE}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_OE}]
+
+# LVDS Tx Constraints
+#######################
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.378 [get_ports {hdmi_txc_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.140 [get_ports {hdmi_txc_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.378 [get_ports {hdmi_txc_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.140 [get_ports {hdmi_txc_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.378 [get_ports {hdmi_txd0_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.140 [get_ports {hdmi_txd0_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.378 [get_ports {hdmi_txd0_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.140 [get_ports {hdmi_txd0_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.378 [get_ports {hdmi_txd1_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.140 [get_ports {hdmi_txd1_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.378 [get_ports {hdmi_txd1_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.140 [get_ports {hdmi_txd1_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.378 [get_ports {hdmi_txd2_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.140 [get_ports {hdmi_txd2_o[*]}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.378 [get_ports {hdmi_txd2_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.140 [get_ports {hdmi_txd2_oe}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -max 0.420 [get_ports {hdmi_txc_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~63~322}] -min -0.175 [get_ports {hdmi_txc_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -max 0.420 [get_ports {hdmi_txd0_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~195~322}] -min -0.175 [get_ports {hdmi_txd0_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -max 0.420 [get_ports {hdmi_txd1_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~31~322}] -min -0.175 [get_ports {hdmi_txd1_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -max 0.420 [get_ports {hdmi_txd2_rst_o}]
+set_output_delay -clock clk_pixel_2x -reference_pin [get_ports {clk_pixel_2x~CLKOUT~55~322}] -min -0.175 [get_ports {hdmi_txd2_rst_o}]
+
+# Clock Latency Constraints
+############################
+# set_clock_latency -source -setup <pll_clk_latency_clk_96m_max + 0.507> [get_ports {tdqss_clk}]
+# set_clock_latency -source -hold <pll_clk_latency_clk_96m_min + 0.328> [get_ports {tdqss_clk}]
+# set_clock_latency -source -setup <pll_clk_latency_clk_96m_max + 0.507> [get_ports {core_clk}]
+# set_clock_latency -source -hold <pll_clk_latency_clk_96m_min + 0.328> [get_ports {core_clk}]
+# set_clock_latency -source -setup <pll_clk_latency_clk_96m_max + 0.507> [get_ports {tac_clk}]
+# set_clock_latency -source -hold <pll_clk_latency_clk_96m_min + 0.328> [get_ports {tac_clk}]
+# set_clock_latency -source -setup <pll_clk_latency_clk_96m_max + 0.507> [get_ports {twd_clk}]
+# set_clock_latency -source -hold <pll_clk_latency_clk_96m_min + 0.328> [get_ports {twd_clk}]
+# set_clock_latency -source -setup <pll_clk_latency_clk_96m_max + 0.507> [get_ports {ddr_pll_CLKOUT4}]
+# set_clock_latency -source -hold <pll_clk_latency_clk_96m_min + 0.328> [get_ports {ddr_pll_CLKOUT4}]
+# set_clock_latency -source -setup <board_max + 0.019> [get_ports {clk_sys}]
+# set_clock_latency -source -hold <board_min + 0.049> [get_ports {clk_sys}]
+# set_clock_latency -source -setup <board_max + 0.019> [get_ports {clk_pixel_2x}]
+# set_clock_latency -source -hold <board_min + 0.049> [get_ports {clk_pixel_2x}]
+# set_clock_latency -source -setup <board_max + 0.019> [get_ports {clk_pixel}]
+# set_clock_latency -source -hold <board_min + 0.049> [get_ports {clk_pixel}]
+# set_clock_latency -source -setup <board_max + 0.019> [get_ports {clk_pixel_10x}]
+# set_clock_latency -source -hold <board_min + 0.049> [get_ports {clk_pixel_10x}]
+# set_clock_latency -source -setup <board_max + 1.907> [get_ports {clk_96m}]
+# set_clock_latency -source -hold <board_min + 1.271> [get_ports {clk_96m}]
+# set_clock_latency -source -setup <board_max + 1.907> [get_ports {clk_20m}]
+# set_clock_latency -source -hold <board_min + 1.271> [get_ports {clk_20m}]

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/Bilinear_interpolation_prj.sdc

@@ -0,0 +1,113 @@
+
+# Auto-generated by Interface Designer
+#
+# WARNING: Any manual changes made to this file will be lost when generating constraints.
+
+# Efinity Interface Designer SDC
+# Version: 2023.2.307
+# Date: 2024-10-07 15:18
+
+# Copyright (C) 2013 - 2023 Efinix Inc. All rights reserved.
+
+# Device: Ti60F225
+# Project: Bilinear_interpolation_prj
+# Timing Model: I3 (final)
+
+# PLL Constraints
+#################
+create_clock -period 10.4167 sys_clk_96M
+create_clock -period 5.9524 biliner_clk_out
+create_clock -period 62.5000 biliner_clk_in
+
+# GPIO Constraints
+####################
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_rxd_1}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_rxd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_txd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_txd_1}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {post_img_href}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {post_img_href}]
+
+# HSIO GPIO Constraints
+#########################
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_rxd_0}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_rxd_0}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_hsync_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_hsync_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_pix_clk_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_pix_clk_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_pix_en_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_pix_en_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[0]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[0]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[1]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[1]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[2]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[2]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[3]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[3]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[4]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[4]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[5]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[5]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[6]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[6]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[7]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[7]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[8]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[8]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[9]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[9]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[10]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[10]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[11]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[11]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[12]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[12]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[13]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[13]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[14]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[14]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[15]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[15]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[16]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[16]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[17]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[17]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[18]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[18]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[19]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[19]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[20]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[20]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[21]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[21]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[22]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[22]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_RGB_data_i[23]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_RGB_data_i[23]}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_vsync_i}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_vsync_i}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {adv7611_rstn}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {adv7611_rstn}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {fpga_txd_0}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {fpga_txd_0}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_scl_o}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_scl_o}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {post_img_vsync}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {post_img_vsync}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_IN}]
+# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_IN}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_OUT}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_OUT}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {hdmi_sda_io_OE}]
+# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {hdmi_sda_io_OE}]
+
+# Clock Latency Constraints
+############################
+# set_clock_latency -source -setup <board_max + 1.354> [get_ports {sys_clk_96M}]
+# set_clock_latency -source -hold <board_min + 0.785> [get_ports {sys_clk_96M}]
+# set_clock_latency -source -setup <board_max + 1.354> [get_ports {biliner_clk_out}]
+# set_clock_latency -source -hold <board_min + 0.785> [get_ports {biliner_clk_out}]
+# set_clock_latency -source -setup <board_max + 1.354> [get_ports {biliner_clk_in}]
+# set_clock_latency -source -hold <board_min + 0.785> [get_ports {biliner_clk_in}]

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/T20F256_devkit/asyn_fifo.v

@@ -0,0 +1,1377 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define IP_UUID _af32f278b05841e694433ae28c490f52
+`define IP_NAME_CONCAT(a,b) a``b
+`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
+module asyn_fifo (
+output almost_full_o,
+output prog_full_o,
+output full_o,
+output overflow_o,
+output wr_ack_o,
+output empty_o,
+output almost_empty_o,
+output underflow_o,
+output rd_valid_o,
+input wr_clk_i,
+input rd_clk_i,
+input wr_en_i,
+input rd_en_i,
+input [10:0] wdata,
+output [12:0] wr_datacount_o,
+output rst_busy,
+output [10:0] rdata,
+output [12:0] rd_datacount_o,
+input a_rst_i
+);
+`IP_MODULE_NAME(efx_fifo_top) #(
+.SYNC_CLK (0),
+.SYNC_STAGE (2),
+.DATA_WIDTH (11),
+.MODE ("FWFT"),
+.OUTPUT_REG (0),
+.PROG_FULL_ASSERT (128),
+.PROGRAMMABLE_FULL ("STATIC_SINGLE"),
+.PROG_FULL_NEGATE (128),
+.PROGRAMMABLE_EMPTY ("NONE"),
+.PROG_EMPTY_ASSERT (0),
+.PROG_EMPTY_NEGATE (2),
+.OPTIONAL_FLAGS (1),
+.PIPELINE_REG (1),
+.DEPTH (8192),
+.FAMILY ("TITANIUM"),
+.ASYM_WIDTH_RATIO (4),
+.BYPASS_RESET_SYNC (0),
+.ENDIANESS (0)
+) u_efx_fifo_top(
+.almost_full_o ( almost_full_o ),
+.prog_full_o ( prog_full_o ),
+.full_o ( full_o ),
+.overflow_o ( overflow_o ),
+.wr_ack_o ( wr_ack_o ),
+.empty_o ( empty_o ),
+.almost_empty_o ( almost_empty_o ),
+.underflow_o ( underflow_o ),
+.rd_valid_o ( rd_valid_o ),
+.wr_clk_i ( wr_clk_i ),
+.rd_clk_i ( rd_clk_i ),
+.wr_en_i ( wr_en_i ),
+.rd_en_i ( rd_en_i ),
+.wdata ( wdata ),
+.wr_datacount_o ( wr_datacount_o ),
+.rst_busy ( rst_busy ),
+.rdata ( rdata ),
+.rd_datacount_o ( rd_datacount_o ),
+.a_rst_i ( a_rst_i )
+);
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   pipe_reg.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Parallel Pipelining Shift Register
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_datasync) #(
+    parameter STAGE = 32,
+    parameter WIDTH = 4
+) (
+ input  wire             clk_i,
+ input  wire [WIDTH-1:0] d_i,
+ output wire [WIDTH-1:0] d_o
+);
+
+(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
+integer i;
+
+always @(posedge clk_i) begin
+  for (i=STAGE-1; i>0; i = i - 1) begin
+    pipe_reg[i] <= pipe_reg[i-1];
+  end
+  pipe_reg[0] <= d_i;
+end
+assign d_o = pipe_reg[STAGE-1];
+   
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   gray2bin.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Gray to Binary Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_gray2bin)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] bin_o,
+ // input
+ input [WIDTH-1:0] gray_i);
+
+//---------------------------------------------------------------------
+// Recursive Module
+// Description: reduction xor
+generate
+   if (WIDTH > 1) begin
+      wire [1:0] bin_1;
+      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
+      if (WIDTH == 2) begin
+	 assign bin_o = bin_1;
+      end
+      else begin
+	 assign bin_o[WIDTH-1] = bin_1[1];
+	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
+      end
+   end
+   else /* if (WIDTH == 1) */
+     assign bin_o = gray_i;
+endgenerate
+   
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   bin2gray.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Binary to Gray Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_bin2gray)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] gray_o,
+ // input
+ input [WIDTH-1:0] bin_i
+ );
+
+//---------------------------------------------------------------------
+// Function :   bit_xor
+// Description: reduction xor
+function bit_xor (
+  input [31:0] nex_bit,
+  input [31:0] curr_bit,
+  input [WIDTH-1:0] xor_in);
+  begin : fn_bit_xor
+    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
+  end
+endfunction
+
+// Convert Binary to Gray, bit by bit
+generate 
+begin
+  genvar bit_idx;
+  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
+    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
+  end
+  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
+end
+endgenerate
+
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_top) # (
+    parameter FAMILY             = "TRION",       // New Param
+    parameter SYNC_CLK           = 0,
+    parameter BYPASS_RESET_SYNC  = 0,             // New Param
+    parameter SYNC_STAGE         = 2,             // New Param
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
+    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
+    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
+    parameter OPTIONAL_FLAGS     = 1,             // Reverted
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_FULL_ASSERT   = 27,
+    parameter PROG_FULL_NEGATE   = 23,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_EMPTY_ASSERT  = 5,
+    parameter PROG_EMPTY_NEGATE  = 7,
+    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
+    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter WADDR_WIDTH        = depth2width(DEPTH),
+    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
+    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
+    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
+    parameter ENDIANESS		 = 0
+
+)(
+    input  wire                   a_rst_i,
+    input  wire                   a_wr_rst_i,
+    input  wire                   a_rd_rst_i,
+    input  wire                   clk_i,
+    input  wire                   wr_clk_i,
+    input  wire                   rd_clk_i,
+    input  wire                   wr_en_i,
+    input  wire                   rd_en_i,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+    output wire                   almost_full_o,
+    output wire                   prog_full_o,
+    output wire                   full_o,
+    output wire                   overflow_o,
+    output wire                   wr_ack_o,
+    output wire [WADDR_WIDTH :0]  datacount_o,
+    output wire [WADDR_WIDTH :0]  wr_datacount_o,
+    output wire                   empty_o,
+    output wire                   almost_empty_o,
+    output wire                   prog_empty_o,
+    output wire                   underflow_o,
+    output wire                   rd_valid_o,
+    output wire [RDATA_WIDTH-1:0] rdata,
+    output wire [RADDR_WIDTH :0]  rd_datacount_o,
+    output wire                   rst_busy
+); 
+
+localparam WR_DEPTH      = DEPTH;
+localparam WDATA_WIDTH   = DATA_WIDTH;
+localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           
+
+wire                   wr_rst_int;
+wire                   rd_rst_int;
+wire                   wr_en_int;
+wire                   rd_en_int;
+wire [WADDR_WIDTH-1:0] waddr;
+wire [RADDR_WIDTH-1:0] raddr;
+wire                   wr_clk_int;
+wire                   rd_clk_int;
+wire [WADDR_WIDTH :0]  wr_datacount_int;
+wire [RADDR_WIDTH :0]  rd_datacount_int;
+
+generate
+    if (ASYM_WIDTH_RATIO == 4) begin
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+            assign datacount_o    = wr_datacount_int;
+            assign wr_datacount_o = 'd0;
+            assign rd_datacount_o = 'd0;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+            assign datacount_o    = 'd0;
+            assign wr_datacount_o = wr_datacount_int;
+            assign rd_datacount_o = rd_datacount_int;
+        end
+    end
+    else begin
+        assign datacount_o    = 'd0;
+        assign wr_datacount_o = wr_datacount_int;
+        assign rd_datacount_o = rd_datacount_int;
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+        end
+    end    
+
+    if (!SYNC_CLK) begin
+        (* async_reg = "true" *) reg [1:0] wr_rst;
+        (* async_reg = "true" *) reg [1:0] rd_rst;
+        
+        always @ (posedge wr_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                wr_rst <= 2'b11;
+            else 
+                wr_rst <= {wr_rst[0],1'b0};            
+        end
+        
+        always @ (posedge rd_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                rd_rst <= 2'b11;
+            else 
+                rd_rst <= {rd_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_wr_rst_i;
+            assign rd_rst_int = a_rd_rst_i; 
+            assign rst_busy   = 1'b0;
+        end 
+        else begin
+            assign wr_rst_int = wr_rst[1];
+            assign rd_rst_int = rd_rst[1]; 
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end
+    else begin
+        (* async_reg = "true" *) reg [1:0] a_rst;
+        
+        always @ (posedge clk_i or posedge a_rst_i) begin
+            if (a_rst_i) 
+                a_rst <= 2'b11;
+            else 
+                a_rst <= {a_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_rst_i;
+            assign rd_rst_int = a_rst_i;
+            assign rst_busy   = 1'b0;
+        end
+        else begin
+            assign wr_rst_int = a_rst[1];
+            assign rd_rst_int = a_rst[1];   
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end 
+endgenerate
+
+`IP_MODULE_NAME(efx_fifo_ram) # (
+    .FAMILY        (FAMILY),
+    .MODE          (MODE),
+    .WR_DEPTH      (WR_DEPTH),
+    .RD_DEPTH      (RD_DEPTH),
+    .WDATA_WIDTH   (WDATA_WIDTH),
+    .RDATA_WIDTH   (RDATA_WIDTH),
+    .WADDR_WIDTH   (WADDR_WIDTH),
+    .RADDR_WIDTH   (RADDR_WIDTH),
+    .OUTPUT_REG    (OUTPUT_REG),
+    .RAM_MUX_RATIO (RAM_MUX_RATIO),
+    .ENDIANESS	   (ENDIANESS)
+) xefx_fifo_ram (
+    .wdata (wdata), 
+    .waddr (waddr),
+    .raddr (raddr), 
+    .we    (wr_en_int), 
+    .re    (rd_en_int),
+    .wclk  (wr_clk_int),
+    .rclk  (rd_clk_int),
+    .rdata (rdata)
+);
+
+`IP_MODULE_NAME(efx_fifo_ctl) # (
+    .FAMILY             (FAMILY),
+    .SYNC_CLK           (SYNC_CLK),
+    .SYNC_STAGE         (SYNC_STAGE),
+    .MODE               (MODE),
+    .WR_DEPTH           (WR_DEPTH),
+    .WADDR_WIDTH        (WADDR_WIDTH),
+    .RADDR_WIDTH        (RADDR_WIDTH),
+    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
+    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .ALMOST_FLAG        (ALMOST_FLAG),
+    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
+    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
+    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
+    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
+    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
+    .OUTPUT_REG         (OUTPUT_REG),
+    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG)
+) xefx_fifo_ctl (
+    .wr_rst          (wr_rst_int),
+    .rd_rst          (rd_rst_int),
+    .wclk            (wr_clk_int),
+    .rclk            (rd_clk_int),
+    .we              (wr_en_i),
+    .re              (rd_en_i),
+    .wr_full         (full_o),
+    .wr_ack          (wr_ack_o),
+    .rd_empty        (empty_o),
+    .wr_almost_full  (almost_full_o),
+    .rd_almost_empty (almost_empty_o),
+    .wr_prog_full    (prog_full_o),
+    .rd_prog_empty   (prog_empty_o),
+    .wr_en_int       (wr_en_int),
+    .rd_en_int       (rd_en_int),
+    .waddr           (waddr),
+    .raddr           (raddr),
+    .wr_datacount    (wr_datacount_int),
+    .rd_datacount    (rd_datacount_int),
+    .rd_vld          (rd_valid_o),
+    .wr_overflow     (overflow_o),
+    .rd_underflow    (underflow_o)
+);
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer width2depth;
+input [31:0] width;
+begin : fnWidth2Depth
+    width2depth = width**2;
+end
+endfunction
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ram) #(
+    parameter FAMILY        = "TRION",
+    parameter MODE          = "STANDARD",
+    parameter WR_DEPTH      = 512,
+    parameter RD_DEPTH      = 512,
+    parameter WDATA_WIDTH   = 8,
+    parameter RDATA_WIDTH   = 8,
+    parameter WADDR_WIDTH   = 9,
+    parameter RADDR_WIDTH   = 9,
+    parameter OUTPUT_REG    = 1,
+    parameter RAM_MUX_RATIO = 4,
+    parameter ENDIANESS 	= 0 //0: Big endian (default)   1: Little endian 
+) (
+    input  wire                     wclk,
+    input  wire                     rclk,
+    input  wire                     we,
+    input  wire                     re,
+    input  wire [(WDATA_WIDTH-1):0] wdata,
+    input  wire [(WADDR_WIDTH-1):0] waddr,
+    input  wire [(RADDR_WIDTH-1):0] raddr,
+    output wire [(RDATA_WIDTH-1):0] rdata
+);
+
+localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
+localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
+localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
+                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
+                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";
+
+reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
+reg [RDATA_WIDTH-1:0]    r_rdata_1P;
+reg [RDATA_WIDTH-1:0]    r_rdata_2P;
+
+wire                     re_int;
+
+generate
+    if (FAMILY == "TRION") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            if (ENDIANESS == 0) begin 
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                    end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                	end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            //integer i;
+        	//reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr; 
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end 
+            end
+            else begin //endianess == 1
+            	always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end
+            end
+        end
+        if (OUTPUT_REG) begin
+            assign re_int = re;
+            assign rdata  = r_rdata_2P;            
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end
+    end
+    else if (FAMILY == "TITANIUM") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            //integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            if (ENDIANESS == 0) begin
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+            
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+        	//integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+            
+            else begin //endianess ==1
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+        end
+        if (MODE == "STANDARD") begin     
+            if (OUTPUT_REG) begin
+                reg re_r;
+                always @ (posedge rclk) begin
+                    re_r <= re;
+                end
+                assign re_int = re | re_r;        
+                assign rdata  = r_rdata_2P;            
+            end
+            else begin
+                assign re_int = re;
+                assign rdata  = r_rdata_1P;
+            end
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end        
+    end
+endgenerate
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ctl) # (
+    parameter FAMILY             = "TRION",
+    parameter SYNC_CLK           = 1,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter WR_DEPTH           = 512,
+    parameter WADDR_WIDTH        = 9,
+    parameter RADDR_WIDTH        = 9,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter RAM_MUX_RATIO      = 1,
+    parameter PIPELINE_REG       = 1,
+    parameter ALMOST_FLAG        = 1,
+    parameter PROGRAMMABLE_FULL  = "NONE",
+    parameter PROG_FULL_ASSERT   = 0,
+    parameter PROG_FULL_NEGATE   = 0,
+    parameter PROGRAMMABLE_EMPTY = "NONE",
+    parameter PROG_EMPTY_ASSERT  = 0,
+    parameter PROG_EMPTY_NEGATE  = 0,
+    parameter OUTPUT_REG         = 0,
+    parameter HANDSHAKE_FLAG     = 1
+)(
+    input   wire                   wr_rst,
+    input   wire                   rd_rst,
+    input   wire                   wclk,
+    input   wire                   rclk,
+    input   wire                   we,
+    input   wire                   re,
+    output  wire                   wr_full,
+    output  reg                    wr_ack,
+    output  wire                   wr_almost_full,
+    output  wire                   rd_empty,
+    output  wire                   rd_almost_empty,
+    output  wire                   wr_prog_full,
+    output  wire                   rd_prog_empty,
+    output  wire                   wr_en_int,
+    output  wire                   rd_en_int,
+    output  wire [WADDR_WIDTH-1:0] waddr,
+    output  wire [RADDR_WIDTH-1:0] raddr,
+    output  wire [WADDR_WIDTH:0]   wr_datacount,
+    output  wire [RADDR_WIDTH:0]   rd_datacount,
+    output  wire                   rd_vld,
+    output  reg                    wr_overflow,
+    output  reg                    rd_underflow
+);
+
+reg  [WADDR_WIDTH:0] waddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr_r;
+reg                  rd_valid;
+
+wire [RADDR_WIDTH:0] raddr_cntr_w;
+wire [WADDR_WIDTH:0] waddr_int;
+wire [RADDR_WIDTH:0] raddr_int;
+wire [RADDR_WIDTH:0] raddr_int_dcount;
+wire [RADDR_WIDTH:0] raddr_dcount;
+wire                 rd_empty_int;
+wire [WADDR_WIDTH:0] wr_datacount_int;
+wire [RADDR_WIDTH:0] rd_datacount_int;
+
+assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
+assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
+assign wr_en_int = we & ~wr_full;
+
+generate
+    if (MODE == "FWFT") begin    
+        reg init_set;
+        reg rd_empty_fwft;
+        assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
+        assign rd_empty      = rd_empty_fwft;
+        assign raddr_cntr_w  = ~rd_empty ? raddr_cntr_r/*raddr_cntr-1*/ : raddr_cntr;
+        
+        if (ASYM_WIDTH_RATIO < 4) begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_empty ? rd_datacount_int : ~init_set ? (rd_datacount_int+1'b1) : rd_datacount_int;
+        end
+        else begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_datacount_int;        
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                init_set <= 1'b1;
+            end
+            else if (~init_set & rd_empty) begin
+                init_set <= 1'b1;            
+            end
+            else if (~rd_empty_int) begin
+                init_set <= 1'b0;            
+            end
+            else if (rd_empty) begin
+                init_set <= 1'b1;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_empty_fwft <= 1'b1;
+            end
+            else if (rd_en_int) begin
+                rd_empty_fwft <= 1'b0;            
+            end
+            else if (re) begin
+                rd_empty_fwft <= 1'b1;            
+            end
+        end          
+        
+        if (FAMILY == "TRION") begin
+            if (OUTPUT_REG) begin
+                always @ (posedge rclk or posedge rd_rst) begin
+                    if (rd_rst) begin
+                        rd_valid <= 1'b0;
+                    end
+                    else begin
+                        rd_valid <= ~rd_empty;
+                    end
+                end
+                assign rd_vld = rd_valid;                
+            end    
+            else begin
+                assign rd_vld = ~rd_empty;                
+            end
+        end
+        else begin
+            assign rd_vld = ~rd_empty;
+        end
+    end
+    else begin
+        assign rd_en_int     = re & ~rd_empty_int;
+        assign rd_empty      = rd_empty_int;
+        assign raddr_cntr_w  = raddr_cntr;
+        assign wr_datacount  = wr_datacount_int;
+        assign rd_datacount  = rd_datacount_int;
+        
+        if (OUTPUT_REG) begin
+            reg rd_valid_r;
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid_r <= 'h0;
+                    rd_valid   <= 'h0;
+                end
+                else begin
+                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
+                end
+            end
+            assign rd_vld = rd_valid;            
+        end
+        else begin
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid  <= 'h0;
+                end
+                else begin
+                    rd_valid <= rd_en_int;
+                end
+            end
+            assign rd_vld = rd_valid;
+        end
+    end
+    
+    if (ALMOST_FLAG) begin
+        assign wr_almost_full   = wr_datacount_int >= WR_DEPTH-1;
+        assign rd_almost_empty  = rd_datacount_int <= 'd1;  
+    end
+    else begin
+        assign wr_almost_full   = 1'b0;
+        assign rd_almost_empty  = 1'b0;        
+    end
+    
+    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end  
+    end
+    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end              
+    end
+    else begin
+        assign wr_prog_full  = 1'b0; 
+    end
+        
+    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end
+    end
+    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end  
+    end
+    else begin
+        assign rd_prog_empty  = 1'b0; 
+    end
+    
+    if (HANDSHAKE_FLAG) begin
+    
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_ack <= 1'b0;
+            end
+            else begin
+                wr_ack <= wr_en_int & ~wr_overflow;
+            end
+        end
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_overflow <= 1'b0;
+            end
+            else if (we && wr_full) begin
+                wr_overflow <= 1'b1;
+            end
+            else begin
+                wr_overflow <= 1'b0;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_underflow <= 1'b0;
+            end
+            else if (re && rd_empty) begin
+                rd_underflow <= 1'b1;
+            end
+            else begin
+                rd_underflow <= 1'b0;            
+            end
+        end
+    end
+    
+    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
+    
+    if (ASYM_WIDTH_RATIO < 4) begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
+        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
+        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
+    end
+    else begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
+        assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
+        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w;
+    end
+endgenerate
+
+always @ (posedge wclk or posedge wr_rst) begin
+    if (wr_rst) begin
+        waddr_cntr <= 'h0;
+    end
+    else if (wr_en_int) begin
+        waddr_cntr <= waddr_cntr + 1'b1;
+    end
+end
+
+always @ (posedge rclk or posedge rd_rst) begin
+    if (rd_rst) begin
+        raddr_cntr   <= 'h0;
+        raddr_cntr_r <= 'h0;
+    end
+    else if (rd_en_int) begin
+        raddr_cntr   <= raddr_cntr + 1'b1;
+        raddr_cntr_r <= raddr_cntr;
+    end
+end
+
+generate
+    if (SYNC_CLK) begin
+        assign waddr_int        = waddr_cntr;
+        assign raddr_int        = raddr_cntr_w;
+    end
+    else begin
+        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
+        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
+        
+        wire [RADDR_WIDTH:0] raddr_cntr_gry;
+        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
+        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
+        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;
+
+        if (PIPELINE_REG) begin
+            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
+            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
+        
+            assign waddr_int        = waddr_cntr_sync_g2b_r;
+            assign raddr_int        = raddr_cntr_sync_g2b_r;
+            
+            always @ (posedge wclk or posedge wr_rst) begin
+                if (wr_rst) begin
+                    raddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
+                end
+            end
+            
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    waddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
+                end
+            end
+        end
+        else begin
+            assign waddr_int        = waddr_cntr_sync_g2b;
+            assign raddr_int        = raddr_cntr_sync_g2b;        
+        end
+      
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                raddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                raddr_cntr_gry_r <= raddr_cntr_gry;
+            end
+        end
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_bin2gray    (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync   (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                waddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                waddr_cntr_gry_r <= waddr_cntr_gry;
+            end
+        end        
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        
+
+    end
+endgenerate
+endmodule
+
+`undef IP_UUID
+`undef IP_NAME_CONCAT
+`undef IP_MODULE_NAME

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/T20F256_devkit/asyn_fifo_define.vh

@@ -0,0 +1,63 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam SYNC_CLK = 0;
+localparam SYNC_STAGE = 2;
+localparam DATA_WIDTH = 11;
+localparam MODE = "FWFT";
+localparam OUTPUT_REG = 0;
+localparam PROG_FULL_ASSERT = 128;
+localparam PROGRAMMABLE_FULL = "STATIC_SINGLE";
+localparam PROG_FULL_NEGATE = 128;
+localparam PROGRAMMABLE_EMPTY = "NONE";
+localparam PROG_EMPTY_ASSERT = 0;
+localparam PROG_EMPTY_NEGATE = 2;
+localparam OPTIONAL_FLAGS = 1;
+localparam PIPELINE_REG = 1;
+localparam DEPTH = 8192;
+localparam FAMILY = "TITANIUM";
+localparam ASYM_WIDTH_RATIO = 4;
+localparam BYPASS_RESET_SYNC = 0;
+localparam ENDIANESS = 0;

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/T20F256_devkit/efx_symmetric_width_fifo_top.v

@@ -0,0 +1,1291 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2021.M.200
+// IP Version: 1.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+module efx_symmetric_width_fifo_top # (
+parameter FAMILY             = "TRION",
+parameter SYNC_CLK           = 1,
+parameter OUTPUT_REG         = 0,
+parameter MODE               = "STANDARD",
+parameter PIPELINE_REG       = 1,
+parameter OPTIONAL_FLAGS     = 0,
+parameter PROGRAMMABLE_FULL  = "NONE",
+parameter PROGRAMMABLE_EMPTY = "NONE",
+parameter ASYM_WIDTH_RATIO   = 4,
+parameter DATA_WIDTH         = 32,
+parameter DEPTH              = 512
+) (
+output almost_full_o,
+output prog_full_o,
+output full_o,
+output overflow_o,
+output wr_ack_o,
+output empty_o,
+output almost_empty_o,
+output prog_empty_o,
+output underflow_o,
+output rd_valid_o,
+output [32:0] rdata,
+input wr_clk_i,
+input rd_clk_i,
+input wr_en_i,
+input rd_en_i,
+input [32:0] wdata,
+output [8:0] wr_datacount_o,
+output [8:0] rd_datacount_o,
+input a_rst_i,
+output rst_busy
+);
+efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #(
+.OPTIONAL_FLAGS (OPTIONAL_FLAGS),
+.SYNC_CLK (SYNC_CLK),
+.DEPTH (DEPTH),
+.DATA_WIDTH (DATA_WIDTH),
+.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO),
+.MODE (MODE),
+.OUTPUT_REG (OUTPUT_REG),
+.BYPASS_RESET_SYNC (0),
+.PROG_FULL_ASSERT (7),
+.PIPELINE_REG (PIPELINE_REG),
+.PROG_FULL_NEGATE (3),
+.SYNC_STAGE (2),
+.PROG_EMPTY_ASSERT (2),
+.PROG_EMPTY_NEGATE (3),
+.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL),
+.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+.FAMILY (FAMILY)
+) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b(
+.almost_full_o ( almost_full_o ),
+.prog_full_o ( prog_full_o ),
+.full_o ( full_o ),
+.overflow_o ( overflow_o ),
+.wr_ack_o ( wr_ack_o ),
+.empty_o ( empty_o ),
+.almost_empty_o ( almost_empty_o ),
+.prog_empty_o ( prog_empty_o ),
+.underflow_o ( underflow_o ),
+.rd_valid_o ( rd_valid_o ),
+.rdata ( rdata ),
+.wr_clk_i ( wr_clk_i ),
+.rd_clk_i ( rd_clk_i ),
+.wr_en_i ( wr_en_i ),
+.rd_en_i ( rd_en_i ),
+.wdata ( wdata ),
+.wr_datacount_o ( wr_datacount_o ),
+.rd_datacount_o ( rd_datacount_o ),
+.rst_busy ( rst_busy ),
+.a_rst_i ( a_rst_i )
+);
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   pipe_reg.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Parallel Pipelining Shift Register
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #(
+    parameter STAGE = 32,
+    parameter WIDTH = 4
+) (
+ input  wire             clk_i,
+ input  wire [WIDTH-1:0] d_i,
+ output wire [WIDTH-1:0] d_o
+);
+
+(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
+integer i;
+
+always @(posedge clk_i) begin
+  for (i=STAGE-1; i>0; i = i - 1) begin
+    pipe_reg[i] <= pipe_reg[i-1];
+  end
+  pipe_reg[0] <= d_i;
+end
+assign d_o = pipe_reg[STAGE-1];
+   
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   gray2bin.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Gray to Binary Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] bin_o,
+ // input
+ input [WIDTH-1:0] gray_i);
+
+//---------------------------------------------------------------------
+// Recursive Module
+// Description: reduction xor
+generate
+   if (WIDTH > 1) begin
+      wire [1:0] bin_1;
+      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
+      if (WIDTH == 2) begin
+	 assign bin_o = bin_1;
+      end
+      else begin
+	 assign bin_o[WIDTH-1] = bin_1[1];
+	 efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
+      end
+   end
+   else /* if (WIDTH == 1) */
+     assign bin_o = gray_i;
+endgenerate
+   
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   bin2gray.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Binary to Gray Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] gray_o,
+ // input
+ input [WIDTH-1:0] bin_i
+ );
+
+//---------------------------------------------------------------------
+// Function :   bit_xor
+// Description: reduction xor
+function bit_xor (
+  input [31:0] nex_bit,
+  input [31:0] curr_bit,
+  input [WIDTH-1:0] xor_in);
+  begin : fn_bit_xor
+    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
+  end
+endfunction
+
+// Convert Binary to Gray, bit by bit
+generate 
+begin
+  genvar bit_idx;
+  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
+    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
+  end
+  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
+end
+endgenerate
+
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    parameter FAMILY             = "TRION",       // New Param
+    parameter SYNC_CLK           = 0,
+    parameter BYPASS_RESET_SYNC  = 0,             // New Param
+    parameter SYNC_STAGE         = 2,             // New Param
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
+    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
+    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
+    parameter OPTIONAL_FLAGS     = 1,             // Reverted
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_FULL_ASSERT   = 27,
+    parameter PROG_FULL_NEGATE   = 23,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_EMPTY_ASSERT  = 5,
+    parameter PROG_EMPTY_NEGATE  = 7,
+    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
+    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter WADDR_WIDTH        = depth2width(DEPTH),
+    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
+    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
+    parameter RADDR_WIDTH        = depth2width(RD_DEPTH)
+
+)(
+    input  wire                   a_rst_i,
+    input  wire                   a_wr_rst_i,
+    input  wire                   a_rd_rst_i,
+    input  wire                   clk_i,
+    input  wire                   wr_clk_i,
+    input  wire                   rd_clk_i,
+    input  wire                   wr_en_i,
+    input  wire                   rd_en_i,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+    output wire                   almost_full_o,
+    output wire                   prog_full_o,
+    output wire                   full_o,
+    output wire                   overflow_o,
+    output wire                   wr_ack_o,
+    output wire [WADDR_WIDTH :0]  datacount_o,
+    output wire [WADDR_WIDTH :0]  wr_datacount_o,
+    output wire                   empty_o,
+    output wire                   almost_empty_o,
+    output wire                   prog_empty_o,
+    output wire                   underflow_o,
+    output wire                   rd_valid_o,
+    output wire [RDATA_WIDTH-1:0] rdata,
+    output wire [RADDR_WIDTH :0]  rd_datacount_o,
+    output wire                   rst_busy
+); 
+
+localparam WR_DEPTH      = DEPTH;
+localparam WDATA_WIDTH   = DATA_WIDTH;
+localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           
+
+wire                   wr_rst_int;
+wire                   rd_rst_int;
+wire                   wr_en_int;
+wire                   rd_en_int;
+wire [WADDR_WIDTH-1:0] waddr;
+wire [RADDR_WIDTH-1:0] raddr;
+wire                   wr_clk_int;
+wire                   rd_clk_int;
+wire [WADDR_WIDTH :0]  wr_datacount_int;
+wire [RADDR_WIDTH :0]  rd_datacount_int;
+
+generate
+    if (ASYM_WIDTH_RATIO == 4) begin
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+            assign datacount_o    = wr_datacount_int;
+            assign wr_datacount_o = 'd0;
+            assign rd_datacount_o = 'd0;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+            assign datacount_o    = 'd0;
+            assign wr_datacount_o = wr_datacount_int;
+            assign rd_datacount_o = rd_datacount_int;
+        end
+    end
+    else begin
+        assign datacount_o    = 'd0;
+        assign wr_datacount_o = wr_datacount_int;
+        assign rd_datacount_o = rd_datacount_int;
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+        end
+    end    
+
+    if (!SYNC_CLK) begin
+        (* async_reg = "true" *) reg [1:0] wr_rst;
+        (* async_reg = "true" *) reg [1:0] rd_rst;
+        
+        always @ (posedge wr_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                wr_rst <= 2'b11;
+            else 
+                wr_rst <= {wr_rst[0],1'b0};            
+        end
+        
+        always @ (posedge rd_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                rd_rst <= 2'b11;
+            else 
+                rd_rst <= {rd_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_wr_rst_i;
+            assign rd_rst_int = a_rd_rst_i; 
+            assign rst_busy   = 1'b0;
+        end 
+        else begin
+            assign wr_rst_int = wr_rst[1];
+            assign rd_rst_int = rd_rst[1]; 
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end
+    else begin
+        (* async_reg = "true" *) reg [1:0] a_rst;
+        
+        always @ (posedge clk_i or posedge a_rst_i) begin
+            if (a_rst_i) 
+                a_rst <= 2'b11;
+            else 
+                a_rst <= {a_rst[0],1'b0};            
+        end
+
+        assign wr_rst_int = a_rst;
+        assign rd_rst_int = a_rst;   
+        assign rst_busy   = wr_rst_int | rd_rst_int;
+    end 
+endgenerate
+
+efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    .FAMILY        (FAMILY),
+    .MODE          (MODE),
+    .WR_DEPTH      (WR_DEPTH),
+    .RD_DEPTH      (RD_DEPTH),
+    .WDATA_WIDTH   (WDATA_WIDTH),
+    .RDATA_WIDTH   (RDATA_WIDTH),
+    .WADDR_WIDTH   (WADDR_WIDTH),
+    .RADDR_WIDTH   (RADDR_WIDTH),
+    .OUTPUT_REG    (OUTPUT_REG),
+    .RAM_MUX_RATIO (RAM_MUX_RATIO)
+) xefx_fifo_ram (
+    .wdata (wdata), 
+    .waddr (waddr),
+    .raddr (raddr), 
+    .we    (wr_en_int), 
+    .re    (rd_en_int),
+    .wclk  (wr_clk_int),
+    .rclk  (rd_clk_int),
+    .rdata (rdata)
+);
+
+efx_fifo_ctl_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    .FAMILY             (FAMILY),
+    .SYNC_CLK           (SYNC_CLK),
+    .SYNC_STAGE         (SYNC_STAGE),
+    .MODE               (MODE),
+    .WR_DEPTH           (WR_DEPTH),
+    .WADDR_WIDTH        (WADDR_WIDTH),
+    .RADDR_WIDTH        (RADDR_WIDTH),
+    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
+    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .ALMOST_FLAG        (ALMOST_FLAG),
+    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
+    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
+    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
+    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
+    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
+    .OUTPUT_REG         (OUTPUT_REG),
+    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG)
+) xefx_fifo_ctl (
+    .wr_rst          (wr_rst_int),
+    .rd_rst          (rd_rst_int),
+    .wclk            (wr_clk_int),
+    .rclk            (rd_clk_int),
+    .we              (wr_en_i),
+    .re              (rd_en_i),
+    .wr_full         (full_o),
+    .wr_ack          (wr_ack_o),
+    .rd_empty        (empty_o),
+    .wr_almost_full  (almost_full_o),
+    .rd_almost_empty (almost_empty_o),
+    .wr_prog_full    (prog_full_o),
+    .rd_prog_empty   (prog_empty_o),
+    .wr_en_int       (wr_en_int),
+    .rd_en_int       (rd_en_int),
+    .waddr           (waddr),
+    .raddr           (raddr),
+    .wr_datacount    (wr_datacount_int),
+    .rd_datacount    (rd_datacount_int),
+    .rd_vld          (rd_valid_o),
+    .wr_overflow     (overflow_o),
+    .rd_underflow    (underflow_o)
+);
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer width2depth;
+input [31:0] width;
+begin : fnWidth2Depth
+    width2depth = width**2;
+end
+endfunction
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #(
+    parameter FAMILY        = "TRION",
+    parameter MODE          = "STANDARD",
+    parameter WR_DEPTH      = 512,
+    parameter RD_DEPTH      = 512,
+    parameter WDATA_WIDTH   = 8,
+    parameter RDATA_WIDTH   = 8,
+    parameter WADDR_WIDTH   = 9,
+    parameter RADDR_WIDTH   = 9,
+    parameter OUTPUT_REG    = 1,
+    parameter RAM_MUX_RATIO = 4
+) (
+    input  wire                     wclk,
+    input  wire                     rclk,
+    input  wire                     we,
+    input  wire                     re,
+    input  wire [(WDATA_WIDTH-1):0] wdata,
+    input  wire [(WADDR_WIDTH-1):0] waddr,
+    input  wire [(RADDR_WIDTH-1):0] raddr,
+    output wire [(RDATA_WIDTH-1):0] rdata
+);
+
+localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
+localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
+localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
+                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
+                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";
+
+reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
+reg [RDATA_WIDTH-1:0]    r_rdata_1P;
+reg [RDATA_WIDTH-1:0]    r_rdata_2P;
+
+wire                     re_int;
+
+generate
+    if (FAMILY == "TRION") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            always @ (posedge wclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                    end
+                end
+            end
+                
+            always @ (posedge rclk) begin 
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+ 
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr; 
+            always @ (posedge rclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (re_int) begin
+                        r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    end
+                        r_rdata_2P <= r_rdata_1P;
+                end
+            end 
+        end     
+
+        if (OUTPUT_REG) begin
+            assign re_int = re;
+            assign rdata  = r_rdata_2P;            
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end
+    end
+    else if (FAMILY == "TITANIUM") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            always @ (posedge wclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                    end
+                end
+            end
+                
+            always @ (posedge rclk) begin 
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            always @ (posedge rclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (re_int) begin
+                        r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                        r_rdata_2P                                                               <= r_rdata_1P;
+                    end
+                end
+            end 
+        end     
+
+        if (MODE == "STANDARD") begin     
+            if (OUTPUT_REG) begin
+                reg re_r;
+                always @ (posedge rclk) begin
+                    re_r <= re;
+                end
+                assign re_int = re | re_r;        
+                assign rdata  = r_rdata_2P;            
+            end
+            else begin
+                assign re_int = re;
+                assign rdata  = r_rdata_1P;
+            end
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end        
+    end
+endgenerate
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_ctl_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    parameter FAMILY             = "TRION",
+    parameter SYNC_CLK           = 1,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter WR_DEPTH           = 512,
+    parameter WADDR_WIDTH        = 9,
+    parameter RADDR_WIDTH        = 9,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter RAM_MUX_RATIO      = 1,
+    parameter PIPELINE_REG       = 1,
+    parameter ALMOST_FLAG        = 1,
+    parameter PROGRAMMABLE_FULL  = "NONE",
+    parameter PROG_FULL_ASSERT   = 0,
+    parameter PROG_FULL_NEGATE   = 0,
+    parameter PROGRAMMABLE_EMPTY = "NONE",
+    parameter PROG_EMPTY_ASSERT  = 0,
+    parameter PROG_EMPTY_NEGATE  = 0,
+    parameter OUTPUT_REG         = 0,
+    parameter HANDSHAKE_FLAG     = 1
+)(
+    input   wire                   wr_rst,
+    input   wire                   rd_rst,
+    input   wire                   wclk,
+    input   wire                   rclk,
+    input   wire                   we,
+    input   wire                   re,
+    output  wire                   wr_full,
+    output  reg                    wr_ack,
+    output  wire                   wr_almost_full,
+    output  wire                   rd_empty,
+    output  wire                   rd_almost_empty,
+    output  wire                   wr_prog_full,
+    output  wire                   rd_prog_empty,
+    output  wire                   wr_en_int,
+    output  wire                   rd_en_int,
+    output  wire [WADDR_WIDTH-1:0] waddr,
+    output  wire [RADDR_WIDTH-1:0] raddr,
+    output  wire [WADDR_WIDTH:0]   wr_datacount,
+    output  wire [RADDR_WIDTH:0]   rd_datacount,
+    output  wire                   rd_vld,
+    output  reg                    wr_overflow,
+    output  reg                    rd_underflow
+);
+
+reg  [WADDR_WIDTH:0] waddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr_r;
+reg                  rd_valid;
+
+wire [RADDR_WIDTH:0] raddr_cntr_w;
+wire [WADDR_WIDTH:0] waddr_int;
+wire [RADDR_WIDTH:0] raddr_int;
+wire [RADDR_WIDTH:0] raddr_int_dcount;
+wire [RADDR_WIDTH:0] raddr_dcount;
+wire                 rd_empty_int;
+wire [WADDR_WIDTH:0] wr_datacount_int;
+wire [RADDR_WIDTH:0] rd_datacount_int;
+
+assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
+assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
+assign wr_en_int = we & ~wr_full;
+
+generate
+    if (MODE == "FWFT") begin    
+        reg init_set;
+        reg rd_empty_fwft;
+        assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
+        assign rd_empty      = rd_empty_fwft;
+        assign raddr_cntr_w  = ~rd_empty ? raddr_cntr_r/*raddr_cntr-1*/ : raddr_cntr;
+        
+        if (ASYM_WIDTH_RATIO < 4) begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_empty ? rd_datacount_int : ~init_set ? (rd_datacount_int+1'b1) : rd_datacount_int;
+        end
+        else begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_datacount_int;        
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                init_set <= 1'b1;
+            end
+            else if (~init_set & rd_empty) begin
+                init_set <= 1'b1;            
+            end
+            else if (~rd_empty_int) begin
+                init_set <= 1'b0;            
+            end
+            else if (rd_empty) begin
+                init_set <= 1'b1;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_empty_fwft <= 1'b1;
+            end
+            else if (rd_en_int) begin
+                rd_empty_fwft <= 1'b0;            
+            end
+            else if (re) begin
+                rd_empty_fwft <= 1'b1;            
+            end
+        end          
+        
+        if (FAMILY == "TRION") begin
+            if (OUTPUT_REG) begin
+                always @ (posedge rclk or posedge rd_rst) begin
+                    if (rd_rst) begin
+                        rd_valid <= 1'b0;
+                    end
+                    else begin
+                        rd_valid <= ~rd_empty;
+                    end
+                end
+                assign rd_vld = rd_valid;                
+            end    
+            else begin
+                assign rd_vld = ~rd_empty;                
+            end
+        end
+        else begin
+            assign rd_vld = ~rd_empty;
+        end
+    end
+    else begin
+        assign rd_en_int     = re & ~rd_empty_int;
+        assign rd_empty      = rd_empty_int;
+        assign raddr_cntr_w  = raddr_cntr;
+        assign wr_datacount  = wr_datacount_int;
+        assign rd_datacount  = rd_datacount_int;
+        
+        if (OUTPUT_REG) begin
+            reg rd_valid_r;
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid_r <= 'h0;
+                    rd_valid   <= 'h0;
+                end
+                else begin
+                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
+                end
+            end
+            assign rd_vld = rd_valid;            
+        end
+        else begin
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid  <= 'h0;
+                end
+                else begin
+                    rd_valid <= rd_en_int;
+                end
+            end
+            assign rd_vld = rd_valid;
+        end
+    end
+    
+    if (ALMOST_FLAG) begin
+        assign wr_almost_full   = wr_datacount_int >= WR_DEPTH-1;
+        assign rd_almost_empty  = rd_datacount_int <= 'd1;  
+    end
+    else begin
+        assign wr_almost_full   = 1'b0;
+        assign rd_almost_empty  = 1'b0;        
+    end
+    
+    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end  
+    end
+    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end              
+    end
+    else begin
+        assign wr_prog_full  = 1'b0; 
+    end
+        
+    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end
+    end
+    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end  
+    end
+    else begin
+        assign rd_prog_empty  = 1'b0; 
+    end
+    
+    if (HANDSHAKE_FLAG) begin
+    
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_ack <= 1'b0;
+            end
+            else begin
+                wr_ack <= wr_en_int & ~wr_overflow;
+            end
+        end
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_overflow <= 1'b0;
+            end
+            else if (we && wr_full) begin
+                wr_overflow <= 1'b1;
+            end
+            else begin
+                wr_overflow <= 1'b0;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_underflow <= 1'b0;
+            end
+            else if (re && rd_empty) begin
+                rd_underflow <= 1'b1;
+            end
+            else begin
+                rd_underflow <= 1'b0;            
+            end
+        end
+    end
+    
+    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
+    
+    if (ASYM_WIDTH_RATIO < 4) begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
+        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
+        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
+    end
+    else begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
+        assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
+        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w;
+    end
+endgenerate
+
+always @ (posedge wclk or posedge wr_rst) begin
+    if (wr_rst) begin
+        waddr_cntr <= 'h0;
+    end
+    else if (wr_en_int) begin
+        waddr_cntr <= waddr_cntr + 1'b1;
+    end
+end
+
+always @ (posedge rclk or posedge rd_rst) begin
+    if (rd_rst) begin
+        raddr_cntr   <= 'h0;
+        raddr_cntr_r <= 'h0;
+    end
+    else if (rd_en_int) begin
+        raddr_cntr   <= raddr_cntr + 1'b1;
+        raddr_cntr_r <= raddr_cntr;
+    end
+end
+
+generate
+    if (SYNC_CLK) begin
+        assign waddr_int        = waddr_cntr;
+        assign raddr_int        = raddr_cntr_w;
+    end
+    else begin
+        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
+        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
+        
+        wire [RADDR_WIDTH:0] raddr_cntr_gry;
+        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
+        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
+        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;
+
+        if (PIPELINE_REG) begin
+            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
+            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
+        
+            assign waddr_int        = waddr_cntr_sync_g2b_r;
+            assign raddr_int        = raddr_cntr_sync_g2b_r;
+            
+            always @ (posedge wclk or posedge wr_rst) begin
+                if (wr_rst) begin
+                    raddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
+                end
+            end
+            
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    waddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
+                end
+            end
+        end
+        else begin
+            assign waddr_int        = waddr_cntr_sync_g2b;
+            assign raddr_int        = raddr_cntr_sync_g2b;        
+        end
+      
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                raddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                raddr_cntr_gry_r <= raddr_cntr_gry;
+            end
+        end
+        efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_bin2gray    (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry));
+        efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync   (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
+        efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                waddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                waddr_cntr_gry_r <= waddr_cntr_gry;
+            end
+        end        
+        efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
+        efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
+        efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        
+
+    end
+endgenerate
+endmodule
+

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/T20F256_devkit/fifo_demo_T20.sdc

@@ -0,0 +1,3 @@
+create_clock -period 8.6    [get_ports pll_clkout_0]
+create_clock -period 8.6    [get_ports pll_clkout_1]
+create_clock -period 200  [get_ports led_clk]

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/T20F256_devkit/fifo_demo_top.v

@@ -0,0 +1,198 @@
+module fifo_demo_top #(
+    parameter SYNC_CLK           = 0,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512, 
+    parameter DATA_WIDTH         = 16,
+    parameter PIPELINE_REG       = 1,
+    parameter OPTIONAL_FLAGS     = 1,
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL",
+    parameter PROG_FULL_ASSERT   = 128,
+    parameter PROG_FULL_NEGATE   = 196,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL",
+    parameter PROG_EMPTY_ASSERT  = 8,
+    parameter PROG_EMPTY_NEGATE  = 16,
+    parameter ASYM_WIDTH_RATIO   = 5
+) (
+    input  wire pll_clkout_0,
+    input  wire pll_clkout_1,
+    input  wire led_clk,
+    input  wire pll_lock,
+    input  wire sys_rst_n,
+    input  wire stop_fifo_wr,
+    input  wire stop_fifo_rd,
+    output wire pll_reset,
+    output reg  led_blink,
+    output wire led_rdata_error,
+    output wire led_fifo_full,
+    output wire led_fifo_empty
+);
+
+wire        wr_clk;
+wire        rd_clk;
+wire [31:0] dut_rdata;
+wire [31:0] golden_rdata;
+wire        dut_rd_valid;
+wire        golden_rd_valid;
+wire        dut_trigger_rd;
+wire        dut_rst_busy;
+wire        golden_rst_busy;
+wire        compare_error;
+wire        dut_wr_en;
+wire        dut_full_o;
+wire        dut_empty_o;
+wire        sys_rst;
+wire        rst_busy_all;
+
+reg        rd_en;
+reg        rdata_error;
+reg        dut_wren;
+reg        dut_wr_en_r;
+reg [15:0] dut_wr_data;
+reg [31:0] golden_wr_data;
+reg        golden_wr_en;
+
+`ifdef SIMULATION
+reg [1:0] led_counter;
+`else
+reg [19:0] led_counter;
+`endif
+
+assign pll_reset       = 1'b1;
+assign led_rdata_error = rdata_error;
+assign led_fifo_full   = dut_full_o;
+assign led_fifo_empty  = dut_empty_o;
+
+// ===========================================================
+// ========== LED will blink if the design is alive ==========
+// ===========================================================
+
+always @ (posedge led_clk) begin
+    if (sys_rst) begin
+        led_counter <= 'd0;	
+    end
+    else begin
+        led_counter <= led_counter + 1'b1;
+    end
+end
+
+always @ (posedge led_clk) begin
+    if (sys_rst) begin
+        led_blink <= 1'b0;	
+    end
+    else if (&led_counter) begin
+        led_blink <= ~led_blink;
+    end
+end
+
+// ===========================================================
+// ========== Asymmetric Width FIFO 1:2 DUT ==================
+// ===========================================================
+
+assign wr_clk    = pll_clkout_0;
+assign rd_clk    = pll_clkout_1;
+assign sys_rst   = ~sys_rst_n;              // push button is active low
+assign dut_wr_en = dut_wren & stop_fifo_wr; // push button is active low
+assign dut_rd_en = rd_en    & stop_fifo_rd; // push button is active low
+
+assign rst_busy_all = ~dut_rst_busy & ~golden_rst_busy; 
+
+always @ (posedge wr_clk or posedge sys_rst) begin 
+    if (sys_rst) begin
+        dut_wren    <= 1'b0;
+        dut_wr_data <= 16'h0;
+    end
+    else if (pll_lock &&  rst_busy_all) begin 
+        dut_wren    <= 1'b1;
+        dut_wr_data <= dut_wr_data + 1'b1;  
+    end
+end
+
+asyn_fifo xdut_1_to_2_fifo (
+    .a_rst_i            (sys_rst),
+    .wr_clk_i           (wr_clk),
+    .wr_en_i            (dut_wr_en),
+    .wdata              (dut_wr_data),
+    .rd_clk_i           (rd_clk),
+    .rd_en_i            (dut_rd_en),
+    .rdata              (dut_rdata),
+    .rd_valid_o         (dut_rd_valid),
+    .prog_full_o        (dut_trigger_rd),
+    .rst_busy           (dut_rst_busy),
+    .full_o             (dut_full_o),
+    .empty_o            (dut_empty_o)
+);
+
+always @ (posedge wr_clk or posedge sys_rst) begin
+    if (sys_rst) begin
+        golden_wr_data <= 'h0;
+        dut_wr_en_r    <= 'h0;
+    end
+    else if (~golden_rst_busy) begin
+        golden_wr_data <= {golden_wr_data[15:0],dut_wr_data};    
+        dut_wr_en_r    <= dut_wren;    
+    end
+end
+
+always @ (posedge wr_clk or posedge sys_rst) begin 
+    if (sys_rst) begin
+        golden_wr_en <= 'h0;
+    end
+    else if (dut_wr_en_r)begin
+        golden_wr_en <= ~golden_wr_en;  
+    end
+end
+
+// ===========================================================
+// ========== Symmetric Width FIFO 1:1 Storage ===============
+// ===========================================================
+
+efx_symmetric_width_fifo_top #(
+    .SYNC_CLK           (0),
+    .OUTPUT_REG         (0),
+    .MODE               ("STANDARD"),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .OPTIONAL_FLAGS     (1'b0),
+    .PROGRAMMABLE_FULL  ("NONE"),
+    .PROGRAMMABLE_EMPTY ("NONE"),
+    .ASYM_WIDTH_RATIO   (4),
+    .DATA_WIDTH         (32),
+    .DEPTH              (DEPTH)
+) xdut_1_to_1_golden (
+    .a_rst_i            (sys_rst),
+    .wr_clk_i           (wr_clk),
+    .wr_en_i            (golden_wr_en),
+    .wdata              (golden_wr_data),
+    .rd_clk_i           (rd_clk),
+    .rd_en_i            (rd_en),
+    .rdata              (golden_rdata),
+    .rd_valid_o         (golden_rd_valid),
+    .rst_busy           (golden_rst_busy)
+);
+
+always @ (posedge rd_clk or posedge sys_rst) begin 
+    if (sys_rst) begin
+        rd_en   <= 1'b0;
+    end
+    else if (dut_trigger_rd) begin
+        rd_en   <= 1'b1;
+    end
+end
+
+// ===========================================================
+// ========== Read Data Comparison Logic =====================
+// ===========================================================
+
+assign compare_error = dut_rd_valid|golden_rd_valid ?  dut_rdata != golden_rdata : 0;
+
+always @ (posedge rd_clk or posedge sys_rst) begin 
+    if (sys_rst) begin
+        rdata_error <= 1'b0;
+    end
+    else if (compare_error) begin
+        rdata_error <= 1'b1;
+    end
+end
+
+endmodule

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Testbench/asyn_fifo.v

@@ -0,0 +1,1377 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define IP_UUID _af32f278b05841e694433ae28c490f52
+`define IP_NAME_CONCAT(a,b) a``b
+`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
+module asyn_fifo (
+output almost_full_o,
+output prog_full_o,
+output full_o,
+output overflow_o,
+output wr_ack_o,
+output empty_o,
+output almost_empty_o,
+output underflow_o,
+output rd_valid_o,
+input wr_clk_i,
+input rd_clk_i,
+input wr_en_i,
+input rd_en_i,
+input [10:0] wdata,
+output [12:0] wr_datacount_o,
+output rst_busy,
+output [10:0] rdata,
+output [12:0] rd_datacount_o,
+input a_rst_i
+);
+`IP_MODULE_NAME(efx_fifo_top) #(
+.SYNC_CLK (0),
+.SYNC_STAGE (2),
+.DATA_WIDTH (11),
+.MODE ("FWFT"),
+.OUTPUT_REG (0),
+.PROG_FULL_ASSERT (128),
+.PROGRAMMABLE_FULL ("STATIC_SINGLE"),
+.PROG_FULL_NEGATE (128),
+.PROGRAMMABLE_EMPTY ("NONE"),
+.PROG_EMPTY_ASSERT (0),
+.PROG_EMPTY_NEGATE (2),
+.OPTIONAL_FLAGS (1),
+.PIPELINE_REG (1),
+.DEPTH (8192),
+.FAMILY ("TITANIUM"),
+.ASYM_WIDTH_RATIO (4),
+.BYPASS_RESET_SYNC (0),
+.ENDIANESS (0)
+) u_efx_fifo_top(
+.almost_full_o ( almost_full_o ),
+.prog_full_o ( prog_full_o ),
+.full_o ( full_o ),
+.overflow_o ( overflow_o ),
+.wr_ack_o ( wr_ack_o ),
+.empty_o ( empty_o ),
+.almost_empty_o ( almost_empty_o ),
+.underflow_o ( underflow_o ),
+.rd_valid_o ( rd_valid_o ),
+.wr_clk_i ( wr_clk_i ),
+.rd_clk_i ( rd_clk_i ),
+.wr_en_i ( wr_en_i ),
+.rd_en_i ( rd_en_i ),
+.wdata ( wdata ),
+.wr_datacount_o ( wr_datacount_o ),
+.rst_busy ( rst_busy ),
+.rdata ( rdata ),
+.rd_datacount_o ( rd_datacount_o ),
+.a_rst_i ( a_rst_i )
+);
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   pipe_reg.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Parallel Pipelining Shift Register
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_datasync) #(
+    parameter STAGE = 32,
+    parameter WIDTH = 4
+) (
+ input  wire             clk_i,
+ input  wire [WIDTH-1:0] d_i,
+ output wire [WIDTH-1:0] d_o
+);
+
+(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
+integer i;
+
+always @(posedge clk_i) begin
+  for (i=STAGE-1; i>0; i = i - 1) begin
+    pipe_reg[i] <= pipe_reg[i-1];
+  end
+  pipe_reg[0] <= d_i;
+end
+assign d_o = pipe_reg[STAGE-1];
+   
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   gray2bin.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Gray to Binary Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_gray2bin)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] bin_o,
+ // input
+ input [WIDTH-1:0] gray_i);
+
+//---------------------------------------------------------------------
+// Recursive Module
+// Description: reduction xor
+generate
+   if (WIDTH > 1) begin
+      wire [1:0] bin_1;
+      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
+      if (WIDTH == 2) begin
+	 assign bin_o = bin_1;
+      end
+      else begin
+	 assign bin_o[WIDTH-1] = bin_1[1];
+	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
+      end
+   end
+   else /* if (WIDTH == 1) */
+     assign bin_o = gray_i;
+endgenerate
+   
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   bin2gray.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Binary to Gray Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_bin2gray)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] gray_o,
+ // input
+ input [WIDTH-1:0] bin_i
+ );
+
+//---------------------------------------------------------------------
+// Function :   bit_xor
+// Description: reduction xor
+function bit_xor (
+  input [31:0] nex_bit,
+  input [31:0] curr_bit,
+  input [WIDTH-1:0] xor_in);
+  begin : fn_bit_xor
+    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
+  end
+endfunction
+
+// Convert Binary to Gray, bit by bit
+generate 
+begin
+  genvar bit_idx;
+  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
+    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
+  end
+  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
+end
+endgenerate
+
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_top) # (
+    parameter FAMILY             = "TRION",       // New Param
+    parameter SYNC_CLK           = 0,
+    parameter BYPASS_RESET_SYNC  = 0,             // New Param
+    parameter SYNC_STAGE         = 2,             // New Param
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
+    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
+    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
+    parameter OPTIONAL_FLAGS     = 1,             // Reverted
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_FULL_ASSERT   = 27,
+    parameter PROG_FULL_NEGATE   = 23,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_EMPTY_ASSERT  = 5,
+    parameter PROG_EMPTY_NEGATE  = 7,
+    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
+    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter WADDR_WIDTH        = depth2width(DEPTH),
+    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
+    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
+    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
+    parameter ENDIANESS		 = 0
+
+)(
+    input  wire                   a_rst_i,
+    input  wire                   a_wr_rst_i,
+    input  wire                   a_rd_rst_i,
+    input  wire                   clk_i,
+    input  wire                   wr_clk_i,
+    input  wire                   rd_clk_i,
+    input  wire                   wr_en_i,
+    input  wire                   rd_en_i,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+    output wire                   almost_full_o,
+    output wire                   prog_full_o,
+    output wire                   full_o,
+    output wire                   overflow_o,
+    output wire                   wr_ack_o,
+    output wire [WADDR_WIDTH :0]  datacount_o,
+    output wire [WADDR_WIDTH :0]  wr_datacount_o,
+    output wire                   empty_o,
+    output wire                   almost_empty_o,
+    output wire                   prog_empty_o,
+    output wire                   underflow_o,
+    output wire                   rd_valid_o,
+    output wire [RDATA_WIDTH-1:0] rdata,
+    output wire [RADDR_WIDTH :0]  rd_datacount_o,
+    output wire                   rst_busy
+); 
+
+localparam WR_DEPTH      = DEPTH;
+localparam WDATA_WIDTH   = DATA_WIDTH;
+localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           
+
+wire                   wr_rst_int;
+wire                   rd_rst_int;
+wire                   wr_en_int;
+wire                   rd_en_int;
+wire [WADDR_WIDTH-1:0] waddr;
+wire [RADDR_WIDTH-1:0] raddr;
+wire                   wr_clk_int;
+wire                   rd_clk_int;
+wire [WADDR_WIDTH :0]  wr_datacount_int;
+wire [RADDR_WIDTH :0]  rd_datacount_int;
+
+generate
+    if (ASYM_WIDTH_RATIO == 4) begin
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+            assign datacount_o    = wr_datacount_int;
+            assign wr_datacount_o = 'd0;
+            assign rd_datacount_o = 'd0;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+            assign datacount_o    = 'd0;
+            assign wr_datacount_o = wr_datacount_int;
+            assign rd_datacount_o = rd_datacount_int;
+        end
+    end
+    else begin
+        assign datacount_o    = 'd0;
+        assign wr_datacount_o = wr_datacount_int;
+        assign rd_datacount_o = rd_datacount_int;
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+        end
+    end    
+
+    if (!SYNC_CLK) begin
+        (* async_reg = "true" *) reg [1:0] wr_rst;
+        (* async_reg = "true" *) reg [1:0] rd_rst;
+        
+        always @ (posedge wr_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                wr_rst <= 2'b11;
+            else 
+                wr_rst <= {wr_rst[0],1'b0};            
+        end
+        
+        always @ (posedge rd_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                rd_rst <= 2'b11;
+            else 
+                rd_rst <= {rd_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_wr_rst_i;
+            assign rd_rst_int = a_rd_rst_i; 
+            assign rst_busy   = 1'b0;
+        end 
+        else begin
+            assign wr_rst_int = wr_rst[1];
+            assign rd_rst_int = rd_rst[1]; 
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end
+    else begin
+        (* async_reg = "true" *) reg [1:0] a_rst;
+        
+        always @ (posedge clk_i or posedge a_rst_i) begin
+            if (a_rst_i) 
+                a_rst <= 2'b11;
+            else 
+                a_rst <= {a_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_rst_i;
+            assign rd_rst_int = a_rst_i;
+            assign rst_busy   = 1'b0;
+        end
+        else begin
+            assign wr_rst_int = a_rst[1];
+            assign rd_rst_int = a_rst[1];   
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end 
+endgenerate
+
+`IP_MODULE_NAME(efx_fifo_ram) # (
+    .FAMILY        (FAMILY),
+    .MODE          (MODE),
+    .WR_DEPTH      (WR_DEPTH),
+    .RD_DEPTH      (RD_DEPTH),
+    .WDATA_WIDTH   (WDATA_WIDTH),
+    .RDATA_WIDTH   (RDATA_WIDTH),
+    .WADDR_WIDTH   (WADDR_WIDTH),
+    .RADDR_WIDTH   (RADDR_WIDTH),
+    .OUTPUT_REG    (OUTPUT_REG),
+    .RAM_MUX_RATIO (RAM_MUX_RATIO),
+    .ENDIANESS	   (ENDIANESS)
+) xefx_fifo_ram (
+    .wdata (wdata), 
+    .waddr (waddr),
+    .raddr (raddr), 
+    .we    (wr_en_int), 
+    .re    (rd_en_int),
+    .wclk  (wr_clk_int),
+    .rclk  (rd_clk_int),
+    .rdata (rdata)
+);
+
+`IP_MODULE_NAME(efx_fifo_ctl) # (
+    .FAMILY             (FAMILY),
+    .SYNC_CLK           (SYNC_CLK),
+    .SYNC_STAGE         (SYNC_STAGE),
+    .MODE               (MODE),
+    .WR_DEPTH           (WR_DEPTH),
+    .WADDR_WIDTH        (WADDR_WIDTH),
+    .RADDR_WIDTH        (RADDR_WIDTH),
+    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
+    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .ALMOST_FLAG        (ALMOST_FLAG),
+    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
+    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
+    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
+    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
+    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
+    .OUTPUT_REG         (OUTPUT_REG),
+    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG)
+) xefx_fifo_ctl (
+    .wr_rst          (wr_rst_int),
+    .rd_rst          (rd_rst_int),
+    .wclk            (wr_clk_int),
+    .rclk            (rd_clk_int),
+    .we              (wr_en_i),
+    .re              (rd_en_i),
+    .wr_full         (full_o),
+    .wr_ack          (wr_ack_o),
+    .rd_empty        (empty_o),
+    .wr_almost_full  (almost_full_o),
+    .rd_almost_empty (almost_empty_o),
+    .wr_prog_full    (prog_full_o),
+    .rd_prog_empty   (prog_empty_o),
+    .wr_en_int       (wr_en_int),
+    .rd_en_int       (rd_en_int),
+    .waddr           (waddr),
+    .raddr           (raddr),
+    .wr_datacount    (wr_datacount_int),
+    .rd_datacount    (rd_datacount_int),
+    .rd_vld          (rd_valid_o),
+    .wr_overflow     (overflow_o),
+    .rd_underflow    (underflow_o)
+);
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer width2depth;
+input [31:0] width;
+begin : fnWidth2Depth
+    width2depth = width**2;
+end
+endfunction
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ram) #(
+    parameter FAMILY        = "TRION",
+    parameter MODE          = "STANDARD",
+    parameter WR_DEPTH      = 512,
+    parameter RD_DEPTH      = 512,
+    parameter WDATA_WIDTH   = 8,
+    parameter RDATA_WIDTH   = 8,
+    parameter WADDR_WIDTH   = 9,
+    parameter RADDR_WIDTH   = 9,
+    parameter OUTPUT_REG    = 1,
+    parameter RAM_MUX_RATIO = 4,
+    parameter ENDIANESS 	= 0 //0: Big endian (default)   1: Little endian 
+) (
+    input  wire                     wclk,
+    input  wire                     rclk,
+    input  wire                     we,
+    input  wire                     re,
+    input  wire [(WDATA_WIDTH-1):0] wdata,
+    input  wire [(WADDR_WIDTH-1):0] waddr,
+    input  wire [(RADDR_WIDTH-1):0] raddr,
+    output wire [(RDATA_WIDTH-1):0] rdata
+);
+
+localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
+localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
+localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
+                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
+                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";
+
+reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
+reg [RDATA_WIDTH-1:0]    r_rdata_1P;
+reg [RDATA_WIDTH-1:0]    r_rdata_2P;
+
+wire                     re_int;
+
+generate
+    if (FAMILY == "TRION") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            if (ENDIANESS == 0) begin 
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                    end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                	end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            //integer i;
+        	//reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr; 
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end 
+            end
+            else begin //endianess == 1
+            	always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end
+            end
+        end
+        if (OUTPUT_REG) begin
+            assign re_int = re;
+            assign rdata  = r_rdata_2P;            
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end
+    end
+    else if (FAMILY == "TITANIUM") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            //integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            if (ENDIANESS == 0) begin
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+            
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+        	//integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+            
+            else begin //endianess ==1
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+        end
+        if (MODE == "STANDARD") begin     
+            if (OUTPUT_REG) begin
+                reg re_r;
+                always @ (posedge rclk) begin
+                    re_r <= re;
+                end
+                assign re_int = re | re_r;        
+                assign rdata  = r_rdata_2P;            
+            end
+            else begin
+                assign re_int = re;
+                assign rdata  = r_rdata_1P;
+            end
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end        
+    end
+endgenerate
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ctl) # (
+    parameter FAMILY             = "TRION",
+    parameter SYNC_CLK           = 1,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter WR_DEPTH           = 512,
+    parameter WADDR_WIDTH        = 9,
+    parameter RADDR_WIDTH        = 9,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter RAM_MUX_RATIO      = 1,
+    parameter PIPELINE_REG       = 1,
+    parameter ALMOST_FLAG        = 1,
+    parameter PROGRAMMABLE_FULL  = "NONE",
+    parameter PROG_FULL_ASSERT   = 0,
+    parameter PROG_FULL_NEGATE   = 0,
+    parameter PROGRAMMABLE_EMPTY = "NONE",
+    parameter PROG_EMPTY_ASSERT  = 0,
+    parameter PROG_EMPTY_NEGATE  = 0,
+    parameter OUTPUT_REG         = 0,
+    parameter HANDSHAKE_FLAG     = 1
+)(
+    input   wire                   wr_rst,
+    input   wire                   rd_rst,
+    input   wire                   wclk,
+    input   wire                   rclk,
+    input   wire                   we,
+    input   wire                   re,
+    output  wire                   wr_full,
+    output  reg                    wr_ack,
+    output  wire                   wr_almost_full,
+    output  wire                   rd_empty,
+    output  wire                   rd_almost_empty,
+    output  wire                   wr_prog_full,
+    output  wire                   rd_prog_empty,
+    output  wire                   wr_en_int,
+    output  wire                   rd_en_int,
+    output  wire [WADDR_WIDTH-1:0] waddr,
+    output  wire [RADDR_WIDTH-1:0] raddr,
+    output  wire [WADDR_WIDTH:0]   wr_datacount,
+    output  wire [RADDR_WIDTH:0]   rd_datacount,
+    output  wire                   rd_vld,
+    output  reg                    wr_overflow,
+    output  reg                    rd_underflow
+);
+
+reg  [WADDR_WIDTH:0] waddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr_r;
+reg                  rd_valid;
+
+wire [RADDR_WIDTH:0] raddr_cntr_w;
+wire [WADDR_WIDTH:0] waddr_int;
+wire [RADDR_WIDTH:0] raddr_int;
+wire [RADDR_WIDTH:0] raddr_int_dcount;
+wire [RADDR_WIDTH:0] raddr_dcount;
+wire                 rd_empty_int;
+wire [WADDR_WIDTH:0] wr_datacount_int;
+wire [RADDR_WIDTH:0] rd_datacount_int;
+
+assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
+assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
+assign wr_en_int = we & ~wr_full;
+
+generate
+    if (MODE == "FWFT") begin    
+        reg init_set;
+        reg rd_empty_fwft;
+        assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
+        assign rd_empty      = rd_empty_fwft;
+        assign raddr_cntr_w  = ~rd_empty ? raddr_cntr_r/*raddr_cntr-1*/ : raddr_cntr;
+        
+        if (ASYM_WIDTH_RATIO < 4) begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_empty ? rd_datacount_int : ~init_set ? (rd_datacount_int+1'b1) : rd_datacount_int;
+        end
+        else begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_datacount_int;        
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                init_set <= 1'b1;
+            end
+            else if (~init_set & rd_empty) begin
+                init_set <= 1'b1;            
+            end
+            else if (~rd_empty_int) begin
+                init_set <= 1'b0;            
+            end
+            else if (rd_empty) begin
+                init_set <= 1'b1;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_empty_fwft <= 1'b1;
+            end
+            else if (rd_en_int) begin
+                rd_empty_fwft <= 1'b0;            
+            end
+            else if (re) begin
+                rd_empty_fwft <= 1'b1;            
+            end
+        end          
+        
+        if (FAMILY == "TRION") begin
+            if (OUTPUT_REG) begin
+                always @ (posedge rclk or posedge rd_rst) begin
+                    if (rd_rst) begin
+                        rd_valid <= 1'b0;
+                    end
+                    else begin
+                        rd_valid <= ~rd_empty;
+                    end
+                end
+                assign rd_vld = rd_valid;                
+            end    
+            else begin
+                assign rd_vld = ~rd_empty;                
+            end
+        end
+        else begin
+            assign rd_vld = ~rd_empty;
+        end
+    end
+    else begin
+        assign rd_en_int     = re & ~rd_empty_int;
+        assign rd_empty      = rd_empty_int;
+        assign raddr_cntr_w  = raddr_cntr;
+        assign wr_datacount  = wr_datacount_int;
+        assign rd_datacount  = rd_datacount_int;
+        
+        if (OUTPUT_REG) begin
+            reg rd_valid_r;
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid_r <= 'h0;
+                    rd_valid   <= 'h0;
+                end
+                else begin
+                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
+                end
+            end
+            assign rd_vld = rd_valid;            
+        end
+        else begin
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid  <= 'h0;
+                end
+                else begin
+                    rd_valid <= rd_en_int;
+                end
+            end
+            assign rd_vld = rd_valid;
+        end
+    end
+    
+    if (ALMOST_FLAG) begin
+        assign wr_almost_full   = wr_datacount_int >= WR_DEPTH-1;
+        assign rd_almost_empty  = rd_datacount_int <= 'd1;  
+    end
+    else begin
+        assign wr_almost_full   = 1'b0;
+        assign rd_almost_empty  = 1'b0;        
+    end
+    
+    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end  
+    end
+    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end              
+    end
+    else begin
+        assign wr_prog_full  = 1'b0; 
+    end
+        
+    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end
+    end
+    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end  
+    end
+    else begin
+        assign rd_prog_empty  = 1'b0; 
+    end
+    
+    if (HANDSHAKE_FLAG) begin
+    
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_ack <= 1'b0;
+            end
+            else begin
+                wr_ack <= wr_en_int & ~wr_overflow;
+            end
+        end
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_overflow <= 1'b0;
+            end
+            else if (we && wr_full) begin
+                wr_overflow <= 1'b1;
+            end
+            else begin
+                wr_overflow <= 1'b0;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_underflow <= 1'b0;
+            end
+            else if (re && rd_empty) begin
+                rd_underflow <= 1'b1;
+            end
+            else begin
+                rd_underflow <= 1'b0;            
+            end
+        end
+    end
+    
+    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
+    
+    if (ASYM_WIDTH_RATIO < 4) begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
+        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
+        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
+    end
+    else begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
+        assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
+        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w;
+    end
+endgenerate
+
+always @ (posedge wclk or posedge wr_rst) begin
+    if (wr_rst) begin
+        waddr_cntr <= 'h0;
+    end
+    else if (wr_en_int) begin
+        waddr_cntr <= waddr_cntr + 1'b1;
+    end
+end
+
+always @ (posedge rclk or posedge rd_rst) begin
+    if (rd_rst) begin
+        raddr_cntr   <= 'h0;
+        raddr_cntr_r <= 'h0;
+    end
+    else if (rd_en_int) begin
+        raddr_cntr   <= raddr_cntr + 1'b1;
+        raddr_cntr_r <= raddr_cntr;
+    end
+end
+
+generate
+    if (SYNC_CLK) begin
+        assign waddr_int        = waddr_cntr;
+        assign raddr_int        = raddr_cntr_w;
+    end
+    else begin
+        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
+        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
+        
+        wire [RADDR_WIDTH:0] raddr_cntr_gry;
+        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
+        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
+        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;
+
+        if (PIPELINE_REG) begin
+            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
+            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
+        
+            assign waddr_int        = waddr_cntr_sync_g2b_r;
+            assign raddr_int        = raddr_cntr_sync_g2b_r;
+            
+            always @ (posedge wclk or posedge wr_rst) begin
+                if (wr_rst) begin
+                    raddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
+                end
+            end
+            
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    waddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
+                end
+            end
+        end
+        else begin
+            assign waddr_int        = waddr_cntr_sync_g2b;
+            assign raddr_int        = raddr_cntr_sync_g2b;        
+        end
+      
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                raddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                raddr_cntr_gry_r <= raddr_cntr_gry;
+            end
+        end
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_bin2gray    (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync   (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                waddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                waddr_cntr_gry_r <= waddr_cntr_gry;
+            end
+        end        
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        
+
+    end
+endgenerate
+endmodule
+
+`undef IP_UUID
+`undef IP_NAME_CONCAT
+`undef IP_MODULE_NAME

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Testbench/asyn_fifo_define.vh

@@ -0,0 +1,63 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam SYNC_CLK = 0;
+localparam SYNC_STAGE = 2;
+localparam DATA_WIDTH = 11;
+localparam MODE = "FWFT";
+localparam OUTPUT_REG = 0;
+localparam PROG_FULL_ASSERT = 128;
+localparam PROGRAMMABLE_FULL = "STATIC_SINGLE";
+localparam PROG_FULL_NEGATE = 128;
+localparam PROGRAMMABLE_EMPTY = "NONE";
+localparam PROG_EMPTY_ASSERT = 0;
+localparam PROG_EMPTY_NEGATE = 2;
+localparam OPTIONAL_FLAGS = 1;
+localparam PIPELINE_REG = 1;
+localparam DEPTH = 8192;
+localparam FAMILY = "TITANIUM";
+localparam ASYM_WIDTH_RATIO = 4;
+localparam BYPASS_RESET_SYNC = 0;
+localparam ENDIANESS = 0;

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Testbench/fifo_tb.sv

@@ -0,0 +1,473 @@
+`resetall
+`timescale 1ns/1ps
+`include "asyn_fifo_define.vh"
+
+module fifo_tb;
+
+`ifdef XRUN
+initial begin
+    $shm_open("fifo_tb.shm");
+    $shm_probe(fifo_tb,"ACMTF");
+end
+`endif
+
+localparam WDATA_WIDTH_WGR	= (ASYM_WIDTH_RATIO == 0)? 16 : 
+                              (ASYM_WIDTH_RATIO == 1)? 16 :
+                              (ASYM_WIDTH_RATIO == 2)? 16 :
+                              (ASYM_WIDTH_RATIO == 3)? 16 :
+                              (ASYM_WIDTH_RATIO == 4)? 16 :
+                              (ASYM_WIDTH_RATIO == 5)? 16 :
+                              (ASYM_WIDTH_RATIO == 6)? 16 :
+                              (ASYM_WIDTH_RATIO == 7)? 16 :
+                              (ASYM_WIDTH_RATIO == 8)? 16 : 16;
+                              
+localparam WDATA_WIDTH_RGW	= (ASYM_WIDTH_RATIO == 0)? 16 : 
+                              (ASYM_WIDTH_RATIO == 1)? 16 :
+                              (ASYM_WIDTH_RATIO == 2)? 16 :
+                              (ASYM_WIDTH_RATIO == 3)? 16 :
+                              (ASYM_WIDTH_RATIO == 4)? 16 :
+                              (ASYM_WIDTH_RATIO == 5)? 8  :
+                              (ASYM_WIDTH_RATIO == 6)? 8  :
+                              (ASYM_WIDTH_RATIO == 7)? 4  :
+                              (ASYM_WIDTH_RATIO == 8)? 1  : 16;
+	
+localparam WDATA_WIDTH        = DATA_WIDTH;
+localparam RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,WDATA_WIDTH);
+localparam RDATA_WIDTH_48     = (ASYM_WIDTH_RATIO >= 4) ? RDATA_WIDTH : 16;
+
+localparam WR_DEPTH           = DEPTH;
+localparam WADDR_WIDTH        = depth2width(WR_DEPTH);
+localparam RD_DEPTH           = rddepthcompute(WR_DEPTH,WDATA_WIDTH,RDATA_WIDTH);
+localparam RADDR_WIDTH        = depth2width(RD_DEPTH);
+localparam MEM_DATA_WIDTH     = (WDATA_WIDTH >= RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;
+localparam RAM_MUX_RATIO      = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                                (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                                (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                                (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                                (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                                (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                                (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                                (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                                (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                                (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; 
+localparam LSB_WIDTH          = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+
+reg                      a_rst_i;
+reg                      wr_clk;
+reg                      rd_clk;
+reg                      wr_en_i;
+reg                      rd_en_i;
+reg [WDATA_WIDTH-1:0]    wdata;
+reg [WADDR_WIDTH-1:0]    waddr;
+reg [RADDR_WIDTH-1:0]    raddr;
+reg [MEM_DATA_WIDTH-1:0] dynamic_a[$];
+reg [MEM_DATA_WIDTH-1:0] dynamic_b[$];
+reg [RDATA_WIDTH-1:0]    monitor, monitor_temp;
+reg [RDATA_WIDTH-1:0]    read_lastdata;
+reg                      temp_empty_o;
+
+wire [RDATA_WIDTH-1:0] rdata;
+wire                   rd_valid_o;
+wire                   prog_full_o;
+wire                   almost_full_o;
+wire                   full_o;
+wire                   overflow_o;
+wire                   wr_ack_o;
+wire                   prog_empty_o;
+wire                   almost_empty_o;
+wire                   empty_o;
+wire                   underflow_o;
+wire [WADDR_WIDTH:0]   datacount_o;
+wire [WADDR_WIDTH:0]   wr_datacount_o;
+wire [RADDR_WIDTH:0]   rd_datacount_o;
+wire                   clk_i;
+wire                   wr_clk_i;
+wire                   rd_clk_i;
+wire                   rst_busy_0;
+
+integer write_period;
+integer read_period;
+integer count;
+integer wr_count;
+integer rd_count;
+
+initial begin
+    wr_clk   = 0;
+    rd_clk   = 0;
+    write_period = 7;
+    read_period  = 9;
+end
+
+always begin
+    #(write_period) wr_clk <= ~wr_clk;
+end
+
+always begin
+    #(read_period) rd_clk <= ~rd_clk;
+end
+
+assign clk_i    = wr_clk;
+assign wr_clk_i = wr_clk;
+assign rd_clk_i = wr_clk; 
+
+initial begin
+    a_rst_i = 1'b1;
+    #1080
+    a_rst_i = 1'b0;
+end
+
+initial begin
+    wr_en_i   = 1'b0;
+    rd_en_i   = 1'b0;
+    wdata     = 'h0;
+    waddr     = 'd0;
+    raddr     = 'd0;
+    dynamic_a = {};
+    dynamic_b = {};
+end
+
+assign wr_count = WR_DEPTH;
+assign rd_count = ASYM_WIDTH_RATIO < 4 ? wr_count * RAM_MUX_RATIO : wr_count / RAM_MUX_RATIO;
+
+initial begin
+    wait (~a_rst_i & rst_busy_0);
+    repeat (10) @ (negedge wr_clk_i) ;  
+    count = WR_DEPTH;
+    repeat (wr_count) @ (negedge wr_clk_i) begin
+        wr_en_i = 1'b1;
+        wdata   = {WDATA_WIDTH{$random}};
+    end
+    repeat (2) @ (negedge wr_clk_i) begin
+        wr_en_i = 1'b0;
+    end
+    repeat (rd_count) @ (negedge wr_clk_i) begin
+        rd_en_i = 1'b1;
+    end
+    repeat (2) @ (negedge wr_clk_i) begin
+        rd_en_i = 1'b0;
+    end
+    repeat (10) @ (negedge wr_clk_i) ;
+    $finish;
+end
+
+initial begin
+    forever begin
+        @(posedge wr_clk_i) begin
+            if (wr_en_i && ~full_o) begin
+                waddr <= waddr +1;
+            end
+        end
+    end
+end
+
+initial begin
+	forever begin
+		@(posedge rd_clk_i) begin
+		    if (rd_en_i && ~empty_o) begin
+		    	raddr <= raddr + 1;
+		    end
+		end
+	end
+end
+
+initial begin
+    forever begin
+        @(posedge wr_clk_i) begin
+            if (wr_en_i && ~full_o) begin
+                if (ENDIANESS == 0) begin
+                	if (WDATA_WIDTH <= RDATA_WIDTH) begin
+                		dynamic_a.push_back(wdata);
+                		dynamic_b.push_back(wdata);
+                		$display("%t - write data %h to address: %d ", $time(), wdata, waddr );
+                		end
+                	else begin
+                		integer i;
+                		reg  [LSB_WIDTH-1 :0 ] lsbaddr;
+                		for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                        	lsbaddr = i;
+                        	dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]);
+                        	dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i)-1 -: WDATA_WIDTH_WGR/RAM_MUX_RATIO]);
+                        end
+                        	$display("%t - write data %h to address: %d", $time(), wdata, waddr);
+                    end
+                end
+                else begin 
+                	if (WDATA_WIDTH <= RDATA_WIDTH) begin 
+                		dynamic_a.push_back(wdata);
+                		dynamic_b.push_back(wdata);
+                		$display("%t - write data %h to address: %d ", $time(), wdata, waddr );
+                		end
+                	else begin //downsize
+                		integer i;
+                		reg  [LSB_WIDTH-1 :0 ] lsbaddr;
+                		for (i=0; i < RAM_MUX_RATIO; i=i+1) begin
+                        	lsbaddr = i;
+                        	dynamic_a.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]);
+                        	dynamic_b.push_back(wdata[((WDATA_WIDTH_WGR/RAM_MUX_RATIO)*i) +: WDATA_WIDTH_WGR/RAM_MUX_RATIO]);
+                        end
+                        	$display("%t - write data %h to address: %d", $time(), wdata, waddr);
+                    end
+                end
+            end
+        end
+    end
+end
+
+initial begin
+    forever begin
+        if (MODE == "STANDARD") begin
+            @(posedge rd_clk_i) begin
+                if (RDATA_WIDTH <= WDATA_WIDTH) begin 
+                    if(rd_en_i == 1 && ~empty_o) begin
+                        monitor <= dynamic_a.pop_front();
+                    end
+                end
+                else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin 
+                    integer i;
+                    for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                        if (rd_en_i && ~empty_o) begin
+                            monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                        end
+                    end
+                end
+                else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 1) begin 
+                	integer i;
+                    for (i=0; i < RAM_MUX_RATIO; i=i+1) begin
+                        if (rd_en_i && ~empty_o) begin
+                            monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                        end
+                    end
+                end
+            end
+        end
+        else begin
+            if (SYNC_CLK) begin
+                @(posedge rd_clk_i) begin
+                    if (RDATA_WIDTH <= WDATA_WIDTH) begin 
+                        if (dynamic_b.size() == RAM_MUX_RATIO) begin
+                            monitor <= dynamic_a.pop_front();
+                        end
+                        else if (rd_en_i == 1 && ~empty_o) begin
+                            monitor <= dynamic_a.pop_front();
+                        end
+                    end
+                    else begin 
+                        integer i;
+                        if (dynamic_b.size() == RAM_MUX_RATIO) begin
+                            for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                                monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                            end	
+                        end
+                        else begin
+                            integer i;
+                            for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                                if (rd_en_i && ~almost_empty_o) begin
+                                    monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                                end
+                            end
+                        end					
+                    end
+                end
+			end
+            else begin
+                @(posedge rd_clk_i) begin
+                    if (RDATA_WIDTH <= WDATA_WIDTH) begin 
+                        #0.1
+                        if (rd_en_i && ~empty_o) begin
+                            monitor <= dynamic_a.pop_front();
+                        end
+                    end
+                    else if(RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin 
+                        integer i;
+                        for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                            if (rd_en_i && ~almost_empty_o) begin
+                                monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                            end
+                        end					
+                    end
+                    else begin 
+                    	integer i;
+                        for (i=0; i < RAM_MUX_RATIO; i=i+1) begin
+                            if (rd_en_i && ~almost_empty_o) begin
+                                monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                            end
+                        end	
+                    end
+                end
+            end
+        end
+    end
+end
+
+initial begin
+    forever begin
+        if (MODE == "FWFT") begin
+            if (SYNC_CLK == 0) begin
+                @ (negedge empty_o) begin
+                    if (~rd_en_i && dynamic_b.size() != 1) begin
+                    	//integer i
+                        if (RDATA_WIDTH <= WDATA_WIDTH) begin 
+                            monitor <= dynamic_a.pop_front();					
+                        end
+                        else if (RDATA_WIDTH > WDATA_WIDTH && ENDIANESS == 0) begin
+                            integer i;
+                            for (i=RAM_MUX_RATIO; i > 0; i=i-1) begin
+                                monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i)-1 -: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                            end
+                        end
+                        else begin
+                        	integer i;
+                            for (i=0; i < RAM_MUX_RATIO; i=i+1) begin
+                                monitor[((RDATA_WIDTH_48/RAM_MUX_RATIO)*i) +: (RDATA_WIDTH_48/RAM_MUX_RATIO)] <= dynamic_a.pop_front();
+                            end
+                        end
+                    end
+                end				
+            end
+            else begin
+                @ (negedge empty_o);
+            end
+		end
+        else begin
+            @ (negedge empty_o);
+        end
+    end
+end
+
+always @ (posedge rd_clk_i)begin
+    monitor_temp <= monitor;
+    temp_empty_o <= empty_o;
+end
+
+initial begin
+    forever begin
+        if (MODE == "STANDARD") begin
+            @(negedge rd_clk_i) begin
+                if (rd_valid_o == 1 && ~a_rst_i) begin
+                    if (monitor  === rdata) begin
+                        $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor);
+                    end
+                    else begin
+                        $error("%t - FAIL! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor);
+                    end
+                end
+            end
+        end
+        else begin
+            @(posedge rd_clk_i) begin
+                if (rd_en_i && rd_valid_o) begin
+                    if (monitor  === rdata) begin
+                        $display("%t - PASS! FIFO read data %h is match to expected data %h", $time(), rdata, monitor);
+                    end
+                    else begin
+                        $error("%t - ERROR! FIFO read data %h does not match to expected data %h", $time(), rdata, monitor);
+                    end
+                end
+            end		
+        end	
+    end
+end
+
+generate
+    if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO == 4) begin
+        asyn_fifo u_efx_fifo_top (
+            .a_rst_i        (a_rst_i),
+            .rst_busy       (rst_busy_0),   
+            .clk_i          (clk_i),
+            .wr_en_i        (wr_en_i),
+            .wdata          (wdata),
+            .rd_en_i        (rd_en_i),
+            .rdata          (rdata),
+            .rd_valid_o     (rd_valid_o),
+            .full_o         (full_o),
+            .almost_empty_o (almost_empty_o),
+            .empty_o        (empty_o)
+        );
+    end
+    else if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO == 4) begin
+        asyn_fifo u_efx_fifo_top (
+            .a_rst_i        (a_rst_i),   
+            .rst_busy       (rst_busy_0),   
+            .wr_clk_i       (wr_clk_i),
+            .wr_en_i        (wr_en_i),
+            .wdata          (wdata),
+            .rd_clk_i       (rd_clk_i),
+            .rd_en_i        (rd_en_i),
+            .rdata          (rdata),
+            .rd_valid_o     (rd_valid_o),
+            .full_o         (full_o),
+            .almost_empty_o (almost_empty_o),
+            .empty_o        (empty_o)
+        );
+    end
+    else if (SYNC_CLK == 1 && ASYM_WIDTH_RATIO != 4) begin
+        asyn_fifo u_efx_fifo_top (
+            .a_rst_i        (a_rst_i),     
+            .rst_busy       (rst_busy_0),   
+            .clk_i          (clk_i),
+            .wr_en_i        (wr_en_i),
+            .wdata          (wdata),
+            .rd_en_i        (rd_en_i),
+            .rdata          (rdata),
+            .rd_valid_o     (rd_valid_o),
+            .full_o         (full_o),
+            .almost_empty_o (almost_empty_o),
+            .empty_o        (empty_o)
+        );
+    end if (SYNC_CLK == 0 && ASYM_WIDTH_RATIO != 4) begin
+        asyn_fifo u_efx_fifo_top (
+            .a_rst_i        (a_rst_i),   
+            .rst_busy       (rst_busy_0),   
+            .wr_clk_i       (wr_clk_i),
+            .wr_en_i        (wr_en_i),
+            .wdata          (wdata),
+            .rd_clk_i       (rd_clk_i),
+            .rd_en_i        (rd_en_i),
+            .rdata          (rdata),
+            .rd_valid_o     (rd_valid_o),
+            .full_o         (full_o),
+            .almost_empty_o (almost_empty_o),
+            .empty_o        (empty_o)
+        );
+    end
+endgenerate
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo.v

@@ -0,0 +1,1377 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define IP_UUID _af32f278b05841e694433ae28c490f52
+`define IP_NAME_CONCAT(a,b) a``b
+`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
+module asyn_fifo (
+output almost_full_o,
+output prog_full_o,
+output full_o,
+output overflow_o,
+output wr_ack_o,
+output empty_o,
+output almost_empty_o,
+output underflow_o,
+output rd_valid_o,
+input wr_clk_i,
+input rd_clk_i,
+input wr_en_i,
+input rd_en_i,
+input [10:0] wdata,
+output [12:0] wr_datacount_o,
+output rst_busy,
+output [10:0] rdata,
+output [12:0] rd_datacount_o,
+input a_rst_i
+);
+`IP_MODULE_NAME(efx_fifo_top) #(
+.SYNC_CLK (0),
+.SYNC_STAGE (2),
+.DATA_WIDTH (11),
+.MODE ("FWFT"),
+.OUTPUT_REG (0),
+.PROG_FULL_ASSERT (128),
+.PROGRAMMABLE_FULL ("STATIC_SINGLE"),
+.PROG_FULL_NEGATE (128),
+.PROGRAMMABLE_EMPTY ("NONE"),
+.PROG_EMPTY_ASSERT (0),
+.PROG_EMPTY_NEGATE (2),
+.OPTIONAL_FLAGS (1),
+.PIPELINE_REG (1),
+.DEPTH (8192),
+.FAMILY ("TITANIUM"),
+.ASYM_WIDTH_RATIO (4),
+.BYPASS_RESET_SYNC (0),
+.ENDIANESS (0)
+) u_efx_fifo_top(
+.almost_full_o ( almost_full_o ),
+.prog_full_o ( prog_full_o ),
+.full_o ( full_o ),
+.overflow_o ( overflow_o ),
+.wr_ack_o ( wr_ack_o ),
+.empty_o ( empty_o ),
+.almost_empty_o ( almost_empty_o ),
+.underflow_o ( underflow_o ),
+.rd_valid_o ( rd_valid_o ),
+.wr_clk_i ( wr_clk_i ),
+.rd_clk_i ( rd_clk_i ),
+.wr_en_i ( wr_en_i ),
+.rd_en_i ( rd_en_i ),
+.wdata ( wdata ),
+.wr_datacount_o ( wr_datacount_o ),
+.rst_busy ( rst_busy ),
+.rdata ( rdata ),
+.rd_datacount_o ( rd_datacount_o ),
+.a_rst_i ( a_rst_i )
+);
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   pipe_reg.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Parallel Pipelining Shift Register
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_datasync) #(
+    parameter STAGE = 32,
+    parameter WIDTH = 4
+) (
+ input  wire             clk_i,
+ input  wire [WIDTH-1:0] d_i,
+ output wire [WIDTH-1:0] d_o
+);
+
+(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
+integer i;
+
+always @(posedge clk_i) begin
+  for (i=STAGE-1; i>0; i = i - 1) begin
+    pipe_reg[i] <= pipe_reg[i-1];
+  end
+  pipe_reg[0] <= d_i;
+end
+assign d_o = pipe_reg[STAGE-1];
+   
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   gray2bin.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Gray to Binary Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_gray2bin)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] bin_o,
+ // input
+ input [WIDTH-1:0] gray_i);
+
+//---------------------------------------------------------------------
+// Recursive Module
+// Description: reduction xor
+generate
+   if (WIDTH > 1) begin
+      wire [1:0] bin_1;
+      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
+      if (WIDTH == 2) begin
+	 assign bin_o = bin_1;
+      end
+      else begin
+	 assign bin_o[WIDTH-1] = bin_1[1];
+	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
+      end
+   end
+   else /* if (WIDTH == 1) */
+     assign bin_o = gray_i;
+endgenerate
+   
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   bin2gray.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Binary to Gray Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module `IP_MODULE_NAME(efx_fifo_bin2gray)
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] gray_o,
+ // input
+ input [WIDTH-1:0] bin_i
+ );
+
+//---------------------------------------------------------------------
+// Function :   bit_xor
+// Description: reduction xor
+function bit_xor (
+  input [31:0] nex_bit,
+  input [31:0] curr_bit,
+  input [WIDTH-1:0] xor_in);
+  begin : fn_bit_xor
+    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
+  end
+endfunction
+
+// Convert Binary to Gray, bit by bit
+generate 
+begin
+  genvar bit_idx;
+  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
+    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
+  end
+  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
+end
+endgenerate
+
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_top) # (
+    parameter FAMILY             = "TRION",       // New Param
+    parameter SYNC_CLK           = 0,
+    parameter BYPASS_RESET_SYNC  = 0,             // New Param
+    parameter SYNC_STAGE         = 2,             // New Param
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
+    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
+    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
+    parameter OPTIONAL_FLAGS     = 1,             // Reverted
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_FULL_ASSERT   = 27,
+    parameter PROG_FULL_NEGATE   = 23,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_EMPTY_ASSERT  = 5,
+    parameter PROG_EMPTY_NEGATE  = 7,
+    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
+    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter WADDR_WIDTH        = depth2width(DEPTH),
+    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
+    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
+    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
+    parameter ENDIANESS		 = 0
+
+)(
+    input  wire                   a_rst_i,
+    input  wire                   a_wr_rst_i,
+    input  wire                   a_rd_rst_i,
+    input  wire                   clk_i,
+    input  wire                   wr_clk_i,
+    input  wire                   rd_clk_i,
+    input  wire                   wr_en_i,
+    input  wire                   rd_en_i,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+    output wire                   almost_full_o,
+    output wire                   prog_full_o,
+    output wire                   full_o,
+    output wire                   overflow_o,
+    output wire                   wr_ack_o,
+    output wire [WADDR_WIDTH :0]  datacount_o,
+    output wire [WADDR_WIDTH :0]  wr_datacount_o,
+    output wire                   empty_o,
+    output wire                   almost_empty_o,
+    output wire                   prog_empty_o,
+    output wire                   underflow_o,
+    output wire                   rd_valid_o,
+    output wire [RDATA_WIDTH-1:0] rdata,
+    output wire [RADDR_WIDTH :0]  rd_datacount_o,
+    output wire                   rst_busy
+); 
+
+localparam WR_DEPTH      = DEPTH;
+localparam WDATA_WIDTH   = DATA_WIDTH;
+localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           
+
+wire                   wr_rst_int;
+wire                   rd_rst_int;
+wire                   wr_en_int;
+wire                   rd_en_int;
+wire [WADDR_WIDTH-1:0] waddr;
+wire [RADDR_WIDTH-1:0] raddr;
+wire                   wr_clk_int;
+wire                   rd_clk_int;
+wire [WADDR_WIDTH :0]  wr_datacount_int;
+wire [RADDR_WIDTH :0]  rd_datacount_int;
+
+generate
+    if (ASYM_WIDTH_RATIO == 4) begin
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+            assign datacount_o    = wr_datacount_int;
+            assign wr_datacount_o = 'd0;
+            assign rd_datacount_o = 'd0;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+            assign datacount_o    = 'd0;
+            assign wr_datacount_o = wr_datacount_int;
+            assign rd_datacount_o = rd_datacount_int;
+        end
+    end
+    else begin
+        assign datacount_o    = 'd0;
+        assign wr_datacount_o = wr_datacount_int;
+        assign rd_datacount_o = rd_datacount_int;
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+        end
+    end    
+
+    if (!SYNC_CLK) begin
+        (* async_reg = "true" *) reg [1:0] wr_rst;
+        (* async_reg = "true" *) reg [1:0] rd_rst;
+        
+        always @ (posedge wr_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                wr_rst <= 2'b11;
+            else 
+                wr_rst <= {wr_rst[0],1'b0};            
+        end
+        
+        always @ (posedge rd_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                rd_rst <= 2'b11;
+            else 
+                rd_rst <= {rd_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_wr_rst_i;
+            assign rd_rst_int = a_rd_rst_i; 
+            assign rst_busy   = 1'b0;
+        end 
+        else begin
+            assign wr_rst_int = wr_rst[1];
+            assign rd_rst_int = rd_rst[1]; 
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end
+    else begin
+        (* async_reg = "true" *) reg [1:0] a_rst;
+        
+        always @ (posedge clk_i or posedge a_rst_i) begin
+            if (a_rst_i) 
+                a_rst <= 2'b11;
+            else 
+                a_rst <= {a_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_rst_i;
+            assign rd_rst_int = a_rst_i;
+            assign rst_busy   = 1'b0;
+        end
+        else begin
+            assign wr_rst_int = a_rst[1];
+            assign rd_rst_int = a_rst[1];   
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end 
+endgenerate
+
+`IP_MODULE_NAME(efx_fifo_ram) # (
+    .FAMILY        (FAMILY),
+    .MODE          (MODE),
+    .WR_DEPTH      (WR_DEPTH),
+    .RD_DEPTH      (RD_DEPTH),
+    .WDATA_WIDTH   (WDATA_WIDTH),
+    .RDATA_WIDTH   (RDATA_WIDTH),
+    .WADDR_WIDTH   (WADDR_WIDTH),
+    .RADDR_WIDTH   (RADDR_WIDTH),
+    .OUTPUT_REG    (OUTPUT_REG),
+    .RAM_MUX_RATIO (RAM_MUX_RATIO),
+    .ENDIANESS	   (ENDIANESS)
+) xefx_fifo_ram (
+    .wdata (wdata), 
+    .waddr (waddr),
+    .raddr (raddr), 
+    .we    (wr_en_int), 
+    .re    (rd_en_int),
+    .wclk  (wr_clk_int),
+    .rclk  (rd_clk_int),
+    .rdata (rdata)
+);
+
+`IP_MODULE_NAME(efx_fifo_ctl) # (
+    .FAMILY             (FAMILY),
+    .SYNC_CLK           (SYNC_CLK),
+    .SYNC_STAGE         (SYNC_STAGE),
+    .MODE               (MODE),
+    .WR_DEPTH           (WR_DEPTH),
+    .WADDR_WIDTH        (WADDR_WIDTH),
+    .RADDR_WIDTH        (RADDR_WIDTH),
+    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
+    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .ALMOST_FLAG        (ALMOST_FLAG),
+    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
+    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
+    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
+    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
+    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
+    .OUTPUT_REG         (OUTPUT_REG),
+    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG)
+) xefx_fifo_ctl (
+    .wr_rst          (wr_rst_int),
+    .rd_rst          (rd_rst_int),
+    .wclk            (wr_clk_int),
+    .rclk            (rd_clk_int),
+    .we              (wr_en_i),
+    .re              (rd_en_i),
+    .wr_full         (full_o),
+    .wr_ack          (wr_ack_o),
+    .rd_empty        (empty_o),
+    .wr_almost_full  (almost_full_o),
+    .rd_almost_empty (almost_empty_o),
+    .wr_prog_full    (prog_full_o),
+    .rd_prog_empty   (prog_empty_o),
+    .wr_en_int       (wr_en_int),
+    .rd_en_int       (rd_en_int),
+    .waddr           (waddr),
+    .raddr           (raddr),
+    .wr_datacount    (wr_datacount_int),
+    .rd_datacount    (rd_datacount_int),
+    .rd_vld          (rd_valid_o),
+    .wr_overflow     (overflow_o),
+    .rd_underflow    (underflow_o)
+);
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer width2depth;
+input [31:0] width;
+begin : fnWidth2Depth
+    width2depth = width**2;
+end
+endfunction
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ram) #(
+    parameter FAMILY        = "TRION",
+    parameter MODE          = "STANDARD",
+    parameter WR_DEPTH      = 512,
+    parameter RD_DEPTH      = 512,
+    parameter WDATA_WIDTH   = 8,
+    parameter RDATA_WIDTH   = 8,
+    parameter WADDR_WIDTH   = 9,
+    parameter RADDR_WIDTH   = 9,
+    parameter OUTPUT_REG    = 1,
+    parameter RAM_MUX_RATIO = 4,
+    parameter ENDIANESS 	= 0 //0: Big endian (default)   1: Little endian 
+) (
+    input  wire                     wclk,
+    input  wire                     rclk,
+    input  wire                     we,
+    input  wire                     re,
+    input  wire [(WDATA_WIDTH-1):0] wdata,
+    input  wire [(WADDR_WIDTH-1):0] waddr,
+    input  wire [(RADDR_WIDTH-1):0] raddr,
+    output wire [(RDATA_WIDTH-1):0] rdata
+);
+
+localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
+localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
+localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
+                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
+                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";
+
+reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
+reg [RDATA_WIDTH-1:0]    r_rdata_1P;
+reg [RDATA_WIDTH-1:0]    r_rdata_2P;
+
+wire                     re_int;
+
+generate
+    if (FAMILY == "TRION") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            if (ENDIANESS == 0) begin 
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                    end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                end
+                always @ (posedge rclk) begin 
+                	if (re_int) begin
+                		r_rdata_1P <= ram[raddr];
+                	end
+                		r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end
+        
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            //integer i;
+        	//reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr; 
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end 
+            end
+            else begin //endianess == 1
+            	always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        		always @ (posedge rclk) begin
+        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    	end
+                        	r_rdata_2P <= r_rdata_1P;
+                    end
+                end
+            end
+        end
+        if (OUTPUT_REG) begin
+            assign re_int = re;
+            assign rdata  = r_rdata_2P;            
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end
+    end
+    else if (FAMILY == "TITANIUM") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            //integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            if (ENDIANESS == 0) begin
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+            
+            else begin //endianess == 1
+            	integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            	always @ (posedge wclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (we) begin
+                            	ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                        end
+                    end
+                 end
+               	always @ (posedge rclk) begin 
+               		if (re_int) begin
+               			r_rdata_1P <= ram[raddr];
+               			r_rdata_2P <= r_rdata_1P;
+               		end
+               	end
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+        	//integer i;
+            //reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+        	if (ENDIANESS == 0) begin
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+            	reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = RAM_MUX_RATIO-1-i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+            
+            else begin //endianess ==1
+        		always @ (posedge wclk) begin
+        			if (we)
+        				ram[waddr] <= wdata;
+        		end
+        		integer i;
+        		reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            	always @ (posedge rclk) begin
+            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    	lsbaddr = i;
+                    	if (re_int) begin
+                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    		r_rdata_2P                                                               <= r_rdata_1P;
+                    	end
+                    end
+                end 
+            end
+        end
+        if (MODE == "STANDARD") begin     
+            if (OUTPUT_REG) begin
+                reg re_r;
+                always @ (posedge rclk) begin
+                    re_r <= re;
+                end
+                assign re_int = re | re_r;        
+                assign rdata  = r_rdata_2P;            
+            end
+            else begin
+                assign re_int = re;
+                assign rdata  = r_rdata_1P;
+            end
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end        
+    end
+endgenerate
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module `IP_MODULE_NAME(efx_fifo_ctl) # (
+    parameter FAMILY             = "TRION",
+    parameter SYNC_CLK           = 1,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter WR_DEPTH           = 512,
+    parameter WADDR_WIDTH        = 9,
+    parameter RADDR_WIDTH        = 9,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter RAM_MUX_RATIO      = 1,
+    parameter PIPELINE_REG       = 1,
+    parameter ALMOST_FLAG        = 1,
+    parameter PROGRAMMABLE_FULL  = "NONE",
+    parameter PROG_FULL_ASSERT   = 0,
+    parameter PROG_FULL_NEGATE   = 0,
+    parameter PROGRAMMABLE_EMPTY = "NONE",
+    parameter PROG_EMPTY_ASSERT  = 0,
+    parameter PROG_EMPTY_NEGATE  = 0,
+    parameter OUTPUT_REG         = 0,
+    parameter HANDSHAKE_FLAG     = 1
+)(
+    input   wire                   wr_rst,
+    input   wire                   rd_rst,
+    input   wire                   wclk,
+    input   wire                   rclk,
+    input   wire                   we,
+    input   wire                   re,
+    output  wire                   wr_full,
+    output  reg                    wr_ack,
+    output  wire                   wr_almost_full,
+    output  wire                   rd_empty,
+    output  wire                   rd_almost_empty,
+    output  wire                   wr_prog_full,
+    output  wire                   rd_prog_empty,
+    output  wire                   wr_en_int,
+    output  wire                   rd_en_int,
+    output  wire [WADDR_WIDTH-1:0] waddr,
+    output  wire [RADDR_WIDTH-1:0] raddr,
+    output  wire [WADDR_WIDTH:0]   wr_datacount,
+    output  wire [RADDR_WIDTH:0]   rd_datacount,
+    output  wire                   rd_vld,
+    output  reg                    wr_overflow,
+    output  reg                    rd_underflow
+);
+
+reg  [WADDR_WIDTH:0] waddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr_r;
+reg                  rd_valid;
+
+wire [RADDR_WIDTH:0] raddr_cntr_w;
+wire [WADDR_WIDTH:0] waddr_int;
+wire [RADDR_WIDTH:0] raddr_int;
+wire [RADDR_WIDTH:0] raddr_int_dcount;
+wire [RADDR_WIDTH:0] raddr_dcount;
+wire                 rd_empty_int;
+wire [WADDR_WIDTH:0] wr_datacount_int;
+wire [RADDR_WIDTH:0] rd_datacount_int;
+
+assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
+assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
+assign wr_en_int = we & ~wr_full;
+
+generate
+    if (MODE == "FWFT") begin    
+        reg init_set;
+        reg rd_empty_fwft;
+        assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
+        assign rd_empty      = rd_empty_fwft;
+        assign raddr_cntr_w  = ~rd_empty ? raddr_cntr_r/*raddr_cntr-1*/ : raddr_cntr;
+        
+        if (ASYM_WIDTH_RATIO < 4) begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_empty ? rd_datacount_int : ~init_set ? (rd_datacount_int+1'b1) : rd_datacount_int;
+        end
+        else begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_datacount_int;        
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                init_set <= 1'b1;
+            end
+            else if (~init_set & rd_empty) begin
+                init_set <= 1'b1;            
+            end
+            else if (~rd_empty_int) begin
+                init_set <= 1'b0;            
+            end
+            else if (rd_empty) begin
+                init_set <= 1'b1;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_empty_fwft <= 1'b1;
+            end
+            else if (rd_en_int) begin
+                rd_empty_fwft <= 1'b0;            
+            end
+            else if (re) begin
+                rd_empty_fwft <= 1'b1;            
+            end
+        end          
+        
+        if (FAMILY == "TRION") begin
+            if (OUTPUT_REG) begin
+                always @ (posedge rclk or posedge rd_rst) begin
+                    if (rd_rst) begin
+                        rd_valid <= 1'b0;
+                    end
+                    else begin
+                        rd_valid <= ~rd_empty;
+                    end
+                end
+                assign rd_vld = rd_valid;                
+            end    
+            else begin
+                assign rd_vld = ~rd_empty;                
+            end
+        end
+        else begin
+            assign rd_vld = ~rd_empty;
+        end
+    end
+    else begin
+        assign rd_en_int     = re & ~rd_empty_int;
+        assign rd_empty      = rd_empty_int;
+        assign raddr_cntr_w  = raddr_cntr;
+        assign wr_datacount  = wr_datacount_int;
+        assign rd_datacount  = rd_datacount_int;
+        
+        if (OUTPUT_REG) begin
+            reg rd_valid_r;
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid_r <= 'h0;
+                    rd_valid   <= 'h0;
+                end
+                else begin
+                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
+                end
+            end
+            assign rd_vld = rd_valid;            
+        end
+        else begin
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid  <= 'h0;
+                end
+                else begin
+                    rd_valid <= rd_en_int;
+                end
+            end
+            assign rd_vld = rd_valid;
+        end
+    end
+    
+    if (ALMOST_FLAG) begin
+        assign wr_almost_full   = wr_datacount_int >= WR_DEPTH-1;
+        assign rd_almost_empty  = rd_datacount_int <= 'd1;  
+    end
+    else begin
+        assign wr_almost_full   = 1'b0;
+        assign rd_almost_empty  = 1'b0;        
+    end
+    
+    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end  
+    end
+    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end              
+    end
+    else begin
+        assign wr_prog_full  = 1'b0; 
+    end
+        
+    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end
+    end
+    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end  
+    end
+    else begin
+        assign rd_prog_empty  = 1'b0; 
+    end
+    
+    if (HANDSHAKE_FLAG) begin
+    
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_ack <= 1'b0;
+            end
+            else begin
+                wr_ack <= wr_en_int & ~wr_overflow;
+            end
+        end
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_overflow <= 1'b0;
+            end
+            else if (we && wr_full) begin
+                wr_overflow <= 1'b1;
+            end
+            else begin
+                wr_overflow <= 1'b0;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_underflow <= 1'b0;
+            end
+            else if (re && rd_empty) begin
+                rd_underflow <= 1'b1;
+            end
+            else begin
+                rd_underflow <= 1'b0;            
+            end
+        end
+    end
+    
+    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
+    
+    if (ASYM_WIDTH_RATIO < 4) begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
+        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
+        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
+    end
+    else begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
+        assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
+        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w;
+    end
+endgenerate
+
+always @ (posedge wclk or posedge wr_rst) begin
+    if (wr_rst) begin
+        waddr_cntr <= 'h0;
+    end
+    else if (wr_en_int) begin
+        waddr_cntr <= waddr_cntr + 1'b1;
+    end
+end
+
+always @ (posedge rclk or posedge rd_rst) begin
+    if (rd_rst) begin
+        raddr_cntr   <= 'h0;
+        raddr_cntr_r <= 'h0;
+    end
+    else if (rd_en_int) begin
+        raddr_cntr   <= raddr_cntr + 1'b1;
+        raddr_cntr_r <= raddr_cntr;
+    end
+end
+
+generate
+    if (SYNC_CLK) begin
+        assign waddr_int        = waddr_cntr;
+        assign raddr_int        = raddr_cntr_w;
+    end
+    else begin
+        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
+        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
+        
+        wire [RADDR_WIDTH:0] raddr_cntr_gry;
+        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
+        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
+        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;
+
+        if (PIPELINE_REG) begin
+            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
+            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
+        
+            assign waddr_int        = waddr_cntr_sync_g2b_r;
+            assign raddr_int        = raddr_cntr_sync_g2b_r;
+            
+            always @ (posedge wclk or posedge wr_rst) begin
+                if (wr_rst) begin
+                    raddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
+                end
+            end
+            
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    waddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
+                end
+            end
+        end
+        else begin
+            assign waddr_int        = waddr_cntr_sync_g2b;
+            assign raddr_int        = raddr_cntr_sync_g2b;        
+        end
+      
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                raddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                raddr_cntr_gry_r <= raddr_cntr_gry;
+            end
+        end
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_bin2gray    (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync   (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                waddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                waddr_cntr_gry_r <= waddr_cntr_gry;
+            end
+        end        
+        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
+        `IP_MODULE_NAME(efx_fifo_datasync) # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
+        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        
+
+    end
+endgenerate
+endmodule
+
+`undef IP_UUID
+`undef IP_NAME_CONCAT
+`undef IP_MODULE_NAME

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Ti60F225_devkit/asyn_fifo_define.vh

@@ -0,0 +1,63 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2023.2.307
+// IP Version: 5.1
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+
+localparam SYNC_CLK = 0;
+localparam SYNC_STAGE = 2;
+localparam DATA_WIDTH = 11;
+localparam MODE = "FWFT";
+localparam OUTPUT_REG = 0;
+localparam PROG_FULL_ASSERT = 128;
+localparam PROGRAMMABLE_FULL = "STATIC_SINGLE";
+localparam PROG_FULL_NEGATE = 128;
+localparam PROGRAMMABLE_EMPTY = "NONE";
+localparam PROG_EMPTY_ASSERT = 0;
+localparam PROG_EMPTY_NEGATE = 2;
+localparam OPTIONAL_FLAGS = 1;
+localparam PIPELINE_REG = 1;
+localparam DEPTH = 8192;
+localparam FAMILY = "TITANIUM";
+localparam ASYM_WIDTH_RATIO = 4;
+localparam BYPASS_RESET_SYNC = 0;
+localparam ENDIANESS = 0;

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Ti60F225_devkit/efx_symmetric_width_fifo_top.v

@@ -0,0 +1,1291 @@
+// =============================================================================
+// Generated by efx_ipmgr
+// Version: 2021.M.200
+// IP Version: 1.0
+// =============================================================================
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//                                                                       
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//                                                                       
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.                                                
+//
+////////////////////////////////////////////////////////////////////////////////
+module efx_symmetric_width_fifo_top # (
+parameter FAMILY             = "TITANIUM",
+parameter SYNC_CLK           = 1,
+parameter OUTPUT_REG         = 0,
+parameter MODE               = "STANDARD",
+parameter PIPELINE_REG       = 1,
+parameter OPTIONAL_FLAGS     = 0,
+parameter PROGRAMMABLE_FULL  = "NONE",
+parameter PROGRAMMABLE_EMPTY = "NONE",
+parameter ASYM_WIDTH_RATIO   = 4,
+parameter DATA_WIDTH         = 32,
+parameter DEPTH              = 512
+) (
+output almost_full_o,
+output prog_full_o,
+output full_o,
+output overflow_o,
+output wr_ack_o,
+output empty_o,
+output almost_empty_o,
+output prog_empty_o,
+output underflow_o,
+output rd_valid_o,
+output [32:0] rdata,
+input wr_clk_i,
+input rd_clk_i,
+input wr_en_i,
+input rd_en_i,
+input [32:0] wdata,
+output [8:0] wr_datacount_o,
+output [8:0] rd_datacount_o,
+input a_rst_i,
+output rst_busy
+);
+efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b #(
+.OPTIONAL_FLAGS (OPTIONAL_FLAGS),
+.SYNC_CLK (SYNC_CLK),
+.DEPTH (DEPTH),
+.DATA_WIDTH (DATA_WIDTH),
+.ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO),
+.MODE (MODE),
+.OUTPUT_REG (OUTPUT_REG),
+.BYPASS_RESET_SYNC (0),
+.PROG_FULL_ASSERT (7),
+.PIPELINE_REG (PIPELINE_REG),
+.PROG_FULL_NEGATE (3),
+.SYNC_STAGE (2),
+.PROG_EMPTY_ASSERT (2),
+.PROG_EMPTY_NEGATE (3),
+.PROGRAMMABLE_FULL (PROGRAMMABLE_FULL),
+.PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+.FAMILY (FAMILY)
+) u_efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b(
+.almost_full_o ( almost_full_o ),
+.prog_full_o ( prog_full_o ),
+.full_o ( full_o ),
+.overflow_o ( overflow_o ),
+.wr_ack_o ( wr_ack_o ),
+.empty_o ( empty_o ),
+.almost_empty_o ( almost_empty_o ),
+.prog_empty_o ( prog_empty_o ),
+.underflow_o ( underflow_o ),
+.rd_valid_o ( rd_valid_o ),
+.rdata ( rdata ),
+.wr_clk_i ( wr_clk_i ),
+.rd_clk_i ( rd_clk_i ),
+.wr_en_i ( wr_en_i ),
+.rd_en_i ( rd_en_i ),
+.wdata ( wdata ),
+.wr_datacount_o ( wr_datacount_o ),
+.rd_datacount_o ( rd_datacount_o ),
+.rst_busy ( rst_busy ),
+.a_rst_i ( a_rst_i )
+);
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   pipe_reg.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Parallel Pipelining Shift Register
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+module efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b #(
+    parameter STAGE = 32,
+    parameter WIDTH = 4
+) (
+ input  wire             clk_i,
+ input  wire [WIDTH-1:0] d_i,
+ output wire [WIDTH-1:0] d_o
+);
+
+(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
+integer i;
+
+always @(posedge clk_i) begin
+  for (i=STAGE-1; i>0; i = i - 1) begin
+    pipe_reg[i] <= pipe_reg[i-1];
+  end
+  pipe_reg[0] <= d_i;
+end
+assign d_o = pipe_reg[STAGE-1];
+   
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   gray2bin.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Gray to Binary Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] bin_o,
+ // input
+ input [WIDTH-1:0] gray_i);
+
+//---------------------------------------------------------------------
+// Recursive Module
+// Description: reduction xor
+generate
+   if (WIDTH > 1) begin
+      wire [1:0] bin_1;
+      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
+      if (WIDTH == 2) begin
+	 assign bin_o = bin_1;
+      end
+      else begin
+	 assign bin_o[WIDTH-1] = bin_1[1];
+	 efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
+      end
+   end
+   else /* if (WIDTH == 1) */
+     assign bin_o = gray_i;
+endgenerate
+   
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   bin2gray.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      Binary to Gray Encoding Convertor
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+// 1.0 Initial rev
+//
+// *******************************
+
+`resetall
+`timescale 1ns/1ps
+
+module efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b
+#(parameter WIDTH=5)
+(// outputs
+ output wire [WIDTH-1:0] gray_o,
+ // input
+ input [WIDTH-1:0] bin_i
+ );
+
+//---------------------------------------------------------------------
+// Function :   bit_xor
+// Description: reduction xor
+function bit_xor (
+  input [31:0] nex_bit,
+  input [31:0] curr_bit,
+  input [WIDTH-1:0] xor_in);
+  begin : fn_bit_xor
+    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
+  end
+endfunction
+
+// Convert Binary to Gray, bit by bit
+generate 
+begin
+  genvar bit_idx;
+  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
+    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
+  end
+  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
+end
+endgenerate
+
+endmodule 
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_top_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    parameter FAMILY             = "TRION",       // New Param
+    parameter SYNC_CLK           = 0,
+    parameter BYPASS_RESET_SYNC  = 0,             // New Param
+    parameter SYNC_STAGE         = 2,             // New Param
+    parameter MODE               = "STANDARD",
+    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
+    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
+    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
+    parameter OPTIONAL_FLAGS     = 1,             // Reverted
+    parameter OUTPUT_REG         = 0,
+    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_FULL_ASSERT   = 27,
+    parameter PROG_FULL_NEGATE   = 23,
+    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
+    parameter PROG_EMPTY_ASSERT  = 5,
+    parameter PROG_EMPTY_NEGATE  = 7,
+    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
+    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter WADDR_WIDTH        = depth2width(DEPTH),
+    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
+    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
+    parameter RADDR_WIDTH        = depth2width(RD_DEPTH)
+
+)(
+    input  wire                   a_rst_i,
+    input  wire                   a_wr_rst_i,
+    input  wire                   a_rd_rst_i,
+    input  wire                   clk_i,
+    input  wire                   wr_clk_i,
+    input  wire                   rd_clk_i,
+    input  wire                   wr_en_i,
+    input  wire                   rd_en_i,
+    input  wire [DATA_WIDTH-1:0]  wdata,
+    output wire                   almost_full_o,
+    output wire                   prog_full_o,
+    output wire                   full_o,
+    output wire                   overflow_o,
+    output wire                   wr_ack_o,
+    output wire [WADDR_WIDTH :0]  datacount_o,
+    output wire [WADDR_WIDTH :0]  wr_datacount_o,
+    output wire                   empty_o,
+    output wire                   almost_empty_o,
+    output wire                   prog_empty_o,
+    output wire                   underflow_o,
+    output wire                   rd_valid_o,
+    output wire [RDATA_WIDTH-1:0] rdata,
+    output wire [RADDR_WIDTH :0]  rd_datacount_o,
+    output wire                   rst_busy
+); 
+
+localparam WR_DEPTH      = DEPTH;
+localparam WDATA_WIDTH   = DATA_WIDTH;
+localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
+                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
+                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           
+
+wire                   wr_rst_int;
+wire                   rd_rst_int;
+wire                   wr_en_int;
+wire                   rd_en_int;
+wire [WADDR_WIDTH-1:0] waddr;
+wire [RADDR_WIDTH-1:0] raddr;
+wire                   wr_clk_int;
+wire                   rd_clk_int;
+wire [WADDR_WIDTH :0]  wr_datacount_int;
+wire [RADDR_WIDTH :0]  rd_datacount_int;
+
+generate
+    if (ASYM_WIDTH_RATIO == 4) begin
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+            assign datacount_o    = wr_datacount_int;
+            assign wr_datacount_o = 'd0;
+            assign rd_datacount_o = 'd0;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+            assign datacount_o    = 'd0;
+            assign wr_datacount_o = wr_datacount_int;
+            assign rd_datacount_o = rd_datacount_int;
+        end
+    end
+    else begin
+        assign datacount_o    = 'd0;
+        assign wr_datacount_o = wr_datacount_int;
+        assign rd_datacount_o = rd_datacount_int;
+        if (SYNC_CLK) begin
+            assign wr_clk_int     = clk_i;    
+            assign rd_clk_int     = clk_i;
+        end
+        else begin
+            assign wr_clk_int     = wr_clk_i;    
+            assign rd_clk_int     = rd_clk_i;
+        end
+    end    
+
+    if (!SYNC_CLK) begin
+        (* async_reg = "true" *) reg [1:0] wr_rst;
+        (* async_reg = "true" *) reg [1:0] rd_rst;
+        
+        always @ (posedge wr_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                wr_rst <= 2'b11;
+            else 
+                wr_rst <= {wr_rst[0],1'b0};            
+        end
+        
+        always @ (posedge rd_clk_int or posedge a_rst_i) begin
+            if (a_rst_i) 
+                rd_rst <= 2'b11;
+            else 
+                rd_rst <= {rd_rst[0],1'b0};            
+        end
+
+        if (BYPASS_RESET_SYNC) begin
+            assign wr_rst_int = a_wr_rst_i;
+            assign rd_rst_int = a_rd_rst_i; 
+            assign rst_busy   = 1'b0;
+        end 
+        else begin
+            assign wr_rst_int = wr_rst[1];
+            assign rd_rst_int = rd_rst[1]; 
+            assign rst_busy   = wr_rst_int | rd_rst_int;
+        end
+    end
+    else begin
+        (* async_reg = "true" *) reg [1:0] a_rst;
+        
+        always @ (posedge clk_i or posedge a_rst_i) begin
+            if (a_rst_i) 
+                a_rst <= 2'b11;
+            else 
+                a_rst <= {a_rst[0],1'b0};            
+        end
+
+        assign wr_rst_int = a_rst;
+        assign rd_rst_int = a_rst;   
+        assign rst_busy   = wr_rst_int | rd_rst_int;
+    end 
+endgenerate
+
+efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    .FAMILY        (FAMILY),
+    .MODE          (MODE),
+    .WR_DEPTH      (WR_DEPTH),
+    .RD_DEPTH      (RD_DEPTH),
+    .WDATA_WIDTH   (WDATA_WIDTH),
+    .RDATA_WIDTH   (RDATA_WIDTH),
+    .WADDR_WIDTH   (WADDR_WIDTH),
+    .RADDR_WIDTH   (RADDR_WIDTH),
+    .OUTPUT_REG    (OUTPUT_REG),
+    .RAM_MUX_RATIO (RAM_MUX_RATIO)
+) xefx_fifo_ram (
+    .wdata (wdata), 
+    .waddr (waddr),
+    .raddr (raddr), 
+    .we    (wr_en_int), 
+    .re    (rd_en_int),
+    .wclk  (wr_clk_int),
+    .rclk  (rd_clk_int),
+    .rdata (rdata)
+);
+
+efx_fifo_ctl_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    .FAMILY             (FAMILY),
+    .SYNC_CLK           (SYNC_CLK),
+    .SYNC_STAGE         (SYNC_STAGE),
+    .MODE               (MODE),
+    .WR_DEPTH           (WR_DEPTH),
+    .WADDR_WIDTH        (WADDR_WIDTH),
+    .RADDR_WIDTH        (RADDR_WIDTH),
+    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
+    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
+    .PIPELINE_REG       (PIPELINE_REG),
+    .ALMOST_FLAG        (ALMOST_FLAG),
+    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
+    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
+    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
+    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
+    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
+    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
+    .OUTPUT_REG         (OUTPUT_REG),
+    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG)
+) xefx_fifo_ctl (
+    .wr_rst          (wr_rst_int),
+    .rd_rst          (rd_rst_int),
+    .wclk            (wr_clk_int),
+    .rclk            (rd_clk_int),
+    .we              (wr_en_i),
+    .re              (rd_en_i),
+    .wr_full         (full_o),
+    .wr_ack          (wr_ack_o),
+    .rd_empty        (empty_o),
+    .wr_almost_full  (almost_full_o),
+    .rd_almost_empty (almost_empty_o),
+    .wr_prog_full    (prog_full_o),
+    .rd_prog_empty   (prog_empty_o),
+    .wr_en_int       (wr_en_int),
+    .rd_en_int       (rd_en_int),
+    .waddr           (waddr),
+    .raddr           (raddr),
+    .wr_datacount    (wr_datacount_int),
+    .rd_datacount    (rd_datacount_int),
+    .rd_vld          (rd_valid_o),
+    .wr_overflow     (overflow_o),
+    .rd_underflow    (underflow_o)
+);
+
+function integer depth2width;
+input [31:0] depth;
+begin : fnDepth2Width
+    if (depth > 1) begin
+        depth = depth - 1;
+        for (depth2width=0; depth>0; depth2width = depth2width + 1)
+            depth = depth>>1;
+        end
+    else
+    depth2width = 0;
+end
+endfunction 
+
+function integer width2depth;
+input [31:0] width;
+begin : fnWidth2Depth
+    width2depth = width**2;
+end
+endfunction
+
+function integer rdwidthcompute;
+input [31:0] asym_option;
+input [31:0] wr_width;
+begin : RdWidthCompute
+    rdwidthcompute = (asym_option==0)? wr_width/16 :
+                     (asym_option==1)? wr_width/8  :
+                     (asym_option==2)? wr_width/4  :
+                     (asym_option==3)? wr_width/2  :
+                     (asym_option==4)? wr_width/1  :
+                     (asym_option==5)? wr_width*2  :
+                     (asym_option==6)? wr_width*4  :
+                     (asym_option==7)? wr_width*8  :
+                     (asym_option==8)? wr_width*16 : wr_width/1;
+end
+endfunction
+
+function integer rddepthcompute;
+input [31:0] wr_depth;
+input [31:0] wr_width;
+input [31:0] rd_width;
+begin : RdDepthCompute
+    rddepthcompute = (wr_depth * wr_width) / rd_width;
+end
+endfunction
+
+endmodule
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_ram_f81c17844c0a4d5fa30d89ba7d75c52b #(
+    parameter FAMILY        = "TRION",
+    parameter MODE          = "STANDARD",
+    parameter WR_DEPTH      = 512,
+    parameter RD_DEPTH      = 512,
+    parameter WDATA_WIDTH   = 8,
+    parameter RDATA_WIDTH   = 8,
+    parameter WADDR_WIDTH   = 9,
+    parameter RADDR_WIDTH   = 9,
+    parameter OUTPUT_REG    = 1,
+    parameter RAM_MUX_RATIO = 4
+) (
+    input  wire                     wclk,
+    input  wire                     rclk,
+    input  wire                     we,
+    input  wire                     re,
+    input  wire [(WDATA_WIDTH-1):0] wdata,
+    input  wire [(WADDR_WIDTH-1):0] waddr,
+    input  wire [(RADDR_WIDTH-1):0] raddr,
+    output wire [(RDATA_WIDTH-1):0] rdata
+);
+
+localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
+localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
+localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
+localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
+                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
+                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
+                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
+                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";
+
+reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
+reg [RDATA_WIDTH-1:0]    r_rdata_1P;
+reg [RDATA_WIDTH-1:0]    r_rdata_2P;
+
+wire                     re_int;
+
+generate
+    if (FAMILY == "TRION") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;
+            always @ (posedge wclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                    end
+                end
+            end
+                
+            always @ (posedge rclk) begin 
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                end
+                r_rdata_2P <= r_rdata_1P;
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+ 
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr; 
+            always @ (posedge rclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (re_int) begin
+                        r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                    end
+                        r_rdata_2P <= r_rdata_1P;
+                end
+            end 
+        end     
+
+        if (OUTPUT_REG) begin
+            assign re_int = re;
+            assign rdata  = r_rdata_2P;            
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end
+    end
+    else if (FAMILY == "TITANIUM") begin
+        if (RDATA_WDATA_RATIO == "ONE") begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+    
+            always @ (posedge rclk) begin
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end 
+        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            always @ (posedge wclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (we) begin
+                            ram[{waddr,lsbaddr}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
+                    end
+                end
+            end
+                
+            always @ (posedge rclk) begin 
+                if (re_int) begin
+                    r_rdata_1P <= ram[raddr];
+                    r_rdata_2P <= r_rdata_1P;
+                end
+            end
+        end
+        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
+            always @ (posedge wclk) begin
+                if (we)
+                    ram[waddr] <= wdata;
+            end
+
+            integer i;
+            reg  [LSB_WIDTH-1 :0 ]   lsbaddr;        
+            always @ (posedge rclk) begin
+                for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
+                    lsbaddr = RAM_MUX_RATIO-1-i;
+                    if (re_int) begin
+                        r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,lsbaddr}];
+                        r_rdata_2P                                                               <= r_rdata_1P;
+                    end
+                end
+            end 
+        end     
+
+        if (MODE == "STANDARD") begin     
+            if (OUTPUT_REG) begin
+                reg re_r;
+                always @ (posedge rclk) begin
+                    re_r <= re;
+                end
+                assign re_int = re | re_r;        
+                assign rdata  = r_rdata_2P;            
+            end
+            else begin
+                assign re_int = re;
+                assign rdata  = r_rdata_1P;
+            end
+        end
+        else begin
+            assign re_int = re;
+            assign rdata  = r_rdata_1P;
+        end        
+    end
+endgenerate
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
+//
+// This   document  contains  proprietary information  which   is        
+// protected by  copyright. All rights  are reserved.  This notice       
+// refers to original work by Efinix, Inc. which may be derivitive       
+// of other work distributed under license of the authors.  In the       
+// case of derivative work, nothing in this notice overrides the         
+// original author's license agreement.  Where applicable, the           
+// original license agreement is included in it's original               
+// unmodified form immediately below this header.                        
+//
+// WARRANTY DISCLAIMER.                                                  
+//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
+//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
+//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
+//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
+//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
+//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
+//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
+//
+// LIMITATION OF LIABILITY.                                              
+//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
+//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
+//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
+//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
+//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
+//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
+//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
+//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
+//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
+//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
+//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
+//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
+//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
+//     APPLY TO LICENSEE.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////
+//           _____       
+//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
+//         / /       \   
+//        / /  ..    /   simple_dual_port_ram_fifo.v
+//       / / .'     /    
+//    __/ /.'      /     Description:
+//   __   \       /      EFX FIFO
+//  /_/ /\ \_____/ /     
+// ____/  \_______/      
+//
+// *******************************
+// Revisions:
+//
+// *******************************
+
+module efx_fifo_ctl_f81c17844c0a4d5fa30d89ba7d75c52b # (
+    parameter FAMILY             = "TRION",
+    parameter SYNC_CLK           = 1,
+    parameter SYNC_STAGE         = 2,
+    parameter MODE               = "STANDARD",
+    parameter WR_DEPTH           = 512,
+    parameter WADDR_WIDTH        = 9,
+    parameter RADDR_WIDTH        = 9,
+    parameter ASYM_WIDTH_RATIO   = 4,
+    parameter RAM_MUX_RATIO      = 1,
+    parameter PIPELINE_REG       = 1,
+    parameter ALMOST_FLAG        = 1,
+    parameter PROGRAMMABLE_FULL  = "NONE",
+    parameter PROG_FULL_ASSERT   = 0,
+    parameter PROG_FULL_NEGATE   = 0,
+    parameter PROGRAMMABLE_EMPTY = "NONE",
+    parameter PROG_EMPTY_ASSERT  = 0,
+    parameter PROG_EMPTY_NEGATE  = 0,
+    parameter OUTPUT_REG         = 0,
+    parameter HANDSHAKE_FLAG     = 1
+)(
+    input   wire                   wr_rst,
+    input   wire                   rd_rst,
+    input   wire                   wclk,
+    input   wire                   rclk,
+    input   wire                   we,
+    input   wire                   re,
+    output  wire                   wr_full,
+    output  reg                    wr_ack,
+    output  wire                   wr_almost_full,
+    output  wire                   rd_empty,
+    output  wire                   rd_almost_empty,
+    output  wire                   wr_prog_full,
+    output  wire                   rd_prog_empty,
+    output  wire                   wr_en_int,
+    output  wire                   rd_en_int,
+    output  wire [WADDR_WIDTH-1:0] waddr,
+    output  wire [RADDR_WIDTH-1:0] raddr,
+    output  wire [WADDR_WIDTH:0]   wr_datacount,
+    output  wire [RADDR_WIDTH:0]   rd_datacount,
+    output  wire                   rd_vld,
+    output  reg                    wr_overflow,
+    output  reg                    rd_underflow
+);
+
+reg  [WADDR_WIDTH:0] waddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr;
+reg  [RADDR_WIDTH:0] raddr_cntr_r;
+reg                  rd_valid;
+
+wire [RADDR_WIDTH:0] raddr_cntr_w;
+wire [WADDR_WIDTH:0] waddr_int;
+wire [RADDR_WIDTH:0] raddr_int;
+wire [RADDR_WIDTH:0] raddr_int_dcount;
+wire [RADDR_WIDTH:0] raddr_dcount;
+wire                 rd_empty_int;
+wire [WADDR_WIDTH:0] wr_datacount_int;
+wire [RADDR_WIDTH:0] rd_datacount_int;
+
+assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
+assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
+assign wr_en_int = we & ~wr_full;
+
+generate
+    if (MODE == "FWFT") begin    
+        reg init_set;
+        reg rd_empty_fwft;
+        assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
+        assign rd_empty      = rd_empty_fwft;
+        assign raddr_cntr_w  = ~rd_empty ? raddr_cntr_r/*raddr_cntr-1*/ : raddr_cntr;
+        
+        if (ASYM_WIDTH_RATIO < 4) begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_empty ? rd_datacount_int : ~init_set ? (rd_datacount_int+1'b1) : rd_datacount_int;
+        end
+        else begin
+            assign wr_datacount  = wr_datacount_int;
+            assign rd_datacount  = rd_datacount_int;        
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                init_set <= 1'b1;
+            end
+            else if (~init_set & rd_empty) begin
+                init_set <= 1'b1;            
+            end
+            else if (~rd_empty_int) begin
+                init_set <= 1'b0;            
+            end
+            else if (rd_empty) begin
+                init_set <= 1'b1;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_empty_fwft <= 1'b1;
+            end
+            else if (rd_en_int) begin
+                rd_empty_fwft <= 1'b0;            
+            end
+            else if (re) begin
+                rd_empty_fwft <= 1'b1;            
+            end
+        end          
+        
+        if (FAMILY == "TRION") begin
+            if (OUTPUT_REG) begin
+                always @ (posedge rclk or posedge rd_rst) begin
+                    if (rd_rst) begin
+                        rd_valid <= 1'b0;
+                    end
+                    else begin
+                        rd_valid <= ~rd_empty;
+                    end
+                end
+                assign rd_vld = rd_valid;                
+            end    
+            else begin
+                assign rd_vld = ~rd_empty;                
+            end
+        end
+        else begin
+            assign rd_vld = ~rd_empty;
+        end
+    end
+    else begin
+        assign rd_en_int     = re & ~rd_empty_int;
+        assign rd_empty      = rd_empty_int;
+        assign raddr_cntr_w  = raddr_cntr;
+        assign wr_datacount  = wr_datacount_int;
+        assign rd_datacount  = rd_datacount_int;
+        
+        if (OUTPUT_REG) begin
+            reg rd_valid_r;
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid_r <= 'h0;
+                    rd_valid   <= 'h0;
+                end
+                else begin
+                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
+                end
+            end
+            assign rd_vld = rd_valid;            
+        end
+        else begin
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    rd_valid  <= 'h0;
+                end
+                else begin
+                    rd_valid <= rd_en_int;
+                end
+            end
+            assign rd_vld = rd_valid;
+        end
+    end
+    
+    if (ALMOST_FLAG) begin
+        assign wr_almost_full   = wr_datacount_int >= WR_DEPTH-1;
+        assign rd_almost_empty  = rd_datacount_int <= 'd1;  
+    end
+    else begin
+        assign wr_almost_full   = 1'b0;
+        assign rd_almost_empty  = 1'b0;        
+    end
+    
+    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end  
+    end
+    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
+        reg    wr_prog_full_int;
+        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_prog_full_int  <= 1'b0;
+            end
+            else begin
+                wr_prog_full_int  <= wr_prog_full;
+            end
+        end              
+    end
+    else begin
+        assign wr_prog_full  = 1'b0; 
+    end
+        
+    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end
+    end
+    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
+        reg    rd_prog_empty_int;
+        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
+            
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_prog_empty_int <= 1'b1;
+            end
+            else begin
+                rd_prog_empty_int <= rd_prog_empty;
+            end
+        end  
+    end
+    else begin
+        assign rd_prog_empty  = 1'b0; 
+    end
+    
+    if (HANDSHAKE_FLAG) begin
+    
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_ack <= 1'b0;
+            end
+            else begin
+                wr_ack <= wr_en_int & ~wr_overflow;
+            end
+        end
+
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                wr_overflow <= 1'b0;
+            end
+            else if (we && wr_full) begin
+                wr_overflow <= 1'b1;
+            end
+            else begin
+                wr_overflow <= 1'b0;            
+            end
+        end
+        
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                rd_underflow <= 1'b0;
+            end
+            else if (re && rd_empty) begin
+                rd_underflow <= 1'b1;
+            end
+            else begin
+                rd_underflow <= 1'b0;            
+            end
+        end
+    end
+    
+    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
+    
+    if (ASYM_WIDTH_RATIO < 4) begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
+        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
+        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
+    end
+    else begin
+        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
+        assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
+        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
+        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr_w;
+    end
+endgenerate
+
+always @ (posedge wclk or posedge wr_rst) begin
+    if (wr_rst) begin
+        waddr_cntr <= 'h0;
+    end
+    else if (wr_en_int) begin
+        waddr_cntr <= waddr_cntr + 1'b1;
+    end
+end
+
+always @ (posedge rclk or posedge rd_rst) begin
+    if (rd_rst) begin
+        raddr_cntr   <= 'h0;
+        raddr_cntr_r <= 'h0;
+    end
+    else if (rd_en_int) begin
+        raddr_cntr   <= raddr_cntr + 1'b1;
+        raddr_cntr_r <= raddr_cntr;
+    end
+end
+
+generate
+    if (SYNC_CLK) begin
+        assign waddr_int        = waddr_cntr;
+        assign raddr_int        = raddr_cntr_w;
+    end
+    else begin
+        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
+        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
+        
+        wire [RADDR_WIDTH:0] raddr_cntr_gry;
+        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
+        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry;
+        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
+        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;
+
+        if (PIPELINE_REG) begin
+            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
+            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
+        
+            assign waddr_int        = waddr_cntr_sync_g2b_r;
+            assign raddr_int        = raddr_cntr_sync_g2b_r;
+            
+            always @ (posedge wclk or posedge wr_rst) begin
+                if (wr_rst) begin
+                    raddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
+                end
+            end
+            
+            always @ (posedge rclk or posedge rd_rst) begin
+                if (rd_rst) begin
+                    waddr_cntr_sync_g2b_r <= 'h0;
+                end
+                else begin
+                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
+                end
+            end
+        end
+        else begin
+            assign waddr_int        = waddr_cntr_sync_g2b;
+            assign raddr_int        = raddr_cntr_sync_g2b;        
+        end
+      
+        always @ (posedge rclk or posedge rd_rst) begin
+            if (rd_rst) begin
+                raddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                raddr_cntr_gry_r <= raddr_cntr_gry;
+            end
+        end
+        efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_bin2gray    (.bin_i(raddr_cntr_w), .gray_o(raddr_cntr_gry));
+        efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1)) xrd2wr_addr_sync   (.clk_i(wclk), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
+        efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(RADDR_WIDTH+1)                     ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
+        
+        always @ (posedge wclk or posedge wr_rst) begin
+            if (wr_rst) begin
+                waddr_cntr_gry_r <= 'h0;
+            end
+            else begin
+                waddr_cntr_gry_r <= waddr_cntr_gry;
+            end
+        end        
+        efx_fifo_bin2gray_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
+        efx_fifo_datasync_f81c17844c0a4d5fa30d89ba7d75c52b # (.STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1)) wr2rd_addr_sync (.clk_i(rclk), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
+        efx_fifo_gray2bin_f81c17844c0a4d5fa30d89ba7d75c52b # (.WIDTH(WADDR_WIDTH+1)                     ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        
+
+    end
+endgenerate
+endmodule
+

Floatkyun_Ultra-Vision/FPGA/Architecture1(2K@50Hz)/2k@50+/2k@50+/data_in_uart_control_new/Bilinear_interpolation_prj/ip/asyn_fifo/Ti60F225_devkit/fifo_demo_Ti60.sdc

@@ -0,0 +1,3 @@
+create_clock -period 3.125 [get_ports pll_clkout_0]
+create_clock -period 6.250 [get_ports pll_clkout_1]
+create_clock -period 200   [get_ports led_clk]