Add Repo: rgwan_kamikaze

rgwan_kamikaze/README.md

@@ -0,0 +1,37 @@
+#Kamikaze: 
+
+Light-weight RV32IMC core for FPGA or ASIC.
+
+Description:
+---------
+
+It realized a RISC-V 32bit core by 4-stage pipeline. It aims to replace Cortex-M3.
+
+Currently is not usable, working in progress.
+
+
+Goals:
+---------
+
+	RISC-V RV32IMC instruction set compatible.
+
+	I will add some instruction to enhance it's performance, if I have enough time working on it.
+
+	Harvard architecture which features I-bus and D-bus.
+
+	Small footprint for small FPGA or ASIC.
+
+	AHB-Lite or AXI bus wrapper.
+
+	Debug supported. The debug register will mapped on MMIO(APB interface), and support debug externally from special UART.
+
+Authors:
+----------
+
+Zhiyuan Wan
+
+License:  
+----------
+
+MIT
+

rgwan_kamikaze/firmware/firmware.c

@@ -0,0 +1,72 @@
+#define GPIO_A_ODR (*(volatile char*)0x10000000)
+void putc(char c)
+{
+	int i;
+	volatile int j;
+	int ch = (c << 1) + (1 << 9);
+	for(i = 0; i < 10; i++) //
+	{
+		if(ch & (1 << i))
+			GPIO_A_ODR = 0x03;
+		else
+			GPIO_A_ODR = 0x00;
+		for(j = 0; j < 9; j++)
+			__asm__("nop");
+			
+	}
+}
+
+void puts(const char *s)
+{
+	volatile int j;
+	while (*s)
+	{
+		putc(*s++);
+		int j;
+		for(j = 0; j < 1000; j++)
+			__asm__("nop");
+	}
+}
+
+
+void *memcpy(void *dest, const void *src, int n)
+{
+	while (n) 
+	{
+		n--;
+		((char*)dest)[n] = ((char*)src)[n];
+	}
+	return dest;
+}
+
+void main()
+{
+	char message[] = "$Uryyb+Jbeyq!+Vs+lbh+pna+ernq+guvf+zrffntr+gura$gur+CvpbEI32+PCH"
+			"+frrzf+gb+or+jbexvat+whfg+svar.$$++++++++++++++++GRFG+CNFFRQ!$$";
+	for (int i = 0; message[i]; i++)
+		switch (message[i])
+		{
+		case 'a' ... 'm':
+		case 'A' ... 'M':
+			message[i] += 13;
+			break;
+		case 'n' ... 'z':
+		case 'N' ... 'Z':
+			message[i] -= 13;
+			break;
+		case '$':
+			message[i] = '\n';
+			break;
+		case '+':
+			message[i] = ' ';
+			break;
+		}
+	while(1)
+	{
+		/*putc(0x55);
+		putc(0xaa);*/
+		puts(message);
+		
+	}
+}
+

rgwan_kamikaze/firmware/makehex.py

@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+#
+# This is free and unencumbered software released into the public domain.
+#
+# Anyone is free to copy, modify, publish, use, compile, sell, or
+# distribute this software, either in source code form or as a compiled
+# binary, for any purpose, commercial or non-commercial, and by any
+# means.
+
+from sys import argv
+
+binfile = argv[1]
+nwords = int(argv[2])
+
+with open(binfile, "rb") as f:
+    bindata = f.read()
+
+assert len(bindata) < 4*nwords
+assert len(bindata) % 4 == 0
+
+for i in range(nwords):
+    if i < len(bindata) // 4:
+        w = bindata[4*i : 4*i+4]
+        print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0]))
+    else:
+        print("0")
+

rgwan_kamikaze/firmware/rom2mif.c

@@ -0,0 +1,63 @@
+#include <stdio.h>
+#include <stdint.h>
+
+int main()
+{
+    FILE *fp, *fp1, *fp2, *fp3, *fp4;
+    fp = fopen("firmware.bin", "rb");
+    fp1 = fopen("hi.mif", "w+");
+    fp2 = fopen("mh.mif", "w+");
+    fp3 = fopen("ml.mif", "w+");
+    fp4 = fopen("lo.mif", "w+");
+    if(!fp)
+	{
+		printf("File doesn't exist!\n");
+		return -1;
+	}
+	fseek(fp, 0, SEEK_END);
+	int size = ftell(fp);
+	fseek(fp, 0, SEEK_SET);
+	printf("Binary length: %d bytes\n", size);
+
+	uint8_t dat[4];
+	int i = 0;
+	fprintf(fp1, "DEPTH = 1024;\nWIDTH = 8;\n"
+				 "ADDRESS_RADIX = HEX;\n"
+				 "DATA_RADIX = HEX;\n"
+				 "CONTENT "
+				 "BEGIN\n \n");
+	fprintf(fp2, "DEPTH = 1024;\nWIDTH = 8;\n"
+				 "ADDRESS_RADIX = HEX;\n"
+				 "DATA_RADIX = HEX;\n"
+				 "CONTENT "
+				 "BEGIN\n \n");
+	fprintf(fp3, "DEPTH = 1024;\nWIDTH = 8;\n"
+				 "ADDRESS_RADIX = HEX;\n"
+				 "DATA_RADIX = HEX;\n"
+				 "CONTENT "
+				 "BEGIN\n \n");
+	fprintf(fp4, "DEPTH = 1024;\nWIDTH = 8;\n"
+				 "ADDRESS_RADIX = HEX;\n"
+				 "DATA_RADIX = HEX;\n"
+				 "CONTENT "
+				 "BEGIN\n \n");
+	while(!feof(fp))
+	{
+		fread(&dat, 1, 4, fp);
+		fprintf(fp1, "%04X : %02X;\n", i, dat[3]);
+		fprintf(fp2, "%04X : %02X;\n", i, dat[2]);
+		fprintf(fp3, "%04X : %02X;\n", i, dat[1]);
+		fprintf(fp4, "%04X : %02X;\n", i, dat[0]);
+		i++;
+	}
+	fprintf(fp1, "\nEND;\n");
+	fprintf(fp2, "\nEND;\n");
+	fprintf(fp3, "\nEND;\n");
+	fprintf(fp4, "\nEND;\n");
+	fclose(fp);
+	fclose(fp1);
+	fclose(fp2);
+	fclose(fp3);
+	fclose(fp4);
+	printf("Done\n");
+}

rgwan_kamikaze/firmware/testserial.c

@@ -0,0 +1,25 @@
+#include <stdio.h>
+
+void tx(char c)
+{
+	int i;
+	volatile int j;
+	int ch = (c << 1) + (1 << 9);
+	for(i = 0; i < 10; i++) //
+	{
+		if(ch & (1 << i))
+			printf("1");
+		else
+			printf("0");
+	}
+}
+
+main()
+{
+	int i;
+	for(i = 0; i < 8; i++)
+	{
+		tx(1 << i);//
+		puts("");
+	}
+}

rgwan_kamikaze/scripts/kamikaze_test/config.v

@@ -0,0 +1 @@
+`define FPGA_ARCH_ANLOGIC_AL3

rgwan_kamikaze/src/compress_decoder.v

@@ -0,0 +1,230 @@
+// Copyright 2015 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+/* It is taken from RI5CY project to kamikaze. Thanks them! */
+////////////////////////////////////////////////////////////////////////////////
+// Engineer:       Sven Stucki - svstucki@student.ethz.ch                     //
+//                                                                            //
+// Design Name:    Compressed instruction decoder                             //
+// Project Name:   RI5CY                                                      //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    Decodes RISC-V compressed instructions into their RV32     //
+//                 equivalent. This module is fully combinatorial.            //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+
+`include "riscv_defines.v"
+
+module kamikaze_compress_decoder
+(
+  input   	[31:0] instr_i,
+  output  reg	[31:0] instr_o,
+  output  reg	illegal_instr_o
+);
+
+  //////////////////////////////////////////////////////////////////////////////////////////////////////
+  //   ____                                                 _   ____                     _            //
+  //  / ___|___  _ __ ___  _ __  _ __ ___  ___ ___  ___  __| | |  _ \  ___  ___ ___   __| | ___ _ __  //
+  // | |   / _ \| '_ ` _ \| '_ \| '__/ _ \/ __/ __|/ _ \/ _` | | | | |/ _ \/ __/ _ \ / _` |/ _ \ '__| //
+  // | |__| (_) | | | | | | |_) | | |  __/\__ \__ \  __/ (_| | | |_| |  __/ (_| (_) | (_| |  __/ |    //
+  //  \____\___/|_| |_| |_| .__/|_|  \___||___/___/\___|\__,_| |____/ \___|\___\___/ \__,_|\___|_|    //
+  //                      |_|                                                                         //
+  //////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  always @*
+  begin
+    illegal_instr_o = 1'b0;
+    instr_o         = 32'bx;
+
+    case (instr_i[1:0])
+      // C0
+      2'b00: begin
+        case (instr_i[15:13])
+          3'b000: begin
+            // c.addi4spn -> addi rd', x2, imm
+            instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], `OPC_OP_IMM};
+            if (instr_i[12:5] == 8'b0)  illegal_instr_o = 1'b1;
+          end
+
+          3'b010: begin
+            // c.lw -> lw rd', imm(rs1')
+            instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], `OPC_LOAD};
+          end
+
+          3'b110: begin
+            // c.sw -> sw rs2', imm(rs1')
+            instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, `OPC_STORE};
+          end
+
+          default: begin
+            illegal_instr_o = 1'b1;
+          end
+        endcase
+      end
+
+      // C1
+      2'b01: begin
+        case (instr_i[15:13])
+          3'b000: begin
+            // c.addi -> addi rd, rd, nzimm
+            // c.nop
+            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPC_OP_IMM};
+          end
+
+          3'b001, 3'b101: begin
+            // 001: c.jal -> jal x1, imm
+            // 101: c.j   -> jal x0, imm
+            instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0, ~instr_i[15], `OPC_JAL};
+          end
+
+          3'b010: begin
+            // c.li -> addi rd, x0, nzimm
+            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPC_OP_IMM};
+            if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;
+          end
+
+          3'b011: begin
+            // c.lui -> lui rd, imm
+            instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], `OPC_LUI};
+
+            if (instr_i[11:7] == 5'h02) begin
+              // c.addi16sp -> addi x2, x2, nzimm
+              instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, `OPC_OP_IMM};
+            end else if (instr_i[11:7] == 5'b0) begin
+              illegal_instr_o = 1'b1;
+            end
+
+            if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
+          end
+
+          3'b100: begin
+            case (instr_i[11:10])
+              2'b00,
+              2'b01: begin
+                // 00: c.srli -> srli rd, rd, shamt
+                // 01: c.srai -> srai rd, rd, shamt
+                instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], `OPC_OP_IMM};
+                if (instr_i[12] == 1'b1)  illegal_instr_o = 1'b1;
+                if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
+              end
+
+              2'b10: begin
+                // c.andi -> andi rd, rd, imm
+                instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], `OPC_OP_IMM};
+              end
+
+              2'b11: begin
+                case ({instr_i[12], instr_i[6:5]})
+                  3'b000: begin
+                    // c.sub -> sub rd', rd', rs2'
+                    instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], `OPC_OP};
+                  end
+
+                  3'b001: begin
+                    // c.xor -> xor rd', rd', rs2'
+                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], `OPC_OP};
+                  end
+
+                  3'b010: begin
+                    // c.or  -> or  rd', rd', rs2'
+                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], `OPC_OP};
+                  end
+
+                  3'b011: begin
+                    // c.and -> and rd', rd', rs2'
+                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], `OPC_OP};
+                  end
+
+                  3'b100,
+                  3'b101,
+                  3'b110,
+                  3'b111: begin
+                    // 100: c.subw
+                    // 101: c.addw
+                    illegal_instr_o = 1'b1;
+                  end
+                endcase
+              end
+            endcase
+          end
+
+          3'b110, 3'b111: begin
+            // 0: c.beqz -> beq rs1', x0, imm
+            // 1: c.bnez -> bne rs1', x0, imm
+            instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], `OPC_BRANCH};
+          end
+
+          default: begin
+            illegal_instr_o = 1'b1;
+          end
+        endcase
+      end
+
+      // C2
+      2'b10: begin
+        case (instr_i[15:13])
+          3'b000: begin
+            // c.slli -> slli rd, rd, shamt
+            instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], `OPC_OP_IMM};
+            if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;
+            if (instr_i[12] == 1'b1 || instr_i[6:2] == 5'b0)  illegal_instr_o = 1'b1;
+          end
+
+          3'b010: begin
+            // c.lwsp -> lw rd, imm(x2)
+            instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], `OPC_LOAD};
+            if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;
+          end
+
+          3'b100: begin
+            if (instr_i[12] == 1'b0) begin
+              // c.mv -> add rd/rs1, x0, rs2
+              instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPC_OP};
+
+              if (instr_i[6:2] == 5'b0) begin
+                // c.jr -> jalr x0, rd/rs1, 0
+                instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, `OPC_JALR};
+              end
+            end else begin
+              // c.add -> add rd, rd, rs2
+              instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPC_OP};
+
+              if (instr_i[11:7] == 5'b0) begin
+                // c.ebreak -> ebreak
+                instr_o = {32'h00_10_00_73};
+                if (instr_i[6:2] != 5'b0)
+                  illegal_instr_o = 1'b1;
+              end else if (instr_i[6:2] == 5'b0) begin
+                // c.jalr -> jalr x1, rs1, 0
+                instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, `OPC_JALR};
+              end
+            end
+          end
+
+          3'b110: begin
+            // c.swsp -> sw rs2, imm(x2)
+            instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, `OPC_STORE};
+          end
+
+          default: begin
+            illegal_instr_o = 1'b1;
+          end
+        endcase
+      end
+
+      default: begin
+        // 32 bit (or more) instruction
+        instr_o = instr_i;
+      end
+    endcase
+  end
+
+endmodule

rgwan_kamikaze/src/csr.txt

@@ -0,0 +1,10 @@
+0x300	MSTATUS:	IE[0], PRIV[2:1], CY[3]
+0x341	MEPC		Storage last pc and jump to interrupt or exception address
+0x342	MCAUSE		INT[31](it is trigged by an interrupt), Exception op-code[4:0]
+0x301	MISA		ISA support RV32IMC
+
+0xF11	MVID		"ANLG"	(Anlogic)
+0xF12	MARCHID		"ZYKZ"	(Zhiyuan Kamikaze)
+0xF13	MIMPID		"0000"	(r0p0)
+
+/* performance counter will not be implemented in this CPU */

rgwan_kamikaze/src/decode.v

@@ -0,0 +1,161 @@
+`include "riscv_defines.v"
+
+/* 解码和寄存器读取 */
+module kamikaze_decode( clk_i,
+			rst_i,
+			is_compressed_instr_i,
+			instr_i,
+			instr_valid_i,
+			pc_i,
+			
+			rf_rs1_o,
+			rf_rs2_o,
+			
+			rf_rs1_i,
+			rf_rs2_i,
+			
+			rf_rd_o,
+			rf_rd_we_o,
+			
+			decode_valid_o,
+			
+			alu_func_o,
+			
+			alu_op1_o,
+			alu_op2_o,
+			
+			ex_we_i,
+			ex_wd_i,
+			ex_wdata_i,
+			
+			
+			pc_o,
+			pc_next_o
+		
+			);
+	
+	input clk_i;
+	input rst_i;
+	
+	input is_compressed_instr_i;
+	input [31:0] instr_i;
+	input instr_valid_i;
+	
+	input [31:0] pc_i; /*虽然没什么卵用*/
+	input [31:0] pc_next_i; /*下一个pc，分支预测是否正确*/
+	
+	/* 寄存器地址输出 */
+	output reg [4:0] rf_rs1_o;
+	output reg [4:0] rf_rs2_o;
+	
+	/* 寄存器数据输入 */
+	input [31:0] rf_rs1_i;
+	input [31:0] rf_rs2_i;
+	
+	/* ALU 输出 */
+	output reg [31:0] alu_op1_o;
+	output reg [31:0] alu_op2_o;
+	
+	/* 到回写阶段的 */
+	output reg [4:0] rf_rd_o  = 0; /* 寄存器 2R 1W地址口, 同步RAM?分布RAM? */
+	output reg rf_rd_we_o;
+	
+	output reg [2:0] alu_func_o = 0;
+	
+	/* 从回写阶段判断是否有写的数据 */
+	input ex_we_i;
+	input [4:0]ex_wd_i;
+	input [31:0]ex_wdata_i;
+	
+	output reg [31:0] pc_o;
+	output wire [31:0] pc_next_o;
+	
+	assign pc_next_o = pc_i;
+	
+	output reg decode_valid_o; /* 指令是否有效 */
+	
+	
+	reg is_compressed_instr = 0;
+	
+	/* 指令解码 */
+	
+	wire [6:0] opcode = instr_i[6:0];
+	
+	/* 寄存器 */
+	wire [4:0] rs1_i = instr_i[19:15];
+	wire [4:0] rs2_i = instr_i[24:20];
+	wire [4:0] rd_i  = instr_i[11:7];
+	
+	/* 立即数 */
+	wire [31:0] d_imm_i = { {21{ instr_i[31] }}, instr_i[30:25], instr_i[24:21], instr_i[20]};
+	wire [31:0] d_imm_s = { {21{ instr_i[31] }}, instr_i[30:25], instr_i[11:8], instr_i[7]};
+	wire [31:0] d_imm_b = { {20{ instr_i[31] }}, instr_i[7], instr_i[30:25], instr_i[11:8], 1'b0};
+	
+	wire [31:0] d_imm_u = { instr_i[31], instr_i[30:20], instr_i[19:12], 12'h000};
+	
+	wire [31:0] d_imm_j = { {12{instr_i[31]}}, instr_i[19:12], instr_i[20], 
+				instr_i[30:25], instr_i[24:21], 1'b0};	
+				
+	
+	wire [2:0] alu_func = instr_i[14:12];
+	
+	wire [31:0]rf_rs1;
+	wire [31:0]rf_rs2;
+	
+	
+	/* 流水线结果前递 */
+	assign rf_rs1 = ex_we_i? (ex_wd_i == rs1_i? ex_wdata_i: rf_rs1_i): rf_rs1_i;
+	assign rf_rs2 = ex_we_i? (ex_wd_i == rs2_i? ex_wdata_i: rf_rs2_i): rf_rs2_i;
+	
+	always @(posedge clk_i or negedge rst_i)
+	begin
+		if(!rst_i)
+		begin
+			decode_valid_o <= 0;
+			rf_rd_we_o <= 0;
+			pc_o <= 0;
+		end
+		else
+		begin			
+			rf_rs1_o <= rs1_i; /* 可能可以提前 */
+			rf_rs2_o <= rs2_i;
+			rf_rd_o  <= rd_i; /* 寄存器解码 */
+			
+			decode_valid_o <= instr_valid_i;
+			
+			alu_func_o <= 0;
+			
+			rf_rd_we_o <= 0;
+			
+			case (opcode)
+				`OPC_OP_IMM:
+				begin
+					alu_func_o <= alu_func;
+					alu_op2_o <= d_imm_i;
+					
+					alu_op1_o <= rf_rs1;
+					
+					rf_rd_we_o <= instr_valid_i;
+				end
+				/*OPC_LUI:
+				OPC_AUIPC:
+				OPC_OP:
+				OPC_JAL:
+				OPC_JALR:
+				OPC_BRANCH:
+				OPC_LOAD:
+				OPC_STORE:
+				OPC_SYSTEM:*/
+				default:
+				begin
+					decode_valid_o <= 0;
+				end
+			endcase
+			
+			pc_o <= pc_i;
+			is_compressed_instr <= is_compressed_instr_i;
+		end
+	end
+	
+	
+endmodule

rgwan_kamikaze/src/execute.v

@@ -0,0 +1,102 @@
+/* 执行和内存访问 */
+`include "riscv_defines.v"
+
+module kamikaze_execute(clk_i,
+			rst_i,
+			
+			alu_op1_i,
+			alu_op2_i,
+			alu_func_i,
+			
+			pc_i,
+			pc_o,
+			
+			/* 到回写阶段 */
+			rf_rd_i,
+			rf_rd_o,
+			rf_rd_we_i,
+			rf_rd_we_o,
+			
+			/* 输出 */
+			result_o
+			);
+	input clk_i;
+	input rst_i;
+	
+	input [31:0]alu_op1_i;/* ALU输入1 */
+	input [31:0]alu_op2_i; /* ALU输入2  */
+	
+	input [2:0]alu_func_i; /* ALU 功能选择 */
+	output reg [31:0] result_o; /* ALU 输出 */
+	
+	
+	/* 到回写阶段 */
+	input [4:0]rf_rd_i;
+	output reg [4:0]rf_rd_o;
+	
+	input rf_rd_we_i;
+	output reg rf_rd_we_o;
+	
+	
+	input [31:0]pc_i;
+	output [31:0] pc_o;
+	
+	reg [31:0] alu_out;
+	
+	reg [31:0] pc;
+	
+	
+	
+	assign pc_o = pc;
+	
+		
+	always @(posedge clk_i or negedge rst_i)
+	begin
+		if(!rst_i)
+		begin
+			pc <= 0;
+		end
+		else
+		begin
+			//pc <= pc_i;
+			/*result_o <= alu_out;
+			
+			rf_rd_o <= rf_rd_i;
+			rf_rd_we_o <= rf_rd_we_i;*/
+		end
+	end
+	
+	always @*
+	begin
+			result_o <= alu_out;
+			
+			rf_rd_o <= rf_rd_i;
+			rf_rd_we_o <= rf_rd_we_i;		
+	end
+
+	/* ALU */
+	
+	/* 加法器和减法器 */
+	
+	/* ALU选择逻辑 */
+	always @*
+	begin
+		case (alu_func_i)
+			`ALU_ADD:
+				alu_out <= alu_op1_i + alu_op2_i;
+			`ALU_XOR:
+				alu_out <= alu_op1_i ^ alu_op2_i;
+			`ALU_OR:
+				alu_out <= alu_op1_i | alu_op2_i;
+			`ALU_AND:
+				alu_out <= alu_op1_i & alu_op2_i;
+			default:
+				alu_out <= 32'bx;
+		endcase
+				
+	end
+	
+
+
+
+endmodule

rgwan_kamikaze/src/fetch.v

@@ -0,0 +1,145 @@
+`timescale 1ns/1ps
+
+module kamikaze_fetch(clk_i,
+		rst_i,
+		
+		im_addr_o,
+		im_data_i,
+		
+		instr_o,
+		instr_valid_o,
+		is_compressed_instr_o,
+		
+		pc_o);
+		
+	input clk_i;
+	input rst_i;
+	input [31:0] im_data_i; 
+	output [31:0] instr_o;
+	output [31:0] im_addr_o;
+	output instr_valid_o;
+	output is_compressed_instr_o;
+	output [31:0] pc_o;
+	output [31:0] pc_next_o;
+	//input stall_i; /* IF 停止信号 */
+	
+	wire [30:0] word_address = im_addr_o[31:2];
+	reg stall_i = 0;
+	
+	reg [31:0] pc;
+	reg [31:0] pc_4;
+	reg [2:0] pc_add;
+	reg [2:0] pc_add_prev;
+	
+	
+	reg [31:0] last_instr; /* 一级缓冲 */
+	reg is_compressed_instr;
+	reg fetch_start;	
+	
+	assign is_compressed_instr_o = is_compressed_instr;
+	
+	reg align_wait;	/* 对齐等待 */
+	
+	assign instr_valid_o = !align_wait && !illegal_instr_c && fetch_start;
+	localparam CPU_START = 32'h0; /* 启动地址 */
+	
+	assign im_addr_o = pc_4[1]? (pc_4 + 2'b10): pc_4; /* 舍入 */
+	assign stall_requiring = (pc_add_prev == 2) && (pc[1:0] == 2'b00); /* 16位对齐等待，防止冲数据 */
+	
+	assign pc_o = pc;
+	
+	reg [31:0]instr_t; /* 临时存放 */
+	
+	wire illegal_instr_c;/* 错误的压缩指令 */
+	
+	always @(posedge clk_i or negedge rst_i)
+	begin
+		if(!rst_i)
+		begin
+			pc_4 <= {CPU_START[31:2], 2'b00};
+			pc <= {CPU_START[31:2], 2'b00};/* PC 比 pc_4 滞后1 CLK */
+			fetch_start <= 0;
+			pc_add_prev <= 4;
+			last_instr <= 32'h0;
+			align_wait = CPU_START[1];
+		end
+		else
+		begin
+			if(!stall_i)
+			begin	
+				if(fetch_start == 1'b0)
+				begin
+					fetch_start <= 1'b1; /* 取 0 指令 */
+					pc_4 <= pc_4 + 16'h4;
+				end
+				else
+				begin
+					if(align_wait)
+						align_wait <= 0;
+						
+					pc_4 <= pc_4 + pc_add;
+					pc <= pc + pc_add;
+				
+					if(!stall_requiring)
+						last_instr <= im_data_i;
+					
+					pc_add_prev <= pc_add;
+				end
+			end
+		end
+	end
+	
+	always @*
+	begin
+		if(pc[1:0] == 2'b00)
+		begin
+			if(stall_requiring)
+			begin
+				if(last_instr[1:0] != 2'b11) /* 对齐的压缩指令 */
+				begin
+					is_compressed_instr <= 1;
+					instr_t = last_instr[15:0];
+				end
+				else
+				begin
+					is_compressed_instr <= 0;
+					instr_t = last_instr[31:0];
+				end
+			end
+			else
+			begin
+				if(im_data_i[1:0] != 2'b11) /* 对齐的压缩指令 */
+				begin
+					is_compressed_instr <= 1;
+					instr_t = im_data_i[15:0];
+				end
+				else
+				begin
+					is_compressed_instr <= 0;
+					instr_t = im_data_i[31:0];
+				end
+			end
+		end
+		else
+		begin //pc[1:0] == 10
+			if(last_instr[17:16] != 2'b11) /* 不对齐的压缩指令 */
+			begin
+				is_compressed_instr <= 1;
+				instr_t = last_instr[31:16];
+			end
+			else			/* 不对齐的非压缩指令 */
+			begin
+				is_compressed_instr <= 0;
+				instr_t = {im_data_i[15:0], last_instr[31:16]};
+			end
+		end
+						
+		pc_add = is_compressed_instr? 2: 4;
+	end
+	
+	kamikaze_compress_decoder c_dec(.instr_i(instr_t), .instr_o(instr_o), .illegal_instr_o(illegal_instr_c));
+	/* 解码压缩指令 */
+	
+	/* 这地方得有个分支预测器，你说我是直接预测全部不跳好，还是预测全部跳好呢？ */
+	
+endmodule

rgwan_kamikaze/src/int_exp.txt

@@ -0,0 +1,11 @@
+interrupt & exception table:
+base_address: IVT_BASE, must be aligned to 4
+
+initial_sp
+reset_address
+bus_error(misaligned/invalid memory access)
+execute_error(divided by zero or illegal instruction)
+sys_call(ecall instruction, ebreak will triggers the debugger if it is online)
+nmi(not maskable interrupt, it is interrupt 0)
+interrupts 1-31
+

rgwan_kamikaze/src/kamikaze.v

@@ -0,0 +1,94 @@
+/* 神疯RISC-V RV32IMC CPU 顶层文件 */
+/* Zhiyuan Wan，Jan. 2017 */
+module kamikaze(clk_i,
+		rst_i,
+		im_addr_o,
+		im_data_i);
+	input clk_i;
+	input rst_i;
+	output [31:0] im_addr_o;
+	input [31:0] im_data_i;
+	
+	wire [31:0] instruction;
+	wire is_compressed_instr;
+	wire instr_valid;
+	
+	wire [31:0] pc_fetch;
+	
+	/* 寄存器 */
+	wire [4:0] reg_raddr_1;
+	wire [4:0] reg_raddr_2;
+	
+	wire [31:0] reg_rdata_1;
+	wire [31:0] reg_rdata_2;
+	
+	wire [4:0] reg_waddr;
+	wire [31:0] reg_wdata;
+	wire reg_we;
+	
+	/* 解码后 */
+	wire [2:0] alu_func;
+	
+	wire [4:0]decoded_rd;
+	wire [31:0]decoded_imm;
+	wire [31:0]decoded_pc;
+	wire [31:0]decoded_pc_next;
+	
+	wire [31:0]alu_op1;
+	wire [31:0]alu_op2;
+	
+	wire decoded_rd_we;
+	wire executed_rd_we;
+	
+	wire [4:0]executed_rd;
+	wire [31:0]executed_rd_data;
+	
+	assign reg_we = executed_rd_we;
+	assign reg_wdata = executed_rd_data;
+	assign reg_waddr = executed_rd;
+
+		
+	kamikaze_fetch fetch(	.clk_i(clk_i), .rst_i(rst_i), /* 取指，扩展 */
+				.im_addr_o(im_addr_o), .im_data_i(im_data_i),
+				.instr_o(instruction), .is_compressed_instr_o(is_compressed_instr),
+				.instr_valid_o(instr_valid), .pc_o(pc_fetch)
+				);
+				
+	kamikaze_decode decode( .clk_i(clk_i), .rst_i(rst_i), /* 解码，读寄存器 */
+				.instr_i(instruction), .is_compressed_instr_i(is_compressed_instr),
+				
+				.pc_i(pc_fetch), .instr_valid_i(instr_valid),
+				
+				.alu_func_o(alu_func),
+				
+				.rf_rs1_o(reg_raddr_1), .rf_rs2_o(reg_raddr_2),
+				.rf_rs1_i(reg_rdata_1), .rf_rs2_i(reg_rdata_2), /* 访问寄存器 */
+				
+				.alu_op1_o(alu_op1), .alu_op2_o(alu_op2),
+				
+				.rf_rd_o(decoded_rd), .rf_rd_we_o(decoded_rd_we),
+				
+				.ex_we_i(reg_we), .ex_wd_i(reg_waddr), .ex_wdata_i(reg_wdata),
+				
+				.pc_o(decoded_pc), .pc_next_o(decoded_pc_next)
+				);
+				
+	kamikaze_execute execute(.clk_i(clk_i), .rst_i(rst_i), /* 执行 */
+	
+				.alu_op1_i(alu_op1), .alu_op2_i(alu_op2),
+				
+				.alu_func_i(alu_func),
+				
+				.pc_i(decoded_pc),
+				
+				.rf_rd_i(decoded_rd),
+				.rf_rd_we_i(decoded_rd_we), .rf_rd_we_o(executed_rd_we),
+				.rf_rd_o(executed_rd), .result_o(executed_rd_data)
+				);
+	
+	kamikaze_regfile regfile(.clk_i(clk_i), /* 写寄存器 */
+				.raddr1_i(reg_raddr_1), .raddr2_i(reg_raddr_2),
+				.rdata1_o(reg_rdata_1), .rdata2_o(reg_rdata_2),
+				.we_i(reg_we), .wdata_i(reg_wdata), .waddr_i(reg_waddr));
+				
+endmodule

rgwan_kamikaze/src/lsu.v

@@ -0,0 +1 @@
+/* Load-Storage Unit，数据存储器访问器。用于访存的程序访问内存和读向量表。*/

rgwan_kamikaze/src/pipeline.txt

@@ -0,0 +1,21 @@
+IF- Fetch and pre-decode compressed instruction to plain instruction. It is possible to add a 32bit-wide prefetcher to realize branch prediction, or we can simply don't use BP.
+
+ID- Decode plain instruction to ALU function, memory access....control signal
+
+EX1/MEM- Calculating address, and/or/xor/add stage. Expanding sign. Half multiply stage. Access the memory.
+	Align process will provided by memory controller, which is not inside the core.(? Maybe I will work around)
+
+EX2/WB - Expanding sign from memory read, write result back to register file.
+
+simple memory interface:
+
+IM:
+
+im_addr_o => instruction memory address, aligned by 4
+im_data_i => instruction memory data
+im_data_ready_i => wait state for instruction memory
+im_data_req_o => instruction memory access signal, low means inactive.
+
+
+
+

rgwan_kamikaze/src/regfile.v

@@ -0,0 +1,77 @@
+module kamikaze_regfile (clk_i,
+			
+			waddr_i,
+			wdata_i,
+			we_i,
+			
+			raddr1_i,
+			rdata1_o,
+			
+			raddr2_i,
+			rdata2_o);
+	input clk_i;
+
+	
+	input [4:0] waddr_i;
+	input [31:0] wdata_i;
+	input we_i;
+	
+	input [4:0] raddr1_i;
+	input [4:0] raddr2_i;
+	
+	output reg [31:0] rdata1_o;
+	output reg [31:0] rdata2_o;
+
+	/* 可能可以加倍时钟速度换取非双口的RAM实现，2R 1W */
+				
+	reg [31:0]memory[0:31];
+	
+	wire [31:0]cpureg_1 = memory[1];
+	wire [31:0]cpureg_2 = memory[2];
+	wire [31:0]cpureg_3 = memory[3];
+	wire [31:0]cpureg_4 = memory[4];
+	wire [31:0]cpureg_5 = memory[5];
+	wire [31:0]cpureg_6 = memory[6];
+	wire [31:0]cpureg_7 = memory[7];
+	wire [31:0]cpureg_8 = memory[8];
+	wire [31:0]cpureg_9 = memory[9];
+	wire [31:0]cpureg_10 = memory[10];
+	wire [31:0]cpureg_11 = memory[11];
+	wire [31:0]cpureg_12 = memory[12];
+	wire [31:0]cpureg_13 = memory[13];
+	wire [31:0]cpureg_14 = memory[14];
+	wire [31:0]cpureg_15 = memory[15];
+	wire [31:0]cpureg_16 = memory[16];
+	wire [31:0]cpureg_17 = memory[17];
+	wire [31:0]cpureg_18 = memory[18];
+	wire [31:0]cpureg_19 = memory[19];
+	wire [31:0]cpureg_20 = memory[20];
+	wire [31:0]cpureg_21 = memory[21];
+	wire [31:0]cpureg_22 = memory[22];
+	wire [31:0]cpureg_23 = memory[23];
+	wire [31:0]cpureg_24 = memory[24];
+	wire [31:0]cpureg_25 = memory[25];
+	wire [31:0]cpureg_26 = memory[26];
+	wire [31:0]cpureg_27 = memory[27];
+	wire [31:0]cpureg_28 = memory[28];
+	wire [31:0]cpureg_29 = memory[29];
+	wire [31:0]cpureg_30 = memory[30];
+	wire [31:0]cpureg_31 = memory[31];	
+
+	integer i;
+	initial
+		for(i = 0; i < 32; i++)
+			memory[i] <= 32'h0;
+	
+	always @(posedge clk_i)
+	begin
+		if(we_i)
+			memory[waddr_i] <= wdata_i;
+	end
+	
+	always @*
+	begin
+		rdata1_o = raddr1_i? memory[raddr1_i]: 0;
+		rdata2_o = raddr2_i? memory[raddr2_i]: 0;
+	end
+endmodule

rgwan_kamikaze/src/riscv_defines.v

@@ -0,0 +1,21 @@
+/* RISC-V的编码常量 */
+
+`define OPC_SYSTEM	7'h73
+`define OPC_FENCE	7'h0f
+`define OPC_OP		7'h33
+`define OPC_OP_IMM	7'h13
+`define OPC_STORE	7'h23
+`define OPC_LOAD	7'h03
+`define OPC_BRANCH	7'h63
+`define OPC_JALR	7'h67
+`define OPC_JAL		7'h6f
+`define OPC_AUIPC	7'h17
+`define OPC_LUI		7'h37
+
+`define ALU_ADD		3'b000
+`define ALU_SLTI	3'b010
+`define ALU_SLTIU	3'b011
+`define ALU_XOR		3'b100
+`define ALU_OR		3'b110
+`define ALU_AND		3'b111
+

rgwan_kamikaze/src/tb.v

@@ -0,0 +1,19 @@
+`timescale 1ns/1ps
+
+module system_tb;
+	reg rst = 0;
+	reg clk = 0;
+	initial begin
+		$dumpfile("kamikaze.vcd");
+		$dumpvars(0, system_tb);
+		#15 rst = 1;
+		#1000 $finish;
+
+	end
+	always begin 
+		#5 clk = !clk; 
+	end
+	
+	top dut(.clk_i(clk), .rst_i(rst));
+	
+endmodule

rgwan_kamikaze/src/top.v

@@ -0,0 +1,33 @@
+module top(clk_i, rst_i, io_o, trap);
+	input clk_i;
+	input rst_i;
+	output [7:0] io_o;
+	output trap;
+
+`ifndef FPGA_ARCH_ANLOGIC_AL3	
+	localparam MEM_SIZE = 4096;
+	reg [31:0] memory [0:MEM_SIZE-1];
+	initial $readmemh("../firmware/firmware.hex", memory);
+`endif
+	
+	wire [31:0] im_addr;
+	reg [31:0] im_data;
+	
+	kamikaze cpu(.clk_i(clk_i),
+			.rst_i(rst_i),
+			.im_addr_o(im_addr),
+			.im_data_i(im_data));
+
+`ifndef FPGA_ARCH_ANLOGIC_AL3	
+	always @(posedge clk_i)
+	begin
+		if(rst_i)
+			im_data <= memory[im_addr[31:2]];
+		else
+			im_data <= 32'h0;
+	end
+`else
+		assign io_o = im_data[7:0] ^ im_data[15:7] ^ im_data[23:16] ^ im_data[31:24];
+`endif
+	
+endmodule

rgwan_kamikaze/src/writeback.v

@@ -0,0 +1,8 @@
+/* 写回寄存器与访存 */
+module kamikaze_writeback(clk_i,
+			rst_i);
+	input clk_i;
+	input rst_i;
+	
+	
+endmodule