WangXuan95_FPGA-HDMI/SIM/tb_pixel_verify.v

//--------------------------------------------------------------------------------------------------------
// Module  : tb_pixel_verify
// Type    : simulation, sub module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: Check if the decoded pixels match the pixels generated by pixel_generate.v
//--------------------------------------------------------------------------------------------------------

module tb_pixel_verify (
    input  wire       clk,
    input  wire       vde,
    input  wire       vsync,
    input  wire [7:0] red,
    input  wire [7:0] green,
    input  wire [7:0] blue
);


reg vde_r=0, vsync_r=0;

always @ (posedge clk) {vde_r, vsync_r} <= {vde, vsync};

integer nrow=0, nframe=0;

reg  [7:0] expect_red, expect_green, expect_blue;


always @ (posedge clk)
    if (vde) begin
        if (~vde_r) begin                 // pixel: start of line
            nrow <= nrow + 1;
            
            $write(" %4d", nrow);
            
            expect_red    =          nrow + nframe;
            expect_green  = 8'hFF - (nrow + nframe);
            expect_blue   =          nrow + nframe;
        end else begin                    // pixel
            expect_red    = expect_red   + 8'h1;
            expect_green  = expect_green - 8'h1;
            expect_blue   = expect_blue  + 8'h1;
        end
        
        if (expect_red   !== red  ) begin $display("mismatch on RED"  ); $finish; end
        if (expect_green !== green) begin $display("mismatch on GREEN"); $finish; end
        if (expect_blue  !== blue ) begin $display("mismatch on BLUE" ); $finish; end
        
    end else if (~vsync_r & vsync) begin  // new frame
        nrow   <= 0;
        nframe <= nframe + 1;
        
        $display("\n\n\n------ frame %6d ------", (nframe+1) );
    end


endmodule