Add Repo: WangXuan95_FPGA-HDMI

WangXuan95_FPGA-HDMI/README.md

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+![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg)
+
+　
+
+<span id="en">FPGA HDMI display controller</span>
+===========================
+
+This repo offers an **FPGA**-based **HDMI** **display** **controller** to display videos via HDMI, features:
+
+* Pure Verilog implementation, compatible with various FPGA platforms.
+* Use a simple user interface to fetch pixels from user's logic.
+* Internally implemented clock domain cross. Therefore, the clock frequency of the user interface can be independent of the HDMI clock.
+
+| ![diagram](document/diagram.png) |
+| :------------------------------: |
+|   Figure: diagram of this IP.    |
+
+　
+
+　
+
+　
+
+# Hardware Setup
+
+### Connection
+
+You should connect 4 TMDS differential pairs (8 pins) from HDMI connector to FPGA chip:
+
+- hdmi_clk_p, hdmi_clk_n
+- hdmi_tx0_p, hdmi_tx0_n
+- hdmi_tx1_p, hdmi_tx1_n
+- hdmi_tx2_p, hdmi_tx2_n
+
+### Signal voltage level
+
+Although these signals are 4 differential pairs, they are actually regarded as 8 single-ended IO pins in FPGA.
+
+All 8 IO pins should be **2.5V** **voltage** **level** , and the corresponding **IO** **bank** **power** **should** **be** **2.5V** .
+
+### FPGA IO constraints
+
+Correspondingly, in the FPGA development software, you should constrain all these 8 IO pins as LVCMOS-2.5V (or LVTTL-2.5V), neither pull-up nor pull-down.
+
+Besides, don't forget to constrain the FPGA IO positions of these 8 pins (refer to the schematic of the FPGA  board).
+
+The format of IO constraint files varies among different FPGA manufacturers. Taking [GOWIN FPGA](https://www.gowinsemi.com.cn/) as an example, the CST constraint file may be written as follows:
+
+```
+IO_LOC  "hdmi_tx0_n" 29;    IO_PORT "hdmi_tx0_n" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+IO_LOC  "hdmi_tx0_p" 30;    IO_PORT "hdmi_tx0_p" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+
+IO_LOC  "hdmi_tx1_n" 31;    IO_PORT "hdmi_tx1_n" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+IO_LOC  "hdmi_tx1_p" 32;    IO_PORT "hdmi_tx1_p" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+
+IO_LOC  "hdmi_tx2_n" 34;    IO_PORT "hdmi_tx2_n" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+IO_LOC  "hdmi_tx2_p" 35;    IO_PORT "hdmi_tx2_p" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+
+IO_LOC  "hdmi_clk_n" 27;    IO_PORT "hdmi_clk_n" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+IO_LOC  "hdmi_clk_p" 28;    IO_PORT "hdmi_clk_p" IO_TYPE=LVCMOS25 PULL_MODE=NONE DRIVE=8;
+```
+
+
+
+### Reference circuit schematic
+
+For specific circuit schematic design, referred to [the schematic of Tang-Nano-4K FPGA board](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-4K/Nano-4K.html#%E8%B5%84%E6%96%99)
+
+| ![hardware](document/hardware_connection.png) |
+| :-------------------------------------------: |
+|      Figure: Reference hardware design.       |
+
+　
+
+　
+　
+
+# Module Description
+
+ [hdmi_tx_top.v](./RTL/hdmi_tx_top.v) is the top design of this IP. The input and output signals are:
+
+```verilog
+module hdmi_tx_top #(
+    // the parameter of request to response latency ---------------------------------------
+    parameter         RESP_LATENCY = 1,        // 1, 2, or 3
+    // paramter of video sizes ------------------------------------------------------------
+    parameter  [13:0] H_TOTAL      = 14'd800,
+    parameter  [13:0] H_DRAW_START = 14'd0,
+    parameter  [13:0] H_DRAW_WIDTH = 14'd640,
+    parameter  [13:0] H_SYNC_START = 14'd656,
+    parameter  [13:0] H_SYNC_WIDTH = 14'd96,
+    parameter  [13:0] V_TOTAL      = 14'd525,
+    parameter  [13:0] V_DRAW_START = 14'd0,
+    parameter  [13:0] V_DRAW_HEIGHT= 14'd480,
+    parameter  [13:0] V_SYNC_START = 14'd490,
+    parameter  [13:0] V_SYNC_HEIGHT= 14'd2
+) (
+    // user's clock and reset -------------------------------------------------------------
+    input  wire       rstn,
+    input  wire       clk,        // can be asynchronous with pclk_x5. Its frequency must be slightly higher than f(pclk_x5) / 5
+    // user's pixel request interface (these signals synchronize with clk) ----------------
+    output reg        req_en,     // request for a pixel
+    output reg        req_sof,    // the requested pixel is at start of frame
+    output reg        req_eof,    // the requested pixel is at end   of frame
+    output reg        req_sol,    // the requested pixel is at start of line
+    output reg        req_eol,    // the requested pixel is at end   of line
+    // user's pixel response interface (these signals synchronize with clk) ---------------
+    input  wire [7:0] resp_red,
+    input  wire [7:0] resp_green,
+    input  wire [7:0] resp_blue,
+    // HDMI driving clock, whose frequency must be 5 * pclk (pclk is the pixel clock) -----
+    input  wire       pclk_x5,
+    // HDMI TX out ------------------------------------------------------------------------
+    output wire       hdmi_clk_p,
+    output wire       hdmi_clk_n,
+    output wire       hdmi_tx0_p,
+    output wire       hdmi_tx0_n,
+    output wire       hdmi_tx1_p,
+    output wire       hdmi_tx1_n,
+    output wire       hdmi_tx2_p,
+    output wire       hdmi_tx2_n
+);
+```
+
+　
+
+### Configure video resolution and frequency
+
+The default parameter settings will generate a video of 640x480 @ 59.5Hz, which corresponds to a pixel frequency of 25MHz.
+
+This configuration is referenced from another [FPGA HDMI project by FPGA4FUN](https://www.fpga4fun.com/HDMI.html) .
+
+If you want other video resolution and frame rate, please refer to relevant specifications.
+
+　
+
+### Clocks
+
+You should provide the following two clocks of this module :
+
+|      Clock name      |             `pclk_x5`             |        `clk`         |
+| :------------------: | :-------------------------------: | :------------------: |
+|   **description**    |        HDMI driving clock         |     user's clock     |
+|    **frequency**     | Five times of the pixel frequency |                      |
+|  **minimum freq.**   |              125MHz               |    f(pclk_x5) / 5    |
+|  **typical freq.**   |    125MHz  (640x480 @ 59.5Hz)     |    25MHz - 200MHz    |
+| **How to determine** | based on video resolution and FPS | based on user needs. |
+
+　
+
+### Pixel request&response interface
+
+When the module is running, it will request for video pixels from outside (i.e. from user), so you should response these pixels according to the module's interface timing. The request and response signals are:
+
+|   Signal Name    | Direction | Bit Width |                         Description                         |
+| :--------------: | :-------: | :-------: | :---------------------------------------------------------: |
+|   **`req_en`**   |  output   |     1     |                     Request for a pixel                     |
+|  **`req_sof`**   |  output   |     1     | The requested pixels is the first pixel of the entire frame |
+|  **`req_eof`**   |  output   |     1     | The requested pixels is the last pixel of the entire frame  |
+|  **`req_sol`**   |  output   |     1     |      The requested pixels is the first pixel of a line      |
+|  **`req_eol`**   |  output   |     1     |      The requested pixels is the last pixel of a line       |
+|  **`resp_red`**  |   input   |     8     |              Red channel of the response pixel              |
+| **`resp_green`** |   input   |     8     |             Green channel of the response pixel             |
+| **`resp_blue`**  |   input   |     8     |             Blue channel of the response pixel              |
+
+Note that **all request and response pixel signals should be operated in the clock domain of** **`clk`** .
+
+The module requests pixels in raster order, that is, frame by frame, row, by row, from left to right.
+
+Whenever `req_en` =1, it indicates that the module is requesting a pixel, and you need to make this pixel appear on the response signals (**`resp_red, resp_green, resp_blue`**) in the *N*th cycle thereafter. Where *N* is the response latency, which can be configured as 1, 2, or 3, achieved by configuring the  `RESP_LATENCY` parameter.
+
+The module also provide several auxiliary request signals:
+
+- When the requested pixel is the first pixel of a entire frame, `req_sof`=1
+- When the requested pixel is the last pixel of a entire frame, `req_eof`=1
+- When the requested pixel is the first pixel of a row, `req_sol`=1
+- When the requested pixel is the first pixel of a row, `req_eol`=1
+
+　
+
+　
+
+　
+
+# FPGA Example
+
+Here we provide a simple FPGA example that can display scrolling green to purple stripes on the screen.
+
+The top Verilog file of this example is [fpga_top.v](./fpga_example/RTL/fpga_top.v) 
+
+This example can directly run on [GOWIN Tang-Nano-4K FPGA board](https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-4K/Nano-4K.html). Just open the project file ([fpga_example/hdmi.gprj](./fpga_example/hdmi.gprj)) use the [GOWIN FPGA Designer Software](https://www.gowinsemi.com.cn/faq.aspx#1), compile the project and program the FPGA.
+
+If you want to run this example on FPGA from other manufacturers, you only need to rewrite the constraint file, without modifying the Verilog code.
+
+The following figure is the block diagram of this example.
+
+| ![hardware](document/fpga_example_diagram.png) |
+| :--------------------------------------------: |
+|   Figure: block diagram of the FPGA example.   |
+
+　
+
+　
+
+　
+
+# Simulation and Verification
+
+The simulation design is in the [SIM](./SIM) folder.
+
+The following figure is the block diagram of the simulation.
+
+| ![hardware](document/simulation_diagram.png) |
+| :------------------------------------------: |
+|   Figure: block diagram of the simulation.   |
+
+　
+
+　
+
+　
+
+# Reference
+
+[1] FPGA HDMI project: https://www.fpga4fun.com/HDMI.html , FPGA4FUN.
+
+[2] GOWIN Tang Nano 4K FPGA development board: https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-4K/Nano-4K.html , Sipeed.
+
+[3] HDMI Specification Version 1.3a: https://ez.analog.com/cfs-file/__key/telligent-evolution-components-attachments/00-317-00-00-00-05-21-37/HDMISpecification13a.pdf
+
+[4] HDMI Specification Version 1.4b: https://www.hdmi.org/spec/hdmi1_4b

WangXuan95_FPGA-HDMI/RTL/hdmi_async_fifo.v

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+
+//--------------------------------------------------------------------------------------------------------
+// Module  : hdmi_async_fifo
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: cross TMDS data from user's clock domain to HDMI clock domain.
+//--------------------------------------------------------------------------------------------------------
+
+module hdmi_async_fifo #(
+    parameter            DW = 8,
+    parameter            EA = 10
+) (
+    //
+    input  wire          i_rstn,
+    input  wire          i_clk,
+    output wire          i_tready,
+    input  wire          i_tvalid,
+    input  wire [DW-1:0] i_tdata,
+    //
+    input  wire          o_rstn,
+    input  wire          o_clk,
+    input  wire          o_tready,
+    output reg           o_tvalid,
+    output reg  [DW-1:0] o_tdata,
+    //
+    output wire          w_half_empty
+);
+
+
+reg  [DW-1:0] buffer [(1<<EA)-1:0];  // may automatically synthesize to BRAM
+
+reg  [EA:0] wptr=0, wq_wptr_grey=0, rq1_wptr_grey=0, rq2_wptr_grey=0;
+reg  [EA:0] rptr=0, rq_rptr_grey=0, wq1_rptr_grey=0, wq2_rptr_grey=0;
+reg  [EA:0] rptr_a1 = {{EA{1'b0}}, 1'b1};                                // rptr_a1 always equal to rptr+1, but using register to optimize timing
+wire [EA:0] rptr_next = (o_tvalid & o_tready) ? rptr_a1 : rptr;
+
+wire [EA:0] wptr_grey      = (wptr >> 1)      ^ wptr;
+wire [EA:0] rptr_grey      = (rptr >> 1)      ^ rptr;
+wire [EA:0] rptr_next_grey = (rptr_next >> 1) ^ rptr_next;
+
+always @ (posedge i_clk or negedge i_rstn)
+    if(~i_rstn)
+        wq_wptr_grey <= 0;
+    else
+        wq_wptr_grey <= wptr_grey;
+
+always @ (posedge o_clk or negedge o_rstn)
+    if(~o_rstn)
+        {rq2_wptr_grey, rq1_wptr_grey} <= 0;
+    else
+        {rq2_wptr_grey, rq1_wptr_grey} <= {rq1_wptr_grey, wq_wptr_grey};
+
+always @ (posedge o_clk or negedge o_rstn)
+    if(~o_rstn)
+        rq_rptr_grey <= 0;
+    else
+        rq_rptr_grey <= rptr_grey;
+
+always @ (posedge i_clk or negedge i_rstn)
+    if(~i_rstn)
+        {wq2_rptr_grey, wq1_rptr_grey} <= 0;
+    else
+        {wq2_rptr_grey, wq1_rptr_grey} <= {wq1_rptr_grey, rq_rptr_grey};
+
+wire w_full  = (wq2_rptr_grey == {~wptr_grey[EA:EA-1], wptr_grey[EA-2:0]} );
+wire r_empty = (rq2_wptr_grey == rptr_next_grey                           );
+
+assign i_tready = ~w_full;
+
+
+
+always @ (posedge i_clk or negedge i_rstn)
+    if(~i_rstn) begin
+        wptr <= 0;
+    end else begin
+        if(i_tvalid & ~w_full)
+            wptr <= wptr + {{EA{1'b0}}, 1'b1};
+    end
+
+always @ (posedge i_clk)
+    if(i_tvalid & ~w_full)
+        buffer[wptr[EA-1:0]] <= i_tdata;
+
+
+
+initial o_tvalid = 1'b0;
+
+always @ (posedge o_clk or negedge o_rstn)
+    if (~o_rstn) begin
+        rptr     <= 0;
+        rptr_a1  <= {{EA{1'b0}}, 1'b1};
+        o_tvalid <= 1'b0;
+    end else begin
+        rptr     <= rptr_next;
+        rptr_a1  <= rptr_next + {{EA{1'b0}}, 1'b1};
+        o_tvalid <= ~r_empty;
+    end
+
+always @ (posedge o_clk)
+    o_tdata <= buffer[rptr_next[EA-1:0]];
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// judge half full
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+function  [EA:0] gray_to_binary;
+    input [EA:0] gray;
+    integer i;
+begin
+    gray_to_binary[EA] = gray[EA];
+    for (i = EA-1; i >= 0; i = i - 1) begin
+        gray_to_binary[i] = gray_to_binary[i+1] ^ gray[i];
+    end
+end
+endfunction
+
+wire [EA-2:0] TMP = 0;
+wire [EA:0] PTR_QUARTER = {2'b01, TMP};
+
+reg  [EA:0] wq2_rptr = 0;
+
+always @ (posedge i_clk or negedge i_rstn)
+    if (~i_rstn)
+        wq2_rptr <= 0;
+    else
+        wq2_rptr <= gray_to_binary(wq1_rptr_grey);
+
+wire [EA:0] wr_delta = wptr - wq2_rptr;
+assign w_half_empty = (wr_delta < PTR_QUARTER);
+
+endmodule
+

WangXuan95_FPGA-HDMI/RTL/hdmi_tddr.v

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+
+//--------------------------------------------------------------------------------------------------------
+// Module  : hdmi_tddr
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: ODDR for hdmi_tx_top.v
+//--------------------------------------------------------------------------------------------------------
+
+module hdmi_tddr (
+    input  wire       clk,
+    input  wire [1:0] din,
+    output wire       dout
+);
+
+reg d0, d1, d1r;
+
+always @ (posedge clk) {d1, d0} <= din;
+
+always @ (negedge clk) d1r <= d1;
+
+assign dout = clk ? d1r : d0;
+
+endmodule
+

WangXuan95_FPGA-HDMI/RTL/hdmi_tmds_encode.v

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+
+//--------------------------------------------------------------------------------------------------------
+// Module  : hdmi_tmds_encode
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: encode VSYNC, HSYNC and pixels to 10-bit TMDS data.
+//--------------------------------------------------------------------------------------------------------
+
+module hdmi_tmds_encode (
+    input  wire       rstn,
+    input  wire       clk,
+    input  wire       i_en,
+    input  wire       i_vde,   // video data enable, to choose between cd (when vde=0) and i_vd (when vde=1)
+    input  wire [7:0] i_vd,    // video data (red, green or blue)
+    input  wire [1:0] i_cd,    // control data
+    output wire       o_en,
+    output wire [9:0] o_tmds_bits
+);
+
+
+wire [3:0] i_n1bs  = {3'd0,i_vd[0]} + {3'd0,i_vd[1]} + {3'd0,i_vd[2]} + {3'd0,i_vd[3]} + {3'd0,i_vd[4]} + {3'd0,i_vd[5]} + {3'd0,i_vd[6]} + {3'd0,i_vd[7]};
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage E
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg        e_en    = 1'b0;
+reg        e_vde   = 1'b0;
+reg  [7:0] e_vd    = 8'd0;
+reg  [1:0] e_cd    = 2'd0;
+reg        e_bxnor = 1'b0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        e_en    <= 1'b0;
+        e_vde   <= 1'b0;
+        e_vd    <= 8'd0;
+        e_cd    <= 2'd0;
+        e_bxnor <= 1'b0;
+    end else begin
+        e_en    <= i_en;
+        e_vde   <= i_vde;
+        e_vd    <= i_vd;
+        e_cd    <= i_cd;
+        e_bxnor <= (i_n1bs>4'd4) || ((i_n1bs==4'd4) && (i_vd[0]==1'b0));
+    end
+
+wire [8:0] d_qm;
+assign d_qm[0] = e_vd[0];
+assign d_qm[1] = e_vd[1] ^ e_bxnor ^ d_qm[0];
+assign d_qm[2] = e_vd[2] ^ e_bxnor ^ d_qm[1];
+assign d_qm[3] = e_vd[3] ^ e_bxnor ^ d_qm[2];
+assign d_qm[4] = e_vd[4] ^ e_bxnor ^ d_qm[3];
+assign d_qm[5] = e_vd[5] ^ e_bxnor ^ d_qm[4];
+assign d_qm[6] = e_vd[6] ^ e_bxnor ^ d_qm[5];
+assign d_qm[7] = e_vd[7] ^ e_bxnor ^ d_qm[6];
+assign d_qm[8] = ~e_bxnor;
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage F
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg        f_en  = 1'b0;
+reg        f_vde = 1'b0;
+reg  [1:0] f_cd  = 2'd0;
+reg  [8:0] f_qm  = 9'd0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        f_en  <= 1'b0;
+        f_vde <= 1'b0;
+        f_cd  <= 2'd0;
+        f_qm  <= 9'd0;
+    end else begin
+        f_en  <= e_en;
+        f_vde <= e_vde;
+        f_cd  <= e_cd;
+        f_qm  <= d_qm;
+    end
+
+wire [3:0] f_bal = {3'd0,f_qm[0]} + {3'd0,f_qm[1]} + {3'd0,f_qm[2]} + {3'd0,f_qm[3]} + {3'd0,f_qm[4]} + {3'd0,f_qm[5]} + {3'd0,f_qm[6]} + {3'd0,f_qm[7]} - 4'd4;
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage G
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg        g_en   = 1'b0;
+reg        g_vde  = 1'b0;
+reg  [1:0] g_cd   = 2'd0;
+reg  [8:0] g_qm   = 9'd0;
+reg  [3:0] g_bal  = 4'd0;
+reg        g_bal0 = 1'b0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        g_en   <= 1'b0;
+        g_vde  <= 1'b0;
+        g_cd   <= 2'd0;
+        g_qm   <= 9'd0;
+        g_bal  <= 4'd0;
+        g_bal0 <= 1'b0;
+    end else begin
+        g_en   <= f_en;
+        g_vde  <= f_vde;
+        g_cd   <= f_cd;
+        g_qm   <= f_qm;
+        g_bal  <= f_bal;
+        g_bal0 <= (f_bal == 4'd0);
+    end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage H
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg        h_en        = 1'b0;
+reg  [3:0] h_acc       = 4'd0;
+reg  [9:0] h_tmds_bits = 10'd0;
+
+wire       eq_0      = (g_bal0 || (h_acc==4'd0));
+wire       eq_sign   = (g_bal[3] == h_acc[3]);
+wire       invert_qm = eq_0 ? (~g_qm[8]) : eq_sign;
+wire       change    = (g_qm[8] ^ ~eq_sign) & ~eq_0;
+wire [3:0] acc_inc   = g_bal - {3'd0, change};
+wire [3:0] acc_new   = invert_qm ? (h_acc - acc_inc) : (h_acc + acc_inc);
+wire [7:0] tmds_datal= g_qm[7:0] ^ {8{invert_qm}};
+wire [9:0] tmds_data = {invert_qm, g_qm[8], tmds_datal};
+
+wire [9:0] tmds_ctrl = (g_cd == 2'b00) ? 10'b1101010100 :
+                       (g_cd == 2'b01) ? 10'b0010101011 :
+                       (g_cd == 2'b10) ? 10'b0101010100 :
+                                         10'b1010101011 ;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        h_en        <= 1'b0;
+        h_acc       <= 4'd0;
+        h_tmds_bits <= 10'd0;
+    end else begin
+        h_en        <= g_en;
+        if (g_en) begin
+            h_acc       <= g_vde ? acc_new   : 4'd0;
+            h_tmds_bits <= g_vde ? tmds_data : tmds_ctrl;
+        end
+    end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// assign output
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+assign o_en        = h_en;
+assign o_tmds_bits = h_tmds_bits;
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/RTL/hdmi_tx_top.v

@@ -0,0 +1,346 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : hdmi_tx_top
+// Type    : synthesizable, IP's top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: A HDMI TX (display) controller.
+//           It can fetch video pixels from user-specified clock domain, cross them to the HDMI clock domain.
+//           Then, display the video to HDMI (following DVI TMDS timing specification).
+//--------------------------------------------------------------------------------------------------------
+
+module hdmi_tx_top #(
+    // the parameter of request to response latency ---------------------------------------
+    parameter         RESP_LATENCY = 1,        // 1, 2, or 3
+    // paramter of video sizes ------------------------------------------------------------
+    parameter  [13:0] H_TOTAL      = 14'd800,
+    parameter  [13:0] H_DRAW_START = 14'd0,
+    parameter  [13:0] H_DRAW_WIDTH = 14'd640,
+    parameter  [13:0] H_SYNC_START = 14'd656,
+    parameter  [13:0] H_SYNC_WIDTH = 14'd96,
+    parameter  [13:0] V_TOTAL      = 14'd525,
+    parameter  [13:0] V_DRAW_START = 14'd0,
+    parameter  [13:0] V_DRAW_HEIGHT= 14'd480,
+    parameter  [13:0] V_SYNC_START = 14'd490,
+    parameter  [13:0] V_SYNC_HEIGHT= 14'd2
+) (
+    // user's clock and reset -------------------------------------------------------------
+    input  wire       rstn,
+    input  wire       clk,        // can be asynchronous with pclk_x5. Its frequency must be slightly higher than f(pclk_x5) / 5
+    // user's pixel request interface (these signals synchronize with clk) ----------------
+    output reg        req_en,     // request for a pixel
+    output reg        req_sof,    // the requested pixel is at start of frame
+    output reg        req_eof,    // the requested pixel is at end   of frame
+    output reg        req_sol,    // the requested pixel is at start of line
+    output reg        req_eol,    // the requested pixel is at end   of line
+    // user's pixel response interface (these signals synchronize with clk) ---------------
+    input  wire [7:0] resp_red,
+    input  wire [7:0] resp_green,
+    input  wire [7:0] resp_blue,
+    // HDMI driving clock, whose frequency must be 5 * pclk (pclk is the pixel clock) -----
+    input  wire       pclk_x5,
+    // HDMI TX out ------------------------------------------------------------------------
+    output wire       hdmi_clk_p,
+    output wire       hdmi_clk_n,
+    output wire       hdmi_tx0_p,
+    output wire       hdmi_tx0_n,
+    output wire       hdmi_tx1_p,
+    output wire       hdmi_tx1_n,
+    output wire       hdmi_tx2_p,
+    output wire       hdmi_tx2_n
+);
+
+
+
+reg  [13:0] hcnt    = 14'd0;
+reg  [13:0] vcnt    = 14'd0;
+
+reg         a_en    = 1'b0;
+reg         a_hsync = 1'b0;
+reg         a_vsync = 1'b0;
+
+reg         b_en    = 1'b0;
+reg         b_hsync = 1'b0;
+reg         b_vsync = 1'b0;
+reg         b_vde   = 1'b0;
+
+reg         c_en    = 1'b0;
+reg         c_hsync = 1'b0;
+reg         c_vsync = 1'b0;
+reg         c_vde   = 1'b0;
+
+reg         d_en    = 1'b0;
+reg         d_hsync = 1'b0;
+reg         d_vsync = 1'b0;
+reg         d_vde   = 1'b0;
+
+reg  [ 7:0] d_red, d_green, d_blue;
+
+//wire        h_rdy;
+wire        h_en;
+wire [ 9:0] h_tmds0_bits;
+wire [ 9:0] h_tmds1_bits;
+wire [ 9:0] h_tmds2_bits;
+
+wire        j_en;
+wire [ 9:0] j_tmds0_bits;
+wire [ 9:0] j_tmds1_bits;
+wire [ 9:0] j_tmds2_bits;
+
+reg  [ 2:0] j_cnt5        = 3'd0;  // HDMI control counter, period=5 (j_cnt5 = 0 -> 1 -> 2 -> 3 -> 4 -> 0)
+reg         j_fetch_start = 1'b0;
+reg         j_fetch       = 1'b0;
+
+wire        half_empty;
+
+reg  [ 9:0] k_tmds0_bits  = 10'd0;
+reg  [ 9:0] k_tmds1_bits  = 10'd0;
+reg  [ 9:0] k_tmds2_bits  = 10'd0;
+reg  [ 9:0] k_tmdsc_bits  = 10'd0;
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// reset synchronize
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg [3:0] rstn_x5_shift = 4'd0;
+wire      rstn_x5 = rstn_x5_shift[3];
+
+always @ (posedge pclk_x5 or negedge rstn)
+    if (~rstn) rstn_x5_shift <= 4'd0;
+    else       rstn_x5_shift <= {rstn_x5_shift[2:0], 1'b1};
+
+reg [3:0] rstn_main_shift = 4'd0;
+wire      rstn_main = rstn_main_shift[3];
+
+always @ (posedge clk or negedge rstn_x5)
+    if (~rstn_x5) rstn_main_shift <= 4'd0;
+    else          rstn_main_shift <= {rstn_main_shift[2:0], 1'b1};
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// pixel coordinate counter
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+always @ (posedge clk or negedge rstn_main)
+    if (~rstn_main) begin
+        hcnt <= 14'd0;
+        vcnt <= 14'd0;
+    end else begin
+        if (half_empty) begin
+            if (hcnt < (H_TOTAL - 14'd1)) begin
+                hcnt <= hcnt + 14'd1;
+            end else begin
+                hcnt <= 14'd0;
+                vcnt <= (vcnt < (V_TOTAL - 14'd1)) ? (vcnt + 14'd1) : 14'd0;
+            end
+        end
+    end
+
+wire hsync  = (hcnt >= H_SYNC_START) && (hcnt < (H_SYNC_START+H_SYNC_WIDTH) );
+wire vsync  = (vcnt >= V_SYNC_START) && (vcnt < (V_SYNC_START+V_SYNC_HEIGHT));
+wire draw   = (hcnt >= H_DRAW_START) && (hcnt < (H_DRAW_START+H_DRAW_WIDTH) ) && (vcnt >= V_DRAW_START) && (vcnt < (V_DRAW_START+V_DRAW_HEIGHT));
+wire hfirst = (hcnt == H_DRAW_START);
+wire hlast  = (hcnt == (H_DRAW_START+H_DRAW_WIDTH-14'd1));
+wire vfirst = (vcnt == V_DRAW_START);
+wire vlast  = (vcnt == (V_DRAW_START+V_DRAW_HEIGHT-14'd1));
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage A : generate HSYNC, VSYNC, and request signals
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+initial {req_en, req_sol, req_eol, req_sof, req_eof} = 5'b0;
+
+always @ (posedge clk or negedge rstn_main)
+    if (~rstn_main) begin
+        {a_en, a_hsync, a_vsync} <= 3'b0;
+        {req_en, req_sol, req_eol, req_sof, req_eof} <= 5'b0;
+    end else begin
+        a_en    <= half_empty;
+        a_hsync <= hsync;
+        a_vsync <= vsync;
+        req_en  <= half_empty & draw;
+        req_sol <= half_empty & draw & hfirst;
+        req_eol <= half_empty & draw & hlast;
+        req_sof <= half_empty & draw & hfirst & vfirst;
+        req_eof <= half_empty & draw & hlast  & vlast;
+    end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage B - D : get user response
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+always @ (posedge clk or negedge rstn_main)
+    if (~rstn_main) begin
+        {b_en, b_hsync, b_vsync, b_vde} <= 4'b0;
+        {c_en, c_hsync, c_vsync, c_vde} <= 4'b0;
+        {d_en, d_hsync, d_vsync, d_vde} <= 4'b0;
+    end else begin
+        {b_en, b_hsync, b_vsync, b_vde} <= {a_en, a_hsync, a_vsync, req_en};
+        {c_en, c_hsync, c_vsync, c_vde} <= {b_en, b_hsync, b_vsync, b_vde};
+        {d_en, d_hsync, d_vsync, d_vde} <= {c_en, c_hsync, c_vsync, c_vde};
+    end
+
+generate
+    if          (RESP_LATENCY >= 3) begin
+        always @ (*)
+            {d_red, d_green, d_blue}  = {resp_red, resp_green, resp_blue};
+        
+    end else if (RESP_LATENCY == 2) begin
+        always @ (posedge clk)
+            {d_red, d_green, d_blue} <= {resp_red, resp_green, resp_blue};
+        
+    end else begin
+        reg  [ 7:0] c_red, c_green, c_blue;
+        always @ (posedge clk) begin
+            {c_red, c_green, c_blue} <= {resp_red, resp_green, resp_blue};
+            {d_red, d_green, d_blue} <= {c_red, c_green, c_blue};
+        end
+    end
+endgenerate
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage E - H : TMDS encoding
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+hdmi_tmds_encode u_tmds_encode_red (
+    .rstn         ( rstn_main                                  ),
+    .clk          ( clk                                        ),
+    .i_en         ( d_en                                       ),
+    .i_vde        ( d_vde                                      ),
+    .i_vd         ( d_red                                      ),
+    .i_cd         ( 2'b00                                      ),
+    .o_en         (                                            ),
+    .o_tmds_bits  ( h_tmds2_bits                               )
+);
+
+hdmi_tmds_encode u_tmds_encode_green (
+    .rstn         ( rstn_main                                  ),
+    .clk          ( clk                                        ),
+    .i_en         ( d_en                                       ),
+    .i_vde        ( d_vde                                      ),
+    .i_vd         ( d_green                                    ),
+    .i_cd         ( 2'b00                                      ),
+    .o_en         (                                            ),
+    .o_tmds_bits  ( h_tmds1_bits                               )
+);
+
+hdmi_tmds_encode u_tmds_encode_blue (
+    .rstn         ( rstn_main                                  ),
+    .clk          ( clk                                        ),
+    .i_en         ( d_en                                       ),
+    .i_vde        ( d_vde                                      ),
+    .i_vd         ( d_blue                                     ),
+    .i_cd         ( {d_vsync, d_hsync}                         ),
+    .o_en         ( h_en                                       ),
+    .o_tmds_bits  ( h_tmds0_bits                               )
+);
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage J : cross to clock domain pclk_x5
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+hdmi_async_fifo #(
+    .DW           ( 30                                         ),
+    .EA           ( 5                                          )
+) u_hdmi_async_fifo (
+    .i_rstn       ( rstn_main                                  ),
+    .i_clk        ( clk                                        ),
+    .i_tready     ( /*h_rdy*/                                  ),
+    .i_tvalid     ( h_en                                       ),
+    .i_tdata      ( {h_tmds0_bits, h_tmds1_bits, h_tmds2_bits} ),
+    .o_rstn       ( rstn_x5                                    ),
+    .o_clk        ( pclk_x5                                    ),
+    .o_tready     ( j_fetch                                    ),
+    .o_tvalid     ( j_en                                       ),
+    .o_tdata      ( {j_tmds0_bits, j_tmds1_bits, j_tmds2_bits} ),
+    .w_half_empty ( half_empty                                 )
+);
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage H : fetch control
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+always @ (posedge pclk_x5 or negedge rstn_x5)
+    if (~rstn_x5) begin
+        j_cnt5        <= 3'd0;
+        j_fetch_start <= 1'b0;
+        j_fetch       <= 1'b0;
+    end else begin
+        j_cnt5  <= j_cnt5[2] ? 3'd0 : (j_cnt5 + 3'd1);
+        if (j_en & j_cnt5[2]) j_fetch_start <= 1'b1;
+        j_fetch <= j_cnt5[2] & j_fetch_start;
+    end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage J : assert that u_hdmi_async_fifo never empty (only for simulation)
+/////////////////////////////////////////////////////////////////////////////////////////////
+/*
+always @ (posedge pclk_x5 or negedge rstn_x5)
+    if (~rstn_x5) begin
+    end else begin
+        if (j_fetch & ~j_en) begin
+            $display("error : u_hdmi_async_fifo empty");
+            $finish;
+        end
+    end*/
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage H : assert that u_hdmi_async_fifo never full (only for simulation)
+/////////////////////////////////////////////////////////////////////////////////////////////
+/*
+always @ (posedge clk or negedge rstn_main)
+    if (~rstn_main) begin
+    end else begin
+        if (~h_rdy & h_en) begin
+            $display("error : u_hdmi_async_fifo full");
+            $finish;
+        end
+    end*/
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// stage K : serialize TMDS signals
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+always @ (posedge pclk_x5)
+    if (j_fetch) begin
+        k_tmds0_bits <= j_tmds0_bits;
+        k_tmds1_bits <= j_tmds1_bits;
+        k_tmds2_bits <= j_tmds2_bits;
+        k_tmdsc_bits <= 10'b0000011111;
+    end else begin
+        k_tmds0_bits <= k_tmds0_bits >> 2;
+        k_tmds1_bits <= k_tmds1_bits >> 2;
+        k_tmds2_bits <= k_tmds2_bits >> 2;
+        k_tmdsc_bits <= k_tmdsc_bits >> 2;
+    end
+
+hdmi_tddr u0p_ddr (pclk_x5,  k_tmds0_bits[1:0], hdmi_tx0_p);
+hdmi_tddr u0n_ddr (pclk_x5, ~k_tmds0_bits[1:0], hdmi_tx0_n);
+hdmi_tddr u1p_ddr (pclk_x5,  k_tmds1_bits[1:0], hdmi_tx1_p);
+hdmi_tddr u1n_ddr (pclk_x5, ~k_tmds1_bits[1:0], hdmi_tx1_n);
+hdmi_tddr u2p_ddr (pclk_x5,  k_tmds2_bits[1:0], hdmi_tx2_p);
+hdmi_tddr u2n_ddr (pclk_x5, ~k_tmds2_bits[1:0], hdmi_tx2_n);
+hdmi_tddr u3p_ddr (pclk_x5,  k_tmdsc_bits[1:0], hdmi_clk_p);
+hdmi_tddr u3n_ddr (pclk_x5, ~k_tmdsc_bits[1:0], hdmi_clk_n);
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/SIM/pixel_generate.v

@@ -0,0 +1,69 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : pixel_generate
+// Type    : synthesizable
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: generate green->purple scroll bars to test hdmi_tx_top.v
+//--------------------------------------------------------------------------------------------------------
+
+module pixel_generate # (
+    // the parameter of request to response latency ---------------------------------------
+    parameter         RESP_LATENCY = 1         // 1, 2, or 3
+) (
+    // user's clock -----------------------------------------------------------------------
+    input  wire       clk,
+    // user's pixel request interface (these signals synchronize with clk) ----------------
+    input  wire       req_en,
+    input  wire       req_sof,
+    input  wire       req_sol,
+    // user's pixel response interface (these signals synchronize with clk) ---------------
+    output wire [7:0] resp_red,
+    output wire [7:0] resp_green,
+    output wire [7:0] resp_blue
+);
+
+
+reg  [7:0] nrow;
+reg  [7:0] nframe = 8'h0;
+
+reg  [7:0] resp1_red, resp1_green, resp1_blue;
+reg  [7:0] resp2_red, resp2_green, resp2_blue;
+reg  [7:0] resp3_red, resp3_green, resp3_blue;
+
+
+generate
+    if      (RESP_LATENCY <= 1) assign {resp_red, resp_green, resp_blue} = {resp1_red, resp1_green, resp1_blue};
+    else if (RESP_LATENCY == 2) assign {resp_red, resp_green, resp_blue} = {resp2_red, resp2_green, resp2_blue};
+    else                        assign {resp_red, resp_green, resp_blue} = {resp3_red, resp3_green, resp3_blue};
+endgenerate
+
+
+always @ (posedge clk)
+    if (req_en) begin
+        if          (req_sof) begin
+            nrow        <= nframe + 8'd1;
+            nframe      <= nframe + 8'd1;
+            resp1_red   <= nframe;
+            resp1_green <= 8'hFF - nframe;
+            resp1_blue  <= nframe;
+        end else if (req_sol) begin
+            nrow        <= nrow + 8'h1;
+            resp1_red   <= nrow;
+            resp1_green <= 8'hFF - nrow;
+            resp1_blue  <= nrow;
+        end else begin
+            resp1_red   <= resp1_red   + 8'h1;
+            resp1_green <= resp1_green - 8'h1;
+            resp1_blue  <= resp1_blue  + 8'h1;
+        end
+    end
+
+
+always @ (posedge clk) begin
+    {resp2_red, resp2_green, resp2_blue} <= {resp1_red, resp1_green, resp1_blue};
+    {resp3_red, resp3_green, resp3_blue} <= {resp2_red, resp2_green, resp2_blue};
+end
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/SIM/tb_clkgen.v

@@ -0,0 +1,35 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : tb_clkgen
+// Type    : simulation, sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: Generate clock with jitter (non-synthesizable!!!, only for simulation)
+//--------------------------------------------------------------------------------------------------------
+
+module tb_clkgen #(
+    parameter OFFSET = 0,
+    parameter PERIOD = 10000,
+    parameter JITTER = 0
+) (
+    output reg clk
+);
+
+integer T = PERIOD / 2;
+integer t0 = 0;
+integer t1 = 0;
+
+initial begin
+    clk = 1'b0;
+    # (OFFSET);
+    while (1) begin
+        t1 = $random;
+        t1 = (t1 < 0) ? -t1 : t1;
+        t1 = (t1 % (2 * JITTER + 1)) - JITTER;
+        # (T - t0 + t1);
+        clk = ~clk;
+        t0 = t1;
+    end
+end
+
+endmodule
+

WangXuan95_FPGA-HDMI/SIM/tb_hdmi_tx_top.v

@@ -0,0 +1,164 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : tb_hdmi_tx_top
+// Type    : simulation, top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: testbench for hdmi_tx_top.v
+//--------------------------------------------------------------------------------------------------------
+
+module tb_hdmi_tx_top ();
+
+
+//initial $dumpvars(1, tb_hdmi_tx_top);
+
+initial begin   repeat(10000000) @ (posedge clk);   $finish;   end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// generate two clocks (clk and pclk_x5)
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+localparam CLK_PEROID     = 37037;  // T=37037ps   f=27MHz
+localparam PCLK_X5_PEROID = 8000;   // T=4000ps    f=125MHz
+
+wire clk;
+wire pclk_x5;
+
+tb_clkgen #(0,     CLK_PEROID, 200) u1_clkgen (clk);       // jitter=200ps
+tb_clkgen #(0, PCLK_X5_PEROID, 200) u2_clkgen (pclk_x5);   // jitter=200ps
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// generate reset_n
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+reg  rstn = 1'b0;
+initial begin   repeat (4) @(posedge clk);   rstn <= 1'b1;   end
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// signals
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+wire       req_en, req_sof, req_sol;         // request for pixel
+wire [7:0] resp_red, resp_green, resp_blue;  // response pixel
+wire       hdmi_clk_p, hdmi_tx0_p, hdmi_tx1_p, hdmi_tx2_p;
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// generate green->purple scroll bars to test hdmi_tx_top
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+localparam RESP_LATENCY   = 1;      // request to response latency
+
+pixel_generate # (
+    .RESP_LATENCY       ( RESP_LATENCY        )
+) u_pixel_generate (
+    .clk                ( clk                 ),
+    .req_en             ( req_en              ),
+    .req_sof            ( req_sof             ),
+    .req_sol            ( req_sol             ),
+    .resp_red           ( resp_red            ),
+    .resp_green         ( resp_green          ),
+    .resp_blue          ( resp_blue           )
+);
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// HDMI TX (display) controller.
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+hdmi_tx_top #(
+    .RESP_LATENCY       ( RESP_LATENCY        )
+) u_hdmi_tx_top (
+    // user's clock and reset -------------------------------------------------------------
+    .rstn               ( rstn                ),
+    .clk                ( clk                 ),
+    // user's pixel request interface (these signals synchronize with clk) ----------------
+    .req_en             ( req_en              ),
+    .req_sof            ( req_sof             ),
+    .req_eof            (                     ),
+    .req_sol            ( req_sol             ),
+    .req_eol            (                     ),
+    // user's pixel response interface (these signals synchronize with clk) ---------------
+    .resp_red           ( resp_red            ),
+    .resp_green         ( resp_green          ),
+    .resp_blue          ( resp_blue           ),
+    // HDMI driving clock, whose frequency must be 5 * pclk (pclk is the pixel clock) -----
+    .pclk_x5            ( pclk_x5             ),
+    // HDMI TX out ------------------------------------------------------------------------
+    .hdmi_clk_p         ( hdmi_clk_p          ),
+    .hdmi_clk_n         (                     ),
+    .hdmi_tx0_p         ( hdmi_tx0_p          ),
+    .hdmi_tx0_n         (                     ),
+    .hdmi_tx1_p         ( hdmi_tx1_p          ),
+    .hdmi_tx1_n         (                     ),
+    .hdmi_tx2_p         ( hdmi_tx2_p          ),
+    .hdmi_tx2_n         (                     )
+);
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// decode three TMDS channels (non-synthesizable!!!, only for simulation)
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+wire       dec_vde, dec_vsync, dec_hsync;
+wire [7:0] dec_red, dec_green, dec_blue;
+
+tb_tmds_decode # (        // only for simulation
+    .HDMI_CLK_PEROID    ( PCLK_X5_PEROID * 5  )
+) u_tmds_decode_red (
+    .tmds_clk           ( hdmi_clk_p          ),
+    .tmds_dat           ( hdmi_tx2_p          ),
+    .decoded_vde        (                     ),
+    .decoded_vsync      (                     ),
+    .decoded_hsync      (                     ),
+    .decoded_data       ( dec_red             )
+);
+
+tb_tmds_decode # (        // only for simulation
+    .HDMI_CLK_PEROID    ( PCLK_X5_PEROID * 5  )
+) u_tmds_decode_green (
+    .tmds_clk           ( hdmi_clk_p          ),
+    .tmds_dat           ( hdmi_tx1_p          ),
+    .decoded_vde        (                     ),
+    .decoded_vsync      (                     ),
+    .decoded_hsync      (                     ),
+    .decoded_data       ( dec_green           )
+);
+
+tb_tmds_decode # (        // only for simulation
+    .HDMI_CLK_PEROID    ( PCLK_X5_PEROID * 5  )
+) u_tmds_decode_blue (
+    .tmds_clk           ( hdmi_clk_p          ),
+    .tmds_dat           ( hdmi_tx0_p          ),
+    .decoded_vde        ( dec_vde             ),
+    .decoded_vsync      ( dec_vsync           ),
+    .decoded_hsync      ( dec_hsync           ),
+    .decoded_data       ( dec_blue            )
+);
+
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// Check if the decoded pixels match the pixels generated by pixel_generate.v
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+tb_pixel_verify u_tb_pixel_verify (
+    .clk                ( hdmi_clk_p          ),
+    .vde                ( dec_vde             ),
+    .vsync              ( dec_vsync           ),
+    .red                ( dec_red             ),
+    .green              ( dec_green           ),
+    .blue               ( dec_blue            )
+);
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/SIM/tb_pixel_verify.v

@@ -0,0 +1,57 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : tb_pixel_verify
+// Type    : simulation, sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: Check if the decoded pixels match the pixels generated by pixel_generate.v
+//--------------------------------------------------------------------------------------------------------
+
+module tb_pixel_verify (
+    input  wire       clk,
+    input  wire       vde,
+    input  wire       vsync,
+    input  wire [7:0] red,
+    input  wire [7:0] green,
+    input  wire [7:0] blue
+);
+
+
+reg vde_r=0, vsync_r=0;
+
+always @ (posedge clk) {vde_r, vsync_r} <= {vde, vsync};
+
+integer nrow=0, nframe=0;
+
+reg  [7:0] expect_red, expect_green, expect_blue;
+
+
+always @ (posedge clk)
+    if (vde) begin
+        if (~vde_r) begin                 // pixel: start of line
+            nrow <= nrow + 1;
+            
+            $write(" %4d", nrow);
+            
+            expect_red    =          nrow + nframe;
+            expect_green  = 8'hFF - (nrow + nframe);
+            expect_blue   =          nrow + nframe;
+        end else begin                    // pixel
+            expect_red    = expect_red   + 8'h1;
+            expect_green  = expect_green - 8'h1;
+            expect_blue   = expect_blue  + 8'h1;
+        end
+        
+        if (expect_red   !== red  ) begin $display("mismatch on RED"  ); $finish; end
+        if (expect_green !== green) begin $display("mismatch on GREEN"); $finish; end
+        if (expect_blue  !== blue ) begin $display("mismatch on BLUE" ); $finish; end
+        
+    end else if (~vsync_r & vsync) begin  // new frame
+        nrow   <= 0;
+        nframe <= nframe + 1;
+        
+        $display("\n\n\n------ frame %6d ------", (nframe+1) );
+    end
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/SIM/tb_tmds_decode.v

@@ -0,0 +1,77 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : tb_tmds_decode
+// Type    : simulation, sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: Decode a TMDS channel (non-synthesizable!!!, only for simulation)
+//--------------------------------------------------------------------------------------------------------
+
+module tb_tmds_decode # (
+    parameter  HDMI_CLK_PEROID = 3145
+) (
+    // input
+    input  wire       tmds_clk,
+    input  wire       tmds_dat,
+    // output decoded data
+    output wire       decoded_vde,
+    output wire       decoded_vsync,
+    output wire       decoded_hsync,
+    output wire [7:0] decoded_data
+);
+
+localparam L1 = HDMI_CLK_PEROID / 20;
+localparam L2 = HDMI_CLK_PEROID / 10;
+
+reg [ 9:0] tmds_data = 10'd0;
+reg [10:0] decoded   = 11'd0;
+reg        started   = 1'b0;
+
+assign {decoded_vde, decoded_vsync, decoded_hsync, decoded_data} = decoded;
+
+initial begin
+    while(1) begin
+        @ (posedge tmds_clk);
+        
+        if (started) begin
+            case (tmds_data)
+                10'b1101010100 : decoded <= 11'b0_00_00000000;
+                10'b0010101011 : decoded <= 11'b0_01_00000000;
+                10'b0101010100 : decoded <= 11'b0_10_00000000;
+                10'b1010101011 : decoded <= 11'b0_11_00000000;
+                
+                default : begin
+                    tmds_data[8] = ~tmds_data[8];
+                    if (tmds_data[9])
+                        tmds_data[7:0] = ~tmds_data[7:0];
+                    
+                    decoded[7] <= tmds_data[7] ^ tmds_data[6] ^ tmds_data[8];
+                    decoded[6] <= tmds_data[6] ^ tmds_data[5] ^ tmds_data[8];
+                    decoded[5] <= tmds_data[5] ^ tmds_data[4] ^ tmds_data[8];
+                    decoded[4] <= tmds_data[4] ^ tmds_data[3] ^ tmds_data[8];
+                    decoded[3] <= tmds_data[3] ^ tmds_data[2] ^ tmds_data[8];
+                    decoded[2] <= tmds_data[2] ^ tmds_data[1] ^ tmds_data[8];
+                    decoded[1] <= tmds_data[1] ^ tmds_data[0] ^ tmds_data[8];
+                    decoded[0] <= tmds_data[0];
+                    
+                    decoded[10:8] <= 3'b1_00;
+                end
+            endcase
+        end
+        
+        started = 1'b1;
+        
+        #(L1) tmds_data[0] = tmds_dat;
+        #(L2) tmds_data[1] = tmds_dat;
+        #(L2) tmds_data[2] = tmds_dat;
+        #(L2) tmds_data[3] = tmds_dat;
+        #(L2) tmds_data[4] = tmds_dat;
+        #(L2) tmds_data[5] = tmds_dat;
+        #(L2) tmds_data[6] = tmds_dat;
+        #(L2) tmds_data[7] = tmds_dat;
+        #(L2) tmds_data[8] = tmds_dat;
+        #(L2) tmds_data[9] = tmds_dat;
+    end
+end
+
+endmodule
+

WangXuan95_FPGA-HDMI/fpga_example/RTL/fpga_top.v

@@ -0,0 +1,91 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : fpga_top
+// Type    : synthesizable, fpga top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: example for hdmi_tx_top.v
+//--------------------------------------------------------------------------------------------------------
+
+module fpga_top (
+    input  wire resetn,     // reset button
+    input  wire clk,        // 27MHz
+    output wire hdmi_clk_p,
+    output wire hdmi_clk_n,
+    output wire hdmi_tx0_p,
+    output wire hdmi_tx0_n,
+    output wire hdmi_tx1_p,
+    output wire hdmi_tx1_n,
+    output wire hdmi_tx2_p,
+    output wire hdmi_tx2_n
+);
+
+
+localparam RESP_LATENCY = 1;
+
+wire       rstn;
+wire       pclk_x5;   // 125MHz
+
+wire       req_en, req_sof, req_sol;         // request for pixel
+wire [7:0] resp_red, resp_green, resp_blue;  // response pixel
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// use PLL to generate pclk_x5 (125MHz)
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+Gowin_PLLVR u_pll (
+    .clkout             ( pclk_x5             ),
+    .lock               ( rstn                ),
+    .reset              ( ~resetn             ),
+    .clkin              ( clk                 )
+);
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// generate green->purple scroll bars to test hdmi_tx_top
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+pixel_generate # (
+    .RESP_LATENCY       ( RESP_LATENCY        )
+) u_pixel_generate (
+    .clk                ( clk                 ),
+    .req_en             ( req_en              ),
+    .req_sof            ( req_sof             ),
+    .req_sol            ( req_sol             ),
+    .resp_red           ( resp_red            ),
+    .resp_green         ( resp_green          ),
+    .resp_blue          ( resp_blue           )
+);
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////
+// HDMI TX (display) controller.
+/////////////////////////////////////////////////////////////////////////////////////////////
+
+hdmi_tx_top #(
+    .RESP_LATENCY       ( RESP_LATENCY        )
+) u_hdmi_tx_top (
+    .rstn               ( rstn                ),
+    .clk                ( clk                 ),
+    .req_en             ( req_en              ),
+    .req_sof            ( req_sof             ),
+    .req_eof            (                     ),
+    .req_sol            ( req_sol             ),
+    .req_eol            (                     ),
+    .resp_red           ( resp_red            ),
+    .resp_green         ( resp_green          ),
+    .resp_blue          ( resp_blue           ),
+    .pclk_x5            ( pclk_x5             ),
+    .hdmi_clk_p         ( hdmi_clk_p          ),
+    .hdmi_clk_n         ( hdmi_clk_n          ),
+    .hdmi_tx0_p         ( hdmi_tx0_p          ),
+    .hdmi_tx0_n         ( hdmi_tx0_n          ),
+    .hdmi_tx1_p         ( hdmi_tx1_p          ),
+    .hdmi_tx1_n         ( hdmi_tx1_n          ),
+    .hdmi_tx2_p         ( hdmi_tx2_p          ),
+    .hdmi_tx2_n         ( hdmi_tx2_n          )
+);
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/fpga_example/RTL/gowin_pllvr/gowin_pllvr.v

@@ -0,0 +1,67 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//GOWIN Version: V1.9.8.11
+//Part Number: GW1NSR-LV4CQN48PC6/I5
+//Device: GW1NSR-4C
+//Created Time: Sun Aug 20 22:10:09 2023
+
+module Gowin_PLLVR (clkout, lock, reset, clkin);
+
+output clkout;
+output lock;
+input reset;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_vcc;
+wire gw_gnd;
+
+assign gw_vcc = 1'b1;
+assign gw_gnd = 1'b0;
+
+PLLVR pllvr_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(reset),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .VREN(gw_vcc)
+);
+
+defparam pllvr_inst.FCLKIN = "27";
+defparam pllvr_inst.DYN_IDIV_SEL = "false";
+defparam pllvr_inst.IDIV_SEL = 7;
+defparam pllvr_inst.DYN_FBDIV_SEL = "false";
+defparam pllvr_inst.FBDIV_SEL = 36;
+defparam pllvr_inst.DYN_ODIV_SEL = "false";
+defparam pllvr_inst.ODIV_SEL = 8;
+defparam pllvr_inst.PSDA_SEL = "0000";
+defparam pllvr_inst.DYN_DA_EN = "true";
+defparam pllvr_inst.DUTYDA_SEL = "1000";
+defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
+defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
+defparam pllvr_inst.CLKFB_SEL = "internal";
+defparam pllvr_inst.CLKOUT_BYPASS = "false";
+defparam pllvr_inst.CLKOUTP_BYPASS = "false";
+defparam pllvr_inst.CLKOUTD_BYPASS = "false";
+defparam pllvr_inst.DYN_SDIV_SEL = 2;
+defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT";
+defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam pllvr_inst.DEVICE = "GW1NSR-4C";
+
+endmodule //Gowin_PLLVR

WangXuan95_FPGA-HDMI/fpga_example/RTL/gowin_pllvr/gowin_pllvr_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//GOWIN Version: V1.9.8.11
+//Part Number: GW1NSR-LV4CQN48PC6/I5
+//Device: GW1NSR-4C
+//Created Time: Sun Aug 20 22:10:09 2023
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    Gowin_PLLVR your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .reset(reset_i), //input reset
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

WangXuan95_FPGA-HDMI/fpga_example/RTL/pixel_generate.v

@@ -0,0 +1,69 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : pixel_generate
+// Type    : synthesizable
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: generate green->purple scroll bars to test hdmi_tx_top.v
+//--------------------------------------------------------------------------------------------------------
+
+module pixel_generate # (
+    // the parameter of request to response latency ---------------------------------------
+    parameter         RESP_LATENCY = 1         // 1, 2, or 3
+) (
+    // user's clock -----------------------------------------------------------------------
+    input  wire       clk,
+    // user's pixel request interface (these signals synchronize with clk) ----------------
+    input  wire       req_en,
+    input  wire       req_sof,
+    input  wire       req_sol,
+    // user's pixel response interface (these signals synchronize with clk) ---------------
+    output wire [7:0] resp_red,
+    output wire [7:0] resp_green,
+    output wire [7:0] resp_blue
+);
+
+
+reg  [7:0] nrow;
+reg  [7:0] nframe = 8'h0;
+
+reg  [7:0] resp1_red, resp1_green, resp1_blue;
+reg  [7:0] resp2_red, resp2_green, resp2_blue;
+reg  [7:0] resp3_red, resp3_green, resp3_blue;
+
+
+generate
+    if      (RESP_LATENCY <= 1) assign {resp_red, resp_green, resp_blue} = {resp1_red, resp1_green, resp1_blue};
+    else if (RESP_LATENCY == 2) assign {resp_red, resp_green, resp_blue} = {resp2_red, resp2_green, resp2_blue};
+    else                        assign {resp_red, resp_green, resp_blue} = {resp3_red, resp3_green, resp3_blue};
+endgenerate
+
+
+always @ (posedge clk)
+    if (req_en) begin
+        if          (req_sof) begin
+            nrow        <= nframe + 8'd1;
+            nframe      <= nframe + 8'd1;
+            resp1_red   <= nframe;
+            resp1_green <= 8'hFF - nframe;
+            resp1_blue  <= nframe;
+        end else if (req_sol) begin
+            nrow        <= nrow + 8'h1;
+            resp1_red   <= nrow;
+            resp1_green <= 8'hFF - nrow;
+            resp1_blue  <= nrow;
+        end else begin
+            resp1_red   <= resp1_red   + 8'h1;
+            resp1_green <= resp1_green - 8'h1;
+            resp1_blue  <= resp1_blue  + 8'h1;
+        end
+    end
+
+
+always @ (posedge clk) begin
+    {resp2_red, resp2_green, resp2_blue} <= {resp1_red, resp1_green, resp1_blue};
+    {resp3_red, resp3_green, resp3_blue} <= {resp2_red, resp2_green, resp2_blue};
+end
+
+
+endmodule
+

WangXuan95_FPGA-HDMI/fpga_example/readme.txt

@@ -0,0 +1,2 @@
+This example can run on (but not only on) Tang-Nano-4K FPGA board,
+see https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-4K

WangXuan95_FPGA-HDMI/fpga_example/top.sdc

@@ -0,0 +1,6 @@
+
+create_clock -name clk27  -period 37.037 [get_ports {clk}]
+
+create_clock -name clk125 -period  8.000 [get_pins {u_pll/pllvr_inst/CLKOUT}]
+
+set_clock_groups -asynchronous -group {clk27} -group {clk125}