| --- |
| title: Assembly |
| summary: What a ship is, how a mesh picture becomes a module, and how several meshes become one device image. |
| tags: |
| - architecture |
| - ship |
| - assembly |
| --- |
| |
| # Assembly |
|
|
| `scripts/py/gen_mesh.py` and what it writes β how the systems become a thing |
| you can build. A project keeps its assemblies under its own tree; the reference |
| one is `src/kohakutpu/top/generated/`. |
|
|
| Three terms are used throughout and defined here once. A **mesh** is the grid of |
| routers, with endpoints attached to their ports, that carries traffic on chip. A |
| **system node** is the single component at the mesh's edge that owns memory |
| access, the host-facing windows and the cross-mesh links β see |
| [sysnode](../sysnode/). An **SLR** is one die of the several this part is built |
| from, and the unit a whole assembly has to fit inside β see |
| [physical](../physical/). |
|
|
| ## What it owns |
|
|
| **A ship.** One complete, self-contained accelerator: a mesh of routers, the |
| endpoints on them, one system node, the memory boundary behind it, and the AXI |
| surface in front. A ship has a name, a fixed shape, and a boundary consisting of |
| clocks, resets and AXI interfaces β and nothing else. |
|
|
| **Generation.** Turning a picture of a mesh into that module, so that topology |
| is a described thing rather than a thousand lines of hand-written instance |
| wiring. |
|
|
| **Composition.** Joining several ships into one device image through the |
| interlink, and deciding the address map that lets a host address all of them. |
|
|
| ## The problem it solves |
|
|
| Every other system in the framework is parameterised over something a specific |
| machine has to pin down: how many routers, in what rectangle, with what on each |
| port, how many memory ports and where, one memory channel or several, one mesh |
| or four. Those choices interact β a memory port's coordinate is meaningful only |
| against the routing rule, an endpoint's coordinate is meaningful only against |
| the grid bounds β and getting one wrong produces a design that elaborates |
| cleanly and routes traffic to a plausible wrong place. |
|
|
| Assembly is where those choices are made **once, together, from one |
| description**. |
|
|
| ## The pages |
|
|
| | Page | What is in it | |
| |---|---| |
| | [what-is-a-ship](what-is-a-ship.md) | the boundary shape and why it is exactly clocks, resets and AXI; the two forms of memory boundary; what a ship costs | |
| | [generation](generation.md) | the mesh picture, the token grammar, what the generator emits, and the conventions for choosing a shape | |
| | [interlink](interlink.md) | several ships in one image: the second routing layer, the three structural properties of a link, what crosses, and the address map | |
| | [v5-interconnect-groundtruth](v5-interconnect-groundtruth.md) | **a historical record**, not the shipping design: the vendor-interconnect device image the purpose-built bus replaced, kept as the baseline it had to beat | |
|
|
| Choosing a shape, and what it costs, is |
| [integrate/mesh-topology](../../integrate/mesh-topology.md). |
|
|
| ## Fixed protocol, addon, convention, or yours |
|
|
| Assembly is the system with the most in the last row, and that is the point: it |
| is where the framework asks you what machine you want. |
|
|
| | Thing | Category | |
| |---|---| |
| | the ship's boundary shape: clocks, resets, AXI, and nothing else β each interface naming its own clock and reset | **fixed protocol**. It is what makes a ship instantiable without hand-wiring | |
| | the token grammar β corners empty, edges outside the router rectangle, tied-off ports | **fixed protocol**. It follows from the routing rule | |
| | the interlink's topology rule, credit classes, registered crossing and encapsulation format | **fixed protocol**. Each has a deadlock or timing argument behind it | |
| | the address map's *shape* β a segment per mesh for memory, a segment per mesh for control, the mesh id in the high address bits | **fixed protocol** | |
| | mesh id as a writable register with the parameter supplying only its reset value | **fixed protocol**. It is what lets one module serve every position | |
| | plain versus concentrated memory boundary | **customizable addon** β a device-image decision | |
| | the endpoint-type registry the generator instantiates from | **customizable addon** β see [generation](generation.md#where-todays-source-disagrees) | |
| | the conventions in [generation](generation.md#conventions) | **convention** β one forced, three free | |
| | **the mesh picture** β grid size, what is on every port, how many memory ports and on which rows | **yours**. This is the primary design input the framework takes | |
| | **which ships an image contains, and their positions in the mesh grid** | **yours** | |
| | the address map's *values* | **yours**, per device image | |
|
|
| ## What a compute-unit author must know |
|
|
| 1. **Your coordinate is assigned by the map, not chosen by you.** Write your |
| unit against `POS_X` / `POS_Y` parameters and never assume a value. |
| 2. **Your unit may land on a router's local port or on an edge ring**, and the |
| two are indistinguishable from inside it. Do not assume you have four |
| neighbours, or any. |
| 3. **How many of you exist is a topology decision.** If your unit only works in |
| groups of a particular size, that constraint has to be expressible in the |
| map β otherwise it will be violated by a shape that looks reasonable. |
| 4. **Nothing you write should know that another mesh exists.** Cross-mesh |
| traffic is recognised at the edge, by a bit in the header, on the way past. |
|
|
| ## What this system does not own |
|
|
| | Not owned | Who owns it | |
| |---|---| |
| | routing, links, the compute-unit port | [noc](../noc/) | |
| | what a memory port does once traffic reaches it | [sysnode](../sysnode/) | |
| | the AXI interfaces at the boundary, and their discipline | [axi](../axi.md) | |
| | which SLR a ship lands on, its pblock, and the frequency of each of its clocks | [physical](../physical/) | |
| | the vendor block design that instantiates ships, memory controllers and the host bridge | the build flow β [workflow/build](../../workflow/build.md) | |
| | what any endpoint computes | the accelerator being built | |
|
|
| The last boundary in that table is the one under most pressure. Assembly has to |
| name endpoint types to instantiate them, so it is the one framework layer that |
| cannot be entirely ignorant of the project. The right shape is a **registry** β |
| the generator knows how to place a thing with a fabric port and a coordinate, |
| and each accelerator supplies its own list of what those things are. |
|
|
| ## Where today's source disagrees |
|
|
| - **The generator has a hardcoded endpoint vocabulary**, ship modules carry a |
| project prefix, topology is described twice, and the edge complex's port count |
| is capped by its parameter list β |
| [generation](generation.md#where-todays-source-disagrees). |
| - **A reusable composition sits in a directory of device tops** β |
| [what-is-a-ship](what-is-a-ship.md#where-todays-source-disagrees). |
|
|