Lichee-Pi_Tang_FPGA_Examples/2.LCD/test_lcd.sdc

# ## Log	:	This file is generated by Anlogic Timing Wizard.
# ## File	:	H:/Work/FPGA/AnLogic/tets_lcd/test_lcd/test_lcd.sdc
# ## Date	:	15 07 2018

#Created Clock
##create_clock -name clk_50m -period 20 [get_nets {clk_50m}]