Add Repo: Lichee-Pi_Tang_FPGA_Examples

Lichee-Pi_Tang_FPGA_Examples/0.LED/src/led.v

@@ -0,0 +1,46 @@
+module led
+	(
+		input wire CLK_IN,
+		input wire RST_N,
+		output wire [2:0]RGB_LED
+	);
+
+	parameter time1 = 25'd24_000_000;//¾§ÕñΪ24Mhz
+
+	reg [2:0]rledout;
+	reg [24:0] count;
+	reg [1:0]shift_cnt;
+	
+	initial
+	begin
+		count=25'b0;
+		rledout=3'b1;
+		shift_cnt=2'b0;
+	end
+
+	always @(posedge CLK_IN)begin
+		if(RST_N==0)begin
+			count <= 25'b0;
+			rledout <= 3'b1;
+			shift_cnt <=2'b0;
+		end
+	
+		if(count == time1)
+ 		begin 
+ 			count<= 25'd0;
+ 			
+ 			if(shift_cnt==2'b10)begin
+				rledout <= 3'b1;
+				shift_cnt <=2'b0;
+ 			end
+ 			else begin
+ 				rledout <= {rledout[1:0],1'b0};
+				shift_cnt <= shift_cnt + 1'b1;
+			end
+ 		end
+ 		else
+ 			count <= count + 1'b1;
+	end
+	
+	assign RGB_LED = rledout;
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_fifo.v

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+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v
+ ** Date	:	2018 07 25
+ ** TD version	:	4.2.217
+\************************************************************/
+
+`timescale 1ns / 1ps
+
+module img_fifo (
+	rst,
+	di, clkw, we,
+	do, clkr, re,
+	empty_flag,
+	full_flag 
+);
+
+	input rst;
+	input [7:0] di;
+	input clkw, we;
+	input clkr,re;
+
+	output [15:0] do;
+	output empty_flag;
+	output full_flag;
+
+EG_LOGIC_FIFO #(
+ 	.DATA_WIDTH_W(8),
+	.DATA_WIDTH_R(16),
+	.DATA_DEPTH_W(8192),
+	.DATA_DEPTH_R(4096),
+	.ENDIAN("BIG"),
+	.RESETMODE("ASYNC"),
+	.E(0),
+	.F(8192),
+	.ASYNC_RESET_RELEASE("SYNC"))
+logic_fifo(
+	.rst(rst),
+	.di(di),
+	.clkw(clkw),
+	.we(we),
+	.csw(3'b111),
+	.do(do),
+	.clkr(clkr),
+	.re(re),
+	.csr(3'b111),
+	.ore(1'b0),
+	.empty_flag(empty_flag),
+	.aempty_flag(),
+	.full_flag(full_flag),
+	.afull_flag()
+
+);
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_fifo_sim.v

@@ -0,0 +1,283 @@
+// Verilog netlist created by TD v4.2.217
+// Wed Jul 25 09:49:21 2018
+
+`timescale 1ns / 1ps
+module img_fifo  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(14)
+  (
+  clkr,
+  clkw,
+  di,
+  re,
+  rst,
+  we,
+  do,
+  empty_flag,
+  full_flag
+  );
+
+  input clkr;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(25)
+  input clkw;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(24)
+  input [7:0] di;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(23)
+  input re;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(25)
+  input rst;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(22)
+  input we;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(24)
+  output [15:0] do;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(27)
+  output empty_flag;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(28)
+  output full_flag;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_fifo.v(29)
+
+  wire empty_flag_neg;
+  wire full_flag_neg;
+
+  EG_PHY_CONFIG #(
+    .DONE_PERSISTN("ENABLE"),
+    .INIT_PERSISTN("ENABLE"),
+    .JTAG_PERSISTN("DISABLE"),
+    .PROGRAMN_PERSISTN("DISABLE"))
+    config_inst ();
+  not empty_flag_inv (empty_flag_neg, empty_flag);
+  not full_flag_inv (full_flag_neg, full_flag);
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_0 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n47,open_n48,open_n49,open_n50,open_n51,open_n52,open_n53,di[0],open_n54}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n75,open_n76,open_n77,open_n78,open_n79,open_n80,open_n81,do[0],do[8]}),
+    .empty_flag(empty_flag),
+    .full_flag(full_flag));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_1 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n82,open_n83,open_n84,open_n85,open_n86,open_n87,open_n88,di[1],open_n89}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n110,open_n111,open_n112,open_n113,open_n114,open_n115,open_n116,do[1],do[9]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_2 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n119,open_n120,open_n121,open_n122,open_n123,open_n124,open_n125,di[2],open_n126}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n147,open_n148,open_n149,open_n150,open_n151,open_n152,open_n153,do[2],do[10]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_3 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n156,open_n157,open_n158,open_n159,open_n160,open_n161,open_n162,di[3],open_n163}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n184,open_n185,open_n186,open_n187,open_n188,open_n189,open_n190,do[3],do[11]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_4 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n193,open_n194,open_n195,open_n196,open_n197,open_n198,open_n199,di[4],open_n200}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n221,open_n222,open_n223,open_n224,open_n225,open_n226,open_n227,do[4],do[12]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_5 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n230,open_n231,open_n232,open_n233,open_n234,open_n235,open_n236,di[5],open_n237}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n258,open_n259,open_n260,open_n261,open_n262,open_n263,open_n264,do[5],do[13]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_6 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n267,open_n268,open_n269,open_n270,open_n271,open_n272,open_n273,di[6],open_n274}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n295,open_n296,open_n297,open_n298,open_n299,open_n300,open_n301,do[6],do[14]}));
+  EG_PHY_FIFO #(
+    .AE(32'b00000000000000000000000000001101),
+    .AEP1(32'b00000000000000000000000000001111),
+    .AF(32'b00000000000000000001111111111010),
+    .AFM1(32'b00000000000000000001111111111001),
+    .ASYNC_RESET_RELEASE("SYNC"),
+    .DATA_WIDTH_A("1"),
+    .DATA_WIDTH_B("2"),
+    .E(32'b00000000000000000000000000000001),
+    .EP1(32'b00000000000000000000000000000011),
+    .F(32'b00000000000000000010000000000000),
+    .FM1(32'b00000000000000000001111111111111),
+    .GSR("DISABLE"),
+    .MODE("FIFO8K"),
+    .REGMODE_A("NOREG"),
+    .REGMODE_B("NOREG"),
+    .RESETMODE("ASYNC"))
+    logic_fifo_7 (
+    .clkr(clkr),
+    .clkw(clkw),
+    .csr({2'b11,empty_flag_neg}),
+    .csw({2'b11,full_flag_neg}),
+    .dia({open_n304,open_n305,open_n306,open_n307,open_n308,open_n309,open_n310,di[7],open_n311}),
+    .orea(1'b0),
+    .oreb(1'b0),
+    .re(re),
+    .rprst(rst),
+    .rst(rst),
+    .we(we),
+    .dob({open_n332,open_n333,open_n334,open_n335,open_n336,open_n337,open_n338,do[7],do[15]}));
+
+endmodule 
+

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_pll.v

@@ -0,0 +1,85 @@
+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v
+ ** Date	:	2018 08 10
+ ** TD version	:	4.2.217
+\************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+//	Input frequency:             24.000Mhz
+//	Clock multiplication factor: 7
+//	Clock division factor:       5
+//	Clock information:
+//		Clock name	| Frequency 	| Phase shift
+//		C0        	| 33.600 MHZ	| 0  DEG     
+//		C1        	| 12.062 MHZ	| 0  DEG     
+//		C2        	| 4.021  MHZ	| 0  DEG     
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns / 100 fs
+
+module ip_pll(refclk,
+		clk0_out,
+		clk1_out,
+		clk2_out);
+
+	input refclk;
+	output clk0_out;
+	output clk1_out;
+	output clk2_out;
+
+	wire clk0_buf;
+
+	EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );
+
+	EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
+		.DYNCFG("DISABLE"),
+		.FIN("24.000"),
+		.FEEDBK_MODE("NORMAL"),
+		.FEEDBK_PATH("CLKC0_EXT"),
+		.STDBY_ENABLE("DISABLE"),
+		.PLLRST_ENA("DISABLE"),
+		.SYNC_ENABLE("DISABLE"),
+		.DERIVE_PLL_CLOCKS("DISABLE"),
+		.GEN_BASIC_CLOCK("DISABLE"),
+		.GMC_GAIN(6),
+		.ICP_CURRENT(3),
+		.KVCO(6),
+		.LPF_CAPACITOR(3),
+		.LPF_RESISTOR(2),
+		.REFCLK_DIV(5),
+		.FBCLK_DIV(7),
+		.CLKC0_ENABLE("ENABLE"),
+		.CLKC0_DIV(14),
+		.CLKC0_CPHASE(14),
+		.CLKC0_FPHASE(0),
+		.CLKC1_ENABLE("ENABLE"),
+		.CLKC1_DIV(39),
+		.CLKC1_CPHASE(39),
+		.CLKC1_FPHASE(0),
+		.CLKC2_ENABLE("ENABLE"),
+		.CLKC2_DIV(117),
+		.CLKC2_CPHASE(117),
+		.CLKC2_FPHASE(0)	)
+	pll_inst (.refclk(refclk),
+		.reset(1'b0),
+		.stdby(1'b0),
+		.extlock(open),
+		.psclk(1'b0),
+		.psdown(1'b0),
+		.psstep(1'b0),
+		.psclksel(3'b000),
+		.psdone(open),
+		.dclk(1'b0),
+		.dcs(1'b0),
+		.dwe(1'b0),
+		.di(8'b00000000),
+		.daddr(6'b000000),
+		.do({open, open, open, open, open, open, open, open}),
+		.fbclk(clk0_out),
+		.clkc({open, open, clk2_out, clk1_out, clk0_buf}));
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_pll_sim.v

@@ -0,0 +1,111 @@
+// Verilog netlist created by TD v4.2.217
+// Fri Aug 10 17:39:33 2018
+
+`timescale 1ns / 1ps
+module ip_pll  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(24)
+  (
+  refclk,
+  clk0_out,
+  clk1_out,
+  clk2_out
+  );
+
+  input refclk;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(29)
+  output clk0_out;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(30)
+  output clk1_out;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(31)
+  output clk2_out;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(32)
+
+  wire clk0_buf;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(34)
+
+  EG_PHY_GCLK bufg_feedback (
+    .clki(clk0_buf),
+    .clko(clk0_out));  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(36)
+  EG_PHY_CONFIG #(
+    .DONE_PERSISTN("ENABLE"),
+    .INIT_PERSISTN("ENABLE"),
+    .JTAG_PERSISTN("DISABLE"),
+    .PROGRAMN_PERSISTN("DISABLE"))
+    config_inst ();
+  EG_PHY_PLL #(
+    .CLKC0_CPHASE(14),
+    .CLKC0_DIV(14),
+    .CLKC0_DIV2_ENABLE("DISABLE"),
+    .CLKC0_ENABLE("ENABLE"),
+    .CLKC0_FPHASE(0),
+    .CLKC1_CPHASE(39),
+    .CLKC1_DIV(39),
+    .CLKC1_DIV2_ENABLE("DISABLE"),
+    .CLKC1_ENABLE("ENABLE"),
+    .CLKC1_FPHASE(0),
+    .CLKC2_CPHASE(117),
+    .CLKC2_DIV(117),
+    .CLKC2_DIV2_ENABLE("DISABLE"),
+    .CLKC2_ENABLE("ENABLE"),
+    .CLKC2_FPHASE(0),
+    .CLKC3_CPHASE(1),
+    .CLKC3_DIV(1),
+    .CLKC3_DIV2_ENABLE("DISABLE"),
+    .CLKC3_ENABLE("DISABLE"),
+    .CLKC3_FPHASE(0),
+    .CLKC4_CPHASE(1),
+    .CLKC4_DIV(1),
+    .CLKC4_DIV2_ENABLE("DISABLE"),
+    .CLKC4_ENABLE("DISABLE"),
+    .CLKC4_FPHASE(0),
+    .DERIVE_PLL_CLOCKS("DISABLE"),
+    .DPHASE_SOURCE("DISABLE"),
+    .DYNCFG("DISABLE"),
+    .FBCLK_DIV(7),
+    .FEEDBK_MODE("NORMAL"),
+    .FEEDBK_PATH("CLKC0_EXT"),
+    .FIN("24.000"),
+    .FREQ_LOCK_ACCURACY(2),
+    .GEN_BASIC_CLOCK("DISABLE"),
+    .GMC_GAIN(6),
+    .GMC_TEST(14),
+    .ICP_CURRENT(3),
+    .IF_ESCLKSTSW("DISABLE"),
+    .INTFB_WAKE("DISABLE"),
+    .KVCO(6),
+    .LPF_CAPACITOR(3),
+    .LPF_RESISTOR(2),
+    .NORESET("DISABLE"),
+    .ODIV_MUXC0("DIV"),
+    .ODIV_MUXC1("DIV"),
+    .ODIV_MUXC2("DIV"),
+    .ODIV_MUXC3("DIV"),
+    .ODIV_MUXC4("DIV"),
+    .PLLC2RST_ENA("DISABLE"),
+    .PLLC34RST_ENA("DISABLE"),
+    .PLLMRST_ENA("DISABLE"),
+    .PLLRST_ENA("DISABLE"),
+    .PLL_LOCK_MODE(0),
+    .PREDIV_MUXC0("VCO"),
+    .PREDIV_MUXC1("VCO"),
+    .PREDIV_MUXC2("VCO"),
+    .PREDIV_MUXC3("VCO"),
+    .PREDIV_MUXC4("VCO"),
+    .REFCLK_DIV(5),
+    .REFCLK_SEL("INTERNAL"),
+    .STDBY_ENABLE("DISABLE"),
+    .STDBY_VCO_ENA("DISABLE"),
+    .SYNC_ENABLE("DISABLE"),
+    .VCO_NORESET("DISABLE"))
+    pll_inst (
+    .daddr(6'b000000),
+    .dclk(1'b0),
+    .dcs(1'b0),
+    .di(8'b00000000),
+    .dwe(1'b0),
+    .fbclk(clk0_out),
+    .psclk(1'b0),
+    .psclksel(3'b000),
+    .psdown(1'b0),
+    .psstep(1'b0),
+    .refclk(refclk),
+    .reset(1'b0),
+    .stdby(1'b0),
+    .clkc({open_n47,open_n48,clk2_out,clk1_out,clk0_buf}));  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_pll.v(83)
+
+endmodule 
+

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_ram.v

@@ -0,0 +1,71 @@
+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_ram.v
+ ** Date	:	2018 07 28
+ ** TD version	:	4.2.217
+\************************************************************/
+
+`timescale 1ns / 1ps
+
+module img_cache ( 
+	dia, addra, cea, clka, rsta, 
+	dob, addrb, ceb, clkb, rstb
+);
+
+	output [15:0] dob;
+
+
+	input  [15:0] dia;
+	input  [15:0] addra;
+	input  [15:0] addrb;
+	input  cea;
+	input  ceb;
+	input  clka;
+	input  clkb;
+	input  rsta;
+	input  rstb;
+
+
+
+
+	EG_LOGIC_BRAM #( .DATA_WIDTH_A(16),
+				.DATA_WIDTH_B(16),
+				.ADDR_WIDTH_A(16),
+				.ADDR_WIDTH_B(16),
+				.DATA_DEPTH_A(32800),
+				.DATA_DEPTH_B(32800),
+				.MODE("PDPW"),
+				.REGMODE_A("NOREG"),
+				.REGMODE_B("NOREG"),
+				.WRITEMODE_A("NORMAL"),
+				.WRITEMODE_B("NORMAL"),
+				.RESETMODE("SYNC"),
+				.IMPLEMENT("9K"),
+				.INIT_FILE("NONE"),
+				.FILL_ALL("NONE"))
+			inst(
+				.dia(dia),
+				.dib({16{1'b0}}),
+				.addra(addra),
+				.addrb(addrb),
+				.cea(cea),
+				.ceb(ceb),
+				.ocea(1'b0),
+				.oceb(1'b0),
+				.clka(clka),
+				.clkb(clkb),
+				.wea(1'b1),
+				.web(1'b0),
+				.bea(1'b0),
+				.beb(1'b0),
+				.rsta(rsta),
+				.rstb(rstb),
+				.doa(),
+				.dob(dob));
+
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_rom.v

@@ -0,0 +1,60 @@
+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/project/al_ip/ip_rom.v
+ ** Date	:	2018 07 25
+ ** TD version	:	4.2.217
+\************************************************************/
+
+`timescale 1ns / 1ps
+
+module img ( doa, addra, clka, rsta );
+
+	output [15:0] doa;
+
+	input  [13:0] addra;
+	input  clka;
+	input  rsta;
+
+
+
+
+	EG_LOGIC_BRAM #( .DATA_WIDTH_A(16),
+				.ADDR_WIDTH_A(14),
+				.DATA_DEPTH_A(9700),
+				.DATA_WIDTH_B(16),
+				.ADDR_WIDTH_B(14),
+				.DATA_DEPTH_B(9700),
+				.MODE("SP"),
+				.REGMODE_A("NOREG"),
+				.RESETMODE("SYNC"),
+				.IMPLEMENT("9K"),
+				.DEBUGGABLE("NO"),
+				.PACKABLE("NO"),
+				.INIT_FILE("../../al_ip/CrazyBird.mif"),
+				.FILL_ALL("NONE"))
+			inst(
+				.dia({16{1'b0}}),
+				.dib({16{1'b0}}),
+				.addra(addra),
+				.addrb({14{1'b0}}),
+				.cea(1'b1),
+				.ceb(1'b0),
+				.ocea(1'b0),
+				.oceb(1'b0),
+				.clka(clka),
+				.clkb(1'b0),
+				.wea(1'b0),
+				.web(1'b0),
+				.bea(1'b0),
+				.beb(1'b0),
+				.rsta(rsta),
+				.rstb(1'b0),
+				.doa(doa),
+				.dob());
+
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/project/al_ip/ip_sdram.v

@@ -0,0 +1,44 @@
+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd_camera/test_camera/al_ip/ip_sdram.v
+ ** Date	:	2018 07 20
+ ** TD version	:	4.2.217
+\************************************************************/
+
+`timescale 1ns / 1ps
+
+module  ip_sdram ( clk, ras_n, cas_n, we_n, addr, ba, dq, cs_n, dm0, dm1, dm2, dm3, cke );
+	input  		clk;
+	input  		ras_n;
+	input  		cas_n;
+	input  		we_n;
+	input  		[10:0] addr;
+	input  		[1:0] ba;
+	inout  		[31:0] dq;
+	input  		cs_n;
+	input  		dm0;
+	input  		dm1;
+	input  		dm2;
+	input  		dm3;
+	input  		cke;
+
+	EG_PHY_SDRAM_2M_32 sdram(
+		.clk(clk),
+		.ras_n(ras_n),
+		.cas_n(cas_n),
+		.we_n(we_n),
+		.addr(addr),
+		.ba(ba),
+		.dq(dq),
+		.cs_n(cs_n),
+		.dm0(dm0),
+		.dm1(dm1),
+		.dm2(dm2),
+		.dm3(dm3),
+		.cke(cke));
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/cameraReader.v

@@ -0,0 +1,91 @@
+module cameraReader
+(
+	input clk,
+	input reset_n,
+	
+	output csi_xclk,
+	
+	input csi_pclk,
+	input [7:0] csi_data,
+	input csi_vsync,
+	input csi_hsync,
+	
+	output reg [15:0] data_out = 0,
+	output wire wrreq,
+	output wire wrclk,
+	output reg [19:0]wraddr
+);
+
+reg [19:0] pixel_counter = 0;
+
+assign csi_xclk = (reset_n == 1) ? clk : 0;
+
+reg vsync_passed = 0;
+reg write_pixel = 0;
+
+reg wrclk1 = 0;
+
+always@(posedge csi_pclk)
+wrclk1 <= ~wrclk1;
+
+always@(negedge wrclk1)
+begin
+	if(csi_hsync == 1)
+		write_pixel <= 1;
+	else
+		write_pixel <= 0;
+end
+
+reg [7:0] subpixel;
+reg [15:0] current_pixel;
+
+always@(posedge wrreq )
+begin
+	data_out <= current_pixel;
+end
+
+always@(posedge csi_pclk)
+begin
+	if(reset_n == 0)
+		begin
+			pixel_counter <= 0;
+			vsync_passed <= 0;
+		end
+	else
+		begin
+			if(csi_vsync == 1)
+			begin
+				pixel_counter <= 0;
+				vsync_passed <= 1;
+				wraddr <= 0;
+			end
+			else
+				if(csi_hsync == 1 && vsync_passed == 1)
+				begin
+					if(pixel_counter[0] == 0)
+					begin
+						pixel_counter <= pixel_counter + 1;
+						subpixel <= csi_data;
+					end
+					else
+					begin
+//						current_pixel <= { subpixel, csi_data};
+						current_pixel <= { csi_data, subpixel};
+						pixel_counter <= pixel_counter + 1;
+						wraddr <= wraddr + 1;
+					end
+				end
+				else
+				begin
+				if(write_pixel == 1)
+					pixel_counter <= pixel_counter + 1;
+				else
+					pixel_counter <= 0;
+				end
+			end
+end
+
+assign wrreq = (write_pixel == 1) && pixel_counter > 2 ? wrclk1 : 0;
+assign wrclk = ~csi_pclk;
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/lcd_sync.v

@@ -0,0 +1,137 @@
+
+module lcd_sync
+#(
+ 	//display image at pos
+	parameter IMG_W = 100,  //图片行像素点个数
+	parameter IMG_H = 100,  //图片场像素点个数
+	parameter IMG_X = 0,
+	parameter IMG_Y = 0
+)
+(
+	input wire clk,
+	input wire rest_n,
+	output wire lcd_clk,
+	output wire lcd_pwm,
+	output wire lcd_hsync, 
+	output wire lcd_vsync, 
+	output wire lcd_de,
+	output wire [10:0] hsync_cnt,
+	output wire [10:0] vsync_cnt,
+	output wire img_ack,
+	output wire [15:0]addr
+	);
+	
+	`define LCD_480800
+`ifdef LCD_480800
+	//800*480
+//	localparam TFT_H = 800;  //TFT屏行像素点个数
+//	localparam TFT_V = 480;  //TFT屏场像素点个数
+	
+//	localparam thb = 256;
+//	localparam th = 1056 + thb;
+
+//	localparam tvb = 45;
+//	localparam tv = 525 + tvb;
+	//640*480
+	localparam TFT_H = 640;  //TFT屏行像素点个数
+	localparam TFT_V = 480;  //TFT屏场像素点个数
+	
+	localparam thb = 160;
+	localparam th = 640 + thb;
+
+	localparam tvb = 45;
+	localparam tv = 525 + tvb;
+`else
+	
+	localparam TFT_H = 480;  //TFT屏行像素点个数
+	localparam TFT_V = 272;  //TFT屏场像素点个数
+	
+	localparam thb = 41;
+	localparam th = 533 + thb;
+
+	localparam tvb = 10;
+	localparam tv = 288 + tvb;
+`endif
+
+	reg [10:0] counter_hs;
+	reg [10:0] counter_vs;
+
+	always@(posedge clk)begin
+	if(rest_n == 1'b0)begin
+		counter_hs <= 0;
+		counter_vs <= 0;
+	end
+	else begin
+	if(counter_hs == th	)begin
+		if(counter_vs == tv)
+			counter_vs <= 0;
+		else
+			counter_vs <= counter_vs + 1;
+			counter_hs <= 0;
+	end
+	else
+		counter_hs <= counter_hs + 1;
+	end	
+	end
+
+	reg [10:0]img_hbegin = 0;   //图片左上角第一个像素点在TFT屏的行向坐标
+	reg [10:0]img_vbegin = 0;   //图片左上角第一个像素点在TFT屏的场向坐标
+
+	assign lcd_clk = (rest_n == 1) ? clk : 1'b0;
+	assign lcd_pwm = (rest_n == 1) ? 1'b1 : 1'b0;
+	assign lcd_hsync = (counter_hs >= (thb+4) && counter_hs < (th-5)) ? 0 : 1;
+	assign lcd_vsync = (counter_vs >= (tvb+2) && counter_vs < (tv-5)) ? 0 : 1;
+	assign lcd_de = (counter_hs >= thb && counter_hs <= th && counter_vs >= tvb  && counter_vs < tv) ? 1 : 0;
+ 	assign hsync_cnt = counter_hs;
+ 	assign vsync_cnt = counter_vs;
+
+	assign img_ack = lcd_de &&
+	((counter_hs - thb) >= IMG_X && (counter_hs - thb) < (IMG_X + IMG_W)) && 
+	((counter_vs - tvb) >= IMG_Y && (counter_vs - tvb) < (IMG_Y + IMG_H))?1'b1:1'b0;
+	
+ 	reg [15:0]read_addr;             //读图片数据rom地址                  
+//    wire [15:0]img_data;       //读出图片数据
+/*
+ 	img mif_img
+ 	(
+ 		.doa(img_data), 
+ 		.addra(addr), 
+ 		.clka(clk), 
+ 		.rsta(!rest_n) 
+ 	);
+ 	*/
+ 	
+ 	assign addr = read_addr;
+ 	
+ 	 always@(posedge clk or negedge rest_n)
+     begin
+         if(!rest_n)
+             read_addr <= 16'd0;
+         else if(img_ack)
+             read_addr <= (counter_hs - IMG_X - thb) + (counter_vs - IMG_Y - tvb)*IMG_W;
+         else
+             read_addr <= 16'd0;  
+     end
+     
+     
+// 		reg [20:0] pixel_counter;
+//always@(posedge clk)
+//begin
+//if(reset == 1'b0)
+//	begin
+//		pixel_counter <= 0;
+//	end
+//	else
+//		begin
+//			if(counter_hs >= 46 && counter_hs <= 686 && counter_vs >= 23  && counter_vs < 503)
+//			begin
+//				pixel_counter <= pixel_counter + 1;
+//			end
+//		else
+//			if(counter_vs == 504)
+//				pixel_counter <= 0;
+//		end	
+//end	 
+
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/sccb_v1/camera_init.v

@@ -0,0 +1,444 @@
+module camera_init (
+
+	input clk,
+	input reset_n,
+
+	output reg ready,
+
+	output wire sda_oe,
+	output wire sda,
+	input wire sda_in,
+	output scl
+);
+
+parameter REGS_TO_INIT = 200;
+
+localparam CAMERA_INIT_1 = 11;
+localparam CAMERA_INIT_2 = 12;
+localparam CAMERA_INIT_3 = 13;
+localparam CAMERA_INIT_4 = 14;
+localparam CAMERA_INIT_5 = 15;
+localparam CAMERA_INIT_6 = 16;
+localparam CAMERA_INIT_7 = 17;
+localparam CAMERA_IDLE = 18;
+
+localparam CONTROL_REG = 3'b000;
+localparam SLAVE_ADDRESS = 3'b001;
+localparam SLAVE_REG_ADDRESS = 3'b010;
+localparam SLAVE_DATA_1 = 3'b011;
+localparam SLAVE_DATA_2 = 3'b100;
+
+//I2C//////////////////////////////////////////
+reg[7:0] data_in_bus = 0;
+reg [2:0] reg_address = 0;
+reg bus_write = 0;
+wire ready_out;
+wire success_out;
+
+i2c_module i2c_write_module(.clk(clk), .reset_n(reset_n), .scl_out(scl), 
+						.writedata(data_in_bus), .address(reg_address),
+						.write(bus_write), .ready(ready_out), .success_out(success_out), .sda_in(sda_in), .sda(sda), .sda_oe(sda_oe)  );
+
+/////////////////////////////////////////
+
+wire[7:0] regs_addr;
+wire[7:0] data_to_write;
+reg[7:0] counter = 0;
+
+reg[7:0] state_next;
+
+
+wire [15:0] regs_data = 
+	counter == 0 ? 16'hff_01:
+	counter == 1 ? 16'h12_80:
+	counter == 2 ? 16'hff_00:
+	counter == 3 ? 16'h2c_ff:
+	counter == 4 ? 16'h2e_df:
+	counter == 5 ? 16'hff_01:
+	counter == 6 ? 16'h3c_32:
+	counter == 7 ? 16'h11_00:
+	counter == 8 ? 16'h09_02:
+	counter == 9 ? 16'h04_d8:
+	counter == 10 ? 16'h13_e5:
+	counter == 11 ? 16'h14_48:
+	counter == 12 ? 16'h2c_0c:
+	counter == 13 ? 16'h33_78:
+	counter == 14 ? 16'h3a_33:
+	counter == 15 ? 16'h3b_fb:
+	counter == 16 ? 16'h3e_00:
+	counter == 17 ? 16'h43_11:
+	counter == 18 ? 16'h16_10:
+	counter == 19 ? 16'h39_92:
+	counter == 20 ? 16'h35_da:
+	counter == 21 ? 16'h22_1a:
+	counter == 22 ? 16'h37_c3:
+	counter == 23 ? 16'h23_00:
+	counter == 24 ? 16'h34_c0:
+	counter == 25 ? 16'h36_1a:
+	counter == 26 ? 16'h06_88:
+	counter == 27 ? 16'h07_c0:
+	counter == 28 ? 16'h0d_87:
+	counter == 29 ? 16'h0e_41:
+	counter == 30 ? 16'h4c_00:
+	counter == 31 ? 16'h48_00:
+	counter == 32 ? 16'h5b_00:
+	counter == 33 ? 16'h42_03:
+	counter == 34 ? 16'h4a_81:
+	counter == 35 ? 16'h21_99:
+	counter == 36 ? 16'h24_40:
+	counter == 37 ? 16'h25_38:
+	counter == 38 ? 16'h26_82:
+	counter == 39 ? 16'h5c_00:
+	counter == 40 ? 16'h63_00:
+	counter == 41 ? 16'h46_00:
+	counter == 42 ? 16'h0c_3c:
+	counter == 43 ? 16'h61_70:
+	counter == 44 ? 16'h62_80:
+	counter == 45 ? 16'h7c_05:
+	counter == 46 ? 16'h20_80:
+	counter == 47 ? 16'h28_30:
+	counter == 48 ? 16'h6c_00:
+	counter == 49 ? 16'h6d_80:
+	counter == 50 ? 16'h6e_00:
+	counter == 51 ? 16'h70_02:
+	counter == 52 ? 16'h71_94:
+	counter == 53 ? 16'h73_c1:
+	counter == 54 ? 16'h3d_34:
+	counter == 55 ? 16'h5a_57:
+	counter == 56 ? 16'h12_00:
+	counter == 57 ? 16'h17_11:
+	counter == 58 ? 16'h18_75:
+	counter == 59 ? 16'h19_01:
+	counter == 60 ? 16'h1a_97:
+	counter == 61 ? 16'h32_36:
+	counter == 62 ? 16'h03_0f:
+	counter == 63 ? 16'h37_40:
+	counter == 64 ? 16'h4f_ca:
+	counter == 65 ? 16'h50_a8:
+	counter == 66 ? 16'h5a_23:
+	counter == 67 ? 16'h6d_00:
+	counter == 68 ? 16'h6d_38:
+	counter == 69 ? 16'hff_00:
+	counter == 70 ? 16'he5_7f:
+	counter == 71 ? 16'hf9_c0:
+	counter == 72 ? 16'h41_24:
+	counter == 73 ? 16'he0_14:
+	counter == 74 ? 16'h76_ff:
+	counter == 75 ? 16'h33_a0:
+	counter == 76 ? 16'h42_20:
+	counter == 77 ? 16'h43_18:
+	counter == 78 ? 16'h4c_00:
+	counter == 79 ? 16'h87_d5:
+	counter == 80 ? 16'h88_3f:
+	counter == 81 ? 16'hd7_03:
+	counter == 82 ? 16'hd9_10:
+	counter == 83 ? 16'hd3_82:
+	counter == 84 ? 16'hc8_08:
+	counter == 85 ? 16'hc9_80:
+	counter == 86 ? 16'h7c_00:
+	counter == 87 ? 16'h7d_00:
+	counter == 88 ? 16'h7c_03:
+	counter == 89 ? 16'h7d_48:
+	counter == 90 ? 16'h7d_48:
+	counter == 91 ? 16'h7c_08:
+	counter == 92 ? 16'h7d_20:
+	counter == 93 ? 16'h7d_10:
+	counter == 94 ? 16'h7d_0e:
+	counter == 95 ? 16'h90_00:
+	counter == 96 ? 16'h91_0e:
+	counter == 97 ? 16'h91_1a:
+	counter == 98 ? 16'h91_31:
+	counter == 99 ? 16'h91_5a:
+	counter == 100 ? 16'h91_69:
+	counter == 101 ? 16'h91_75:
+	counter == 102 ? 16'h91_7e:
+	counter == 103 ? 16'h91_88:
+	counter == 104 ? 16'h91_8f:
+	counter == 105 ? 16'h91_96:
+	counter == 106 ? 16'h91_a3:
+	counter == 107 ? 16'h91_af:
+	counter == 108 ? 16'h91_c4:
+	counter == 109 ? 16'h91_d7:
+	counter == 110 ? 16'h91_e8:
+	counter == 111 ? 16'h91_20:
+	counter == 112 ? 16'h92_00:
+	counter == 113 ? 16'h93_06:
+	counter == 114 ? 16'h93_e3:
+	counter == 115 ? 16'h93_05:
+	counter == 116 ? 16'h93_05:
+	counter == 117 ? 16'h93_00:
+	counter == 118 ? 16'h93_04:
+	counter == 119 ? 16'h93_00:
+	counter == 120 ? 16'h93_00:
+	counter == 121 ? 16'h93_00:
+	counter == 122 ? 16'h93_00:
+	counter == 123 ? 16'h93_00:
+	counter == 124 ? 16'h93_00:
+	counter == 125 ? 16'h93_00:
+	counter == 126 ? 16'h96_00:
+	counter == 127 ? 16'h97_08:
+	counter == 128 ? 16'h97_19:
+	counter == 129 ? 16'h97_02:
+	counter == 130 ? 16'h97_0c:
+	counter == 131 ? 16'h97_24:
+	counter == 132 ? 16'h97_30:
+	counter == 133 ? 16'h97_28:
+	counter == 134 ? 16'h97_26:
+	counter == 135 ? 16'h97_02:
+	counter == 136 ? 16'h97_98:
+	counter == 137 ? 16'h97_80:
+	counter == 138 ? 16'h97_00:
+	counter == 139 ? 16'h97_00:
+	counter == 140 ? 16'hc3_ef:
+	counter == 141 ? 16'ha4_00:
+	counter == 142 ? 16'ha8_00:
+	counter == 143 ? 16'hc5_11:
+	counter == 144 ? 16'hc6_51:
+	counter == 145 ? 16'hbf_80:
+	counter == 146 ? 16'hc7_10:
+	counter == 147 ? 16'hb6_66:
+	counter == 148 ? 16'hb8_a5:
+	counter == 149 ? 16'hb7_64:
+	counter == 150 ? 16'hb9_7c:
+	counter == 151 ? 16'hb3_af:
+	counter == 152 ? 16'hb4_97:
+	counter == 153 ? 16'hb5_ff:
+	counter == 154 ? 16'hb0_c5:
+	counter == 155 ? 16'hb1_94:
+	counter == 156 ? 16'hb2_0f:
+	counter == 157 ? 16'hc4_5c:
+	counter == 158 ? 16'hc0_c8:
+	counter == 159 ? 16'hc1_96:
+	counter == 160 ? 16'h8c_00:
+	counter == 161 ? 16'h86_3d:
+	counter == 162 ? 16'h50_00:
+	counter == 163 ? 16'h51_90:
+	counter == 164 ? 16'h52_2c:
+	counter == 165 ? 16'h53_00:
+	counter == 166 ? 16'h54_00:
+	counter == 167 ? 16'h55_88:
+	counter == 168 ? 16'h5a_90:
+	counter == 169 ? 16'h5b_2c:
+	counter == 170 ? 16'h5c_05:
+	counter == 171 ? 16'hd3_02:
+	counter == 172 ? 16'hc3_ed:
+	counter == 173 ? 16'h7f_00:
+	counter == 174 ? 16'hda_09:
+	counter == 175 ? 16'he5_1f:
+	counter == 176 ? 16'he1_67:
+	counter == 177 ? 16'he0_00:
+	counter == 178 ? 16'hdd_7f:
+	counter == 179 ? 16'h05_00:
+	//Set OV2640 to RGB565 Mode
+	counter == 180 ? 16'hff_00:
+	counter == 181 ? 16'hda_09:
+	counter == 182 ? 16'hd7_03:
+	counter == 183 ? 16'hdf_02:
+	counter == 184 ? 16'h33_a0:
+	counter == 185 ? 16'h3c_00:
+	counter == 186 ? 16'he1_67:
+	counter == 187 ? 16'hff_01:
+	counter == 188 ? 16'he0_00:
+	counter == 189 ? 16'he1_00:
+	counter == 190 ? 16'he5_00:
+	counter == 191 ? 16'hd7_00:
+	counter == 192 ? 16'hda_00:
+	counter == 193 ? 16'he0_00:
+	//[OV2640_OutSize_Set] width:480 height:272
+	counter == 194 ? 16'hff_00:
+	counter == 195 ? 16'he0_04:
+	counter == 196 ? 16'h5a_32:	//OUTW/4&0xff
+	counter == 197 ? 16'h5b_29: //OUTH/4&0xff
+	counter == 198 ? 16'h5c_00:
+	counter == 199 ? 16'he0_00:
+	16'hFF;
+
+//assign regs_addr = 	counter == 0 ? 8'h12 :
+//							counter == 1 ? 8'h12 :
+//							counter == 2 ? 8'h12 :	
+//							counter == 3 ? 8'h40 :
+//							counter == 4 ? 8'h58 :
+//							counter == 5 ? 8'h1e :
+//							counter == 6 ? 8'h3c :
+//							8'hFF;
+							
+//assign data_to_write = 	counter == 0 ? 8'h80 :
+//								counter == 1 ? 8'h04 :
+//								counter == 2 ? 8'h04 :	
+//								counter == 3 ? 8'hd0 :
+//								counter == 4 ? 8'h9e :
+//								counter == 5 ? 8'h01 :
+//								counter == 6 ? 8'h78 :
+//								8'hFF;
+								
+always@(posedge clk)
+begin
+		if(state_next == CAMERA_IDLE)
+			ready <= 1'b1;
+		else
+			ready <= 1'b0;
+end
+	
+always@(posedge clk)
+begin
+
+	if(reset_n == 1'b0)
+	begin
+		state_next <= CAMERA_INIT_1;	
+	end
+	else
+	begin
+		case(state_next)
+			
+			CAMERA_INIT_1:
+				begin 
+					state_next <= CAMERA_INIT_2;		
+				end
+			
+			CAMERA_INIT_2:
+				begin
+						state_next <= CAMERA_INIT_3;
+				end
+			
+			CAMERA_INIT_3:
+				begin
+					state_next <= CAMERA_INIT_4;
+				
+				end
+				
+			CAMERA_INIT_4:
+				begin
+					state_next <= CAMERA_INIT_7;
+				end
+			
+			//wait until ready_out is set to 0
+			CAMERA_INIT_7:
+			begin
+				if(ready_out == 1'b0)
+					state_next <= CAMERA_INIT_5;
+			end
+				
+			CAMERA_INIT_5:
+				begin
+					if(ready_out == 1'b1)
+					begin
+						if(success_out == 1'b1)
+						begin
+							if(counter == REGS_TO_INIT - 1)
+							begin
+								state_next <= CAMERA_IDLE;
+							end
+							else
+							state_next <= CAMERA_INIT_6;
+						end
+						else
+						state_next <= CAMERA_INIT_2;
+					end	
+				end
+				
+			CAMERA_INIT_6:
+				begin
+					state_next <= CAMERA_INIT_2;
+				end
+				
+			CAMERA_IDLE:
+				begin
+					state_next <= CAMERA_IDLE;
+				end
+				
+		endcase
+	end
+end
+
+//always@(posedge clk)
+//begin
+//	if(state_next == CAMERA_INIT_6)
+//		counter <= counter + 1'b1;
+//	else
+//		counter <= counter;
+//	
+//end	
+//	
+always@(posedge clk)
+begin
+	if(reset_n == 1'b0)
+	begin
+		reg_address <= 0;
+		data_in_bus <= 0;
+		bus_write <= 1'b0;
+		counter <= 0;
+	end
+	else
+	begin
+		case(state_next)
+			
+			CAMERA_INIT_1:
+				begin
+					reg_address <= SLAVE_ADDRESS;
+					data_in_bus <= 8'h60; // slave address
+					bus_write <= 1'b1;
+				end
+			
+			CAMERA_INIT_2:
+				begin
+					reg_address <= SLAVE_REG_ADDRESS;
+					data_in_bus <= regs_data[15:8];
+					bus_write <= 1'b1;	
+				end
+			
+			CAMERA_INIT_3:
+				begin
+					reg_address <= SLAVE_DATA_1;
+					data_in_bus <= regs_data[7:0];
+					bus_write <= 1'b1;			
+				end
+				
+			CAMERA_INIT_4:
+				begin
+					reg_address <= CONTROL_REG;
+					data_in_bus <= 3'b001;
+					bus_write <= 1'b1;
+				end
+			
+			CAMERA_INIT_5:
+				begin
+					reg_address <= 0;
+					data_in_bus <= 0;
+					bus_write <= 1'b0;
+				end
+				
+			CAMERA_INIT_6:
+				begin
+					bus_write <= 1'b0;
+
+					reg_address <= 0;
+					data_in_bus <= 0;
+					
+					counter <= counter + 1'b1;
+				end
+				
+			CAMERA_INIT_7:
+				begin
+					reg_address <= 0;
+					data_in_bus <= 0;
+					bus_write <= 1'b0;
+				end
+				
+			CAMERA_IDLE:
+				begin
+					reg_address <= 0;
+					data_in_bus <= 0;
+					bus_write <= 1'b0;
+				end
+				
+			default:
+				begin
+					bus_write <= 1'b0;
+					reg_address <= 3'd0;
+					data_in_bus <= 8'd0;
+				end
+		endcase
+	end
+end
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/sccb_v1/i2c_module.v

@@ -0,0 +1,1069 @@
+
+module i2c_module(
+	input clk, //50MHz
+	input reset_n,
+	
+	output reg sda_oe = 1,
+	input wire sda_in,
+	output reg sda = 1,
+	
+	output reg scl_out,
+		
+	input[7:0] writedata,
+	input write,
+	input[2:0] address,
+	
+	output reg ready = 1,
+	output reg success_out = 0
+
+);
+
+reg[7:0] state_next = 0;
+
+localparam STATE_IDLE = 0;
+localparam STATE_ADDRESS_START = 1;
+localparam STATE_ADDRESS_START_2 = 111;
+localparam STATE_ADDRESS_START_3 = 112;
+localparam STATE_ADDRESS_BIT_1 = 2;
+localparam STATE_ADDRESS_BIT_2 = 3;
+localparam STATE_ADDRESS_BIT_3 = 4;
+localparam STATE_ADDRESS_BIT_4 = 5;
+localparam STATE_ADDRESS_BIT_5 = 6;
+localparam STATE_ADDRESS_BIT_6 = 7;
+localparam STATE_ADDRESS_BIT_7 = 8;
+localparam STATE_ADDRESS_BIT_8 = 9;
+localparam STATE_ADDRESS_ACK = 10;
+//localparam STATE_ADDRESS_ACK_2 = 101;
+
+localparam STATE_TRANSIT_1 =	102;
+
+localparam STATE_REG_BIT_1 = 11;
+localparam STATE_REG_BIT_2 = 12;
+localparam STATE_REG_BIT_3 = 13;
+localparam STATE_REG_BIT_4 = 14;
+localparam STATE_REG_BIT_5 = 15;
+localparam STATE_REG_BIT_6 = 16;
+localparam STATE_REG_BIT_7 = 17;
+localparam STATE_REG_BIT_8 = 18;
+localparam STATE_REG_ACK = 19;
+//localparam STATE_REG_ACK_2 = 191;
+
+localparam STATE_TRANSIT_2 =	192;
+
+localparam STATE_DATA_BIT_1 = 20;
+localparam STATE_DATA_BIT_2 = 21;
+localparam STATE_DATA_BIT_3 = 22;
+localparam STATE_DATA_BIT_4 = 23;
+localparam STATE_DATA_BIT_5 = 24;
+localparam STATE_DATA_BIT_6 = 25;
+localparam STATE_DATA_BIT_7 = 26;
+localparam STATE_DATA_BIT_8 = 27;
+localparam STATE_DATA_ACK = 28;
+//localparam STATE_DATA_ACK_2 = 32;
+
+localparam STATE_STOP = 29;
+localparam STATE_STOP_1 = 30;
+localparam STATE_STOP_2 = 31;
+
+//reg[16:0] divider = 0;
+reg clk_div = 0;
+wire clk_div_2;
+reg[7:0] divider2 = 0; 
+
+always@(posedge clk_div_2)
+begin
+		clk_div <= ~clk_div;
+end
+
+always@(posedge clk)
+begin
+	divider2 <= divider2 + 8'b1;
+end
+
+assign clk_div_2 = divider2[7];
+
+reg [7:0] control_reg = 0;
+reg [7:0] slave_address = 0;
+reg [7:0] slave_reg_address = 0;
+reg [7:0] slave_data_1 = 0;
+reg [7:0] slave_data_2 = 0;
+
+always@(posedge clk)
+begin
+	if(reset_n == 0)
+	begin
+		control_reg <= 0;
+		slave_address <= 0;
+		slave_reg_address <= 0;
+		slave_data_1 <= 0;
+		slave_data_2 <= 0;
+	end
+	else
+	begin
+		if(write == 1'b1)
+		begin
+			case(address)
+				3'b000: control_reg <= writedata;
+				3'b001:	slave_address <= writedata;
+				3'b010:	slave_reg_address <= writedata;
+				3'b011:	slave_data_1 <= writedata;
+				3'b100:	slave_data_2 <= writedata;
+			endcase
+		end
+	
+		if(state_next != STATE_IDLE)
+			control_reg <= 0;
+	end
+end
+
+
+reg scl_output_enable = 0;
+reg scl_output_zero = 0;
+
+always@(posedge clk_div_2)
+begin
+	if(scl_output_enable == 1)
+	begin
+		scl_out <= ~scl_out;
+	end
+	else
+	begin
+			if(scl_output_zero == 0)
+				scl_out <= 1'b1;
+			else
+				scl_out <= 1'b0;
+	end
+		
+end
+
+//assign scl_out = scl_output_enable == 1 ? clk_div : scl_output_zero == 0 ? 1'b1 : 1'b0;
+
+reg success = 0;
+
+reg ack_ok = 0;
+
+always@(posedge clk_div_2)
+begin
+	if( (state_next == STATE_ADDRESS_ACK || state_next == STATE_REG_ACK || state_next == STATE_DATA_ACK) && sda_in == 1'b0 && clk_div == 1)
+	begin	
+		ack_ok <= 1'b1;
+	end
+		else
+		ack_ok <= 1'b0;
+end
+
+
+always@(negedge clk_div_2)
+begin
+	if(clk_div == 1)
+	begin
+		if(state_next == STATE_STOP && success == 1'b1)
+			success_out <= 1'b1;
+		else
+			if(state_next == STATE_ADDRESS_START)
+				success_out <= 1'b0;
+	end
+
+end
+
+always@(negedge clk_div_2)
+begin
+	if(reset_n == 0)
+	begin
+	 state_next <= STATE_IDLE;
+	end
+	else
+	begin
+
+		case(state_next)
+			STATE_IDLE:
+			begin
+				if(control_reg[0] == 1'b1 )
+				begin
+					state_next <= STATE_ADDRESS_START;
+				end
+			end
+			
+			STATE_ADDRESS_START:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_START_2;
+				end
+			end
+			
+			STATE_ADDRESS_START_2:
+			begin
+				if(clk_div == 1)
+				begin
+					state_next <= STATE_ADDRESS_START_3;
+				end
+			end
+			
+			STATE_ADDRESS_START_3:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_1;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_2;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_3;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_4;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_5;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_6;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_7;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_BIT_8;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_ADDRESS_ACK;
+				end
+			end
+			
+			STATE_ADDRESS_ACK:
+			begin
+			if(clk_div == 0)
+				begin
+				if(ack_ok == 1'b1)
+					begin
+						state_next <= STATE_TRANSIT_1;
+					end
+					else
+					begin
+						state_next <= STATE_STOP;
+					end
+				end
+			end
+			
+			STATE_TRANSIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_1;
+				end
+			end
+			
+//			STATE_ADDRESS_ACK_2:
+//			begin
+//				if(clk_div == 0)
+//				begin
+//					state_next <= STATE_REG_BIT_1;
+//				end
+//			end
+			
+			STATE_REG_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_2;
+				end
+			end
+			
+			STATE_REG_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_3;
+				end
+			end
+			
+			STATE_REG_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_4;
+				end
+			end
+			
+			STATE_REG_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_5;
+				end
+			end
+			
+			STATE_REG_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_6;
+				end
+			end
+			
+			STATE_REG_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_7;
+				end
+			end
+			
+			STATE_REG_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_BIT_8;
+				end
+			end
+			
+			STATE_REG_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_REG_ACK;
+				end
+			end
+			
+			STATE_REG_ACK:
+			begin
+				if(clk_div == 0)
+				begin
+					if(ack_ok == 1'b1)
+					begin
+						state_next <= STATE_TRANSIT_2;
+					end
+					else
+					begin
+						state_next <= STATE_STOP;
+					end
+				end
+			end
+			
+//			STATE_REG_ACK_2:
+//			begin
+//				if(clk_div == 0)
+//				begin
+//					state_next <= STATE_DATA_BIT_1;
+//				end
+//			end
+
+			STATE_TRANSIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_1;
+				end
+			end
+			
+			
+			STATE_DATA_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_2;
+				end
+			end
+			
+			STATE_DATA_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_3;
+				end
+			end
+			
+			STATE_DATA_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_4;
+				end
+			end
+			
+			STATE_DATA_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_5;
+				end
+			end
+			
+			STATE_DATA_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_6;
+				end
+			end
+			
+			STATE_DATA_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_7;
+				end
+			end
+			
+			STATE_DATA_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_BIT_8;
+				end
+			end
+			
+			STATE_DATA_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_DATA_ACK;
+				end
+			end
+			
+			STATE_DATA_ACK:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_STOP;
+				end
+			end
+
+////////////////////////////////			
+//			STATE_DATA_ACK_2:
+//			begin
+//				if(clk_div == 1)
+//				begin
+//					state_next <= STATE_STOP;
+//				end
+//			end
+////////////////////////////////
+			
+			STATE_STOP:
+			begin
+				if(clk_div == 1)
+				begin
+					state_next <= STATE_STOP_1;
+				end
+			end
+			
+			STATE_STOP_1:
+			begin
+				if(clk_div == 0)
+				begin
+					state_next <= STATE_IDLE;
+				end
+			end
+			
+			STATE_STOP_2:
+			begin
+				if(clk_div == 1)
+				begin
+					state_next <= STATE_IDLE;
+				end
+			end
+						
+		endcase
+	end
+end
+
+always@(negedge clk_div_2)
+begin
+	if(reset_n == 1'b0)
+	begin
+		sda <= 1'b1;
+		sda_oe <= 1'b1;
+		scl_output_enable <= 1'b0;
+		ready <= 1;
+		success <= 0;
+	end
+	else
+	begin
+		case(state_next)
+			STATE_IDLE:
+			begin
+				sda <= 1'b1;
+				sda_oe <= 1'b1;
+				scl_output_enable <= 1'b0;
+				ready <= 1;
+				success <= 0;
+				scl_output_zero = 0;
+			end
+			
+			STATE_ADDRESS_START:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 0;
+					sda_oe <= 1;
+					sda <= 0;
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_ADDRESS_START_2:
+			begin
+				if(clk_div == 1)
+				begin
+					scl_output_zero <= 1;
+					scl_output_enable <= 0;
+					sda_oe <= 1;
+					sda <= 0;
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_ADDRESS_START_3:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[7];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[6];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[5];
+					ready <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[4];
+					ready <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[3];
+					ready <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[2];
+					ready <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[1];
+					ready <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_address[0];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_ADDRESS_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					ready <= 0;
+					scl_output_enable <= 1;
+					sda_oe = 0;
+					sda <= 0;
+					success <= 0;	
+				end
+			end
+			
+			STATE_ADDRESS_ACK:
+			begin
+				if(clk_div == 0)
+				begin
+					if(ack_ok == 1'b1)
+					begin
+						scl_output_zero <= 1;
+						ready <= 0;
+						sda_oe <= 1'b1;
+						scl_output_enable <= 0;
+						sda <= 0;
+						success <= 0;
+					end
+					else
+					begin
+						sda_oe <= 1'b1;
+						sda <= 1'b0;
+						scl_output_enable = 1'b0;
+						ready <= 0;
+						success <= 0;
+						scl_output_zero <= 1;
+					end
+				end
+			end
+			
+////////////////////////////////			
+//			STATE_ADDRESS_ACK_2:
+//			begin
+//				if(clk_div == 1)
+//				begin
+//					ready <= 0;
+//					scl_output_enable <= 1;
+//					sda_oe = 1;
+//					sda <= 0;
+//					success <= 0;
+//				end
+//			end
+//////////////////////////////	
+
+			STATE_TRANSIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[7];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+		
+			STATE_REG_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[6];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+				scl_output_zero <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[5];
+					ready <= 0;
+					success <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[4];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[3];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[2];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[1];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_reg_address[0];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+					ready <= 0;
+					scl_output_enable <= 1;
+					sda_oe = 0;
+					sda <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_REG_ACK:
+			begin
+				if(clk_div == 0)
+				begin
+					if(ack_ok == 1'b1)
+					begin
+						ready <= 0;
+						sda_oe <= 1'b1;
+						scl_output_enable <= 0;
+						sda <= 0;
+						success <= 0;
+						scl_output_zero <= 1;
+					end
+					else
+					begin
+						sda_oe <= 1'b1;
+						sda <= 1'b0;
+						scl_output_enable = 1'b0;
+						ready <= 0;
+						success <= 0;
+						scl_output_zero <= 1;
+					end
+				end
+			end
+			
+//			STATE_REG_ACK_2:
+//			begin
+//					ready <= 0;
+//					scl_output_enable <= 0;
+//					sda_oe = 0;
+//					sda <= 0;
+//					success <= 0;
+//			end
+
+			STATE_TRANSIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[7];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_1:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[6];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_2:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[5];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_3:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[4];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_4:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[3];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_5:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[2];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_6:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[1];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_7:
+			begin
+				if(clk_div == 0)
+				begin
+					scl_output_enable <= 1;
+					sda_oe <= 1;
+					sda <= slave_data_1[0];
+					ready <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_BIT_8:
+			begin
+				if(clk_div == 0)
+				begin
+					ready <= 0;
+					scl_output_enable <= 1;
+					sda_oe <= 0;
+					sda <= 0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_DATA_ACK:
+			begin
+				if(clk_div == 0)
+				begin
+					if(ack_ok == 1'b1)
+					begin
+						sda_oe <= 1'b1;
+						sda <= 1'b0;
+						scl_output_enable = 1'b1;
+						ready <= 0;
+						scl_output_zero = 1;
+						
+						success <= 1;
+					end
+					else
+					begin
+						sda_oe <= 1'b1;
+						sda <= 1'b0;
+						scl_output_enable = 1'b0;
+						ready <= 0;
+						success <= 0;
+						scl_output_zero = 1;
+					end
+				end
+			end
+			
+//			STATE_DATA_ACK_2:
+//			begin
+//					ready <= 0;
+//					scl_output_enable <= 0;
+//					sda_oe = 0;
+//					sda <= 0;
+//					success <= 0;
+//			end
+			
+			STATE_STOP:
+			begin
+				if(clk_div == 1)
+				begin
+					ready <= 0;
+					sda_oe <= 1'b1;
+					sda <= 1'b0;
+					scl_output_enable <= 1'b0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_STOP_1:
+			begin
+				if(clk_div == 0)
+				begin
+					ready <= 0;
+					sda <= 1'b1;
+					sda_oe <= 1'b1;
+					scl_output_enable = 1'b0;
+					success <= 0;
+					scl_output_zero <= 0;
+				end
+			end
+			
+			STATE_STOP_2:
+				begin
+					if(clk_div == 1)
+					begin
+						
+					end
+				end
+			
+			default:
+			begin
+				sda <= 1'b1;
+				sda_oe <= 1'b1;
+				scl_output_enable <= 1'b0;
+				ready <= 1;
+				scl_output_zero <= 0;
+				success <= 0;
+			end
+			
+		endcase
+	end
+end
+
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/sccb_v2/I2C_Interface.v

@@ -0,0 +1,175 @@
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+// I2C_Interface.v
+//
+// Author:			Thanh Tien Truong
+//
+// Description:
+// ------------
+// SCCB interface to communicate with OV7670
+//  - Implementing two-wire data transmission of SCCB protocol
+//	- Using 3-phase write transmission cycle of SCCB protocol
+//
+//////////////////////////////////////////////////////////////////////////////////////////////////////
+`include "global.h"
+`ifndef SCCB_V1
+module I2C_Interface ( 
+    input clk,                                  // 50Mhz clock signal
+    inout siod,                                 // Data signal for SCCB
+    output sioc,                                // Clock signal for SCCB
+    output taken,                               // Flag to go to next address of LUT
+    input send,                                 // Flag to indicate if configuration is finshed
+    input [7:0] rega,                           // Resgister address
+    input [7:0] value);                         // Data to write into a regsiter address
+                            
+    
+    // Internal signals
+    reg [7:0] divider = 8'b00000001;
+    reg [31:0] busy_sr = {32{1'b0}};
+    reg [31:0] data_sr = {32{1'b1}};
+    reg sioc_temp;
+    reg taken_temp;
+    reg siod_temp;
+    
+    // ID of an OV7670 for SCCB protocol
+//    localparam id = 8'h42;
+	// ID of an OV2640 for SCCB protocol
+    localparam id = 8'h60;
+    
+    // Assign value for outputs
+    assign siod = siod_temp;
+    assign sioc = sioc_temp;
+    assign taken = taken_temp;
+    
+    always @ (busy_sr or data_sr[31]) begin
+        // when the bus is idle SIOD must be tri-state
+        if(busy_sr[11:10] == 2'b10 || busy_sr[20:19] == 2'b10 || busy_sr[29:28] == 2'b10) begin
+            siod_temp <= 1'bZ;
+        end
+        // else SIOD will be driven my master (FPGA board)
+        else begin
+            siod_temp <= data_sr[31];
+        end
+    end
+        
+    always @ (posedge clk) begin
+        taken_temp <= 1'b0;
+        
+        // If all 31 bits are transmitted 
+        if(busy_sr[31] == 0) begin
+            // Assert SIOC high for starting new transmission
+            sioc_temp <= 1;
+            
+            // If New data is arrived from LUT 
+            if(send == 1) begin
+                if(divider == 8'b00000000) begin
+                    // Create an data to send through the data signal of the SCCB
+                    // The data is created using 3-phase write transmission cycle of SCCB protocol
+                    //
+                    // Data:  
+                    // 3'b100 --> SIOD will go from 1 to 0 to indicate a start transmission
+                    //            the last bit is an don't care bit
+                    // id     --> the ID of a slave (8'h60). The last bit of the slave is 0 inidicate a write transaction
+                    // 1'b0   --> don't care bit to seperate phases
+                    // rega   --> register address that want to write into
+                    // 1'b0   --> don't care bit to seperate phases
+                    // value  --> data to write into the register address
+                    // 1'b0   --> don't care bit to seperate phases
+                    // 2'b01  --> SIOD will go from 0 to 1 to indicate a stop tranmission
+                    
+                    data_sr <= {3'b100, id, 1'b0, rega, 1'b0, value, 1'b0, 2'b01};
+                    busy_sr <= {3'b111, 9'b111111111, 9'b111111111, 9'b111111111, 2'b11};
+                    taken_temp <= 1'b1;
+                end
+                else begin
+                    divider <= divider + 1;
+                end
+            end
+            
+        end
+        
+        // Implement two-write data transmission of SCCB protocol
+        else begin
+            case ({busy_sr[31:29],busy_sr[2:0]})        // Checking for the start and stop condition
+                // For START condition
+                6'b111_111: begin                       // bit 31th of data_sr is transmitted, SIOC must be high
+                    case (divider[7:6])                 // --> SIOD goes from tri-state to high             
+                        2'b00: sioc_temp <= 1;          
+                        2'b01: sioc_temp <= 1;          
+                        2'b10: sioc_temp <= 1;          
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+                
+                6'b111_110: begin                       // bit 30th of data_sr is transmitted
+                    case (divider[7:6])                 // --> SIOD goes from high to low, SIOC must be high
+                        2'b00: sioc_temp <= 1;          // --> complete START condition
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b111_100: begin                       // bit 29th of data_sr is transmitted (don't care bit)
+                    case (divider[7:6])                 // --> SIOD goes from tri-state to high, then high to low 
+                        2'b00: sioc_temp <= 0;          //     after SIOC goes from high to low 
+                        2'b01: sioc_temp <= 0;          // --> Ready for first transmission from Master to Slave
+                        2'b10: sioc_temp <= 0;
+                        default: sioc_temp <= 0;
+                    endcase
+                end
+            
+                // For STOP condition
+                6'b110_000: begin                       // bit 2nd of data_sr is transmitted (don't care bit)
+                    case (divider[7:6])                 // SIOC waits for 1 clock cyle of 200Khz then go high    
+                        2'b00: sioc_temp <= 0;
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b100_000: begin                       // bit 1st of data_sr is transmitted
+                    case (divider[7:6])                 // SIOD is low
+                        2'b00: sioc_temp <= 1;          // SIOC must be high
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b000_000: begin                       // bit 0th of data_sr is transmitted
+                    case (divider[7:6])                 // SIOD is high
+                        2'b00: sioc_temp <= 1;          // --> SIOD goes from low to high while SIOC is high
+                        2'b01: sioc_temp <= 1;          // --> complete STOP condition for SCCB protocol    
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+                
+                // Between START and STOP condition
+                // SIOC is high on 2 cycles of 400Khz and low on 2 cycle of 400Khz
+                // --> SIOC is 200Khz
+                default: begin                          
+                    case (divider[7:6])
+                        2'b00: sioc_temp <= 0;          
+                        2'b01: sioc_temp <= 1;          
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 0;
+                    endcase
+                end
+            endcase
+        
+            // Create a frequency for SCCB with is 200KHz
+            if(divider == 8'b11111111) begin
+                busy_sr <= {busy_sr[30:0], 1'b0};        // Update number of bit that get transmitted
+                data_sr <= {data_sr[30:0], 1'b1};        // Update new bit 31th by bit 30th
+                divider <= {8{1'b0}};                   // Reset counter for clock divider
+            end
+            else begin
+                divider <= divider + 1;
+            end
+        
+        end
+    end
+endmodule
+`endif

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/sccb_v2/OV7670_Controller.v

@@ -0,0 +1,68 @@
+//////////////////////////////////////////////////////////////////////////////////
+// OV7670_Controller.v
+//
+// Author:			Thanh Tien Truong
+//
+// Description:
+// ------------
+// - Sending data to OV7670 registers through SCCB interface
+//   to configure the mode of the OV7670
+//
+// - The module has 2 instances:
+//   OV7670_Registers    - Like a LUT containing all the registers address 
+//                              and data to write into a registers
+//   I2C_Interface       - SCCB interface to communicate with OV7670
+//	
+//////////////////////////////////////////////////////////////////////////////////
+`include "global.h"
+`ifndef SCCB_V1
+module OV7670_Controller (
+    input clk,                              // 50Mhz clock signal
+    input resend,                           // Reset signal
+    output config_finished,                 // Flag to indicate that the configuration is finished
+    output sioc,                            // SCCB interface - clock signal
+    inout siod,                             // SCCB interface - data signal
+    output reset,                           // RESET signal for OV7670
+    output pwdn                             // PWDN signal for OV7670
+);
+
+    // Internal signals
+    wire [15:0] command;
+    wire finished;
+    wire taken;
+    reg send = 0;
+   
+    // Signal for testing
+    assign config_finished = finished;
+    
+    // Signals for RESET and PWDN OV7670
+    assign reset = 1'b1;
+    assign pwdn = 1'b0;
+    
+    // Signal to indicate that the configuration is finshied    
+    always @ (finished) begin
+        send = ~finished;
+    end
+    
+    // Create an instance of a LUT table 
+    OV7670_Registers u_OV7670_Registers(
+        .clk(clk),                          // 50Mhz clock signal
+        .advance(taken),                    // Flag to advance to next register
+        .command(command),                  // register value and data for OV7670
+        .finished(finished),                // Flag to indicate the configuration is finshed
+        .resend(resend)                     // Re-configure flag for OV7670
+    );
+    
+    // Create an instance of a SCCB interface
+    I2C_Interface u_I2C_Interface(
+        .clk(clk),                          // 50Mhz clock signal
+        .taken(taken),                      // Flag to advance to next register
+        .siod(siod),                        // Clock signal for SCCB interface
+        .sioc(sioc),                        // Data signal for SCCB interface 
+        .send(send),                        // Continue to configure OV7670
+        .rega(command[15:8]),               // Register address
+        .value(command[7:0])                // Data to write into register
+    );
+    
+endmodule
+`endif

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/sccb_v2/OV7670_Registers.v

@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////////////////
+// OV7670_Registers.v
+//
+// Author:			Thanh Tien Truong
+//
+// Description:
+// ------------
+//  LUT containing all the registers address and values 
+//                            
+//////////////////////////////////////////////////////////////////////////////////
+`include "global.h"
+
+`ifndef SCCB_V1
+module OV7670_Registers (
+    input clk, 
+    input resend, 
+    input advance, 
+    output [15:0] command, 
+    output finished
+);
+
+    // Internal signals
+    reg [15:0] sreg;
+    reg finished_temp;
+    reg [7:0] address = {8{1'b0}};
+    
+    // Assign values to outputs
+    assign command = sreg; 
+    assign finished = finished_temp;
+    
+    // When register and value is FFFF
+    // a flag is asserted indicating the configuration is finished
+    always @ (sreg) begin
+        if(sreg == 16'hFFFF) begin
+            finished_temp <= 1;
+        end
+        else begin
+            finished_temp <= 0;
+        end
+    end
+    
+    // Get value out of the LUT
+    always @ (posedge clk) begin
+        if(resend == 0) begin           // reset the configuration
+            address <= {8{1'b0}};
+        end
+        else if(advance == 1) begin     // Get the next value
+            address <= address+1;
+        end
+
+        case (address) 
+
+	0 : sreg <= 16'hff_01;
+	1 : sreg <= 16'h12_80;
+	2 : sreg <= 16'hff_00;
+	3 : sreg <= 16'h2c_ff;
+	4 : sreg <= 16'h2e_df;
+	5 : sreg <= 16'hff_01;
+	6 : sreg <= 16'h3c_32;
+	7 : sreg <= 16'h11_00;
+	8 : sreg <= 16'h09_02;
+	9 : sreg <= 16'h04_d8;
+	10 : sreg <= 16'h13_e5;
+	11 : sreg <= 16'h14_48;
+	12 : sreg <= 16'h2c_0c;
+	13 : sreg <= 16'h33_78;
+	14 : sreg <= 16'h3a_33;
+	15 : sreg <= 16'h3b_fb;
+	16 : sreg <= 16'h3e_00;
+	17 : sreg <= 16'h43_11;
+	18 : sreg <= 16'h16_10;
+	19 : sreg <= 16'h39_92;
+	20 : sreg <= 16'h35_da;
+	21 : sreg <= 16'h22_1a;
+	22 : sreg <= 16'h37_c3;
+	23 : sreg <= 16'h23_00;
+	24 : sreg <= 16'h34_c0;
+	25 : sreg <= 16'h36_1a;
+	26 : sreg <= 16'h06_88;
+	27 : sreg <= 16'h07_c0;
+	28 : sreg <= 16'h0d_87;
+	29 : sreg <= 16'h0e_41;
+	30 : sreg <= 16'h4c_00;
+	31 : sreg <= 16'h48_00;
+	32 : sreg <= 16'h5b_00;
+	33 : sreg <= 16'h42_03;
+	34 : sreg <= 16'h4a_81;
+	35 : sreg <= 16'h21_99;
+	36 : sreg <= 16'h24_40;
+	37 : sreg <= 16'h25_38;
+	38 : sreg <= 16'h26_82;
+	39 : sreg <= 16'h5c_00;
+	40 : sreg <= 16'h63_00;
+	41 : sreg <= 16'h46_22;
+	42 : sreg <= 16'h0c_3c;
+	43 : sreg <= 16'h61_70;
+	44 : sreg <= 16'h62_80;
+	45 : sreg <= 16'h7c_05;
+	46 : sreg <= 16'h20_80;
+	47 : sreg <= 16'h28_30;
+	48 : sreg <= 16'h6c_00;
+	49 : sreg <= 16'h6d_80;
+	50 : sreg <= 16'h6e_00;
+	51 : sreg <= 16'h70_02;
+	52 : sreg <= 16'h71_94;
+	53 : sreg <= 16'h73_c1;
+	54 : sreg <= 16'h3d_34;
+	55 : sreg <= 16'h5a_57;
+	56 : sreg <= 16'h12_40;
+	57 : sreg <= 16'h17_11;
+	58 : sreg <= 16'h18_43;
+	59 : sreg <= 16'h19_00;
+	60 : sreg <= 16'h1a_4b;
+	61 : sreg <= 16'h32_09;
+	62 : sreg <= 16'h37_c0;
+	63 : sreg <= 16'h4f_ca;
+	64 : sreg <= 16'h50_a8;
+	65 : sreg <= 16'h5a_23;
+	66 : sreg <= 16'h6d_00;
+	67 : sreg <= 16'h3d_38;
+	68 : sreg <= 16'hff_00;
+	69 : sreg <= 16'he5_7f;
+	70 : sreg <= 16'hf9_c0;
+	71 : sreg <= 16'h41_24;
+	72 : sreg <= 16'he0_14;
+	73 : sreg <= 16'h76_ff;
+	74 : sreg <= 16'h33_a0;
+	75 : sreg <= 16'h42_20;
+	76 : sreg <= 16'h43_18;
+	77 : sreg <= 16'h4c_00;
+	78 : sreg <= 16'h87_d5;
+	79 : sreg <= 16'h88_3f;
+	80 : sreg <= 16'hd7_03;
+	81 : sreg <= 16'hd9_10;
+	82 : sreg <= 16'hd3_82;
+	83 : sreg <= 16'hc8_08;
+	84 : sreg <= 16'hc9_80;
+	85 : sreg <= 16'h7c_00;
+	86 : sreg <= 16'h7d_00;
+	87 : sreg <= 16'h7c_03;
+	88 : sreg <= 16'h7d_48;
+	89 : sreg <= 16'h7d_48;
+	90 : sreg <= 16'h7c_08;
+	91 : sreg <= 16'h7d_20;
+	92 : sreg <= 16'h7d_10;
+	93 : sreg <= 16'h7d_0e;
+	94 : sreg <= 16'h90_00;
+	95 : sreg <= 16'h91_0e;
+	96 : sreg <= 16'h91_1a;
+	97 : sreg <= 16'h91_31;
+	98 : sreg <= 16'h91_5a;
+	99 : sreg <= 16'h91_69;
+	100 : sreg <= 16'h91_75;
+	101 : sreg <= 16'h91_7e;
+	102 : sreg <= 16'h91_88;
+	103 : sreg <= 16'h91_8f;
+	104 : sreg <= 16'h91_96;
+	105 : sreg <= 16'h91_a3;
+	106 : sreg <= 16'h91_af;
+	107 : sreg <= 16'h91_c4;
+	108 : sreg <= 16'h91_d7;
+	109 : sreg <= 16'h91_e8;
+	110 : sreg <= 16'h91_20;
+	111 : sreg <= 16'h92_00;
+	112 : sreg <= 16'h93_06;
+	113 : sreg <= 16'h93_e3;
+	114 : sreg <= 16'h93_05;
+	115 : sreg <= 16'h93_05;
+	116 : sreg <= 16'h93_00;
+	117 : sreg <= 16'h93_04;
+	118 : sreg <= 16'h93_00;
+	119 : sreg <= 16'h93_00;
+	120 : sreg <= 16'h93_00;
+	121 : sreg <= 16'h93_00;
+	122 : sreg <= 16'h93_00;
+	123 : sreg <= 16'h93_00;
+	124 : sreg <= 16'h93_00;
+	125 : sreg <= 16'h96_00;
+	126 : sreg <= 16'h97_08;
+	127 : sreg <= 16'h97_19;
+	128 : sreg <= 16'h97_02;
+	129 : sreg <= 16'h97_0c;
+	130 : sreg <= 16'h97_24;
+	131 : sreg <= 16'h97_30;
+	132 : sreg <= 16'h97_28;
+	133 : sreg <= 16'h97_26;
+	134 : sreg <= 16'h97_02;
+	135 : sreg <= 16'h97_98;
+	136 : sreg <= 16'h97_80;
+	137 : sreg <= 16'h97_00;
+	138 : sreg <= 16'h97_00;
+	139 : sreg <= 16'hc3_ed;
+	140 : sreg <= 16'ha4_00;
+	141 : sreg <= 16'ha8_00;
+	142 : sreg <= 16'hc5_11;
+	143 : sreg <= 16'hc6_51;
+	144 : sreg <= 16'hbf_80;
+	145 : sreg <= 16'hc7_10;
+	146 : sreg <= 16'hb6_66;
+	147 : sreg <= 16'hb8_a5;
+	148 : sreg <= 16'hb7_64;
+	149 : sreg <= 16'hb9_7c;
+	150 : sreg <= 16'hb3_af;
+	151 : sreg <= 16'hb4_97;
+	152 : sreg <= 16'hb5_ff;
+	153 : sreg <= 16'hb0_c5;
+	154 : sreg <= 16'hb1_94;
+	155 : sreg <= 16'hb2_0f;
+	156 : sreg <= 16'hc4_5c;
+	157 : sreg <= 16'hc0_64;
+	158 : sreg <= 16'hc1_4b;
+	159 : sreg <= 16'h8c_00;
+	160 : sreg <= 16'h86_3d;
+	161 : sreg <= 16'h50_00;
+	162 : sreg <= 16'h51_c8;
+	163 : sreg <= 16'h52_96;
+	164 : sreg <= 16'h53_00;
+	165 : sreg <= 16'h54_00;
+	166 : sreg <= 16'h55_00;
+	167 : sreg <= 16'h5a_c8;
+	168 : sreg <= 16'h5b_96;
+	169 : sreg <= 16'h5c_00;
+	170 : sreg <= 16'hd3_02;
+	171 : sreg <= 16'hc3_ed;
+	172 : sreg <= 16'h7f_00;
+	173 : sreg <= 16'hda_09;
+	174 : sreg <= 16'he5_1f;
+	175 : sreg <= 16'he1_67;
+	176 : sreg <= 16'he0_00;
+	177 : sreg <= 16'hdd_7f;
+	178 : sreg <= 16'h05_00;
+	179 : sreg <= 16'hff_00;
+	180 : sreg <= 16'hda_09;
+	181 : sreg <= 16'hd7_03;
+	182 : sreg <= 16'hdf_02;
+	183 : sreg <= 16'h33_a0;
+	184 : sreg <= 16'h3c_00;
+	185 : sreg <= 16'he1_67;
+	186 : sreg <= 16'hff_01;
+	187 : sreg <= 16'he0_00;
+	188 : sreg <= 16'he1_00;
+	189 : sreg <= 16'he5_00;
+	190 : sreg <= 16'hd7_00;
+	191 : sreg <= 16'hda_00;
+	192 : sreg <= 16'he0_00;
+	193 : sreg <= 16'hff_00;
+	194 : sreg <= 16'he0_04;
+	195 : sreg <= 16'h5a_2d;
+	196 : sreg <= 16'h5b_2d;
+	197 : sreg <= 16'h5c_00;
+	198 : sreg <= 16'he0_00;
+//	199 : sreg <= 16'hff_01;
+//	200 : sreg <= 16'h12_42;
+
+
+        default : sreg <= 16'hFF_FF;    // End configuration
+        endcase  
+    end
+endmodule
+`endif

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/src/test_cmera.v

@@ -0,0 +1,145 @@
+
+module test_cmera
+	(
+		input wire CLK_IN,	 	//ϵͳʱ
+		input wire RST_N,		//λ,Ĭ
+		//camera
+		input wire CSI_PCLK,	//CSIʱ
+		output wire CSI_XCLK,	//CSIϵͳʱ
+		input wire CSI_HREF,	//ͬ
+		input wire CSI_VSYNC,	//֡ͬ
+		output wire CSI_PWDN,	//ģʽ
+		output wire CSI_RST,	//λ
+		output wire CSI_SOIC,	//SCCB,ʱ
+		inout wire CSI_SOID,	//SCCB,
+		input wire [7:0]CSI_D,	//
+		//lcd
+		output wire [7:0] R,
+		output wire [7:0] G,
+		output wire [7:0] B,
+		output wire LCD_CLK,
+		output wire LCD_HSYNC,
+		output wire LCD_VSYNC,
+		output wire LCD_DEN,
+		output wire LCD_PWM,	//backlight,set to high
+		//test
+		output wire TESTA,
+		output wire TESTB,
+		output wire TESTC,
+		output wire TESTD,
+		output wire TESTE,
+		output wire TESTF,
+		output wire [0:7]OD
+	 );
+	 
+	wire clk_lcd;
+	wire clk_cam;
+	wire clk_sccb;
+	
+	ip_pll pll(
+		.refclk(CLK_IN),		//24M
+		.clk0_out(clk_lcd),		//lcd clk
+		.clk1_out(clk_cam),		//12m,for cam xclk
+		.clk2_out(clk_sccb)		//4m,for sccb init
+	);
+	
+	reg init_state;
+	wire init_ready;
+	wire sda_oe;
+	wire sda;
+	wire sda_in;
+	wire scl;
+
+	camera_init u_camera_init
+	(
+		.clk(clk_sccb),
+		.reset_n(RST_N),
+		.ready(init_ready),
+		.sda_oe(sda_oe),
+		.sda(sda),
+		.sda_in(sda_in),
+		.scl(scl)
+	);
+	assign CSI_SOID = (sda_oe == 1'b1) ? sda : 1'bz;
+	assign sda_in = CSI_SOID;
+	assign CSI_SOIC = scl;
+	assign CSI_PWDN = 1'b0;
+	assign CSI_RST = 1'b1;
+	//test
+//	assign TESTE = (sda_oe == 1'b1) ? sda : 1'bz;
+//	assign TESTF = scl;
+
+	//lcd display
+	wire [10:0] hsync_cnt;
+	wire [10:0] vsync_cnt;
+	wire lcd_rden;
+	wire [15:0]lcd_rddat;	//lcd read
+	wire [15:0]lcd_rdaddr;
+	
+	lcd_sync 
+	#(
+		.IMG_W(200),
+		.IMG_H(164),
+		.IMG_X(50),
+		.IMG_Y(50)
+	)
+	u_lcd_sync
+	(
+  		.clk		(clk_lcd),
+  		.rest_n		(RST_N),
+		.lcd_clk	(LCD_CLK),
+		.lcd_pwm	(LCD_PWM),
+  		.lcd_hsync	(LCD_HSYNC), 
+  		.lcd_vsync	(LCD_VSYNC), 
+  		.lcd_de		(LCD_DEN),
+  		.hsync_cnt	(hsync_cnt),
+  		.vsync_cnt	(vsync_cnt),
+		.img_ack	(lcd_rden),
+		.addr		(lcd_rdaddr)
+  	);
+  
+	wire camera_wrreq,camera_wclk;
+	wire [15:0]camera_wrdat;
+	wire [19:0]camera_addr;
+
+	cameraReader u_cameraReader
+	(
+		.clk(clk_cam),
+		.reset_n(RST_N),
+		.csi_xclk(CSI_XCLK),
+		.csi_pclk(CSI_PCLK),
+		.csi_data(CSI_D),
+		.csi_vsync(!CSI_VSYNC),
+		.csi_hsync(CSI_HREF),
+		.data_out(camera_wrdat),
+		.wrreq(camera_wrreq),
+		.wrclk(camera_wclk),
+		.wraddr(camera_addr)
+	);
+
+  	img_cache uimg 
+  	( 
+  		//write 45000*8
+		.dia(camera_wrdat), 
+		.addra(camera_addr), 
+		.cea(camera_wrreq), 
+		.clka(camera_wclk), 
+		.rsta(!RST_N), 
+		//read 22500*16
+		.dob(lcd_rddat), 
+		.addrb(lcd_rdaddr), 
+		.ceb(lcd_rden),
+		.clkb(clk_lcd), 
+		.rstb(!RST_N)
+	);
+
+//	assign TESTA = fifo_we;
+//	assign TESTB = CSI_PCLK;
+//	assign TESTC = CSI_VSYNC;
+//	assign TESTD = CSI_HREF;
+//	assign OD = CSI_D;
+
+	assign R = lcd_rden ? {lcd_rddat[15:11], lcd_rddat[15:13]} : 8'h00;
+	assign G = lcd_rden ? {lcd_rddat[10:5], lcd_rddat[10:9]} : 8'h00;
+	assign B = lcd_rden ? {lcd_rddat[4:0], lcd_rddat[4:2]} : 8'h00;
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/Imagedata_send.v

@@ -0,0 +1,11 @@
+module Imgdata_send(
+      input wire clk,
+      input wire tft_de,
+      input wire hcount,
+      input wire vcount,
+      output wire img_ack
+  );
+     
+
+     
+ endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/UartTx.v

@@ -0,0 +1,82 @@
+//--------------------------------------------------------------------------------
+// UartTx.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  Straightforward yet simple UART transmitter implementation for FPGA written in Verilog
+//  One stop bit setting is hardcoded
+//  Features continuous data output at BAUD levels up to CLK_HZ / 2
+//  Features early asynchronous 'busy' set and reset to gain time to prepare new data
+//  If multiple UartTX instances should be inferred - make tx_sample_cntr logic common for all TX instances for effective chip area usage
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+UartTx UT1 (
+    .clk(),
+    .nrst( 1'b1 ),
+	//.tx_do_sample(),
+	.tx_data(),
+	.tx_start(),
+	.tx_busy(),
+	.txd()
+    );
+defparam UT1.CLK_HZ = 200_000_000;
+defparam UT1.BAUD = 9600;	// max. BAUD is CLK_HZ / 2
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module UartTx(clk, nrst, tx_data, tx_start, tx_busy, txd);
+//module UartTx(clk, nrst, tx_do_sample, tx_data, tx_start, tx_busy, txd);
+
+parameter CLK_HZ = 200_000_000;
+parameter BAUD = 9600;
+parameter BAUD_DIVISOR = CLK_HZ / BAUD;
+
+input wire clk;
+input wire nrst;
+//input wire tx_do_sample;
+
+input wire [7:0] tx_data;
+input wire tx_start;		// write strobe
+output reg tx_busy = 0;
+output reg txd = 1;
+
+
+reg [9:0] tx_shifter = 0;
+reg [15:0] tx_sample_cntr = 0;
+always @ (posedge clk) begin
+	if ((~nrst) || (tx_sample_cntr[15:0] == 0)) begin
+		tx_sample_cntr[15:0] <= (BAUD_DIVISOR-1);
+	end else begin
+		tx_sample_cntr[15:0] <= tx_sample_cntr[15:0] - 1;
+	end
+end
+wire tx_do_sample = (tx_sample_cntr[15:0] == 0);
+
+
+always @ (posedge clk) begin
+	if (~nrst) begin
+		tx_busy <= 0;
+		tx_shifter[9:0] <= 0;
+		txd <= 1;
+	end else begin
+		if (~tx_busy) begin
+			if (tx_start) begin		// asynchronous data load and 'busy' set
+				tx_shifter[9:0] <= {1'b1,tx_data[7:0],1'b0};
+				tx_busy <= 1;
+			end
+		end else begin
+		
+			if (tx_do_sample) begin		// next bit
+				{tx_shifter[9:0],txd} <= {tx_shifter[9:0],txd} >> 1;	// txd MUST change only on tx_do_sample although data may be loaded earlier
+				if (~|tx_shifter[9:1]) begin		// early asynchronous 'busy' reset
+					tx_busy <= 0;					// txd still holds data, but shifter is ready to get new info
+				end			
+			end	// tx_do_sample
+			
+		end	// ~tx_busy
+	end // ~nrst
+end
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/big_lcd.v

@@ -0,0 +1,80 @@
+module big_lcd(
+
+input clk,
+input reset,
+input [15:0] lcd_readdata,
+output lcd_read,
+
+output wire [7:0] R,
+output wire [7:0] G,
+output wire [7:0] B,
+output wire HSYNC,
+output wire VSYNC,
+output wire LCD_CLK
+
+);
+
+reg [10:0] counter_hs;
+reg [10:0] counter_vs;
+
+reg [20:0] pixel_counter;
+
+assign LCD_CLK = (reset == 1) ? clk : 0;
+
+always@(posedge clk)
+begin
+if(reset == 1'b0)
+	begin
+		counter_hs <= 0;
+		counter_vs <= 0;
+	end
+	else
+		begin
+			if(counter_hs == 1055	)
+			begin
+			
+				if(counter_vs == 524)
+					counter_vs <= 0;
+				else
+					counter_vs <= counter_vs + 1;
+			
+				counter_hs <= 0;
+			end
+			else
+				counter_hs <= counter_hs + 1;
+		end	
+end
+
+wire data_en;
+
+assign lcd_read = (counter_hs >= 42 && counter_hs <= 681 && counter_vs >= 23  && counter_vs < 503) ? 1 : 0;
+
+assign data_en = (counter_hs >= 46 && counter_hs <= 686 && counter_vs >= 23  && counter_vs < 503) ? 1 : 0;
+
+assign VSYNC = (counter_vs >= 0 && counter_vs < 10) ? 0 : 1;
+assign HSYNC = (counter_hs >= 0 && counter_hs < 10) ? 0 : 1;
+
+assign R = data_en == 1 ? {lcd_readdata[15:11], lcd_readdata[15:13]} : 8'hff;
+assign G = data_en == 1 ? {lcd_readdata[10:5], lcd_readdata[10:9]} : 8'h00;
+assign B = data_en == 1 ? {lcd_readdata[4:0], lcd_readdata[4:2]} : 8'h0f;
+
+
+//always@(posedge clk)
+//begin
+//if(reset == 1'b0)
+//	begin
+//		pixel_counter <= 0;
+//	end
+//	else
+//		begin
+//			if(counter_hs >= 46 && counter_hs <= 686 && counter_vs >= 23  && counter_vs < 503)
+//			begin
+//				pixel_counter <= pixel_counter + 1;
+//			end
+//		else
+//			if(counter_vs == 504)
+//				pixel_counter <= 0;
+//		end	
+//end	 
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/cameraReader.v

@@ -0,0 +1,93 @@
+module cameraReader
+#(
+parameter x_size = 800,
+parameter y_size = 480
+)
+(
+	input clk_in,
+	input reset_n,
+	
+	output xclk,
+	
+	input pclk,
+	input [7:0] data,
+	input vsync,
+	input hsync,
+	
+	output reg [15:0] data_out = 0,
+	output wire wrreq,
+	output wire wrclk
+);
+
+reg [19:0] pixel_counter = 0;
+
+assign xclk = reset_n == 1 ? clk_in : 0;
+
+reg vsync_passed = 0;
+reg write_pixel = 0;
+
+reg wrclk1 = 0;
+
+//2��Ƶ
+always@(posedge pclk)
+	wrclk1 <= ~wrclk1;
+
+always@(negedge wrclk1)
+begin
+	if(hsync == 1)
+		write_pixel <= 1;
+	else
+		write_pixel <= 0;
+end
+
+reg [7:0] subpixel;
+reg [15:0] current_pixel;
+
+always@(posedge wrreq )
+begin
+	data_out <= current_pixel;
+end
+
+always@(posedge pclk)
+begin
+	if(reset_n == 0)
+		begin
+			pixel_counter <= 0;
+			vsync_passed <= 0;
+		end
+	else
+		begin
+			if(vsync == 1)
+			begin
+				pixel_counter <= 0;
+				vsync_passed <= 1;
+			end
+			else
+				if(hsync == 1 && vsync_passed == 1)
+				begin
+					if(pixel_counter[0] == 0)
+					begin
+						pixel_counter <= pixel_counter + 1;
+						subpixel <= data;
+					end
+					else
+					begin
+						current_pixel <= { subpixel, data};
+						pixel_counter <= pixel_counter + 1;
+					end
+				end
+				else
+				begin
+				if(write_pixel == 1)
+					pixel_counter <= pixel_counter + 1;
+				else
+					pixel_counter <= 0;
+				end
+		end
+end
+
+assign wrreq = write_pixel == 1 && pixel_counter > 2 ? wrclk1 : 0;
+
+assign wrclk = wrclk1;
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/div_2.v

@@ -0,0 +1,12 @@
+module div_2 (q,clk,reset); //   ���q������ʱ��CLK��ͬ����λ�ź�RESET.
+    output q;
+    input reset;
+    input clk;
+    reg q;
+    always @ (posedge clk or posedge reset)
+    if (reset==0)
+      q<=1'b0; // �����
+      else
+      q<=~q; // ����q�źŷ�ת
+endmodule
+

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/sdram_ctrl.v

@@ -0,0 +1,405 @@
+module sys_sdram (
+    input wire clk,
+    input wire rst_n,
+    input wire i_valid,
+    output reg o_ready,
+    input wire [31:0] i_addr,
+    input wire [15:0] i_wdata,
+    input wire [3:0] i_wstrb,
+    output reg [15:0] o_rdata
+);
+
+parameter CLK_CYCLE_NS = 20;
+parameter POWERON_DELAY_NS = 200000;
+parameter REFRESH_INTERVAL_NS = 15000;
+parameter T_RC = 3+1;
+parameter T_RP = 1+1;
+parameter T_WR = 2+1;
+parameter T_MRD = 2+1;
+parameter T_RFC = 3+1;
+parameter T_RCD = 1+1;
+parameter T_RRD = 1+1;
+parameter CL = 3+1;
+
+reg sdram_ras_n;
+reg sdram_cas_n;
+reg sdram_we_n;
+reg [10:0] sdram_addr;
+reg [1:0] sdram_ba;
+
+wire [15:0] sdram_dq;
+reg [15:0] sdram_dq_r;
+reg sdram_dq_ie;
+assign sdram_dq = sdram_dq_ie ? sdram_dq_r : 'hz;
+
+reg sdram_cs_n;
+reg [3:0] sdram_dm;
+reg sdram_cke;
+
+/*
+*/
+EG_PHY_SDRAM_2M_32 sdr_sdram(
+    .clk(clk),
+    .ras_n(sdram_ras_n),
+    .cas_n(sdram_cas_n),
+    .we_n(sdram_we_n),
+    .addr(sdram_addr),
+    .ba(sdram_ba),
+    .dq(sdram_dq),
+    .cs_n(sdram_cs_n),
+    .dm0(sdram_dm[0]),
+    .dm1(sdram_dm[1]),
+    .dm2(1'b1),
+    .dm3(1'b1),
+    .cke(sdram_cke)
+);
+
+reg [31:0] counter;
+reg [31:0] counter_refresh;
+// 0: power up wait
+// 1: power up precharge all banks
+// 2: power up auto refresh 2 times
+// 3: power up set mode
+// 4: idle
+// 5: refresh
+// 6: reada
+// 7: writea
+reg [4:0] stage;
+
+always @ (posedge clk) begin
+    if (!rst_n) begin
+        counter <= 0;
+        counter_refresh <= 0;
+        stage <= 0;
+    end
+    if (rst_n) begin
+        counter_refresh <= counter_refresh + 1;
+        if (stage == 'h0) begin
+            // nop
+            sdram_cke <= 1;
+            sdram_cs_n <= 0;
+            sdram_ras_n <= 1;
+            sdram_cas_n <= 1;
+            sdram_we_n <= 1;
+
+            sdram_dm <= 4'b1;
+            // wait for 200us
+            if (counter < POWERON_DELAY_NS/CLK_CYCLE_NS) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 1;
+            end
+        end
+        if (stage == 'h1) begin
+            if (counter == 0) begin
+                // precharge all
+                sdram_cke <= 1;
+                sdram_addr[10] <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 0;
+            end else begin
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_RP) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 2;
+            end
+        end
+        if (stage == 'h2) begin
+            if (counter == 0) begin
+                // auto refresh
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 1;
+            end else if (counter == T_RFC) begin
+                // auto refresh
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 1;
+            end else begin
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_RFC*2) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 3;
+            end
+        end
+        if (stage == 'h3) begin
+            if (counter == 0) begin
+                // Mode Register Set
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 0;
+
+                // reserved
+                sdram_ba <= 2'b00;
+                sdram_addr[10] <= 1'b0;
+                // Write Burst Length: Single Bit
+                sdram_addr[9] <= 1;
+                // Test Mode: Normal
+                sdram_addr[8:7] <= 2'b00;
+                // CAS Latency: 3
+                sdram_addr[6:4] <= 3'b011;
+                // Burst Type: Sequential
+                sdram_addr[3] <= 1'b0;
+                // Burst Length: 1
+                sdram_addr[2:0] <= 3'b000;
+            end else begin
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_MRD) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                counter_refresh <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 4;
+            end
+        end
+        if (stage == 'h4) begin
+            if (counter_refresh > REFRESH_INTERVAL_NS/CLK_CYCLE_NS) begin
+                // goto refresh
+                counter <= 0;
+                counter_refresh <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 5;
+            end else if (i_valid) begin
+                if (i_wstrb == 'h0) begin
+                    // goto read
+                    counter <= 0;
+                    // nop
+                    sdram_cke <= 1;
+                    sdram_cs_n <= 0;
+                    sdram_ras_n <= 1;
+                    sdram_cas_n <= 1;
+                    sdram_we_n <= 1;
+                    // next stage
+                    stage <= 6;
+                end else begin
+                    // goto write
+                    counter <= 0;
+                    // nop
+                    sdram_cke <= 1;
+                    sdram_cs_n <= 0;
+                    sdram_ras_n <= 1;
+                    sdram_cas_n <= 1;
+                    sdram_we_n <= 1;
+                    // next stage
+                    stage <= 7;
+                end
+            end else begin
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+        end
+        if (stage == 'h5) begin
+            if (counter == 0) begin
+                // PrechargeAll
+                sdram_cke <= 1;
+                sdram_addr[10] <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 0;
+
+                sdram_dm <= 4'b0;
+            end else if (counter == T_RP) begin
+                // AutoRefresh
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 1;
+            end else begin
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_RP+T_RFC) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 4;
+            end
+        end
+        if (stage == 'h6) begin
+            if (counter == 0) begin
+                // BankActivate
+                sdram_cke <= 1;
+                sdram_ba <= i_addr[3:2];
+                sdram_addr <= i_addr[22:12];
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+
+                sdram_dm <= 4'b0;
+            end else if (counter == T_RCD) begin
+                // Read and Autoprecharge
+                sdram_cke <= 1;
+                sdram_dm <= 4'b0;
+                sdram_ba <= i_addr[3:2];
+                sdram_addr[10] <= 1;
+                sdram_addr[7:0] <= i_addr[11:4];
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 1;
+
+                sdram_dq_ie <= 0;
+            end else if (counter == T_RCD+CL) begin
+                // read complete
+                o_rdata <= sdram_dq;
+                o_ready <= 1;
+            end else begin
+                o_ready <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_RCD+CL+T_RP) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 4;
+            end
+        end
+        if (stage == 'h7) begin
+            if (counter == 0) begin
+                // BankActivate
+                sdram_cke <= 1;
+                sdram_ba <= i_addr[3:2];
+                sdram_addr <= i_addr[22:12];
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 0;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+
+                sdram_dm <= ~i_wstrb;
+            end else if (counter == T_RCD) begin
+                // Write and Autoprecharge
+                sdram_cke <= 1;
+                sdram_dm <= ~i_wstrb;
+                sdram_ba <= i_addr[3:2];
+                sdram_addr[10] <= 1;
+                sdram_addr[7:0] <= i_addr[11:4];
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 0;
+                sdram_we_n <= 0;
+
+                sdram_dq_ie <= 1;
+                sdram_dq_r <= i_wdata;
+                o_ready <= 1;
+            end else begin
+                o_ready <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+            end
+            if (counter < T_RCD+T_WR+T_RP) begin
+                counter <= counter + 1;
+            end else begin
+                counter <= 0;
+                // nop
+                sdram_cke <= 1;
+                sdram_cs_n <= 0;
+                sdram_ras_n <= 1;
+                sdram_cas_n <= 1;
+                sdram_we_n <= 1;
+                // next stage
+                stage <= 4;
+            end
+        end
+    end
+end
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/spi_slave.v

@@ -0,0 +1,161 @@
+/******************************************************************************
+Copyright 2017 Gnarly Grey LLC
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+******************************************************************************/
+
+module spi_slave (
+  input           clk,
+  input           reset_n,
+  
+  input           sclk,
+  input           mosi,
+  input           ssel,
+  output          miso,
+  
+  output [16:0]   mem_addr,
+  input  [7:0]    mem_data  
+  );
+  
+  
+  reg    [1:0]    sclk_reg;
+  reg    [1:0]    mosi_reg;
+  reg    [2:0]    bit_cnt;
+  wire   [7:0]    data_to_send;
+  reg    [7:0]    data_to_send_buf;
+  reg    [7:0]    data_received;
+  reg             byte_received;
+  reg             addr_data_flag;
+  
+  reg    [16:0]   rd_addr_reg;
+  
+  wire            sclk_rising_edge = (sclk_reg == 2'b01);
+  wire            sclk_falling_edge = (sclk_reg == 2'b10);
+  wire            mosi_data = mosi_reg[1];
+  
+  assign          miso = data_to_send_buf[7];
+  assign          mem_addr = rd_addr_reg;
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        sclk_reg <= 2'b00;
+      else
+      if (ssel)
+        sclk_reg <= 2'b00;
+      else
+        sclk_reg <= {sclk_reg[0], sclk};      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        mosi_reg <= 2'b00;
+      else
+      if (ssel)
+        mosi_reg <= 2'b00;
+      else
+        mosi_reg <= {mosi_reg[0], mosi};      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        begin
+          bit_cnt <= 3'h0;
+          data_received <= 8'h00;
+        end
+      else
+      if (ssel)
+        begin
+          bit_cnt <= 3'h0;
+          data_received <= 8'h00;        
+        end
+      else
+      if (sclk_rising_edge)
+        begin
+          bit_cnt <= bit_cnt + 3'h1;
+          data_received <= {data_received[6:0], mosi_data};
+        end
+      else
+        begin
+          bit_cnt <= bit_cnt;
+          data_received <= data_received;
+        end        
+    end
+    
+  always @ (posedge clk or negedge reset_n)  
+    begin
+      if (!reset_n)
+        byte_received <= 1'b0;
+      else
+      if ((!ssel) && sclk_rising_edge && (bit_cnt == 3'h7)) 
+        byte_received <= 1'b1;
+      else
+        byte_received <= 1'b0;      
+    end
+    
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        data_to_send_buf <= 8'h00;
+      else
+      if (ssel)
+        data_to_send_buf <= 8'h00;
+      else
+      if ((bit_cnt == 3'h0) && sclk_falling_edge)
+        data_to_send_buf <= data_to_send;
+      else
+      if (sclk_falling_edge)
+        data_to_send_buf <= {data_to_send_buf[6:0], 1'b0};
+      else
+        data_to_send_buf <= data_to_send_buf;      
+    end    
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        addr_data_flag <= 1'b0;
+      else
+      if (ssel)
+        addr_data_flag <= 1'b0;
+      else
+      if ((!ssel) && byte_received)
+        addr_data_flag <= 1'b1;
+      else
+        addr_data_flag <= addr_data_flag;      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        rd_addr_reg <= 17'h00000;
+      else
+      if ((!addr_data_flag) && byte_received)     
+        rd_addr_reg <= {9'h000, data_received};
+      else
+      if (addr_data_flag && byte_received)
+        rd_addr_reg <= rd_addr_reg + 17'h00001;
+      else
+        rd_addr_reg <= rd_addr_reg;      
+    end  
+
+  assign          data_to_send = mem_data;
+  
+endmodule  

Lichee-Pi_Tang_FPGA_Examples/1.CAM2LCD/test/top.v

@@ -0,0 +1,117 @@
+/******************************************************************************
+Copyright 2017 Gnarly Grey LLC
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+******************************************************************************/
+
+module top 
+(
+ 	input wire CLK_IN,		//24M
+ 	input wire RST_N,
+ 	
+  output          xclk,
+  input           pclk,
+  input           vsync,
+  input           href,
+  input  [7:0]    pdata,
+  output          cam_reset_n,
+  output          cam_pwrdn,
+  
+  output          sioc,
+  inout           siod
+
+  );
+
+  wire            clk_24m /* synthesis syn_keep=1 */;
+  
+  reg    [17:0]   pixel_cnt;
+  reg             pixel_wr_disable;
+  wire            cam_config_done;
+  
+  wire   [16:0]   mem_rd_addr;
+  wire   [7:0]    mem_rd_data;
+  wire            reset_n = 1'b1;
+  
+  //considering two bytes per pixel, taking only one byte out of two by having condition (pixel_cnt[0] == 1'b0)
+  wire            pixel_wr = q_href && (!pixel_wr_disable) && (pixel_cnt[0]==0);
+  wire            xclk_in;  
+  
+  reg    [7:0]    q_pdata;
+  reg             q_vsync, q_href;
+  reg    [15:0]   pix_per_line;
+  
+  always @(posedge pclk)
+    begin
+      q_pdata <= pdata;
+      q_vsync <= vsync;
+      q_href  <= href & (pix_per_line < (320*2));  
+    end
+
+  assign          xclk = clk_24m;
+
+  always @ (posedge pclk)
+    begin
+      pix_per_line <= href ? pix_per_line+1 : 0;
+    end
+
+  //Manage address for writing in DPRAM through pixel counter
+  always @ (posedge pclk)
+    begin
+      if (!reset_n)
+        begin
+          pixel_cnt    <= 18'h00000;
+        end
+      else
+      if (q_vsync)
+        begin
+          pixel_cnt    <= 18'h00000;
+        end
+      else
+      if (q_href) 
+        begin
+          pixel_cnt    <= (pixel_cnt<(320*400*2))    ?  pixel_cnt + 18'h00001 : pixel_cnt;
+        end
+      else
+        begin
+          pixel_cnt <= pixel_cnt;     
+        end  
+    end  
+      
+/*
+  //Disable pixel data write from next frame if SPI transfer has been initiated
+  always @ (posedge pclk)
+    begin
+      if (q_vsync)
+        pixel_wr_disable <= !ssel;
+      else
+        pixel_wr_disable <= pixel_wr_disable;
+    end
+*/
+
+  OV7670_Controller u_OV7670_Controller(
+    .clk             (clk_24m),          // 24Mhz clock signal
+    .resend          (1'b0),             // Reset signal
+    .config_finished (cam_config_done),  // Flag to indicate that the configuration is finished
+    .sioc            (sioc),             // SCCB interface - clock signal
+    .siod            (siod),             // SCCB interface - data signal
+    .reset           (cam_reset_n),      // RESET signal for OV7670
+    .pwdn            (cam_pwrdn)         // PWDN signal for OV7670
+  );  
+  
+endmodule  

Lichee-Pi_Tang_FPGA_Examples/2.LCD/Imagedata_send.v

@@ -0,0 +1,100 @@
+
+`ifdef IMGTEST
+module Imagedata_send
+	(
+      	input wire clk_lcd,			//ϵͳʱ�ӣ�Ĭ��50M
+      	input wire rst_n,			//��λ�źţ��͵�ƽ��Ч
+      	input wire den,			//TFT����ʹ��
+      	input wire [10:0] hcount,	//TFT��ɨ�������
+      	input wire [10:0] vcount,	//TFT��ɨ�������
+		input wire clk,
+      	output wire [7:0] R,
+      	output wire [7:0] G,
+		output wire [7:0] B
+  	);
+  	
+  	 parameter HSYNC_BLANK_WIDTH = 256; // thb
+  	 parameter VSYNC_BLANK_WIDTH = 45;	//tvb
+
+     wire img_ack;              //ͼƬ����ʹ��
+     wire [23:0]img_data;       //����ͼƬ����
+     reg [23:0]imgd;
+
+     localparam IMG_H = 100,  //ͼƬ�����ص����
+                  IMG_V = 100;  //ͼƬ�����ص����
+                   
+     localparam TFT_H = 800,  //TFT�������ص����
+                  TFT_V = 480;  //TFT�������ص����
+                   
+     localparam IMG_HM = TFT_H - IMG_H,  //ͼƬ�з�����ƶ����ص����
+                IMG_VM = TFT_V - IMG_V;    //ͼƬ��������ƶ����ص����
+                   
+     reg [10:0]img_hbegin = 100;   //ͼƬ���Ͻǵ�һ�����ص���TFT������������
+     reg [10:0]img_vbegin = 100;   //ͼƬ���Ͻǵ�һ�����ص���TFT���ij�������
+     
+	 assign img_ack = den && ((hcount - HSYNC_BLANK_WIDTH) >= img_hbegin && (hcount - HSYNC_BLANK_WIDTH) < img_hbegin + IMG_H) &&
+                           ((vcount - VSYNC_BLANK_WIDTH) >= img_vbegin && (vcount - VSYNC_BLANK_WIDTH) < img_vbegin + IMG_V)?1'b1:1'b0;
+                           
+
+//	reg [31:0]timecnt;
+//	reg [10:0]plus;
+//	reg vdir,hdir;
+	
+//	initial
+//	begin
+//		plus<=1;
+//		hdir<=1;;
+//		vdir<=1;
+//	end
+	
+//	always@(posedge clk)
+//	begin
+//          timecnt <= timecnt + 1'b1;
+//		  if(timecnt == 2_400_000)
+//			begin
+//				timecnt <= 0;
+				
+//				if(hdir==1)
+//					begin
+//						img_hbegin <= img_hbegin + plus;
+//					end
+//				else
+//					begin
+//						img_hbegin <= img_hbegin - plus;
+//					end
+					
+//				if(vdir==1)
+//					begin
+//						img_vbegin <= img_vbegin + plus;
+//					end
+//				else
+//					begin
+//						img_vbegin <= img_vbegin - plus;
+//					end
+//					/*
+//				if((img_vbegin == 0) || (img_vbegin == IMG_VM))
+//					begin
+//						vdir = ~vdir;
+//						plus<=5;
+//						imgd<=24'hff0000;
+//					end
+
+//				if((img_hbegin == 0) || (img_hbegin == IMG_HM))
+//					begin
+//						hdir = ~hdir;
+//						plus<=10;
+//						imgd<=24'h0000ff;
+//					end
+//					*/
+//			end
+//	end
+
+//	assign imgd = 24'h00ff00;
+    assign img_data = img_ack ? 24'h00ff00 : 24'h0;
+    
+	assign B = img_data[7:0];
+	assign G = img_data[15:8];
+	assign R = img_data[23:16];
+
+ endmodule
+`endif

Lichee-Pi_Tang_FPGA_Examples/2.LCD/al_ip/ip_pll.v

@@ -0,0 +1,75 @@
+/************************************************************\
+ **  Copyright (c) 2011-2021 Anlogic, Inc.
+ **  All Right Reserved.
+\************************************************************/
+/************************************************************\
+ ** Log	:	This file is generated by Anlogic IP Generator.
+ ** File	:	H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v
+ ** Date	:	2018 08 09
+ ** TD version	:	4.2.217
+\************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+//	Input frequency:             24.000Mhz
+//	Clock multiplication factor: 18
+//	Clock division factor:       13
+//	Clock information:
+//		Clock name	| Frequency 	| Phase shift
+//		C0        	| 33.231 MHZ	| 0  DEG     
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns / 100 fs
+
+module ip_pll(refclk,
+		reset,
+		extlock,
+		clk0_out);
+
+	input refclk;
+	input reset;
+	output extlock;
+	output clk0_out;
+
+	wire clk0_buf;
+
+	EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );
+
+	EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
+		.DYNCFG("DISABLE"),
+		.FIN("24.000"),
+		.FEEDBK_MODE("NORMAL"),
+		.FEEDBK_PATH("CLKC0_EXT"),
+		.STDBY_ENABLE("DISABLE"),
+		.PLLRST_ENA("ENABLE"),
+		.SYNC_ENABLE("ENABLE"),
+		.DERIVE_PLL_CLOCKS("DISABLE"),
+		.GEN_BASIC_CLOCK("DISABLE"),
+		.GMC_GAIN(6),
+		.ICP_CURRENT(3),
+		.KVCO(6),
+		.LPF_CAPACITOR(3),
+		.LPF_RESISTOR(2),
+		.REFCLK_DIV(13),
+		.FBCLK_DIV(18),
+		.CLKC0_ENABLE("ENABLE"),
+		.CLKC0_DIV(30),
+		.CLKC0_CPHASE(30),
+		.CLKC0_FPHASE(0)	)
+	pll_inst (.refclk(refclk),
+		.reset(reset),
+		.stdby(1'b0),
+		.extlock(extlock),
+		.psclk(1'b0),
+		.psdown(1'b0),
+		.psstep(1'b0),
+		.psclksel(3'b000),
+		.psdone(open),
+		.dclk(1'b0),
+		.dcs(1'b0),
+		.dwe(1'b0),
+		.di(8'b00000000),
+		.daddr(6'b000000),
+		.do({open, open, open, open, open, open, open, open}),
+		.fbclk(clk0_out),
+		.clkc({open, open, open, open, clk0_buf}));
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/2.LCD/al_ip/ip_pll_sim.v

@@ -0,0 +1,112 @@
+// Verilog netlist created by TD v4.2.217
+// Thu Aug  9 17:48:06 2018
+
+`timescale 1ns / 1ps
+module ip_pll  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(22)
+  (
+  refclk,
+  reset,
+  clk0_out,
+  extlock
+  );
+
+  input refclk;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(27)
+  input reset;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(28)
+  output clk0_out;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(30)
+  output extlock;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(29)
+
+  wire clk0_buf;  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(32)
+
+  EG_PHY_GCLK bufg_feedback (
+    .clki(clk0_buf),
+    .clko(clk0_out));  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(34)
+  EG_PHY_CONFIG #(
+    .DONE_PERSISTN("ENABLE"),
+    .INIT_PERSISTN("ENABLE"),
+    .JTAG_PERSISTN("DISABLE"),
+    .PROGRAMN_PERSISTN("DISABLE"))
+    config_inst ();
+  EG_PHY_PLL #(
+    .CLKC0_CPHASE(30),
+    .CLKC0_DIV(30),
+    .CLKC0_DIV2_ENABLE("DISABLE"),
+    .CLKC0_ENABLE("ENABLE"),
+    .CLKC0_FPHASE(0),
+    .CLKC1_CPHASE(1),
+    .CLKC1_DIV(1),
+    .CLKC1_DIV2_ENABLE("DISABLE"),
+    .CLKC1_ENABLE("DISABLE"),
+    .CLKC1_FPHASE(0),
+    .CLKC2_CPHASE(1),
+    .CLKC2_DIV(1),
+    .CLKC2_DIV2_ENABLE("DISABLE"),
+    .CLKC2_ENABLE("DISABLE"),
+    .CLKC2_FPHASE(0),
+    .CLKC3_CPHASE(1),
+    .CLKC3_DIV(1),
+    .CLKC3_DIV2_ENABLE("DISABLE"),
+    .CLKC3_ENABLE("DISABLE"),
+    .CLKC3_FPHASE(0),
+    .CLKC4_CPHASE(1),
+    .CLKC4_DIV(1),
+    .CLKC4_DIV2_ENABLE("DISABLE"),
+    .CLKC4_ENABLE("DISABLE"),
+    .CLKC4_FPHASE(0),
+    .DERIVE_PLL_CLOCKS("DISABLE"),
+    .DPHASE_SOURCE("DISABLE"),
+    .DYNCFG("DISABLE"),
+    .FBCLK_DIV(18),
+    .FEEDBK_MODE("NORMAL"),
+    .FEEDBK_PATH("CLKC0_EXT"),
+    .FIN("24.000"),
+    .FREQ_LOCK_ACCURACY(2),
+    .GEN_BASIC_CLOCK("DISABLE"),
+    .GMC_GAIN(6),
+    .GMC_TEST(14),
+    .ICP_CURRENT(3),
+    .IF_ESCLKSTSW("DISABLE"),
+    .INTFB_WAKE("DISABLE"),
+    .KVCO(6),
+    .LPF_CAPACITOR(3),
+    .LPF_RESISTOR(2),
+    .NORESET("DISABLE"),
+    .ODIV_MUXC0("DIV"),
+    .ODIV_MUXC1("DIV"),
+    .ODIV_MUXC2("DIV"),
+    .ODIV_MUXC3("DIV"),
+    .ODIV_MUXC4("DIV"),
+    .PLLC2RST_ENA("DISABLE"),
+    .PLLC34RST_ENA("DISABLE"),
+    .PLLMRST_ENA("DISABLE"),
+    .PLLRST_ENA("ENABLE"),
+    .PLL_LOCK_MODE(0),
+    .PREDIV_MUXC0("VCO"),
+    .PREDIV_MUXC1("VCO"),
+    .PREDIV_MUXC2("VCO"),
+    .PREDIV_MUXC3("VCO"),
+    .PREDIV_MUXC4("VCO"),
+    .REFCLK_DIV(13),
+    .REFCLK_SEL("INTERNAL"),
+    .STDBY_ENABLE("DISABLE"),
+    .STDBY_VCO_ENA("DISABLE"),
+    .SYNC_ENABLE("ENABLE"),
+    .VCO_NORESET("DISABLE"))
+    pll_inst (
+    .daddr(6'b000000),
+    .dclk(1'b0),
+    .dcs(1'b0),
+    .di(8'b00000000),
+    .dwe(1'b0),
+    .fbclk(clk0_out),
+    .psclk(1'b0),
+    .psclksel(3'b000),
+    .psdown(1'b0),
+    .psstep(1'b0),
+    .refclk(refclk),
+    .reset(reset),
+    .stdby(1'b0),
+    .clkc({open_n47,open_n48,open_n49,open_n50,clk0_buf}),
+    .extlock(extlock));  // H:/Work/FPGA/AnLogic/LicheeTang/demo/test_lcd/al_ip/ip_pll.v(73)
+
+endmodule 
+

Lichee-Pi_Tang_FPGA_Examples/2.LCD/data_out.v

@@ -0,0 +1,92 @@
+
+module data_out
+	(	
+		input wire clk_lcd, 
+		output wire [7:0] R,
+		output wire [7:0] G,
+		output wire [7:0] B,
+		input  wire den,
+		input  wire [10:0] hsync,
+		input  wire [10:0] vsync
+	);
+
+	reg [7:0] r_R;
+	reg [7:0] r_G;
+	reg [7:0] r_B;
+
+  parameter HSYNC_BLANK_WIDTH = 256; // thb
+  parameter HSYNC_WIDTH = 1056 + HSYNC_BLANK_WIDTH;     // th
+
+  parameter VSYNC_BLANK_WIDTH = 45;	//tvb
+  parameter VSYNC_WIDTH = 525 + VSYNC_BLANK_WIDTH;		//tv
+
+reg scan_dir;
+reg [31:0]timecnt;
+
+always@(posedge clk_lcd)
+begin
+	timecnt<=timecnt+1'b1;
+	if(timecnt==32'd33_000_000)
+	begin
+		timecnt<=32'h0;
+		scan_dir = ~scan_dir;
+	end
+	
+	if (den) 
+		begin 
+			if(scan_dir==1)
+			begin
+				if (vsync<(160+VSYNC_BLANK_WIDTH)) 
+					begin 
+						r_R<=8'hff; 
+						r_B<=8'h00; 
+						r_G<=8'h00; 
+					end 
+				else if (vsync<(320+VSYNC_BLANK_WIDTH)) 
+					begin 
+						r_R<=8'h00; 
+						r_B<=8'hff; 
+						r_G<=8'h00; 
+					end
+				else if (vsync<VSYNC_WIDTH) 
+					begin 
+						r_R<=8'h00; 
+						r_B<=8'h00; 
+						r_G<=8'hff; 
+					end
+			end
+			else
+			begin
+				if (hsync<(266+HSYNC_BLANK_WIDTH)) 
+					begin 
+						r_R<=8'hff; 
+						r_B<=8'h00; 
+						r_G<=8'h00; 
+					end 
+				else if (hsync<(532+HSYNC_BLANK_WIDTH)) 
+					begin 
+						r_R<=8'h00; 
+						r_B<=8'hff; 
+						r_G<=8'h00; 
+					end 
+				else if (hsync<HSYNC_WIDTH) 
+					begin 
+						r_R<=8'h00; 
+						r_B<=8'h00; 
+						r_G<=8'hff; 
+					end
+				end
+		end
+	else 
+		begin 
+			r_R<=8'h00; 
+			r_B<=8'h00; 
+			r_G<=8'h00;
+		end
+end
+
+	assign R = r_R;
+	assign G = r_G;
+	assign B = r_B;
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/2.LCD/lcd_sync.v

@@ -0,0 +1,139 @@
+
+module lcd_sync
+#(
+ 	//display image at pos
+	parameter IMG_W = 100,  //ͼƬص
+	parameter IMG_H = 100,  //ͼƬص
+	parameter IMG_X = 0,
+	parameter IMG_Y = 0
+)
+(
+	input wire clk,
+	input wire rest_n,
+	output wire lcd_clk,
+	output wire lcd_pwm,
+	output wire lcd_hsync, 
+	output wire lcd_vsync, 
+	output wire lcd_de,
+	output wire [10:0] hsync_cnt,
+	output wire [10:0] vsync_cnt,
+	output wire img_ack,
+	output wire [15:0]addr
+	);
+	
+	`define LCD_480800
+`ifdef LCD_480800
+	//800*480
+	localparam TFT_H = 800;  //TFTص
+	localparam TFT_V = 480;  //TFTص
+	
+	localparam thb = 256;
+	localparam th = 1056 + thb;
+
+	localparam tvb = 45;
+	localparam tv = 525 + tvb;
+
+
+	//640*480
+//	localparam TFT_H = 640;  //TFTص
+//	localparam TFT_V = 480;  //TFTص
+	
+//	localparam thb = 160;
+//	localparam th = 640 + thb;
+
+//	localparam tvb = 45;
+//	localparam tv = 525 + tvb;
+`else
+	
+	localparam TFT_H = 480;  //TFTص
+	localparam TFT_V = 272;  //TFTص
+	
+	localparam thb = 41;
+	localparam th = 533 + thb;
+
+	localparam tvb = 10;
+	localparam tv = 288 + tvb;
+`endif
+
+	reg [10:0] counter_hs;
+	reg [10:0] counter_vs;
+
+	always@(posedge clk)begin
+	if(rest_n == 1'b0)begin
+		counter_hs <= 0;
+		counter_vs <= 0;
+	end
+	else begin
+	if(counter_hs == th	)begin
+		if(counter_vs == tv)
+			counter_vs <= 0;
+		else
+			counter_vs <= counter_vs + 1;
+			counter_hs <= 0;
+	end
+	else
+		counter_hs <= counter_hs + 1;
+	end	
+	end
+
+	reg [10:0]img_hbegin = 0;   //ͼƬϽǵһصTFT
+	reg [10:0]img_vbegin = 0;   //ͼƬϽǵһصTFTij
+
+	assign lcd_clk = (rest_n == 1) ? clk : 1'b0;
+	assign lcd_pwm = (rest_n == 1) ? 1'b1 : 1'b0;
+	assign lcd_hsync = (counter_hs >= (thb+4) && counter_hs < (th-5)) ? 0 : 1;
+	assign lcd_vsync = (counter_vs >= (tvb+2) && counter_vs < (tv-5)) ? 0 : 1;
+	assign lcd_de = (counter_hs >= thb && counter_hs <= th && counter_vs >= tvb  && counter_vs < tv) ? 1 : 0;
+ 	assign hsync_cnt = counter_hs;
+ 	assign vsync_cnt = counter_hs;
+
+	assign img_ack = lcd_de &&
+	((counter_hs - thb) >= IMG_X && (counter_hs - thb) < (IMG_X + IMG_W)) && 
+	((counter_vs - tvb) >= IMG_Y && (counter_vs - tvb) < (IMG_Y + IMG_H))?1'b1:1'b0;
+	
+ 	reg [15:0]read_addr;             //ͼƬromַ                  
+//    wire [15:0]img_data;       //ͼƬ
+/*
+ 	img mif_img
+ 	(
+ 		.doa(img_data), 
+ 		.addra(addr), 
+ 		.clka(clk), 
+ 		.rsta(!rest_n) 
+ 	);
+ 	*/
+ 	
+ 	assign addr = read_addr;
+ 	
+ 	 always@(posedge clk or negedge rest_n)
+     begin
+         if(!rest_n)
+             read_addr <= 16'd0;
+         else if(img_ack)
+             read_addr <= (counter_hs - IMG_X - thb) + (counter_vs - IMG_Y - tvb)*IMG_W;
+         else
+             read_addr <= 16'd0;  
+     end
+     
+     
+// 		reg [20:0] pixel_counter;
+//always@(posedge clk)
+//begin
+//if(reset == 1'b0)
+//	begin
+//		pixel_counter <= 0;
+//	end
+//	else
+//		begin
+//			if(counter_hs >= 46 && counter_hs <= 686 && counter_vs >= 23  && counter_vs < 503)
+//			begin
+//				pixel_counter <= pixel_counter + 1;
+//			end
+//		else
+//			if(counter_vs == 504)
+//				pixel_counter <= 0;
+//		end	
+//end	 
+
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/2.LCD/test_lcd.sdc

@@ -0,0 +1,6 @@
+# ## Log	:	This file is generated by Anlogic Timing Wizard.
+# ## File	:	H:/Work/FPGA/AnLogic/tets_lcd/test_lcd/test_lcd.sdc
+# ## Date	:	15 07 2018
+
+#Created Clock
+##create_clock -name clk_50m -period 20 [get_nets {clk_50m}]

Lichee-Pi_Tang_FPGA_Examples/2.LCD/test_lcd.v

@@ -0,0 +1,68 @@
+
+module test_lcd
+(
+	input wire CLK_IN,
+	input wire RST_N,
+	output wire [0:7] R,
+	output wire [0:7] G,
+	output wire [0:7] B,
+	output wire LCD_CLK,
+	output wire LCD_HSYNC,
+	output wire LCD_VSYNC,
+	output wire LCD_DEN,
+	output wire LCD_PWM		//backlight,set to high
+);
+	wire clk_lcd;
+	wire clklock;
+	wire [10:0] hsync;
+	wire [10:0] vsync;
+
+	ip_pll pll
+	(
+		.refclk		(CLK_IN),
+		.reset		(~RST_N),
+		.extlock		(clklock),
+		.clk0_out	(clk_lcd)
+	);
+	
+	//lcd display
+	wire [10:0] hsync_cnt;
+	wire [10:0] vsync_cnt;
+	wire lcd_rden;
+	wire [15:0]lcd_rddat;	//lcd read
+	wire [15:0]lcd_rdaddr;
+	
+	lcd_sync 
+	#(
+		.IMG_W(800),
+		.IMG_H(480),
+		.IMG_X(0),
+		.IMG_Y(0)
+	)
+	u_lcd_sync
+	(
+  		.clk			(clk_lcd),
+  		.rest_n		(RST_N),
+		.lcd_clk		(LCD_CLK),
+		.lcd_pwm		(LCD_PWM),
+  		.lcd_hsync	(LCD_HSYNC), 
+  		.lcd_vsync	(LCD_VSYNC), 
+  		.lcd_de		(LCD_DEN),
+  		.hsync_cnt	(hsync_cnt),
+  		.vsync_cnt	(vsync_cnt),
+		.img_ack		(lcd_rden),
+		.addr		(lcd_rdaddr)
+  	);
+
+ 	data_out datout
+	(	
+		.clk_lcd		(clk_lcd), 
+		.R			(R),
+		.G			(G),
+		.B			(B),
+		.den			(lcd_rden),
+		.hsync		(hsync_cnt),
+		.vsync		(vsync_cnt)
+	);
+
+endmodule

Lichee-Pi_Tang_FPGA_Examples/README.md

@@ -0,0 +1,8 @@
+# LicheeTang FPGA例程
+
+#0. LED RGB led 闪烁
+
+#1. Camera to LCD
+
+## IDE Download 
+[http://dl.sipeed.com/TANG/Premier/IDE](http://dl.sipeed.com/TANG/Premier/IDE)