TimRudy_ice-chips-verilog/docs/technical-notes.md

Technical Notes

Under construction...

• Floating inputs

• Open Collector (OC) outputs

• 7474, 74112: Meaning of the NonFPGACycleAccurateModels branch, the async/sync behaviour change of devices due to FPGA constraint: "There is no hardware primitive for two async signals together, set and clear"

• 7485

• 74181