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7df9186 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 | // clk_out must be more than twice as fast as the gate_in rate.
`timescale 1ns / 1ns
module data_xdomain #(
parameter size=16
) (
input clk_in,
input gate_in,
input [size-1:0] data_in,
input clk_out,
output gate_out,
output [size-1:0] data_out
);
reg [size-1:0] data_latch=0;
always @(posedge clk_in) if (gate_in) data_latch <= data_in;
wire gate_x;
flag_xdomain foo(
.clk1(clk_in), .flagin_clk1(gate_in),
.clk2(clk_out), .flagout_clk2(gate_x));
wire [size-1:0] data_pipe;
`ifdef HAPPY_VIVADO
// Using data_latch directly is OK by Vivado, but simulation shows
// that doing so markedly reduces the available throughput.
assign data_pipe = data_latch;
`else
// Vivado complains bitterly about this version, calling it
// CDC-4 Critical. See UG906 for discussion.
reg_tech_cdc #(.POST_STAGES(0)) rtc[size-1:0] (.C(clk_out),
.I(data_latch), .O(data_pipe));
`endif
// CDC-15 Warning Clock enable controlled CDC structure detected
// "The CDC engine only checks that [CE] is [valid in clk_out].
// Also, you are responsible for constraining the latency from the
// [clk_in] domain to [clk_out latch input], which is usually done
// by a set_max_delay -datapath_only constraint."
reg [size-1:0] data_out_r=0;
reg gate_out_r=0;
always @(posedge clk_out) begin
if (gate_x) data_out_r <= data_pipe;
gate_out_r <= gate_x;
end
assign data_out = data_out_r;
assign gate_out = gate_out_r;
endmodule
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