Add Batch 8 with 10 repos

BerkeleyLab_Bedrock/.github/workflows/build.yml

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+name: Bedrock documentation
+
+on: [push, pull_request]
+
+jobs:
+  build:
+    # We want to run on external PRs, but not on our own internal PRs as
+    # they'll be run by the push to the branch. Without this if check,
+    # checks are duplicated since internal PRs match both the push and
+    # pull_request events.
+    if: >
+      github.event_name == 'push' ||
+        github.event.pull_request.head.repo.full_name != github.repository
+
+    runs-on: ubuntu-latest
+
+    strategy:
+      fail-fast: false
+
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Setup python
+        uses: actions/setup-python@v5
+        with:
+            python-version: '3.8'
+
+      - name: Install python PIP packages
+        run: |
+          python -m pip install \
+                sphinx==5.0.2 \
+                sphinx_rtd_theme \
+                numpy m2r2==0.3.2
+
+      - name: Install documentation tools
+        run: |
+          sudo apt-get update
+          sudo apt-get -y install make \
+                          imagemagick ghostscript \
+                          iverilog xvfb gtkwave \
+                          texlive-binaries
+          sudo sed -i -e '/pattern="PS"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+                      -e '/pattern="PDF"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+                      -e '/pattern="EPS"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+                      -e '/<\/policymap>/i \  <policy domain="coder" rights="read|write" pattern="{GIF,JPEG,PNG,WEBP}" \/>' /etc/ImageMagick-*/policy.xml
+
+      - name: Build sphinx docs
+        run: |
+          make -C doc html
+
+      - name: Deploy gh-pages
+        uses: peaceiris/actions-gh-pages@v4
+        with:
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          publish_dir: ./doc/_build/html
+
+      - name: Upload artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: badger-doc
+          path: badger/doc/*.svg

BerkeleyLab_Bedrock/.gitlab-ci.yml

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+stages:
+  - build
+  - test
+  - synthesis
+  - program
+  - docs
+
+variables:
+  XILINX_VIVADO: /non-free/Xilinx/Vivado/2020.2
+  CI_REGISTRY: mohs.dhcp.lbl.gov
+  IMAGE_BASE: bedrock_testing_base
+  IMAGE_VARIANT: bookworm
+  DEFAULT_IMAGE: ${CI_REGISTRY}/${IMAGE_BASE}_${IMAGE_VARIANT}
+  DOCKER_HOST: tcp://docker:2375/
+  DOCKER_DRIVER: overlay2
+  FF_SCRIPT_SECTIONS: "true"
+
+# default image if no other specified
+image: $DEFAULT_IMAGE:$CI_COMMIT_REF_NAME
+
+.build-images:
+  parallel:
+    IMAGE_VARIANT: [bookworm, trixie]
+
+# build matrix for docker image generation
+.build-matrix:
+  variables:
+    IMAGE: ${CI_REGISTRY}/${IMAGE_BASE}_${IMAGE_VARIANT}
+    DOCKERFILE: Dockerfile.${IMAGE_BASE}_${IMAGE_VARIANT}
+  parallel:
+    matrix:
+      - !reference [.build-images, parallel]
+
+include:
+  - local: .gitlab/ci/badger.gitlab-ci.yml
+  - local: .gitlab/ci/build.gitlab-ci.yml
+  - local: .gitlab/ci/board_support.gitlab-ci.yml
+  - local: .gitlab/ci/docs.gitlab-ci.yml
+  - local: .gitlab/ci/serial_io.gitlab-ci.yml
+  - local: .gitlab/ci/other_hdl.gitlab-ci.yml
+  - local: .gitlab/ci/soc.gitlab-ci.yml
+  - local: .gitlab/ci/oscope.gitlab-ci.yml
+  - local: .gitlab/ci/cmoc.gitlab-ci.yml
+  - local: .gitlab/ci/comms_top.gitlab-ci.yml
+  - local: .gitlab/ci/dsp.gitlab-ci.yml
+  - local: .gitlab/ci/marble_family.gitlab-ci.yml
+  - local: .gitlab/ci/swap_gitid.gitlab-ci.yml
+  - local: .gitlab/ci/cdc_check.gitlab-ci.yml
+  - local: .gitlab/ci/localbus.gitlab-ci.yml
+  - local: .gitlab/ci/ctrace.gitlab-ci.yml
+
+flake8:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - find . -name "*.py" -exec flake8 {} +

BerkeleyLab_Bedrock/.gitlab/ci/badger.gitlab-ci.yml

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+badger_test:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  before_script:
+    - cd badger/tests && make clean && sh ./tap-setup.sh
+  script:
+    - make && bash tftp_test.sh && bash speed_check.sh
+
+.badger-targets:
+  parallel:
+    TARGET: [ac701, obsidian]
+
+.badger-matrix:
+  extends:
+    - .build-images
+    - .badger-targets
+
+.badger-build-matrix:
+  variables: !reference [.build-matrix, variables]
+  parallel:
+    matrix:
+      - !reference [.badger-matrix, parallel]
+
+.badger-run-matrix:
+  variables: !reference [.build-matrix, variables]
+  parallel:
+    matrix:
+      - !reference [.build-images, parallel]
+
+badger_top:
+  extends: .badger-build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd badger/tests && ls /non-free
+  script:
+    - PATH=$XILINX_VIVADO/bin:$PATH make ${TARGET}_rgmii_vtest.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 2 days
+    paths:
+      - badger/tests/_xilinx/${TARGET}_rgmii_test.reports
+      - badger/tests/${TARGET}_rgmii_vtest.bit
+
+badger_ac701_run:
+  extends: .badger-run-matrix
+  image: $IMAGE
+  stage: program
+  tags:
+    - deploy
+  needs:
+    - job: badger_top
+      parallel:
+        matrix:
+          - IMAGE_VARIANT: !reference [.build-images, parallel, IMAGE_VARIANT]
+            TARGET: ac701
+      artifacts: true
+  script:
+    - cd badger/tests && test -r ac701_rgmii_vtest.bit && SERIAL_NUM_OPT="-s 210203356870" sh teststand_ac701.sh
+  environment: hw_ac701
+  resource_group: hw_ac701

BerkeleyLab_Bedrock/.gitlab/ci/board_support.gitlab-ci.yml

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+board_support_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd board_support
+  stage: test
+  script:
+    - make -C bmb7_kintex jxj_gate_check

BerkeleyLab_Bedrock/.gitlab/ci/build.gitlab-ci.yml

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+check_rebuild:
+  extends: .build-matrix
+  image: docker:stable
+  stage: build
+  script: |
+    echo "DOCKERFILE=${DOCKERFILE}"
+    echo "DOCKER_IMAGE_REBUILD=1" > build.env
+  artifacts:
+    reports:
+      dotenv: build.env
+  rules:
+    - if: '$CI_COMMIT_BRANCH == "master"'
+    - if: $CI_COMMIT_BRANCH
+      changes:
+        - ${DOCKERFILE}
+        - build-tools/litex_meta.sh
+        - .gitlab/ci/build.gitlab-ci.yml
+
+check_exists:
+  extends: .build-matrix
+  image: docker:stable
+  stage: build
+  script: |
+    export DOCKER_CLI_EXPERIMENTAL=enabled
+    docker manifest inspect $IMAGE:$CI_COMMIT_REF_NAME > /dev/null && \
+        DOCKER_IMAGE_EXISTS=1 || DOCKER_IMAGE_EXISTS=0
+    echo "DOCKER_IMAGE_EXISTS=${DOCKER_IMAGE_EXISTS}" > build.env
+  artifacts:
+    reports:
+      dotenv: build.env
+
+# With Gitlab 16.8 we should be able to do"
+#  extends: .build-matrix
+#  needs:
+#    - job: check_rebuild
+#      optional: true
+#      parallel:
+#        matrix:
+#          - IMAGE_VARIANT: ['$[[ matrix.IMAGE_VARIANT ]]']
+#    - job: check_exists
+#      parallel:
+#        matrix:
+#          - IMAGE_VARIANT: ['$[[ matrix.IMAGE_VARIANT ]]']
+
+.build:
+  image: docker:stable
+  stage: build
+  variables:
+  services:
+    - name: mohs.dhcp.lbl.gov/docker:29.4.0-dind
+      command: ["--insecure-registry", "mohs.dhcp.lbl.gov"]
+      alias: docker
+  before_script:
+    - cat /etc/hosts
+    - cat /etc/resolv.conf
+    - docker info
+    - echo $IMAGE:$CI_COMMIT_REF_NAME
+    - echo $IMAGE:$CI_COMMIT_SHORT_SHA
+    - echo $IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA
+  script: |
+    echo "DOCKER_IMAGE_REBUILD=${DOCKER_IMAGE_REBUILD}"
+    echo "DOCKER_IMAGE_EXISTS=${DOCKER_IMAGE_EXISTS}"
+    if [ \( -z "$DOCKER_IMAGE_REBUILD" -o "$DOCKER_IMAGE_REBUILD" == "0" \) -a \
+        "$DOCKER_IMAGE_EXISTS" == "1" ]; then
+      exit 0
+    fi
+    IMAGE_BASENAME=${IMAGE##*/}
+    docker pull $IMAGE:latest || true
+    docker build --cache-from $IMAGE:latest \
+        -t $IMAGE:$CI_COMMIT_REF_NAME \
+        -t $IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA \
+        -t $IMAGE:latest \
+        -f Dockerfile.${IMAGE_BASENAME} \
+        .
+    docker run --rm $IMAGE bash -c 'echo -n "Debian version: "; cat "/etc/debian_version"'
+    docker push $IMAGE:$CI_COMMIT_REF_NAME
+    docker push $IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA
+    docker push $IMAGE:latest
+
+
+build_bookworm:
+  extends: .build
+  variables:
+    IMAGE_VARIANT: bookworm
+    IMAGE: ${CI_REGISTRY}/${IMAGE_BASE}_${IMAGE_VARIANT}
+  needs:
+    - job: check_rebuild
+      optional: true
+      parallel:
+        matrix:
+          - IMAGE_VARIANT: bookworm
+    - job: check_exists
+      parallel:
+        matrix:
+          - IMAGE_VARIANT: bookworm
+
+build_trixie:
+  extends: .build
+  variables:
+    IMAGE_VARIANT: trixie
+    IMAGE: ${CI_REGISTRY}/${IMAGE_BASE}_${IMAGE_VARIANT}
+  needs:
+    - job: check_rebuild
+      optional: true
+      parallel:
+        matrix:
+          - IMAGE_VARIANT: trixie
+    - job: check_exists
+      parallel:
+        matrix:
+          - IMAGE_VARIANT: trixie

BerkeleyLab_Bedrock/.gitlab/ci/cdc_check.gitlab-ci.yml

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+badger_cdc:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C badger/tests hw_test_cdc.txt
+
+marble_cdc:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C projects/test_marble_family marble_base_cdc.txt

BerkeleyLab_Bedrock/.gitlab/ci/cmoc.gitlab-ci.yml

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+rtsim_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd rtsim && make clean && make
+  stage: test
+  script:
+    - make clean && make checks && make rtsim.dat
+
+cmoc_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd cmoc
+  stage: test
+  script:
+    - make && make checks
+
+# Because Gitlab doesn't support using extends with
+# multiple parallel:matrix + Issue 439828 (https://gitlab.com/gitlab-org/gitlab/-/issues/439828)
+# the following is the best I could think of to merge 2 parallel:matrix lists:
+
+# 1. Define the specific dictionary you want
+.marble-targets:
+  parallel:
+    TARGET: [marblemini, marble]
+
+# 2. Merge the above dictionary with tth .build-matrix defined in .gitlab-ci.yml
+# with extends: https://docs.gitlab.com/ci/yaml/yaml_optimization/#merge-details
+.cmoc-top-matrix:
+  extends:
+    - .build-images
+    - .marble-targets
+
+# 3. re-build the yaml structure of .build-matrix replacing "parallel:matrix"
+# with the newly created dictionary on 2.
+.cmoc-top-build-matrix:
+  variables: !reference [.build-matrix, variables]
+  parallel:
+    matrix:
+      - !reference [.cmoc-top-matrix, parallel]
+
+cmoc_top:
+  extends: .cmoc-top-build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/cmoc_top/marblemini && ls /non-free
+  stage: synthesis
+  script:
+    - XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make HARDWARE=${TARGET} cmoc_top.bit
+    - mv cmoc_top.bit cmoc_top_${TARGET}.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - projects/cmoc_top/marblemini/cmoc_top_${TARGET}.bit

BerkeleyLab_Bedrock/.gitlab/ci/comms_top.gitlab-ci.yml

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+comms_top:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/comms_top && ls /non-free
+  stage: synthesis
+  script:
+    - PATH=$XILINX_VIVADO/bin:$PATH make comms_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - projects/comms_top/comms_top.bit
+
+comms_top_run:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: program
+  tags:
+    - deploy
+  dependencies:
+    - comms_top
+  script:
+    - cd projects/comms_top
+    - sh qf2_070_3_setup.sh
+    - make QF2_TOOLS=qf2-pre-users QF2_IP=192.168.1.30 hwload && sleep 8 && make hwtest
+  environment: hw_qf2_pre
+  resource_group: hw_qf2_pre
+
+.doublebit-targets:
+  parallel:
+    DOUBLEBIT: ["0", "1"]
+
+.gige-top-matrix:
+  extends:
+    - .build-images
+    - .doublebit-targets
+
+.gige-top-build-matrix:
+  variables: !reference [.build-matrix, variables]
+  parallel:
+    matrix:
+      - !reference [.gige-top-matrix, parallel]
+
+gige_sfp_ac701:
+  extends: .gige-top-build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd projects/comms_top/gige_eth && ls /non-free
+  script:
+    - PATH=$XILINX_VIVADO/bin:$PATH make HARDWARE=ac701 DOUBLEBIT=$DOUBLEBIT gige_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-DB$DOUBLEBIT-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - projects/comms_top/gige_eth/gige_top.bit
+
+gige_sfp_ac701_run:
+  extends: .gige-top-build-matrix
+  image: $IMAGE
+  stage: program
+  tags:
+    - deploy
+  needs:
+    - job: gige_sfp_ac701
+  script:
+    - cd projects/comms_top/gige_eth && make hwload_ac701 SERIAL_NUM_OPT="-s 210203356870" && sleep 7 && make hwtest_ac701
+  environment: hw_ac701
+  resource_group: hw_ac701

BerkeleyLab_Bedrock/.gitlab/ci/ctrace.gitlab-ci.yml

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+ctrace_test:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C projects/ctrace

BerkeleyLab_Bedrock/.gitlab/ci/docs.gitlab-ci.yml

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+make_docs:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd build-tools/make-demo && make clean
+  stage: test
+  script:
+    - make check consistency
+
+sphinx_docs:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: docs
+  before_script: |
+    apt-get update
+    apt-get install -y \
+        imagemagick \
+        ghostscript \
+        xvfb \
+        gtkwave \
+        texlive-binaries
+    python3 -m pip install \
+        standard-imghdr \
+        sphinx==8.1.3 \
+        sphinx_rtd_theme \
+        m2r2==0.3.4
+    sed -i -e '/pattern="PS"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+        -e '/pattern="PDF"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+        -e '/pattern="EPS"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
+        -e '/<\/policymap>/i \  <policy domain="coder" rights="read|write" pattern="{GIF,JPEG,PNG,WEBP}" \/>' \
+    /etc/ImageMagick-*/policy.xml
+  script:
+    - make -C doc html

BerkeleyLab_Bedrock/.gitlab/ci/dsp.gitlab-ci.yml

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+dsp_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp
+  stage: test
+  script:
+    - make && make checks
+
+dsp_hosted_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp/hosted && export PYTHONPATH=../../build-tools/
+  stage: test
+  script:
+    - make && make checks
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - dsp/hosted/fdbk_core_plot.pdf
+
+digaree_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp/digaree
+  stage: test
+  script:
+    - make
+
+feedforward_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp/feedforward
+  stage: test
+  script:
+    - make
+
+chirp_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp/chirp
+  stage: test
+  script:
+    - make && make checks
+
+cocotb_test:
+  # includes all cocotb testbenches in dsp
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd dsp
+  stage: test
+  script:
+    - make TESTBENCH=cic_simple_s_tb -f Makefile_cocotb
+    - make TESTBENCH=dds_tb -f Makefile_cocotb

BerkeleyLab_Bedrock/.gitlab/ci/localbus.gitlab-ci.yml

@@ -0,0 +1,6 @@
+localbus:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C localbus

BerkeleyLab_Bedrock/.gitlab/ci/marble_family.gitlab-ci.yml

@@ -0,0 +1,97 @@
+marble_sim:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C projects/test_marble_family all net_slave_check
+    - make -C projects/test_marble_family/pps_lock
+
+marble_i2c_check:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C projects/test_marble_family/i2c tests
+
+.bitgen:
+  stage: synthesis
+  before_script:
+    - cd projects/test_marble_family && ls /non-free
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 2 days
+
+.synth_base:
+  extends:
+    - .build-matrix
+    - .bitgen
+  image: $IMAGE
+  script:
+    - PATH=$XILINX_VIVADO/bin:$PATH make CONFIG=${CONFIG} bit
+  artifacts:
+    paths:
+      - projects/test_marble_family/marble*.bit
+      - projects/test_marble_family/vivado.log
+      - projects/test_marble_family/_xilinx/${CONFIG}.runs/*.rpt
+      - projects/test_marble_family/_xilinx/${CONFIG}.runs/synth_1/marble_top_*.rpt
+      - projects/test_marble_family/_xilinx/${CONFIG}.runs/impl_1/marble_top_*.rpt
+
+marble_mini_synth:
+  extends: .synth_base
+  variables:
+    CONFIG: marblemini
+
+marble_v2_synth:
+  extends: .synth_base
+  variables:
+    CONFIG: marble
+
+marble_fiber_synth:
+  extends: .synth_base
+  variables:
+    CONFIG: marble_fiber
+
+.run_base:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: program
+  tags:
+    - deploy
+  before_script:
+    - cd projects/test_marble_family && ln -s ${CONFIG}.*.bit ${CONFIG}.bit
+  script:
+    - make CONFIG=${CONFIG} hwload ${SERIAL_ARG} && make CONFIG=${CONFIG} hwtest ${SERIAL_ARG}
+    - if [ -n "$RUN_I2C" ]; then make -C i2c live_oneshot ${SERIAL_ARG}; fi
+
+marble_mini_run:
+  extends: .run_base
+  dependencies:
+    - marble_mini_synth
+  environment: hw_marble_mini
+  resource_group: hw_marble_mini
+  variables:
+    CONFIG: marblemini
+    SERIAL_ARG: ""
+    RUN_I2C: ""
+
+marble_run:
+  extends: .run_base
+  dependencies:
+    - marble_v2_synth
+  environment: hw_marble
+  resource_group: hw_marble
+  variables:
+    CONFIG: marble
+    SERIAL_ARG: "SERIAL=39"
+    RUN_I2C: "true"
+
+marble_fiber_run:
+  extends: .run_base
+  dependencies:
+    - marble_fiber_synth
+  environment: hw_marble
+  resource_group: hw_marble
+  variables:
+    CONFIG: marble_fiber
+    SERIAL_ARG: "SERIAL=39"
+    RUN_I2C: "true"

BerkeleyLab_Bedrock/.gitlab/ci/oscope.gitlab-ci.yml

@@ -0,0 +1,97 @@
+oscope_top_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/oscope/bmb7_cu
+  stage: test
+  script:
+    - make Voscope_top_tb && make Voscope_top_leep && make clean
+
+# We know the design doesn't yet get evaluated as CDC-clean, at least in part
+# due to Verilog inout ports being poorly supported by our tools.
+# Please take out the error bypass (echo) if this ever gets fixed.
+oscope_cdc:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/oscope/marble_family
+  stage: test
+  script:
+    - make dep && make oscope_prep_yosys.json && (make oscope_prep_cdc.txt || echo "Found CDC violation, as expected; continuing")
+  artifacts:
+    expire_in: 1 week
+    paths:
+      - projects/oscope/marble_family/oscope_prep_cdc.txt
+
+oscope_top_bmb7:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/oscope/bmb7_cu && ls /non-free
+  stage: synthesis
+  script:
+    - verilator -V && XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make oscope_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - projects/oscope/bmb7_cu/oscope_top.bit
+
+oscope_top_marble:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd projects/oscope/marble_family && ls /non-free
+  stage: synthesis
+  script:
+    - verilator -V && XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make oscope_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - projects/oscope/marble_family/oscope_top.bit
+
+# LITEX_INSTALL_PATH is defined in the Docker image
+marble_ddr3_test:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets
+  script:
+    - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && python3 berkeleylab_marble.py --build
+    - echo $CI_PROJECT_DIR
+    - cp $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets/build/berkeleylab_marble/gateware/berkeleylab_marble.bit $CI_PROJECT_DIR/
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    when: always
+    paths:
+      - berkeleylab_marble.bit
+
+litex_trigger_capture:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd projects/trigger_capture
+  script:
+    XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && make marble.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    when: always
+    paths:
+      - projects/trigger_capture/build/marble/gateware/marble.bit
+      - projects/trigger_capture/csr.csv
+
+# oscope_program:
+#   extends: .build-matrix
+#   image: $IMAGE
+#   before_script:
+#     - cd projects/oscope/software/bmb7 && wget -r -nH http://sliderule.dhcp.lbl.gov:8000/{r1,configuration} && cd ..
+#   stage: program
+#   dependencies:
+#     - oscope_top_bmb7
+#   script:
+#     - export PYTHONPATH=$PYTHONPATH:../../../build-tools/:../../../dsp && python3 prc.py -a 192.168.1.121 -r -b ../bmb7_cu/oscope_top.bit

BerkeleyLab_Bedrock/.gitlab/ci/other_hdl.gitlab-ci.yml

@@ -0,0 +1,35 @@
+# grab-bag of other Verilog/HDL simulation tests
+
+cordic_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd cordic && make clean
+  stage: test
+  script:
+    - make all
+
+freq_demo:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C homeless/freq_demo
+    - make -C homeless all checks
+
+peripheral_test:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C peripheral_drivers
+    - make -C peripheral_drivers/idelay_scanner
+    - make -C peripheral_drivers/ds1822
+    - make -C peripheral_drivers/i2cbridge
+
+xilinx_test:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: test
+  script:
+    - make -C fpga_family/xilinx

BerkeleyLab_Bedrock/.gitlab/ci/serial_io.gitlab-ci.yml

@@ -0,0 +1,8 @@
+serial_io_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd serial_io
+  stage: test
+  script:
+    - make && make checks && cd chitchat && make && make checks && cd - && cd EVG_EVR && make

BerkeleyLab_Bedrock/.gitlab/ci/soc.gitlab-ci.yml

@@ -0,0 +1,57 @@
+soc_picorv32_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd soc/picorv32/test
+  stage: test
+  script:
+    - make
+
+# soc_picorv32_unisims_test:
+#   before_script:
+#     - cd soc/picorv32/test/zest
+#   stage: test
+#   script:
+#     - XILINX_VIVADO=/non-free/Xilinx/Vivado/2019.1 PATH=$XILINX_VIVADO/bin:$PATH make
+
+soc_picorv32_kc705:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd soc/picorv32/project/kc705/synth
+  script:
+      # Run kc705 with older version of Vivado that has suport to non-webpack FPGAs
+    - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE XILINX_VIVADO=/non-free/Xilinx/Vivado/2018.3 PATH=$XILINX_VIVADO/bin:$PATH make system_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - soc/picorv32/project/kc705/synth/system_top.bit
+
+soc_picorv32_cmod_a7:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: synthesis
+  before_script:
+    - cd soc/picorv32/project/cmod_a7/synth
+  script:
+    - PATH=$XILINX_VIVADO/bin:$PATH make system_top.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    paths:
+      - soc/picorv32/project/cmod_a7/synth/system_top.bit
+
+soc_picorv32_cmod_a7_run:
+  extends: .build-matrix
+  image: $IMAGE
+  stage: program
+  dependencies:
+    - soc_picorv32_cmod_a7
+  before_script:
+    - cd soc/picorv32/project/cmod_a7
+  script:
+    - xc3sprog -c jtaghs1_fast -s 210328A6DA47 synth/system_top.bit && python3 hw_test.py 210328A6DA47
+  environment: hw_cmod_a7
+  resource_group: hw_cmod_a7

BerkeleyLab_Bedrock/.gitlab/ci/swap_gitid.gitlab-ci.yml

@@ -0,0 +1,8 @@
+swap_gitid_test:
+  extends: .build-matrix
+  image: $IMAGE
+  before_script:
+    - cd build-tools/vivado_tcl
+  stage: test
+  script:
+    - tclsh test_swap_gitid.tcl

BerkeleyLab_Bedrock/CONTRIBUTING.md

@@ -0,0 +1,251 @@
+# Contributing Guidelines
+
+Entails contribution guidelines to all projects in the group hdl-libraries.
+We are actively looking for meaningful contributions to our codebase. A
+meaningful contribution can entail anything from:
+
+1. A typo
+2. A readability enhancement
+3. A code or Makefile simplification
+4. A bug report
+5. A test
+6. A new source file that you deem fits into this codebase and
+preferably a test that goes with it!
+7. Support for a new board or a chip on the existing projects
+8. A new project
+9. A new way to build code within the code base
+10. New synthesis or simulation framework
+
+## TL;DR
+
+### Adding a small feature?
+
+1. Create a branch, and write code following guidelines here
+2. Add tests
+3. Add them to CI, and ensure they are passing with all the other tests you may have inadvertently broken
+4. Make a pull request and have somebody else other than you merge it into master
+5. Feel free to request for help during any stage
+
+### Adding a large feature?
+
+1. Start an issue or a wiki link with a detailed feature description/request
+2. Obtain general consensus or feedback
+3. Create a branch, and start a Merge/Pull Request at an early stage, in order to get early feedback from community
+4. Add tests
+5. Add them to CI, and ensure they are passing with all the other tests you may have inadvertently broken
+6. Add documentation
+7. Feel free to request for help during any stage
+
+## Code of Conduct
+
+Behavior in this community is always expected to be professional, courteous, and constructive.
+Berkeley Lab in particular mandates support of
+[Inclusion, Diversity, Equity, and Accountability](https://diversity.lbl.gov/).
+Please make all contributors feel welcome, assume good intent, and be considerate of others.
+On-line, that often means re-reading your messages carefully before pressing "send."
+
+Our team supports the principles and goals expressed in/by the
+[Contributor Covenant](https://www.contributor-covenant.org/).
+As employees of the University of California, where this project is
+part of our workplace environment, it is not obvious that we have
+the right to unilaterally choose, impose, or enforce such a covenant.
+
+## Contents of a repository
+
+A source repository should be primarily reserved for source code.
+"The source code for a work means the preferred form of the work for
+making modifications to it."
+
+Occasionally binary files will creep in, for example visual images
+for documentation purposes.  Each such file demands some note as to
+how it was generated.
+
+All checked-in files should be permissively licensed, consistent with
+the [LICENSE.md](LICENSE.md) file.
+
+Sometimes files are needed that can be legally downloaded from the public Internet,
+but we either don't have permission to redistribute them, or we have other reasons to
+not want them checked into this repository (all GPL code falls in this category,
+due to guidance from University of California lawyers).  It's OK to script the
+download of these files; please include a check that the result has the expected
+[SHA256](https://en.wikipedia.org/wiki/SHA-2). Do NOT redistribute or embed
+any files within Bedrock unless they have a suitably permissive license.
+Any download steps should be visibly documented, and users are encouraged to take that step
+once per repository checkout. An example (not currently in use -- that's another story) is found in
+[riscv_prep.sh](build-tools/riscv_prep.sh), which downloads source files needed to build
+a riscv toolchain (binutils, gcc, newlib), and is used in building our CI Docker image.
+
+Please do NOT check-in machine generated code. If unavoidable, document it explicitly,
+and give instructions for how to reproduce.
+
+Understanding that the choice of a programming language depends on the task at hand:
+Currently, synthesizable code is written in Verilog, machine-generated Verilog
+typically comes from Python, test benches that are too complex for Verilog resort to Python,
+and network runtime support is in Python, C, or C++.
+
+Standard implementations and standard libraries are preferred for obvious reasons.
+
+Automatic generation of documentation is a topic of current discussion. Suggestions welcome!
+
+
+## Makefiles
+
+We have an [explanation](build-tools/makefile.md) about how
+our existing Makefiles are put together.
+
+
+## Reproducible builds
+
+All constructed files (sometimes called artifacts) should be reproducible.
+See [reproducible-builds.org](https://reproducible-builds.org).  This includes pretty much any machine-generated file.
+
+Purposefully embedded "built-on" date stamps are deprecated; use
+a git commit ID (or similar) instead.
+
+PDF and object files often take extra effort to make reproducible.
+
+FPGA bitfiles are not typically shown to be reproducible, but Xilinx
+[acknowledges](https://adaptivesupport.amd.com/s/article/61599?language=en_US) that is a
+reasonable goal (they call it "repeatable").
+Our toolchain has demonstrated this working in at least couple of cases.
+
+## Readability
+
+Readability is a key goal for shared software. Lowering the barrier of entry for
+a newcomer enables the codebase to flourish. This can be easily achieved by adhering
+to commonly accepted best practices. Although, it may be impractical to adhere to
+every single best practice: reading guidelines, reviewing each others code, and
+having healthy discussions can tremendously improve the standard of software.
+
+We're not the first group to deal with this topic. The following are
+useful resources:
+
+1. [Linux kernel coding style guide](https://www.kernel.org/doc/html/v4.10/process/coding-style.html) many of the concepts it discusses have general applicability.
+2. [Google python guide](https://google.github.io/styleguide/pyguide.html) and [PEP8](https://www.python.org/dev/peps/pep-0008/)
+3. [GNU Coding Standards: Makefile Conventions](https://www.gnu.org/prep/standards/html_node/Makefile-Conventions.html)
+
+Please spell-check your code, comments, and documentation.
+
+### A few rules of thumb
+
+#### Naming
+(This includes traditional function and variable names in compiled languages
+like C, as wall as the various user-created names in Python, and wires,
+regs, and module names in Verilog)
+
+In most use cases and languages, please avoid CamelCase. You can resort to
+snake_case instead to enhance readability of long names.
+
+See Linux coding style "4) Naming".  Pay attention to the namespace.
+Use names that are easy to read and type, and that are not too hard to
+grep for.
+
+If you can reuse an existing name, for instance in Verilog using
+the same name for a reg and the port name of a module that receives
+that value, please do so.  Creating new and slightly different names
+for the same thing is a wasteful cognitive load.
+
+#### Whitespace
+
+Readability is the goal, and specialized techniques to gain readability
+(like vertical alignment of parallel semantics) is allowed and even encouraged.
+
+Trailing whitespace is pure useless entropy.
+
+Unix-style line breaks, ASCII 0x0a.
+
+No other control characters besides 0x0a (LF) and 0x09 (HT) in text/source files.
+
+See comments above concerning binary files.
+
+Tabs should not be used in any place other than the beginning of a line; doing so
+invites "tab damage".  OTOH, using tabs consistently at the beginning of lines
+to represent logical indentation level has advantages; people's setting of tab
+width can systematically and locally adjust the visual indentation level. Just
+like Wikipedia's English vs. American spelling policy, don't gratuitously
+change the tab vs. spaces convention of a file.  See also
+[Silicon Valley - S03E06 - Tabs versus Spaces](https://www.youtube.com/watch?v=cowtgmZuai0) (2:01).
+
+Special case for python files:
+  No tabs, per [PEP8](https://www.python.org/dev/peps/pep-0008/)
+
+Special case for Makefiles:
+  Semantic tabs
+
+Special case for Xcircuit PostScript files:
+  See [hack_xcirc](build-tools/hack_xcirc); consider creating and submitting a patch to
+avoid this in the distant future.
+
+### Verilog
+
+#### Of syntax
+Verilog files should always start with a human-readable description of
+its function.  Adding a template giving name, version, and author is
+discouraged; that's what we have version control for.
+
+Use ANSI-C style port naming, as introduced in Verilog-2001.
+Suggest a high proportion of comments connected with the port definitions.
+
+Pay extra attention to module names, that are global in Verilog,
+see "Universal considerations for names" above.
+
+Pay extra attention to "8) Commenting" in Linux kernel style guide.
+
+Verilog include files should use ".vh" as the name suffix.
+
+Suggest, but do not mandate, tabs for logical indentation level, see above.
+
+Verilog modules tend to be longer on average than C functions.  This is partially
+an unfortunate consequence of the limitations of Verilog and the overhead involved
+in constructing a new layer/module.  That is no excuse for pathologically long
+and complicated modules, that egregiously violate Linux style guide section
+"6) Functions".  Please find ways to break up and/or autogenerate those modules.
+
+#### Of semantics
+
+Most of our effort should be focused on portable synthesizable Verilog modules
+and their testing.  FPGA-specific instantiations (e.g., clock management and
+MGTs) should be separated from our functional code.  Too-tight a connection
+between them gets in the way of testing, since the Xilinx-supplied models are
+non-redistributable and sometimes encrypted.
+
+Portable synthesizable code should be written in a way that makes the hardware
+representation clear to both humans and the synthesizer.  All logic, flip-flops,
+multipliers, and RAM should be inferred.
+
+Most of our code is intended to run at relatively high clock rates.  Even
+modules that don't actually need high throughput are often put in a clock
+domain shared with high-throughput logic.  This consideration necessitates
+strongly pipelined logic.
+
+### Coding and style guidelines
+
+In addition to the general recommendations above, we strive for a uniform
+Verilog coding style that emphasizes readability, reduces systematic errors and promotes
+code re-use. The [RTL Guidelines](guidelines/rtl_guidelines.md) document, which is itself
+open to improvements and suggestions, attempts to formalize this process in the
+form of coding and style guidelines that apply to some of the most common facets of RTL coding.
+
+### Python
+
+We want all python files compatible with python2 and python3.
+Some legacy code can be tolerated as python2 only.
+Some new code can be tolerated as python3 only.
+
+A quick book for understanding patterns and Python in general: https://effectivepython.com/
+
+## Testing
+
+Ideally all code will be paired with a regression test that fully exercises
+its functionality, maybe even cross-checked with a code coverage tool.
+The more complex the function, the more important are such tests.
+
+In general, file foo.v should define module foo, and have an associated
+testbench in file foo_tb.v (which defines module foo_tb).  There will be
+exceptions to this rule.  It's OK for other modules to be defined in
+file foo.v, if they will never be instantiated by by any other code.
+If possible, the testbench will give foo a thorough exercise, and print
+PASS only if everything checks out.  More complex tests may involve
+helper code in e.g., python, that will determine if the module is performing
+as expected.  In all cases, the regression tests will be automated by
+a Makefile rule called foo_check.

BerkeleyLab_Bedrock/LICENSE.md

@@ -0,0 +1,21 @@
+## Copyright Notice and License Agreement
+
+"Bedrock v1.0" Copyright (c) 2019, The Regents of the University of California, through Lawrence Berkeley National Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy).  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+(1) Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+(2) Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+(3) Neither the name of the University of California, Lawrence Berkeley National Laboratory, U.S. Dept. of Energy, nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+You are under no obligation whatsoever to provide any bug fixes, patches, or upgrades to the features, functionality or performance of the source code ("Enhancements") to anyone; however, if you choose to make your Enhancements available either publicly, or directly to Lawrence Berkeley National Laboratory, without imposing a separate written license agreement for such Enhancements, then you hereby grant the following license: a non-exclusive, royalty-free perpetual license to install, use, modify, prepare derivative works, incorporate into other computer software, distribute, and sublicense such enhancements or derivative works thereof, in binary and source code form.
+
+NOTICE.  This Software was developed under funding from the U.S. Department of Energy and the U.S. Government consequently retains certain rights. As such, the U.S. Government has been granted for itself and others acting on its behalf a paid-up, non-exclusive, irrevocable, worldwide license in the Software to reproduce, distribute copies to the public, prepare derivative works, and perform publicly and display publicly, and to permit others to do so.
+
+If you have questions about your rights to use or distribute this software, please contact Berkeley Lab's Intellectual Property Office at: IPO@lbl.gov.
+
+************************************************************************************

BerkeleyLab_Bedrock/README.md

@@ -0,0 +1,107 @@
+Overview
+========
+
+Bedrock generated documentation: https://berkeleylab.github.io/Bedrock/
+
+[Bedrock](https://gitlab.lbl.gov/hdl-libraries/bedrock) is largely an accumulation
+of Verilog codebase written over the past several years at LBNL. It contains
+platform-independent Verilog, and whatever it takes to get it onto FPGA platforms like Xilinx etc.
+
+It is currently a conglomerate of code broken into the following subdirectories:
+
+* [dsp](dsp): Various Digital Signal Processing algorithms
+implemented in platform-independent (portable) Verilog, and their test benches;
+modules include DDS, Down-conversion, Up-conversion, CIC Filters,
+Low-Pass filters, High-Pass filters, Mixers
+* [cordic](cordic): A self contained Verilog implementation of a
+[CORDIC](https://en.wikipedia.org/wiki/CORDIC);
+includes several operating modes that can be selected at build-time or run-time
+* rtsim: Real-Time simulation of various components of an RF system like a
+resonant cavity, its Electrical and Mechanical modes, ADCs, Cables, Piezos etc.
+* cmoc: Verilog implementation of an RF controller, that connects to either a
+real world ADCs or simulated components within rtsim
+* [badger](badger): A real-time Ethernet/IP/UDP packet responder core in fabric
+* fpga_family: Several FPGA specific constraint files and hooks for vendor-specific features
+* [localbus](localbus): Documentation and features related to the on-chip localbus that is widely used within bedrock
+* board_support: Several board specific pin mapping related files
+* projects: Instantiated projects that build and synthesize bit files that go on
+FPGAs sitting on various boards that talk various platforms
+
+
+A few comments regarding the codebase
+
+1. All software is set up to easily run on *nix systems.
+2. Currently everything is [built using GNU Make](build-tools/makefile.md).
+We are on an active lookout for other methods, if they're actually better for us.
+3. iverilog is used for simulation. We are slowly starting to use [Verilator](https://www.veripool.org/verilator/) as well
+(see badger)
+4. Xilinx tools are used for synthesis, and starting to support [YoSys](https://yosyshq.net/yosys/) (again see badger)
+5. This repository is connected to Gitlab CI. All simulation based tests run
+automatically upon every commit on the continuous integration server. This helps
+us move faster (without breaking things).  A helpful subset of those tests
+can be run locally on your workstation via [selftest.sh](selftest.sh).
+
+
+Graphical x Batch mode
+======================
+
+Bedrock is structured in such a way to make use of traditional *nix
+tools, such as `make` and `grep`, shell and python scripts from the
+command-line. This makes it easy to automate the build process, customize
+steps, and gives flexibility to add hooks for generating code, stubs,
+definitions and much more.
+
+However, there are valid cases for using a graphical, interactive
+interface such as: analyzing elaborated, synthesized or implemented
+design schematic; adding/removing placement constraints;
+customizing a block design; customizing an IP core from a vendor.
+
+Bedrock keeps all the vendor-specific generated files in a _<VENDOR_NAME>
+directory in the synthesis directory. So, for instance, when synthesizing
+a design for `Xilinx`, Bedrock scripts will create a directory called
+`_xilinx` with the unmodified vendor files within.
+
+In this way, after the vendor project file is created (see the
+[build-tools discussion](build-tools/makefile.md) for details),
+one can simply invoke the vendor tool manually with the project
+file name as the argument.
+
+For instance, if using Vivado, one can use the following command
+to open a project in Graphical mode:
+
+```bash
+vivado <PROJECT_DIRECTORY>/_xilinx/<TOP_LEVEL_DESIGN_NAME>/<TOP_LEVEL_DESIGN_NAME>.xpr
+```
+
+in which `<PROJECT_DIRECTORY>` is the directory in which you invoked
+`make` and `<TOP_LEVEL_DESIGN_NAME>` is the bitstream name without the
+`.bit` extension.
+
+Dependencies
+============
+
+Required:
+
+*  GNU Make
+*  iverilog
+*  Python
+
+Recommended:
+
+*  GTKWave
+*  Xilinx Vivado
+*  Verilator
+*  YoSys
+
+Full list: see [dependencies.txt](dependencies.txt) and [Dockerfile](Dockerfile.bedrock_testing_base_trixie).
+
+On contributing
+===============
+See our first take [here](CONTRIBUTING.md)
+
+************************************************************************************
+
+
+### Copyright Notice and License Agreement
+
+See [LICENSE](LICENSE.md).

BerkeleyLab_Bedrock/badger/README.md

@@ -0,0 +1,179 @@
+# Packet Badger
+
+## Introduction
+
+Packet Badger is a digital logic design, implemented on an FPGA, that
+digs through Ethernet packets to construct a response.  Its intended
+application is to let workstations and servers communicate with FPGA-based
+instruments over UDP.  On its own, it provides ARP, ICMP echo, and UDP echo
+services.  It has a (documented and tested) interface to add additional
+UDP services that provide the application-useful data flow.
+
+Packet Badger attaches to Ethernet using the GMII standard.  Adapter layers
+inside the FPGA can let it connect to GMII, RGMII, SGMII, or MGT PHY hardware.
+Mechanisms are provided to attach a software-based simulation of Packet Badger
+to the computer's TUN/TAP subsystem (requires root access for setup),
+or single clients to a UDP socket, permitting development of client software
+and HDL without depending on the target hardware.
+
+Packet Badger is written in portable, synthesizable Verilog.  When targeting
+Xilinx 7-series chips, it occupies about 1000 LUTs and 1 RAMB18.
+
+Packet Badger is designed to only respond promptly to packets, never initiate
+traffic.  It is tuned for plug-in modules (one per UDP service port) that can
+respond in a fixed number (parameterized) of clock cycles latency.  Examples
+are given for such modules that:
+
+* Gateway to an on-chip local bus (protocol [documentation](mem_gate.md))
+* Give read/write access to an SPI Flash memory
+
+Unlike logic designs that use a soft core to implement Ethernet/IP protocols,
+it is capable of full-rate gigabit-per-second data transfer, and has a
+relatively small footprint in the FPGA fabric and memory.
+
+This design roughly parallels an earlier LBNL Ethernet fabric design
+(PSPEPS), but with architectural bugs fixed.  If the Ethernet physical
+link stays up, it will never drop a packet.
+
+The architecture permits adding a MAC for a soft-core CPU, that could be
+useful for low-bandwidth setup functions like DHCP or SCPI.  An initial
+implementation is included.
+
+The author asserts that its architecture will permit addition of strong
+authentication to each packet, without adding (much) overhead in latency,
+throughput, or hardware resources.  Efforts to demonstrate that are still
+in a prototyping stage, and are not included here.
+
+Only synthesizable code, programs (and their data) to generate synthesizable
+code, and documentation are here in the base directory.  Files that implement
+the extensive self-test capability, including test builds for hardware, are
+squirreled away in the tests/ directory.  Projects that instantiate this
+code are expected to accomplish the build step by including rules.mk.
+
+## Block Diagram
+
+![block diagram](doc/rtefi.svg)
+
+## Self-tests
+
+An extensive set of self-tests and demonstrations are programmed up in
+the tests subdirectory.  These range from simple exercises for the
+input packet scanner to running a TFTP server that uses the MAC feature.
+Some of these tests attach the simulated logic to the host network.
+
+The self-tests are run as part of a Continuous Integration (CI) process.
+You can also run them on your workstation with a simple "cd tests; make".
+
+## Functionality
+
+Input packets are checked according to the following.
+Failures are not reported, just dropped.
+
+All packets:
+
+* Source MAC is unicast, not multicast
+* CRC32 OK
+* Total GMII frame length (including Ethernet header and CRC32) <= 1536
+* Minimum frame length _not_ checked
+
+ARP request:
+
+* EtherType 0x0806
+* Hardware address space 1 (Ethernet)
+* Protocol address space 0x0800 (Ethernet/IP)
+* 6-byte hardware addresses, 4-byte protocol addresses
+* Opcode 1 (request)
+* _No_ checks on embedded source IP or MAC
+* Dest IP matches our configuration
+* _No_ checks on embedded dest MAC
+* _No_ checks on Ethernet header dest MAC (normally broadcast)
+
+IP:
+
+* Dest MAC matches our configuration
+* EtherType 0x0800
+* IPv4
+* No options
+* IP total length fits within its GMII frame
+* No fragmentation
+* Non-zero TTL
+* IP header checksum OK
+* _No_ checks on source IP address
+* Dest IP matches our configuration
+
+ICMP echo request (depends on IP):
+
+* IP Protocol 1
+* ICMP type 8, code 0
+* ICMP checksum OK
+
+UDP (depends on IP):
+
+* IP Protocol 17
+* Source port >= 1024
+* Dest port matches one of the clients (but not zero)
+* Length fits within IP packet
+* UDP checksum _not_ checked
+
+If a reply is sent, it _always_ has its destination MAC transcribed
+from the requesting packet's source MAC.  Likewise, the destination IP
+is transcribed from the source IP (although this means different things
+for ARP and IP), and the UDP destination port is transcribed from the
+source port.
+
+Up to eight on-chip plug-in clients (UDP ports) are currently supported,
+and their default ports are numbered sequentially starting at 801.
+This can be overridden at build time with Verilog parameters, or
+at run time with a local configuration bus.
+
+It is strongly recommended that UDP destination port numbers get configured
+to be < 1024, to resist UDP loops.  Somehow this well-known (CA-1996-01:
+UDP Port Denial-of-Service Attack) possibility was rediscovered
+in 2024, and assigned CVE-2024-2169: Loop DoS.  Separating "services"
+(ports < 1024) from "clients" (ports > 1023) is Preventive measure 2
+listed in the Loop DoS advisory.
+
+## Example "live" test run
+
+Demonstrating both Packet Badger functionality, and the test framework's
+ability to attach the simulation to the host's Ethernet subsystem.
+
+Your development machine needs to provide a traditional unix-y environment,
+e.g., make, cc, python, awk, cmp.  Also some version of [Icarus Verilog](https://steveicarus.github.io/iverilog/); see [status.md](status.md) for more details.
+
+In one shell session (Linux terminal), try:
+
+    cd tests
+    sudo tunctl -u $USER && sudo ifconfig tap0 192.168.7.1 up
+    make tap_start
+
+In another terminal, try the following to pull contents from `fake_config_romx.v`
+through `mem_gateway.v` at IP address `192.168.7.4`, localbus UDP port 803:
+
+    printf "sillyoneT\x1\x0\x0yyyyT\x1\x0\x1yyyyT\x1\x0\x2yyyyT\x1\x0\x3yyyy" | nc -q 1 -u 192.168.7.4 803 | hexdump -v -e '8/1 "%2.2x " "  "' -e '8/1 "%_p" "\n"'
+
+Expected result:
+
+    73 69 6c 6c 79 6f 6e 65  sillyone
+    54 01 00 00 00 00 80 0a  T.......
+    54 01 00 01 00 00 73 34  T.....s4
+    54 01 00 02 00 00 b9 48  T......H
+    54 01 00 03 00 00 d2 76  T......v
+
+You can now interrupt (control-C) the simulation.  That process should
+have left behind a rtefi_pipe.vcd file that can be viewed with gtkwave;
+a pre-configured gtkwave pane can be brought up with "make rtefi_pipe_view".
+
+## Attachment of clients:
+![client interface timing diagram](doc/clients.svg)
+
+Each client handles one UDP port.
+Up to eight clients can be attached to a Packet Badger instance.
+
+## Other documentation
+
+* Design notes: [rtefi_notes.txt](rtefi_notes.txt)
+* Memory addressing figure: [memory access diagram](doc/memory.svg)
+* Data path in construct.v: [data path diagram](doc/tx_path.svg)
+* SPI Boot Flash programming support: [flash.md](flash.md)
+* Status: [status.md](status.md)

BerkeleyLab_Bedrock/badger/base_rx_mac.v

@@ -0,0 +1,46 @@
+// Baseline/provisional/experimental Rx MAC,
+// ties to functionality in pbuf_writer.v
+//
+// 11-bit host_raddr for dpram addressing.
+// Packet memory appears to host as 16 bits wide,
+// so 4 kBytes overall.
+module base_rx_mac (
+	// Host side of Rx MAC memory
+	input host_clk,
+	input [10:0] host_raddr,
+	output reg [15:0] host_rdata,
+	// port to Rx MAC memory
+	input rx_clk,
+	input [7:0] rx_mac_d,
+	input [11:0] rx_mac_a,
+	input rx_mac_wen,
+	// port to Rx MAC packet selector
+	output rx_mac_accept,
+	input [7:0] rx_mac_status_d,
+	input rx_mac_status_s
+);
+initial host_rdata=0;
+
+// Dual-port RAM
+localparam aw=11;
+reg [7:0] pack_mem_l[0:(1<<aw)-1];
+reg [7:0] pack_mem_h[0:(1<<aw)-1];
+// Write from Ethernet, 8-bit port and therefore aw+1 address bits coming in
+wire a_lsb = rx_mac_a[0];
+wire [aw-1:0] a_msb = rx_mac_a[aw:1];
+always @(posedge rx_clk) if (rx_mac_wen) begin
+	if (a_lsb) pack_mem_l[a_msb] <= rx_mac_d;
+	else       pack_mem_h[a_msb] <= rx_mac_d;
+end
+// Read from host
+wire [aw-1:0] raddr = host_raddr;
+always @(posedge host_clk) host_rdata <= {pack_mem_h[raddr], pack_mem_l[raddr]};
+
+// Accept valid IP packets addressed to us, that won't be handled by fabric.
+// See comments regarding status_vec in scanner.v.
+reg rx_mac_accept_r=0;
+always @(posedge rx_clk) if (rx_mac_status_s)
+	rx_mac_accept_r <= rx_mac_status_d[4:0] == 5'b11100;
+assign rx_mac_accept = rx_mac_accept_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/collect_clients.py

@@ -0,0 +1,112 @@
+# Parses one Verilog file per client, and creates rtefi_preblob.vh
+# that will define the instantiation and I/O port routing of the final
+# rtefi_blob.v.
+#
+# The fundamental bug with this program is that it's
+# based on text patterns, not semantics.
+# At least it doesn't use magic comments!
+from sys import argv
+import re
+xlist = []
+params = []
+
+
+def handle_port(plist, x2list, ptype, name, ix):
+    special_list = {'clk': 1, 'len_c': 1, 'idata': 1,
+                    'raw_l': 1, 'raw_s': 1, 'odata': 1}
+    ename = name
+    if name not in special_list:
+        ename = "p%d_%s" % (ix, name)
+        # print("adding to x2list: %s, %s" % (ptype, ename))
+        x2list += [(ptype, ename)]
+    if name == "raw_l" or name == "raw_s":
+        ename = "%s[%d]" % (name, ix-1)
+    if name == "odata":
+        ename = "%s_p%d" % (name, ix)
+    plist += [".%s(%s)" % (name, ename)]
+
+
+def map_params(ix, spec, params):
+    # print("// map_params(%d, %s ..)" % (ix, spec))
+    prefix = "p%d_" % ix
+
+    # Define a function to be used as repl argument to re.sub()
+    # Ideally we'd not try to process the leading input / output string
+    def param_replace(matchobj):
+        m = matchobj.group(0)
+        # print(m)
+        return prefix+m if m in params else m
+    ss = re.sub(r'([a-zA-Z]\w*)', param_replace, spec)
+    # print("// After: %s" % ss)
+    return ss
+
+
+# regexps for I/O ports, with and without a specified width
+# It would be cool if we could also propagate comments
+# associated with ports and parameters.
+PORT_N = r'^\s*,?(input|output|inout)\s+(signed)?\s*(\[[^]]+\])\s*(\w+)'
+PORT_0 = r'^\s*,?(input|output|inout)\s+(signed)?\s*(\w+)'
+PARAM = r'^\s*,?parameter\s+(\w+)\s*=\s*(\d+)'
+
+
+def file_grab(fname, ix):
+    plist = []
+    x2list = []
+    global xlist
+    global params
+    param_map = []
+    param_set = [".n_lat(n_lat)"]
+    with open(fname, 'r') as f:
+        for li in f.read().split('\n'):
+            if li == "":
+                continue
+            # print(l)
+            m = re.search(PORT_N, li)
+            if m:
+                ll = [m.group(jx) for jx in [1, 2, 3]]
+                p = " ".join([x if x is not None else "" for x in ll])
+                handle_port(plist, x2list, p, m.group(4), ix)
+            m = re.search(PORT_0, li)
+            if m:
+                ll = [m.group(jx) for jx in [1, 2]]
+                p = " ".join([x if x is not None else "" for x in ll])
+                handle_port(plist, x2list, p, m.group(3), ix)
+            m = re.search(PARAM, li)
+            if m and m.group(1) != "n_lat":
+                pn = m.group(1)
+                pv = m.group(2)
+                params += ["\tparameter p%d_%s = %s," % (ix, pn, pv)]
+                param_set += [".%s(p%d_%s)" % (pn, ix, pn)]
+                param_map += [pn]
+        for p_spec, p_name in x2list:
+            p_spec2 = map_params(ix, p_spec, param_map)
+            xlist += ['\t%s %s,' % (p_spec2, p_name)]
+        # Generate the module name from the file name;
+        # directories and .v suffixes aren't kept.
+        # print("// Finalizing %s" % fname)
+        # print(plist)
+        mod_name = fname.split('/')[-1]
+        mod_name = mod_name.split('.')[0]
+        param_sets = ", ".join(param_set)
+        ss = "%s #(%s) p%d_client(" % (mod_name, param_sets, ix)
+        ss += ", ".join(plist)
+        ss += ");"
+        return ss
+
+
+ss = []
+n_used = len(argv)-1
+print("// This Verilog include file was machine-generated by {}".format(__file__))
+for ix, fname in enumerate(argv[1:]):
+    print("// %d %s" % (ix+1, fname))
+    ss += [file_grab(fname, ix+1)]
+print("// filling in unused UDP ports starting at %d" % (n_used+1))
+for ix in range(n_used+1, 8):
+    ss += ["assign odata_p%d = 8'h%2x;" % (ix, 48+ix)]
+
+print("`define BLOB_INSTANCES \\")
+print("\\\n".join(ss))
+print("`define BLOB_PORTS \\")
+print("\\\n".join(xlist))
+print("`define BLOB_PARAMS \\")
+print("\\\n".join(params))

BerkeleyLab_Bedrock/badger/construct.v

@@ -0,0 +1,204 @@
+// Output packet construction
+
+// Handles Ethernet, ARP, and IP layers, ready to hand over
+// to the application-layer UDP content handling.
+// The core of the data path is documented in doc/tx_path.eps,
+// with the table generated by tx_gen.py based on
+// tx_*_table.csv.
+
+// Synthesized on its own, without the associated packet memory
+// or MAC/IP config memory, it takes up about 74 LUTs.
+
+module construct #(
+	parameter paw=11,  // packet address width, 11 IRL, maybe less for simulations
+	parameter p_offset = 480  // Keep an eye on this.
+	// Has to be at least 6 for usual fp_offset of 0, but also
+	// add -min(fp_offset)+guard.  The guard needs to include
+	// allowance Rx/Tx frequency offset.
+	// At the other end, p_offset + max(fp_offset) < (2048-MTU-guard)
+) (
+	input clk,  // timespec 6.8 ns
+	input [paw-1:0] gray_state,
+	// port to MAC/IP config, single-cycle latency
+	output [3:0] ip_a,
+	input [7:0] ip_d,
+	// Read port of 1 MTU DPRAM, again single-cycle latency
+	output [paw-1:0] addr,
+	input [8:0] pbuf_out,
+	// Debugging hook
+	output badge_stb,
+	output [7:0] badge_data,
+	output xdomain_fault,
+	output xcheck_fault,
+	// Output to xformer
+	output [5:0] pc,
+	output [1:0] category,
+	output [2:0] udp_sel,
+	output [7:0] eth_data_out,
+	output eth_strobe_long,  // includes GMII preamble and CRC32
+	output eth_strobe_short  // doesn't
+);
+
+// Capture state across clock domains, then convert back to binary
+wire [paw-1:0] gray_l;
+// Better to pull this first step up to rtefi_center?
+reg_tech_cdc gcx[paw-1:0] (.C(clk), .I(gray_state), .O(gray_l));
+// verilator lint_save
+// verilator lint_off UNOPTFLAT
+wire [paw-1:0] new_state = gray_l ^ {1'b0, new_state[paw-1:1]};
+// verilator lint_restore
+reg [paw-1:0] state=0;
+always @(posedge clk) state <= new_state;
+
+// Debugging hook
+reg [paw-1:0] old_state=0, state_diff=0;
+reg xdomain_fault_r=0;
+always @(posedge clk) begin
+	old_state <= state;
+	state_diff <= state - old_state;
+	// state_diff must be 0, 1, or 2 for things to work right
+	xdomain_fault_r <= |state_diff[paw-1:2] || &state_diff[1:0];
+end
+assign xdomain_fault = xdomain_fault_r;
+
+
+// Construct frame pointer that tracks the one in scanner.v
+wire packet_active;
+wire [paw-1:0] fp;
+`ifdef COMMON_CLOCKS
+assign fp = state + p_offset;
+`else
+// cope with max 100 ppm frequency offset between input and output.
+reg [paw-1:0] fp_r=0;
+assign fp = packet_active ? fp_r+1 : state+p_offset;
+always @(posedge clk) fp_r <= fp;
+// This will be really slow.  Have to pack an increment, mux, add,
+// and RAM access into a single cycle.
+`endif
+// XXX Deserves a consistency check to find out if fp drifts into
+// a danger zone relative to state.
+
+reg [5:0] pc_r=0;
+// SOF: Start Of Frame
+wire pre_sof = pbuf_out[8] & ~pbuf_out[7] && (pc_r==0);
+wire sof = pbuf_out[8] & pbuf_out[7] && (pc_r==0);  // hack to get around x's in fp_offset
+wire [7:0] pbuf_out8 = pbuf_out[7:0];
+wire signed [5:0] fp_offset, cf_offset;
+reg live=0;
+assign packet_active = pre_sof | sof | live;
+reg [10:0] pack_len_r=0;
+wire pc_not_saturated = |(~pc_r[5:4]);  // check if pc < 48
+wire [5:0] next_pc = sof ? 2 : live ? pc_r + pc_not_saturated : 0;
+
+// reference: status_vec = {port_p, pass_ip, pass_ethmac, crc_zero, category};
+reg [7:0] status_vec=0;
+assign category = status_vec[1:0];
+assign udp_sel = status_vec[7:5];
+reg p_strobe=0;  // Reading packet content (including checksum)
+reg o_strobe=0;  // ignores checksum
+reg sof_d=0;
+// Would it take fewer resources to replace sof_d with (live && pc_r == 2)?
+// Or to replace (live && pc_r==3) with sof_dd?  Need to measure to find out.
+// Could be worth breaking this up into 2 always blocks (badge and data)?
+// Not really, since they both have to touch the "live" register.
+always @(posedge clk) begin
+	pc_r <= next_pc;
+	sof_d <= sof;
+	if (sof) begin
+		live <= 1;
+		pack_len_r[6:0] <= pbuf_out8[6:0];
+	end
+	if (sof_d) pack_len_r[10:7] <= pbuf_out8[3:0];
+	if (live && pc_r==3) status_vec <= pbuf_out8;
+	// pc_r == 5 the badge has been read!
+	if (live && pc_r==5 && category!=0) begin o_strobe <= 1; p_strobe <= 1; end
+	if (live && pc_r==5 && category==0) begin live <= 0; pack_len_r <= 0; end
+	if (p_strobe) pack_len_r <= pack_len_r-1;
+	if (pack_len_r==5) o_strobe <= 0;
+	if (pack_len_r==1) begin p_strobe <= 0; live <= 0; end
+end
+
+// Debug
+reg [2:0] sof_chain=0;
+always @(posedge clk) sof_chain <= {sof_chain[1:0], sof};
+assign badge_stb = sof | (|sof_chain);
+assign badge_data = pbuf_out8;
+
+// Look up instruction and start using it
+wire [1:0] out, chk_in;
+wire [7:0] template;
+construct_tx_table prog(.a({category, pc_r}),
+	.v({out, fp_offset, cf_offset, chk_in, template}));
+assign addr = fp + {{5{fp_offset[5]}}, fp_offset};
+assign ip_a = pc_r + cf_offset;
+
+// Align cycles with the one-cycle delay going through RAM
+// (a bit wasteful, could mess with table generation instead?)
+// Pipelining not shown in doc/tx_path.eps
+reg [7:0] template_d=0;
+reg [1:0] out_d=0, chk_in_d=0;
+always @(posedge clk) begin
+	template_d <= template;
+	out_d <= out;
+	chk_in_d <= chk_in;
+end
+
+// Multiplexers, need to stay consistent with tx_gen.py
+reg [7:0] d_chk=0;
+always @(posedge clk) case (chk_in_d)
+	2'b00: d_chk <= pbuf_out8;
+	2'b01: d_chk <= ip_d;
+	2'b10: d_chk <= template_d;
+	2'b11: d_chk <= 8'd0;
+endcase
+wire [7:0] ip_head_chksum_data;
+// IP header checksum calculation
+reg chksum_zero=0, chksum_gate=0;
+always @(posedge clk) begin
+	chksum_zero <= pc_r <= 3;
+	chksum_gate <= (chk_in_d != 2'b11) & ~chksum_zero;
+end
+ones_chksum ck(.clk(clk), .clear(chksum_zero), .gate(chksum_gate),
+	.din(d_chk), .sum(ip_head_chksum_data));
+
+reg [7:0] d_out_pre=0;
+always @(posedge clk) case (out_d)
+	2'b00: d_out_pre <= pbuf_out8;
+	2'b01: d_out_pre <= ip_d;
+	2'b10: d_out_pre <= template_d;
+	2'b11: d_out_pre <= 0;
+endcase
+// Last-minute insertion of IP header checksum result .. haha minute
+reg out_d_chk_sub=0;
+always @(posedge clk) out_d_chk_sub <= out_d == 2'b11;
+wire [7:0] d_out = out_d_chk_sub ? ip_head_chksum_data : d_out_pre;
+// This could create a critical speed path
+
+// Close out timing within this module
+reg [7:0] eth_data_out_r=0;   always @(posedge clk) eth_data_out_r <= d_out;
+reg eth_strobe_short_r=0;     always @(posedge clk) eth_strobe_short_r <= o_strobe;
+reg pack_len_nz=0;     always @(posedge clk) pack_len_nz <= pack_len_r != 0;
+reg [5:0] pc_d=0;      always @(posedge clk) pc_d <= pc_r;
+
+assign eth_data_out = eth_data_out_r;
+assign eth_strobe_short = eth_strobe_short_r;
+assign eth_strobe_long = pack_len_nz && pc_r > 3 && category != 0;
+assign pc = pc_d;
+
+// Debug only; will be dropped if you don't hook up the xcheck_fault port:
+// Cross-check the IP header checksum we just computed
+reg xcheck_zero=0, xcheck_gate=0, xcheck_ones_d=0;
+reg xcheck_capture=0, xcheck_fault_r=0;
+wire xcheck_ones;
+always @(posedge clk) begin
+	xcheck_zero <= pc_r <= 4;
+	xcheck_gate <= pc_r >= 20 && pc_r < 40;
+	xcheck_ones_d <= xcheck_ones;
+	xcheck_capture <= pc_r == 40;
+	xcheck_fault_r <= xcheck_capture & ~xcheck_ones & ~xcheck_ones_d;
+end
+ones_chksum xchk(.clk(clk), .clear(xcheck_zero), .gate(xcheck_gate),
+	.din(eth_data_out), .all_ones(xcheck_ones));
+assign xcheck_fault = xcheck_fault_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/crc8e_guts.v

@@ -0,0 +1,66 @@
+// Hacked to support Ethernet
+module crc8e_guts(
+	input clk,
+	input gate,
+	input first,  // set this during the first clock cycle of a new block of data
+	input [7:0] d_in,
+	output [7:0] d_out,
+	output zero
+);
+// https://en.wikipedia.org/wiki/Cyclic_redundancy_check
+parameter wid=32;
+parameter init=32'hffffffff;
+
+// Three names are magic to crc_guts.vh:
+//   D    data in
+//   O    old CRC value
+//   crc  new CRC value
+reg [wid-1:0] crc=0;
+wire [7:0] D = d_in;
+wire [wid-1:0] O = first ? init : crc;
+always @(posedge clk) if (gate) begin
+// Machine generated by ./crc_derive -lsb 32 0x4c11db7 8
+// D is the 8-bit input data (lsb-first)
+// crc and O are the new and old 32-bit CRC
+// Generating polynomial is 0x4c11db7 (normal form, leading 1 suppressed)
+// Reference: https://en.wikipedia.org/wiki/Cyclic_redundancy_check
+crc[0] <= D[7]^D[1]^O[24]^O[30];
+crc[1] <= D[7]^D[6]^D[1]^D[0]^O[24]^O[25]^O[30]^O[31];
+crc[2] <= D[7]^D[6]^D[5]^D[1]^D[0]^O[24]^O[25]^O[26]^O[30]^O[31];
+crc[3] <= D[6]^D[5]^D[4]^D[0]^O[25]^O[26]^O[27]^O[31];
+crc[4] <= D[7]^D[5]^D[4]^D[3]^D[1]^O[24]^O[26]^O[27]^O[28]^O[30];
+crc[5] <= D[7]^D[6]^D[4]^D[3]^D[2]^D[1]^D[0]^O[24]^O[25]^O[27]^O[28]^O[29]^O[30]^O[31];
+crc[6] <= D[6]^D[5]^D[3]^D[2]^D[1]^D[0]^O[25]^O[26]^O[28]^O[29]^O[30]^O[31];
+crc[7] <= D[7]^D[5]^D[4]^D[2]^D[0]^O[24]^O[26]^O[27]^O[29]^O[31];
+crc[8] <= D[7]^O[0]^D[6]^D[4]^D[3]^O[24]^O[25]^O[27]^O[28];
+crc[9] <= D[6]^O[1]^D[5]^D[3]^D[2]^O[25]^O[26]^O[28]^O[29];
+crc[10] <= D[7]^D[5]^O[2]^D[4]^D[2]^O[24]^O[26]^O[27]^O[29];
+crc[11] <= D[7]^D[6]^D[4]^O[3]^D[3]^O[24]^O[25]^O[27]^O[28];
+crc[12] <= D[7]^D[6]^D[5]^D[3]^O[4]^D[2]^D[1]^O[24]^O[25]^O[26]^O[28]^O[29]^O[30];
+crc[13] <= D[6]^D[5]^D[4]^D[2]^O[5]^D[1]^D[0]^O[25]^O[26]^O[27]^O[29]^O[30]^O[31];
+crc[14] <= D[5]^D[4]^D[3]^D[1]^O[6]^D[0]^O[26]^O[27]^O[28]^O[30]^O[31];
+crc[15] <= D[4]^D[3]^D[2]^D[0]^O[7]^O[27]^O[28]^O[29]^O[31];
+crc[16] <= D[7]^D[3]^D[2]^O[8]^O[24]^O[28]^O[29];
+crc[17] <= D[6]^D[2]^D[1]^O[9]^O[25]^O[29]^O[30];
+crc[18] <= D[5]^D[1]^D[0]^O[10]^O[26]^O[30]^O[31];
+crc[19] <= D[4]^D[0]^O[11]^O[27]^O[31];
+crc[20] <= D[3]^O[12]^O[28];
+crc[21] <= D[2]^O[13]^O[29];
+crc[22] <= D[7]^O[14]^O[24];
+crc[23] <= D[7]^D[6]^D[1]^O[15]^O[24]^O[25]^O[30];
+crc[24] <= D[6]^D[5]^D[0]^O[16]^O[25]^O[26]^O[31];
+crc[25] <= D[5]^D[4]^O[17]^O[26]^O[27];
+crc[26] <= D[7]^D[4]^D[3]^D[1]^O[18]^O[24]^O[27]^O[28]^O[30];
+crc[27] <= D[6]^D[3]^D[2]^D[0]^O[19]^O[25]^O[28]^O[29]^O[31];
+crc[28] <= D[5]^D[2]^D[1]^O[20]^O[26]^O[29]^O[30];
+crc[29] <= D[4]^D[1]^D[0]^O[21]^O[27]^O[30]^O[31];
+crc[30] <= D[3]^D[0]^O[22]^O[28]^O[31];
+crc[31] <= D[2]^O[23]^O[29];
+end
+wire [7:0] dr = ~crc[wid-1:wid-8]; // note polarity inversion
+assign d_out = {dr[0],dr[1],dr[2],dr[3],dr[4],dr[5],dr[6],dr[7]};
+// note bit order reversal
+
+// assign zero = ~(|crc);
+assign zero = crc==32'hc704dd7b;
+endmodule

BerkeleyLab_Bedrock/badger/doc/README.md

@@ -0,0 +1,29 @@
+# Figures
+
+This directory holds diagrams that document various aspects of Packet Badger.
+The Verilog source code refers to these as appropriate.
+Some of them are also used by the README.md in the root directory.
+
+All the .eps files here are created and editable by [xcircuit](http://opencircuitdesign.com/xcircuit/).
+Rules in the associated Makefile convert them to the web-compatible SVG format.
+
+### Block Diagram
+![block diagram](rtefi.svg)
+
+### Context at the system level
+![implementation stack block diagram](stack.svg)
+
+### Attachment of clients:
+![client interface timing diagram](clients.svg)
+
+### Memory gateway (localbus) timing:
+![mem_gateway timing](mem_gateway.svg)
+
+### Internal memory addressing:
+![memory access diagram](memory.svg)
+
+### Data path in construct.v:
+![data path diagram](tx_path.svg)
+
+### Design study for a precog upgrade
+![timing diagram](precog_upg.svg)

BerkeleyLab_Bedrock/badger/ethernet_crc_add.v

@@ -0,0 +1,46 @@
+// Appends 32-bit Ethernet CRC to the end of a packet
+// Also inserts GMII preamble
+//
+// The cycle-by-cycle timing definition for these tasks
+// comes from the raw_s (short) and raw_l (long) strobes;
+// raw_s is valid just for the (incoming) packet data.
+// raw_l is also valid for a few cycles before, and 4 cycles after, that.
+module ethernet_crc_add(
+	input clk,  // timespec 6.8 ns
+	input raw_s,
+	input raw_l,
+	input [7:0] raw_d,
+	output opack_s,
+	output [7:0] opack_d
+);
+
+// Strobes are easy
+reg raw_s_d=0, raw_l_d=0;
+always @(posedge clk) begin
+	raw_s_d <= raw_s;
+	raw_l_d <= raw_l;
+end
+wire first_crc = raw_s & ~raw_s_d;
+wire trail = raw_s_d & ~raw_s;
+wire gate_crc;
+wire out_crc_sel;
+
+// Instantiation
+wire [7:0] crc_out;
+crc8e_guts #(.wid(32)) crc8e(.clk(clk), .gate(gate_crc),
+	.first(first_crc), .d_in(out_crc_sel ? ~crc_out : raw_d),
+	.d_out(crc_out), .zero());
+
+// Multiplexing
+reg [1:0] crc_cnt=0;
+reg [7:0] opack_r=0;
+assign gate_crc = raw_s | raw_s_d | (crc_cnt != 0);
+assign out_crc_sel = trail | (|crc_cnt);
+always @(posedge clk) begin
+	crc_cnt <= out_crc_sel ? crc_cnt+1 : 0;
+	opack_r <= out_crc_sel ? crc_out : raw_s ? raw_d : 8'h55;
+end
+assign opack_d = first_crc ? 8'hd5 : opack_r;
+assign opack_s = raw_l | raw_l_d;
+
+endmodule

BerkeleyLab_Bedrock/badger/flash.md

@@ -0,0 +1,134 @@
+# SPI Boot Flash programming support in Packet Badger
+
+Modern FPGAs typically have the ability to boot from SPI flash.
+Then when operating, those flash pins are available for the fabric
+to interact with.  Thus the FPGA can program its own boot flash.
+
+Packet Badger includes a set of (synthesizable, portable) Verilog
+modules to take advantage of this, and a host python program to
+manipulate the system.
+
+Verilog code:
+
+* [spi_flash.v](spi_flash.v)
+* [spi_flash_engine.v](spi_flash_engine.v)
+* [reg_delay.v](../dsp/reg_delay.v)
+
+They optionally reference Xilinx primitives ICAP_SPARTAN6 or ICAPE2.
+When running on a Xilinx Spartan 6 or 7-Series FPGA, this allows
+run-time selection among multiple bitfiles stored on a single flash chip.
+
+Python (host) code:
+
+* [spi_test.py](tests/spi_test.py)
+
+## Write protect
+
+Modern SPI flash chips include write-protect features.  This can be messy
+and complicated.  Our goal is to make the system resistant to bricking,
+by holding a "golden image" in a write-protected zone of the flash.
+Two open-hardware example boards designed around that principle are
+
+* [Marble](https://github.com/BerkeleyLab/Marble)
+* [Marble-Mini](https://github.com/BerkeleyLab/Marble-Mini)
+
+Other COTS boards like the SP605 and AC701 can also be used, but they
+don't have the hardware switch on the flash chip's WP# line that can
+guarantee protection of the golden image.
+
+This discussion and software revolves around the write-protect feature
+of a Spansion/Cypress/Infineon S25FL128S
+(note that Spansion merged with Cypress in 2014,
+which was in turn acquired by Infineon in 2020).
+See the Infineon [data sheet for S25FL128S, S25FL256S](https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_%2816_MB%29_256_Mb_%2832_MB%29_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17),
+001-98283 Rev. *R, 2022-06-10.
+
+```
+fc4dff8ef4d8ebf6815c1e994812f8177c917b63c59a4913b7360eef01785af6  Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v19_00-EN.pdf
+```
+
+As a metric of the complexity of these chips, note that the data sheet
+is 165 pages long!  I think the features discussed here are likely to show up
+on other flash chips, but I can't confirm they are JEDEC-standard.
+
+Use of the write-protect feature centers on two registers,
+Status Register 1 (SR1) and Configuration Register 1 (CR1).
+We demand that TBPROT is set, so the protected blocks are at low addresses.
+This is important, because Xilinx FPGAs boot starting at address 0.
+
+## Operation
+
+Quoting p. 55 of that data sheet:
+"The desired state of TBPROT must be selected during the initial configuration
+of the device during system manufacture; before the first program or erase
+operation on the main flash array. TBPROT must not be programmed after
+programming or erasing is done in the main flash array."
+
+Other crucial paragraphs to read are p. 52 about the Status Register
+Write Disable (SRWD) bit SR1[7], and p. 56 about the Freeze Protection
+(FREEZE) bit CR1[0].
+
+The board first needs to have a Packet Badger-based bitfile loaded
+over JTAG.  Ethernet must be connected and routed to your workstation,
+so you can `ping $IP`.  Put your shell in the `badger/tests` directory
+for the steps below.
+
+```sh
+python3 spi_test.py --ip $IP --id
+```
+
+If this comes back CONFIG_REG (CR1) = 0x00, this chip is likely
+fresh-from-the-factory.  Make sure the Write Protect switch is off, then
+
+```sh
+python3 spi_test.py --ip $IP --config_init
+python3 spi_test.py --ip $IP --id
+```
+
+Now it should report CONFIG_REG (CR1) = 0x21, with the TBPROT and FREEZE
+bits set.  Because of the OTP (one-time-programmable) nature of bits in CR1,
+this step has not been extensively tested.
+
+To program the golden image at address zero,
+make sure the Write Protect switch is off, use the --id feature
+to check that the FREEZE bit is off (may require a power-cycle), and
+
+```sh
+python3 spi_test.py --ip $IP --program $BITFILE --force_write_enable
+```
+
+and then turn the Write Protect switch on.
+
+To program an application image in the second half of the 16 MByte
+flash chip, leave the Write Protect switch on, and
+
+```sh
+python3 spi_test.py --ip $IP --upper --program $BITFILE
+```
+
+When running the golden bitfile after a power cycle or hardware reset,
+reboot to that second-half bitfile with
+
+```sh
+python3 spi_test.py --ip $IP --reboot7 --upper
+```
+
+If you get in trouble, make liberal use of
+
+```sh
+python3 spi_test.py --ip $IP --clear_status
+python3 spi_test.py --ip $IP --id
+```
+
+## Performance
+
+Quick comment about timing, approximate of course.
+With a Kintex 7K160 and its 6693 kByte bitfile,
+
+* 1 second boot from flash (SPI_BUSWIDTH 2, CONFIGRATE 33)
+* 4 second program via USB JTAG (openocd adapter_khz 15000)
+* 146 second program flash via Ethernet and spi_flash.v
+* 40 second verify flash via Ethernet and spi_flash.v
+
+So while flash is great for deploying production bitfiles, it's not
+the best choice for edit/synthesize/test development cycles.

BerkeleyLab_Bedrock/badger/hack_icmp_cksum.v

@@ -0,0 +1,44 @@
+// Subtracts 0x800 from an ICMP checksum
+// Sounds easy, right?  But actually pretty tricky to correctly
+// handle 16-bit one's-complement arithmetic on data flying by 8-bits
+// at a time.  Tricky enough that Du got it wrong in icmp_rx.v;
+// that code gets the right checksum only 31/32 of the time.
+// Quoting RFC 792:
+//    The checksum is the 16-bit ones's [sic] complement of the one's
+//    complement sum of the ICMP message starting with the ICMP Type.
+
+// Output is delayed two cycles from input.
+// kick needs to be asserted on the second of the two cycles
+//   with the checksum at the input.
+
+module hack_icmp_cksum(
+	input clk,
+	input kick,
+	input [7:0] idat,
+	output [7:0] odat
+);
+
+// Precompute the all-ones condition
+wire ones_i = &idat;
+reg ones_r=0;
+always @(posedge clk) ones_r <= ones_i;
+wire all_ones = ones_i & ones_r;
+
+// Insert modified checksum into stream
+wire [15:0] x3;
+reg [7:0] dat1=0, dat2=0;
+always @(posedge clk) begin
+	dat1 <= kick ? x3[7:0] : idat;
+	dat2 <= kick ? x3[15:8] : dat1;
+end
+
+// 16-bit checksum arithmetic
+// Because of the extra inversion, we really add 0x800.
+wire [15:0] x0 = {dat1, idat};
+wire [15:0] x1 = {x0[10:0], x0[15:11]};  // rotate right 11 bits
+wire [15:0] x2 = x1 + 1 + all_ones;
+assign x3 = {x2[4:0], x2[15:5]};  // rotate left 11 bits
+
+assign odat = dat2;
+
+endmodule

BerkeleyLab_Bedrock/badger/hello.v

@@ -0,0 +1,27 @@
+// Demo client
+module hello(
+	input clk,
+	// client interface with RTEFI, see doc/clients.eps
+	input [10:0] len_c,
+	input [7:0] idata,
+	input raw_l,
+	input raw_s,
+	output [7:0] odata
+);
+
+parameter n_lat=2;
+
+reg [255:0] test_msg_rom = "Hello world from Packet Badger!\n";
+reg [4:0] a;
+reg [7:0] test_msg=0;
+always @(posedge clk) begin
+	a <= len_c[4:0] - 9;
+	test_msg <= test_msg_rom[{a,3'b0} +: 8];
+end
+
+// 13 bits input, 8 bits output, choose to pipeline output
+reg_delay #(.len(n_lat-2), .dw(8)) align(.clk(clk), .gate(1'b1), .reset(1'b0),
+	.din(test_msg), .dout(odata));
+
+
+endmodule

BerkeleyLab_Bedrock/badger/lb_gateway.v

@@ -0,0 +1,58 @@
+// Simple wrapper of mem_gateway.v
+// Rename ports to get something more familiar to:
+// - newad.py
+// - picorv32 memory bus bridge
+// - xilinx DRP bridge
+// - potential axi-lite/wishbone bridge
+module lb_gateway #(
+    parameter n_lat        =8,
+    parameter read_pipe_len=3
+) (
+    input         clk,   // timespec 6.8 ns
+    // client interface with RTEFI, see doc/clients.eps
+    input  [10:0] len_c,
+    input  [ 7:0] idata,
+    input         raw_l,
+    input         raw_s,
+    output [ 7:0] odata,
+    // local bus master
+    output        lb_clk,
+    output [23:0] lb_addr,
+    output        lb_write,
+    output        lb_read,
+    output        lb_rvalid,
+    output        lb_pre_rvalid,
+    output        lb_prefill,
+    output [31:0] lb_wdata,
+    input  [31:0] lb_rdata
+);
+
+wire control_strobe, control_rd;
+wire [read_pipe_len:0] control_pipe_rd;
+
+mem_gateway #(
+    .n_lat          (n_lat),
+    .read_pipe_len  (read_pipe_len)
+) mem_gateway_i (
+    .clk             (clk),
+    .len_c           (len_c),
+    .idata           (idata),
+    .raw_l           (raw_l),
+    .raw_s           (raw_s),
+    .odata           (odata),
+    .addr            (lb_addr),
+    .control_strobe  (control_strobe),
+    .control_rd      (control_rd),
+    .control_rd_valid(lb_rvalid),
+    .control_pipe_rd (control_pipe_rd),
+    .control_prefill (lb_prefill),
+    .data_out        (lb_wdata),
+    .data_in         (lb_rdata)
+);
+
+assign lb_clk    = clk;
+assign lb_write  = control_strobe & ~control_rd;
+assign lb_read   = |control_pipe_rd;
+assign lb_pre_rvalid = control_pipe_rd[read_pipe_len-1];
+
+endmodule

BerkeleyLab_Bedrock/badger/lbus_access.py

@@ -0,0 +1,219 @@
+'''
+Access to Packet Badger's localbus gateway
+'''
+# mostly cribbed from FEED/src/python/leep/
+import argparse
+import socket
+import numpy
+import random
+import ast
+# import binascii
+be32 = numpy.dtype('>u4')
+
+
+class lbus_access:
+    def __init__(self, host, timeout=1.02, port=803, force_burst=False, allow_burst=True, verbose=False):
+        self.dest = (host, int(port))
+        self.sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM, 0)
+        self.sock.settimeout(timeout)
+        self.verbose = verbose
+        if force_burst:
+            self.burst_avail = True
+        elif allow_burst:
+            self.burst_avail = self._burst_avail()
+        else:
+            self.burst_avail = False
+
+    def _burst_avail(self):
+        """Determines if device supports block-transfer/repeat-count
+        """
+        # TODO: Extract device capabilities automatically
+        dev_burst_en = False
+
+        # Ugly, noisy, fragile, and invasive PoC
+        msg = numpy.zeros(14, dtype=be32)
+        msg[0] = random.randint(0, 0xffffffff)
+        msg[1] = msg[0] ^ 0xffffffff
+        msg[2] = 0x10000002  # read 2
+        msg[3] = 0xa5a5a5a5  # pad
+        msg[4] = 0x10000001  # read 1
+        msg[5] = 0xa5a5a5a5  # pad
+        msg[6] = 0x20000002  # repeat 2 / write 2
+        msg[7] = 0x10000001  # read 1 / write data
+        msg[8] = 0x10000001  # pad / read 1
+        msg[9] = 0xa5a5a5a5  # pad
+        msg[10] = 0x20000002  # repeat 2 / write 2
+        msg[11] = 0x10000001  # read 1 / write data
+        msg[12] = 0x10000002  # pad / read 2
+        msg[13] = 0xa5a5a5a5  # pad
+
+        tosend = msg.tobytes()
+        # print("%s Send (%d) %s", self.dest, len(tosend), binascii.hexlify(tosend))
+        self.sock.sendto(tosend, self.dest)
+        if True:
+            reply, src = self.sock.recvfrom(15000)
+            if len(reply) == 14*4:
+                reply = numpy.frombuffer(reply, be32)
+                for n in [0, 1, 2, 4, 6, 7, 10, 11]:
+                    if reply[n] != msg[n]:
+                        print("bad mismatch %8.8x != %8.8x" % (reply[n], msg[n]))
+                r1 = reply[5]
+                r2 = reply[3]
+                if msg[8] == reply[8] and r1 == reply[9] and msg[12] == reply[12] and r2 == reply[13]:
+                    if self.verbose:
+                        print("Seems to be no-burst")
+                    return False
+                elif r1 == reply[8] and r2 == reply[9] and r1 == reply[12] and r2 == reply[13]:
+                    if self.verbose:
+                        print("Seems to be burst")
+                    return True
+                else:
+                    if self.verbose:
+                        print("Burst autodetect failed")
+                    return False
+                # for jx, x in enumerate(reply):
+                #    print("%2d %8.8x" % (jx, x))
+
+        return dev_burst_en
+
+    def _exchange(self, addrs, values=None, drop_reply=False, burst=False):
+        """Exchange a single low level message
+        """
+
+        if not burst:
+            msg = numpy.zeros(2+2*len(addrs), dtype=be32)
+        else:
+            msg = numpy.zeros(2+2+len(addrs), dtype=be32)
+
+        msg[0] = random.randint(0, 0xffffffff)
+        msg[1] = msg[0] ^ 0xffffffff
+
+        if not burst:
+            for i, (A, V) in enumerate(zip(addrs, values), 1):
+                A &= 0x00ffffff
+                if V is None:
+                    A |= 0x10000000
+                msg[2*i] = A
+                msg[2*i+1] = V or 0
+        else:
+            RC = (len(addrs) & 0x00ffffff) | 0x20000000
+            A = addrs[0]
+            A &= 0x00ffffff
+            if values[0] is None:
+                A |= 0x10000000
+            msg[2] = RC
+            msg[3] = A
+            for i, V in enumerate(values, 4):
+                msg[i] = V or 0
+
+        tosend = msg.tobytes()
+        if False:
+            mm = ".".join(["%8.8x" % x for x in msg])
+            print("%s Send (%d) %s" % (self.dest, len(tosend), mm))
+        self.sock.sendto(tosend, self.dest)
+
+        if drop_reply:
+            return None
+
+        while True:
+            reply, src = self.sock.recvfrom(15000)
+            # print("%s Recv (%d) %s", src, len(reply), binascii.hexlify(reply))
+
+            byte_align = 8 if not burst else 4
+            if len(reply) % byte_align:
+                reply = reply[:-(len(reply) % byte_align)]
+
+            if len(tosend) != len(reply):
+                print("Reply truncated %d %d" % (len(tosend), len(reply)))
+                continue
+
+            reply = numpy.frombuffer(reply, be32)
+            if (msg[:2] != reply[:2]).any():
+                print('Ignore reply w/o matching nonce %s %s' % (msg[:2], reply[:2]))
+                continue
+            elif not burst and (msg[2::2] != reply[2::2]).any():
+                print('reply addresses are out of order')
+                continue
+            elif burst and (msg[2:3] != reply[2:3]).any():
+                print('Non-matching start address')
+                continue
+            break
+
+        ret = reply[3::2] if not burst else reply[4::1]
+        return ret
+
+    def exchange(self, addrs, values=None, drop_reply=False):
+        """Accepts a list of address and values (None to read).
+        Returns a numpy.ndarray in the same order.
+        """
+        addrs = list(addrs)
+
+        consec = False
+        # Check for consecutive addresses if burst mode available
+        if self.burst_avail and len(addrs) > 1 and (addrs == list(range(addrs[0], addrs[-1]+1))):
+            consec = True
+
+        if values is None:
+            values = [None]*len(addrs)
+        else:
+            values = list(values)
+
+        ret = numpy.zeros(len(addrs), be32)
+        n_tx = 255 if consec else 127
+        for i in range(0, len(addrs), n_tx):
+            A, B = addrs[i:i+n_tx], values[i:i+n_tx]
+
+            P = self._exchange(A, B, drop_reply=drop_reply, burst=consec)
+            if not drop_reply:
+                ret[i:i+n_tx] = P
+
+        return ret
+
+
+def read_write(dev, args):
+    for pair in args.reg:
+        reg, _eq, val = pair.partition('=')
+        reg = ast.literal_eval(reg)
+        if not len(val):  # read operation
+            val = None
+        else:
+            val = ast.literal_eval(val)
+
+        retval = dev.exchange([reg], [val])
+        if val is None:
+            print("%s: \t%08x" % (reg, retval[0]))
+
+
+def mem_read(dev, args):
+    for pair in args.mem:
+        baseaddr, _eq, length = pair.partition(':')
+        baseaddr = ast.literal_eval(baseaddr)
+        length = ast.literal_eval(length)
+
+        retmem = dev.exchange(range(baseaddr, baseaddr+length))
+        if args.string:
+            print("".join([chr(x) for x in retmem]))
+        else:
+            print(retmem)
+
+
+if __name__ == "__main__":
+    p = argparse.ArgumentParser()
+    p.add_argument('-a', '--address', help='IP address of device', default='localhost')
+    p.add_argument('-p', '--port', help='UDP port for I/O', default=803)
+    p.add_argument('-t', '--timeout', help='UDP timeout, in seconds', type=float, default=1.02)
+    p.add_argument('--string', help='Format output as string', action='store_true', dest='string')
+
+    sp = p.add_subparsers()
+    s = sp.add_parser('reg', help='read/write registers')
+    s.set_defaults(func=read_write)
+    s.add_argument('reg', nargs='+', help='register[=newvalue]')
+
+    s = sp.add_parser('mem', help='read contiguous memory')
+    s.set_defaults(func=mem_read)
+    s.add_argument('mem', nargs='+', help='baseaddr:size')
+    args = p.parse_args()
+
+    lbus_acc = lbus_access(args.address, timeout=args.timeout, port=args.port, force_burst=False)
+
+    args.func(lbus_acc, args)

BerkeleyLab_Bedrock/badger/mac_subset.v

@@ -0,0 +1,83 @@
+module mac_subset #(
+	parameter mac_aw=10,  // 16-bit words
+	parameter big_endian=0,
+	parameter latency=256,
+	parameter stretch=4,  // minimum value 2, should be 4 for GMII
+	parameter ifg=24   // must have more padding than just Ethernet IFG
+) (
+	// connect the 2 below to an external 16 bit dual port ram
+	output [mac_aw - 1: 0] host_raddr,
+	input [15:0] host_rdata,
+	// address where we should start transmitting from
+	input [mac_aw - 1: 0] buf_start_addr,
+	// set start to trigger transmit, wait for done, reset start
+	input tx_mac_start,
+	output tx_mac_done,
+	// crucial information from input scanner
+	input scanner_busy,
+	// Connection to output multiplexer, right after xformer.v,
+	// data path will get routed to have CRC added, strobes are
+	// as needed by that step: strobe_s includes data only,
+	// strobe l includes time slots for GMII preamble and CRC.
+	input tx_clk,
+	output strobe_s,
+	output strobe_l,
+	output [7:0] mac_data
+);
+
+reg host_start_=0;
+always @(posedge tx_clk) begin
+	host_start_ <= tx_mac_start;
+end
+
+// Instantiate MAC
+wire req;
+wire [10:0] len_req;
+wire mac_strobe;
+test_tx_mac #(
+	.mac_aw(mac_aw)
+) mac(
+	.clk(tx_clk),
+	.host_addr(host_raddr),
+	.host_d(host_rdata),
+	.start(host_start_),
+	.buf_start_addr(buf_start_addr),
+	.done(tx_mac_done),
+	.req(req),
+	.len_req(len_req),
+	.strobe(mac_strobe),
+	.mac_data(mac_data)
+);
+
+// Move scanner_busy to tx_clk domain for use by precog
+// Better to pull this step up to rtefi_center?
+wire scanner_busy_tx;
+reg_tech_cdc scanner_busy_cdc(.I(scanner_busy), .C(tx_clk), .O(scanner_busy_tx));
+
+// Instantiate precog
+wire clear_to_send;
+wire [10:0] precog_width = len_req + 2*ifg;
+precog #(
+	.PAW (11),
+	.LATENCY (latency+ifg)
+) precog (
+	.clk (tx_clk),
+	.tx_packet_width  (precog_width),
+	.scanner_busy     (scanner_busy_tx),
+	.request_to_send  (req),
+	.clear_to_send    (clear_to_send)
+);
+
+// Manipulate simple strobe from precog
+// final system wants 4 cycles lead (for GMII preamble) and
+// 4 cycle trailer (for CRC) on strobe_l compared to strobe_s.
+// TODO this should be moved to precog
+reg [stretch-1:0] strobe_sr1=0;
+always @(posedge tx_clk) strobe_sr1 <= {strobe_sr1[stretch-2:0], clear_to_send};
+reg [stretch-1:0] strobe_sr2=0;
+always @(posedge tx_clk) strobe_sr2 <= {strobe_sr2[stretch-2:0], req};
+assign mac_strobe = strobe_sr1[stretch-1] & req;
+assign strobe_s = mac_strobe;
+assign strobe_l = clear_to_send & strobe_sr2[stretch-1];
+
+endmodule

BerkeleyLab_Bedrock/badger/mem_gate.md

@@ -0,0 +1,211 @@
+# Lightweight Address Space Serialization
+
+LASS is an encoding of reads and writes to a traditional VME-like address space.
+It is designed for transport over UDP, and has a coordinated set of features
+that make it useful for data exchange between a commodity computer master and
+an FPGA slave, with high throughput and controlled latency.
+
+LASS is agnostic as to the details of the bus that is driven; it is suitable
+for use with AXI, Wishbone, or the minimalist local bus in use by LBNL ATG.
+The underlying bus configuration is fixed at 32 bits data, 24 bits of
+word-address.  Byte access is not supported.  Of course, fewer address bits
+and narrower data words can be accommodated with padding.
+
+## Packet structure
+
+LASS packets are composed of a 64-bit transaction ID followed by a string of
+consecutive transactions.
+
+Two types of transactions are supported. A single-beat transaction where single read
+or write bus cycles are encoded, and a more complex, block-transfer based, where a
+burst of reads or writes to consecutive addresses are encoded in a more efficient
+manner.
+
+A single-beat transaction is encoded in 64 bits and is composed of command, address
+and data fields. The diagram below shows how this transaction type can be used to
+form a simple packet containing two single-beat read or write transactions.
+
+```
+ 0                   1                   2                   3
+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [31:0]                      |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [63:32]                     |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|    Command    |                    Address 0                  |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 0                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|    Command    |                    Address 1                  |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 1                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+```
+
+**NOTE:** This and all other packet diagrams follow the convention used in RFC-791,
+whereby bytes are shown as they are sent 'on the wire', i.e., network-byte-order.
+
+The packet space consumed by a block-transfer transaction depends on how many data
+beats are being read or written. At a minimum, this type of transaction can be encoded
+in 96 bits and adds an additional command and a repetition-count field to the
+single-beat transaction described previously. The additional command field is used
+to signal that the transaction being decoded is of type 'burst'. The following diagram
+depicts the structure of a packet containing a single block-transfer transaction where
+two beats of data are either read or written.
+```
+ 0                   1                   2                   3
+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [31:0]                      |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [63:32]                     |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|  Cmd (Burst)  |                Repetition Count (2)           |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|    Command    |                    Address 0                  |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 0                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 1                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+```
+
+Note that each transmitted packet can string together any combination of these two
+transaction types, provided the maximum packet length is not exceeded (see section
+on practical considerations). This can be useful when, e.g., a long array and the
+status register indicating its validity must both be read, and splitting the operation
+into two packets is not desirable. The diagram below shows how such a packet could
+be structured.
+
+```
+ 0                   1                   2                   3
+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [31:0]                      |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                    Transaction ID [63:32]                     |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|    Command    |                    Address 0                  |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 0                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|  Cmd (Burst)  |                Repetition Count (3)           |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|    Command    |                    Address 1                  |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 1                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 2                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|                           Data 3                              |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+```
+
+## Data encoding
+
+For both transaction types, the bit-widths add up such that all transactions
+start on a 32-bit boundary. Data encoding is big-endian, a.k.a. network byte order.
+
+In order to preserve 32-bit boundaries, the Command and Repetition Count fields
+are oversized in relation to the information they convey.
+
+The 8-bit Command field carries a single 2-bit operation sub-field (OP), according to the
+following encoding:
+```
+ 0  1  2  3  4  5  6  7
++--+--+--+--+--+--+--+--+
+| RSV | OP  |    RSV    |
++--+--+--+--+--+--+--+--+
+
+OP [1:0]:
+   2'b00 - Write
+   2'b01 - Read
+   2'b10 - Burst
+   2'b11 - Reserved
+```
+
+N.B.: Reserved bits should be set to 0 by software. Failing to do this may result
+in undefined behavior, since they may be defined in some future revision. One valid
+response from the FPGA is therefore to drop packets that have unused bits set.
+
+The 24-bit Repetition Count field only uses 9 bits to encode the actual repetition count, as
+shown below. Note that while the width of the COUNT sub-field places an upper bound on
+the number of data beats that can be transferred in a single packet, typical UDP
+packet sizes place additional restrictions on this number. These limitations are
+outlined in the next section.
+```
+ 0                   1                   2
+ 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+|            Reserved         |      COUNT      |
++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+
+COUNT [8:0]:
+   9'd0 - Illegal
+   9'd1 - 1 Beat
+   9'd2 - 2 Beats
+   ...
+   9'dN - N Beats
+
+```
+
+## Practical considerations
+
+A key design element of this protocol is that every reply packet has
+the same structure and length as the corresponding request packet.
+Read requests put padding in the place where results will be returned;
+replies to write requests echo the data that was written.
+This balance naturally avoids overloading the reply channel, at least
+in the common case of wire or fiber Ethernet deployments, because they
+are full-duplex with symmetric bandwidth.
+In this context, the processing logic embedded in the FPGA
+can guarantee it will reply to every request.
+
+The 64-bit ID can be any value chosen by the host, and will simply be echoed
+by the FPGA.  This gives the software an easy mechanism to match up received
+packets with outstanding requests.
+
+In a typical Ethernet environment with 1500 MTU, UDP packets can have a
+maximum payload size of 1472 octets.  Accounting for the 64-bit ID, there
+is space for a maximum of 183 single-beat transactions per packet.
+
+Likewise, it is possible to fill a packet with a block-transfer transaction with
+364 data words, thus setting a practical limit on the values that can be used in
+the Repetition Count block.
+
+Exceeding the Ethernet MTU will trigger fragmentation on the software side,
+which both is theoretically undesirable, and practically not supported by
+typical FPGA UDP/IP implementations.
+
+Driver software should have the maximum packet size easily configurable,
+to be adaptable to changes in MTU or additional protocol layering.
+An authentication layer could reduce the available packet size by 16 octets.
+
+## Implementation and discussion
+
+A subset of LASS, without the repeat-count feature, has been used at LBNL
+since about 2010.  Its FPGA-side implementation was rewritten in 2018
+(Packet Badger) to operate properly on high-traffic networks.
+This new version gives stronger real-time guarantees, and responds correctly
+to "simultaneous" requests from multiple hosts/masters.
+
+For maximum compatibility with legacy software that might set unused control
+bits to non-zero, the implementation in mem_gateway.v does _not_ enable the
+repeat count feature by default.  Engaging it requires setting the
+enable_bursts parameter to 1.
+
+This feature set is extremely similar to EtherBone, sharing much of the
+motivation and boundary conditions.  LASS is a bit more granular, is limited
+to 24-bit addresses instead of 32, and is not specialized for Wishbone.
+It would be interesting if someone rewrote or ported the EtherBone code
+base/protocol as a plug-in to Packet Badger.
+
+It's relatively easy to attach a simulated LASS FPGA-end to a real UDP port,
+to exercise the combination of software and (virtual) hardware for debugging.
+Packet Badger includes two demos of this setup, one using Verilator and one
+using Icarus Verilog.
+
+LASS as implemented on Packet Badger (including Ethernet/IP/UDP and other
+features like ARP and ICMP echo, for attachment to a GMII PHY) occupies about
+1100 LUTs of Xilinx Spartan-6 or 7-Series chips. [Comparison to EtherBone?]

BerkeleyLab_Bedrock/badger/mem_gateway.v

@@ -0,0 +1,145 @@
+// Uber-simple mapping of a UDP packet to a register read/write port.
+// Lead with 64 bits of padding (sequence number, ID, nonce, ...),
+// then alternate 32 bits of control+address with data.
+// Stick with 24 bits of address, leave 8 bits for control.
+// One of those control bits is the R/W line.
+// Every packet is returned to the sender with the read data filled in.
+// Local bus read latency is fixed, configurable at compile time.
+// Uses standard network byte order (big endian).
+//
+// This version has one more feature (disabled by default for paranoid
+// compatibility reasons, see the enable_bursts parameter), where a repeat
+// count for the following operation can be specified.  The address
+// autoincrements in that case, and each repeated operation (read or write)
+// consumes one more 32-bit data field in the input stream.  This feature
+// has been tested, but so far it lacks meaningful software support.
+//
+// For a longer description of the on-the-wire protocol, see mem_gate.md
+// Software and local-bus compatible with mem_gateway in ethernet-core.
+
+// The control_rd port (a.k.a. not write) is just a level that changes at
+// the start of each transaction, timing exactly like addr and data_out.
+//
+// control_pipe_rd is new; it's for people who want to pay attention to
+// the pipelining of each read operation.  It shows the strobe propagating
+// all the way from the start of the read request to the cycle (marked by
+// control_rd_valid, exactly equal to control_pipe_read[read_pipe_len]) when
+// this module latches data_in.  Note that the "active" bit(s) flow through
+// all read_pipe_len cycles of activity, plus one more at the end, and thus
+// has a possibly surprising length.
+//
+// If read_pipe_len is increased, and bus cycles are spaced close together
+// (traditionally every 8 cycles, goes down to every 4 when bursts are used)
+// there can be multiple bus transactions in the pipeline simultaneously.
+
+// Write operations start on the cycle marked by control_write.
+// At the moment, there is no check that they complete, so any pipelining
+// that takes place is outside the purview of this module.
+
+module mem_gateway #(
+	parameter read_pipe_len=3,  // minimum allowed value is 1
+	parameter n_lat=8,  // minimum allowed value is 5 + read_pipe_len
+	parameter enable_bursts=0
+) (
+	input clk,   // timespec 6.8 ns
+	// client interface with RTEFI, see doc/clients.eps
+	input [10:0] len_c,
+	input [7:0] idata,
+	input raw_l,
+	input raw_s,
+	output [7:0] odata,
+	// local bus
+	output [23:0] addr,
+	output control_strobe,
+	output control_rd,
+	output control_write,
+	output control_rd_valid,
+	output control_prefill,
+	// length of control_pipe_rd is read_pipe_len+1, see above
+	output [read_pipe_len:0] control_pipe_rd,
+	output [31:0] data_out,
+	input [31:0] data_in
+);
+
+// Pipeline match
+wire [7:0] pdata;
+reg_delay #(.len(read_pipe_len+1), .dw(8)) align(.clk(clk), .gate(1'b1), .reset(1'b0),
+	.din(idata), .dout(pdata));
+
+// Create localbus output signals
+reg [8:0] repeat_count=0;
+reg [23:0] isr=0;  // input shift register
+wire [31:0] next_isr = {isr, idata};
+reg [63:0] big_r=0;  // command, address, data
+reg [1:0] c4=0;
+reg data_phase=0;
+reg pre_body=0, body=0;
+reg do_op=0;
+wire next_do_op = body & &c4 & data_phase;
+wire set_repeat = ~data_phase & next_isr[29] & enable_bursts;
+wire set_repeat_view = body & &c4 & set_repeat; // Debug signal
+reg inc_address=0;
+always @(posedge clk) begin
+	isr <= next_isr[23:0];
+	c4 <= raw_s ? c4+1 : 0;
+	if (&c4) pre_body <= 1;
+	if (&c4 & pre_body) body <= 1;
+	if (~raw_s) begin  // reset between packets
+		pre_body <= 0;
+		body <= 0;
+	end
+	if (body & &c4) begin
+		inc_address <= 0;
+		if (set_repeat) begin
+			repeat_count <= next_isr[8:0] - 1;
+		end else if (~data_phase) begin
+			data_phase <= 1;
+			big_r[63:32] <= next_isr;
+		end else if (|repeat_count) begin
+			big_r[31:0] <= next_isr;
+			repeat_count <= repeat_count - 1;
+			inc_address <= 1;
+		end else begin
+			big_r[31:0] <= next_isr;
+			data_phase <= 0;
+		end
+		if (inc_address) big_r[63:32] <= big_r[63:32] + 1;
+	end
+	do_op <= next_do_op;
+end
+assign addr = big_r[23+32:32];
+assign data_out = big_r[31:0];
+assign control_rd = big_r[28+32];
+assign control_strobe = do_op;
+assign control_write = control_strobe & ~control_rd;
+
+// Keep track of the read pipeline
+reg [read_pipe_len-1:0] read_pipe_markers=0;
+wire read_op = control_strobe & control_rd;
+always @(posedge clk) read_pipe_markers <= {read_pipe_markers[read_pipe_len-2:0], read_op};
+assign control_pipe_rd = {read_pipe_markers, read_op};
+wire capture = control_pipe_rd[read_pipe_len];
+assign control_rd_valid = capture;
+
+// capture result
+reg [31:0] osr=0;
+always @(posedge clk) begin
+	osr <= {osr[23:0], pdata};
+	if (capture) osr <= data_in;
+end
+wire [7:0] xdata = osr[31:24];  // Data to be transmitted
+
+// Final alignment of the Tx data with that of all the other clients
+reg_delay #(.len(n_lat-read_pipe_len-5), .dw(8)) finale(.clk(clk),
+	.gate(1'b1), .reset(1'b0),
+	.din(xdata), .dout(odata));
+
+// Experimental - leading edge detect on raw_l
+reg raw_l_r=0, control_prefill_r;
+always @(posedge clk) begin
+	raw_l_r <= raw_l;
+	control_prefill_r <= raw_l & ~raw_l_r;
+end
+assign control_prefill = control_prefill_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/ones_chksum.v

@@ -0,0 +1,28 @@
+// 16-bit ones-complement checksum calculator
+// Applies to all of IP header, ICMP, and UDP checksums
+// Well, difficult to use with UDP because of its pathological
+// inclusion of _two_ copies of the UDP length.
+// mostly cribbed from core/assemble_eth.v
+
+module ones_chksum(
+	input clk,
+	input clear,
+	input gate,
+	input [7:0] din,
+	output [7:0] sum,
+	output all_ones
+);
+
+reg [7:0] chksum=0, chksum1=0;
+reg chksum_carry=0;
+always @(posedge clk) begin
+	if (clear) {chksum_carry, chksum} <= 9'h0;
+	else if (gate) {chksum_carry, chksum} <=
+		chksum1 + din + chksum_carry;
+	if (clear) chksum1 <= 8'h0;
+	else if (gate) chksum1 <= chksum;
+end
+assign sum = ~(chksum1 + chksum_carry);
+assign all_ones = &chksum;
+
+endmodule

BerkeleyLab_Bedrock/badger/packet_categorize.v

@@ -0,0 +1,41 @@
+// Reduce number of bits representing the category
+// of a Packet Badger Rx packet from 8 to 4.
+// Keep the categories here in-sync with badger_stat.py.
+// Output is delayed one cycle; clock domain is unchanged.
+// 0:  not used
+// 1:  failed CRC
+// 2:  ARP for us
+// 3:  not MAC-addressed for us
+// 4:  packet type is not IP
+// 5:  other unrecognized
+// 6:  ICMP
+// 7:  not used
+// 8-15:  UDP to a configured port
+
+module packet_categorize(
+	input clk,
+	input strobe,
+	input [7:0] status,  // from Badger's scanner.v
+	output strobe_o,
+	output [3:0] category
+);
+
+reg strobe_r=0;
+reg [3:0] category_r;
+always @(posedge clk) begin
+	strobe_r <= strobe;
+	// 0 not used
+	if      (~status[2])            category_r <= 4'h1;  // failed CRC
+	else if ( status[1:0] == 2'b01) category_r <= 4'h2;  // ARP
+	else if (~status[3])            category_r <= 4'h3;  // not MAC-addressed for us
+	else if (~status[4])            category_r <= 4'h4;  // not IP
+	else if ( status[1:0] == 2'b00) category_r <= 4'h5;  // other unrecognized
+	else if ( status[1:0] == 2'b10) category_r <= 4'h6;  // ICMP
+	// 7 not used
+	else                            category_r <= {1'b1, status[7:5]};  // UDP, status[1:0] == 2'b11
+end
+
+assign strobe_o = strobe_r;
+assign category = category_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/pbuf_writer.v

@@ -0,0 +1,138 @@
+// Takes results from scanner and forms the 9-bit output stream for
+// the packet buffer, according to the plan shown in doc/memory.eps.
+// Five-word "badge" written at the beginning of a packet:
+//   1. Dummy, needed in case construct.v skips forward two
+//   2. Length msb
+//   3. Length lsb
+//   4. Status
+//   5. Reserved, currently zero
+// .. where words 1 and 2 have the 9th bit set to mark start-of-frame.
+// This structure must be kept consistent with decoder in construct.v.
+//
+// The datapath for the packet buffer data is reused to also produce
+// a port that can write data to an Rx MAC.  A 4 kByte buffer memory
+// is the smallest that can guarantee holding two full packets, and
+// we simply double buffer instead of trying something more complicated.
+
+module pbuf_writer #(
+	parameter paw=11  // packet address width, 11 IRL, maybe less for simulations
+) (
+	input clk,
+	// Simple flow of data from input state machine
+	// conforms to AXI-stream-lite, if I adjust the names?
+	input [7:0] data_in,
+	input data_s,
+	input data_f,
+	// Results of scanning process provided to us
+	input [10:0] pack_len,
+	input [7:0] status_vec,
+	input status_valid,
+	// port to DPRAM, write every cycle
+	output [8:0] mem_d,
+	output [paw-1:0] mem_a,
+	// port to Rx MAC memory
+	output [7:0] rx_mac_d,
+	output [11:0] rx_mac_a,
+	output rx_mac_wen,
+	// port to Rx MAC handshake
+	// Double buffering works as follows from the host point of view:
+	//   * rx_mac_buf_status = [rx_mac_hbank_r, mac_bank]
+	//   * rx_mac_hbank_r = points to the bank currently read (and blocked) by the host
+	//     mac_bank = points to the bank the badger will write the next packet to (highest address bit)
+	//  1) badger toggles mac_bank once a packet has been completely received
+	//  2) The host knows new data is available when rx_mac_hbank_r == mac_bank
+	//  3) Host toggles rx_mac_hbank and is allowed to read the slot indexed by rx_mac_hbank_r in the next cycle
+	//  4) This allows badger to receive and write to the other slot, cycle continues from 1
+	input rx_mac_hbank,
+	output [1:0] rx_mac_buf_status,
+	// port to Rx MAC packet selector
+	input rx_mac_accept,
+	// Other
+	output [paw-1:0] gray_state,  // Valid read pointer, Rx needs to know this
+	output badge_stb  // debugging hook
+);
+
+// Possibly stupid waste of 8 FF, but makes development much easier
+reg [7:0] status_r=0;
+always @(posedge clk) if (status_valid) status_r <= status_vec;
+
+// Synthesize address and data for output DPRAM.
+// It's critical that we're able to fill in the badge once the packet has ended.
+// See doc/memory.eps for a simplified description of what we're trying to accomplish.
+reg [paw-1:0] fp=0;   // unperturbed frame counter/pointer
+reg [paw-1:0] fpp=0;  // actual destination address
+reg [paw-1:0] origin=0;  // pointer to start of badge
+reg [2:0] post_cnt=5;
+reg [8:0] pxd=0;   // data + sof marker in 9th bit
+wire not_head = post_cnt==5;
+reg badge_stb_r=0;
+reg data_s_d=0;
+wire trig = data_s & ~data_s_d;
+always @(posedge clk) begin
+	data_s_d <= data_s;
+	// Setup counter to start writing the badge at the end of data
+	// Stagnate counter at 5, and if that's the case write data through
+	post_cnt <= data_f ? 3'd0 : not_head ? 3'd5 : post_cnt+1;
+	if (trig) origin <= fp;
+	case (post_cnt)
+		// 12 unused bits, will find customers later, including authentication
+		// Note that the 0 to 1 transition in bit 7 position between states 0 and 1
+		// is absolutely CRITICALLY IMPORTANT to let the reader find the beginning
+		// of the packet even when it occasionally skips reading a word, in the
+		// case where the reader (Tx side) clock is slower than this clock.
+		0: pxd <= {1'b1, 1'b0, 7'b0};
+		1: pxd <= {1'b1, 1'b1, pack_len[6:0]};
+		2: pxd <= {1'b0, 4'd0, pack_len[10:7]};
+		3: pxd <= {1'b0, status_r};
+		4: pxd <= {1'b0, 8'd0};
+		5: pxd <= {1'b0, data_in};
+		default: pxd <= 9'bx;
+	endcase
+	fp <= fp+1;
+	fpp <= data_s ? fp + 5 : not_head ? fp : origin + post_cnt;
+	badge_stb_r <= post_cnt!=0 && post_cnt!=5;
+end
+
+// Output ports
+assign mem_a = fpp;
+assign mem_d = pxd;
+assign badge_stb = badge_stb_r;
+
+// We need rx_mac_hbank in our own clk domain
+// Better to pull this step up to rtefi_center?
+wire rx_mac_hbank_r;
+reg_tech_cdc rx_mac_hbank_cdc(.I(rx_mac_hbank), .C(clk), .O(rx_mac_hbank_r));
+
+// MAC logic
+reg [10:0] mac_a0=0;
+reg mac_bank=0;
+wire bank_ready = mac_bank != rx_mac_hbank_r;
+assign rx_mac_buf_status = {rx_mac_hbank_r, mac_bank};
+reg mac_save=0, mac_stopping=0;
+reg mac_queue=0;
+always @(posedge clk) begin
+	if (trig & bank_ready) mac_save <= 1;
+	if (trig) mac_a0 <= 4;
+	else if (post_cnt==1) mac_a0 <= 0;
+	else mac_a0 <= mac_a0 + 1;
+	mac_stopping <= post_cnt == 4;
+	if (mac_stopping) mac_save <= 0;
+	if ((post_cnt==1) & mac_save & rx_mac_accept) begin
+		// At his point we know we'll forward the packet to the host
+		mac_queue <= 1;
+	end
+	if (mac_stopping & mac_queue) begin
+		mac_bank <= ~mac_bank;
+		mac_queue <= 0;
+	end
+end
+assign rx_mac_d = pxd[7:0];
+assign rx_mac_a = {mac_bank, mac_a0};
+assign rx_mac_wen = mac_save;
+
+// Convert to Gray code for Rx side, so Rx and Tx can be in different clock domains
+wire [paw-1:0] fp_gray = fp ^ {1'b0, fp[paw-1:1]};
+reg [paw-1:0] gray_state_r=0; always @(posedge clk) gray_state_r <= fp_gray;
+assign gray_state = gray_state_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/precog.v

@@ -0,0 +1,77 @@
+// A gap detector for timing transmissions from the MAC.
+// The `scanner` module looks ahead for a suitable gap in the packet badger
+// data stream. Once found it indicates to the MAC, downstream of the
+// ring-buffer, that its TX - packet can now be multiplexed onto the stream.
+
+module precog #(
+	// packet address width, 11 IRL
+	parameter PAW=11,
+	// latency from beginning of detected gap to `clear_to_send` going high
+	parameter LATENCY=11
+) (
+	input clk,
+	// during a gap of N cycles, `scanner_busy` goes low for N cycles
+	input scanner_busy,
+	// Minimum width of the gap. tx_packet_width must be <= LATENCY - 2
+	input [PAW-1:0] tx_packet_width,
+	// pulse to latch `tx_packet_width` and start searching for a gap
+	input request_to_send,
+	// Rising edge: `LATENCY` cycles after the beginning of the detected gap
+	// Falling edge: `tx_packet_width` cycles after the rising edge
+	output reg clear_to_send
+);
+
+initial clear_to_send = 0;
+reg [PAW-1:0] gap_width = 0;
+reg [PAW-1:0] tx_packet_width_l = 0;
+reg [   11:0] delay_cnt = 0;
+reg [    1:0] state = 0;
+wire is_gap = gap_width >= tx_packet_width_l;
+localparam ST_WAIT_RTS = 0;
+localparam ST_WAIT_GAP = 1;
+localparam ST_WAIT_RISING = 2;
+localparam ST_WAIT_FALLING = 3;
+
+always @(posedge clk) begin
+	clear_to_send <= 0;
+	if (scanner_busy) gap_width <= 0;
+	else if (~(&gap_width)) gap_width <= gap_width + 1;
+	case (state)
+		ST_WAIT_RTS: begin
+			tx_packet_width_l <= tx_packet_width;
+			if (request_to_send)
+				state <= ST_WAIT_GAP;
+		end
+
+		ST_WAIT_GAP: begin
+			delay_cnt <= 0;
+			if (is_gap)
+				state <= ST_WAIT_RISING;
+		end
+
+		ST_WAIT_RISING: begin
+			delay_cnt <= delay_cnt + 1;
+			if (delay_cnt >= LATENCY - tx_packet_width_l - 2) begin
+				delay_cnt <= 0;
+				clear_to_send <= 1;
+				state <= ST_WAIT_FALLING;
+			end
+		end
+
+		ST_WAIT_FALLING: begin
+			delay_cnt <= delay_cnt + 1;
+			if (delay_cnt >= tx_packet_width_l - 1)
+				state <= ST_WAIT_RTS;
+			else
+				clear_to_send <= 1;
+		end
+
+		default: begin
+			state <= ST_WAIT_RTS;
+			gap_width <= 0;
+			delay_cnt <= 0;
+		end
+	endcase
+end
+
+endmodule

BerkeleyLab_Bedrock/badger/rtefi_center.v

@@ -0,0 +1,300 @@
+// Full RTEFI Rx/Tx pipeline
+//
+// Ports are abstract GMII (maybe should adjust their names?).
+// Non-GMII hardware can and should add an adapter layer to get
+// from GMII to RGMII or the MGT.  Actual GMII hardware can just
+// connect these ports to the physical pins.
+//
+// Up to seven clients, each handling a UDP port, attach here.
+//
+// This module instantiates a series of modules for the data path
+// linking GMII Rx through to GMII Tx, shown in doc/rtefi.eps.
+// The several steps have instance names starting with a through e
+// (a_scan through e_crc).
+//
+module rtefi_center #(
+	parameter paw = 11,  // packet (memory) address width, nominal 11
+	parameter n_lat = 3,  // latency of client pipeline
+	parameter mac_aw = 10,  // sets size (in 16-bit words) of DPRAM in Tx MAC
+	parameter handle_arp = 1,
+	parameter handle_icmp = 1,
+	// The following parameters set the synthesis-time default, but all
+	// can be overridden at run-time using the configuration port.
+	// UDP ports 0 through 7 represent the index given in udp_sel.
+	// While udp_port_cam.v is written parameterized, we limit it to
+	// three bits and 8 ports for timing reasons.  Port 0 is internally
+	// implemented as echo; the rest will be user-defined via synthesis-time
+	// plug-ins.  Generally the UDP port numbers should be "well known",
+	// but the case can be made to have them run-time override-able (without
+	// resynthesizing) to help cope with unexpected network issues.
+	// When a udp_port number is set to 0, that port is disabled.
+	parameter [31:0] ip = {8'd192, 8'd168, 8'd7, 8'd4},  // 192.168.7.4
+	parameter [47:0] mac = 48'h12555500012d,
+	parameter udp_port0 = 7,
+	parameter udp_port1 = 801,
+	parameter udp_port2 = 802,
+	parameter udp_port3 = 803,
+	parameter udp_port4 = 0,
+	parameter udp_port5 = 0,
+	parameter udp_port6 = 0,
+	parameter udp_port7 = 0
+) (
+	// GMII Input (Rx)
+	input rx_clk,
+	input [7:0] rxd,
+	input rx_dv,
+	input rx_er,
+	// GMII Output (Tx)
+	input tx_clk,
+	output [7:0] txd,
+	output tx_en,
+	// Configuration
+	// When changing configuration (like IP) at run time with these ports,
+	// it's recommended to turn off enable_rx during that process.
+	input enable_rx,
+	input config_clk,
+	input [3:0] config_a,
+	input [7:0] config_d,
+	input config_s,  // MAC/IP address write
+	input config_p,  // UDP port number write
+	// Host side of Tx MAC
+	// connect the 2 below to an external 16 bit dual port ram
+	output [mac_aw - 1: 0] host_raddr,
+	input [15:0] host_rdata,
+	// address where we should start transmitting from
+	input [mac_aw - 1: 0] buf_start_addr,
+	// set start to trigger transmission, wait for done, reset start
+	input tx_mac_start,
+	output tx_mac_done,
+	// As documented in doc/clients.eps
+	output [10:0] len_c,
+	output [6:0] raw_l,
+	output [6:0] raw_s,
+	output [7:0] idata,
+	input [7*8-1:0] mux_data_in,  // collection of odata
+	// port to Rx MAC memory
+	output [7:0] rx_mac_d,
+	output [11:0] rx_mac_a,
+	output rx_mac_wen,
+	// port to Rx MAC handshake
+	input rx_mac_hbank,
+	output [1:0] rx_mac_buf_status,
+	// port to Rx MAC packet selector
+	input rx_mac_accept,
+	output [7:0] rx_mac_status_d,
+	output rx_mac_status_s,
+	// Debugging
+	output ibadge_stb,
+	output [7:0] ibadge_data,
+	output obadge_stb,
+	output [7:0] obadge_data,
+	output xdomain_fault,
+	// Dumb stuff to get LEDs blinking
+	output [3:0] scanner_debug,
+	output rx_mon,
+	output tx_mon,
+	// Simulation-only
+	output in_use
+);
+
+// Overhead: make sure the tools can create an IOB on all GMII inputs
+reg [7:0] eth_in_r=0;
+reg eth_in_s_r=0, eth_in_e_r=0;
+always @(posedge rx_clk) begin
+	eth_in_r <= rxd;
+	eth_in_s_r <= rx_dv;
+	eth_in_e_r <= rx_er;
+end
+
+// First real step: scan the input packet
+wire [3:0] ip_a;  reg [7:0] ip_d=0;  // MAC/IP config, Rx side
+wire [3:0] pno_a; reg [7:0] pno_d=0;  // UDP port numbers
+wire [7:0] sdata;
+wire scanner_busy;
+wire sdata_s, sdata_l;
+wire [10:0] pack_len;
+wire [7:0] status_vec; wire status_valid;
+scanner #(.handle_arp(handle_arp), .handle_icmp(handle_icmp)) a_scan(
+	.clk(rx_clk),
+	.eth_in(eth_in_r), .eth_in_s(eth_in_s_r), .eth_in_e(eth_in_e_r),
+	.enable_rx(enable_rx),
+	.ip_a(ip_a), .ip_d(ip_d),
+	.pno_a(pno_a), .pno_d(pno_d),
+	.busy(scanner_busy), .debug(scanner_debug),
+	.odata(sdata), .odata_s(sdata_s), .odata_f(sdata_l),
+	.pack_len(pack_len), .status_vec(status_vec), .status_valid(status_valid)
+);
+assign rx_mac_status_d = status_vec;
+assign rx_mac_status_s = status_valid;
+`ifdef SIMULATE
+// always @(negedge rx_clk) if (status_valid) $display("Rx scanner status %x", status_vec);
+`endif
+
+// Second step: create data flow to DPRAM
+wire [paw-1:0] pbuf_a_rx, gray_state;
+wire [8:0] pbuf_din;
+pbuf_writer #(.paw(paw)) b_write(.clk(rx_clk),
+	.data_in(sdata), .data_s(sdata_s), .data_f(sdata_l),
+	.pack_len(pack_len), .status_vec(status_vec), .status_valid(status_valid),
+	.mem_a(pbuf_a_rx), .mem_d(pbuf_din),
+	.rx_mac_d(rx_mac_d), .rx_mac_a(rx_mac_a), .rx_mac_wen(rx_mac_wen),
+	.rx_mac_hbank(rx_mac_hbank), .rx_mac_buf_status(rx_mac_buf_status),
+	.rx_mac_accept(rx_mac_accept),
+	.gray_state(gray_state),
+	.badge_stb(ibadge_stb)
+);
+assign ibadge_data = pbuf_din[7:0];
+
+// 1 MTU DPRAM; note the ninth bit used to mark Start of Frame.
+// Also note the lack of a write-enable; just write every cycle.
+// I hate jumbo frames.  Expect paw=11, so memory is big enough to hold 1500 MTU.
+reg [8:0] pbuf[0:(1<<paw)-1];
+reg [8:0] pbuf_out=0;
+wire [paw-1:0] mem_a2;  // see below
+always @(posedge rx_clk) pbuf[pbuf_a_rx] <= pbuf_din;
+always @(posedge tx_clk) pbuf_out <= pbuf[mem_a2];
+integer jx;
+initial for (jx=0; jx<(1<<paw); jx=jx+1) pbuf[jx]=0;
+
+// Third step: sift through that packet's data to
+// synthesize the reply packet's header
+wire [3:0] ip_mem_a_tx;  reg[7:0] ip_mem_d_tx=0;  // MAC/IP config, Tx side
+// Signals sent from construct to xformer
+wire [5:0] pc;
+wire [1:0] category;
+wire [2:0] udp_sel;
+wire [7:0] eth_data_out;
+wire eth_strobe_short, eth_strobe_long;
+localparam p_offset=480;  // see notes in construct.v
+construct #(.paw(paw), .p_offset(p_offset)) c_construct(.clk(tx_clk),
+	.gray_state(gray_state),
+	.ip_a(ip_mem_a_tx), .ip_d(ip_mem_d_tx),
+	.addr(mem_a2), .pbuf_out(pbuf_out),
+	.pc(pc), .category(category), .udp_sel(udp_sel),
+	.badge_stb(obadge_stb), .badge_data(obadge_data),
+	.xdomain_fault(xdomain_fault),
+	.eth_data_out(eth_data_out), .eth_strobe_short(eth_strobe_short), .eth_strobe_long(eth_strobe_long)
+);
+
+// Data multiplexer
+wire xraw_s, xraw_l;  wire [7:0] raw_d;  // Output, still needs CRC
+xformer #(.n_lat(n_lat), .handle_icmp(handle_icmp)) d_xform(.clk(tx_clk),
+	.pc(pc), .category(category), .udp_sel(udp_sel),
+	.idata(eth_data_out), .eth_strobe_short(eth_strobe_short), .eth_strobe_long(eth_strobe_long),
+	.len_c(len_c),
+	.raw_l(raw_l), .raw_s(raw_s),
+	.mux_data_in(mux_data_in),
+	.odata(raw_d), .ostrobe_s(xraw_s), .ostrobe_l(xraw_l)
+);
+assign idata = eth_data_out;
+
+// Tx MAC
+// Disable by setting mac_aw=1
+// precog_latency is kind of important;
+// check resulting interpacket gap in simulations
+localparam precog_latency = (1<<paw) - p_offset + 4 + n_lat;
+wire [7:0] tx_mac_data;
+wire tx_mac_strobe_s, tx_mac_strobe_l;
+generate if (mac_aw > 1) begin : mac_b
+    mac_subset #(
+	.mac_aw(mac_aw),
+	.latency(precog_latency)
+    ) txmac (
+	.host_raddr(host_raddr),
+	.host_rdata(host_rdata),
+	.buf_start_addr(buf_start_addr),
+	.tx_mac_start(tx_mac_start),
+	.tx_mac_done(tx_mac_done),
+	.scanner_busy(scanner_busy),
+	.tx_clk(tx_clk),
+	.mac_data(tx_mac_data),
+	.strobe_s(tx_mac_strobe_s),
+	.strobe_l(tx_mac_strobe_l)
+    );
+end else begin : no_mac_b
+	assign host_raddr = 0;
+	assign tx_mac_strobe_s = 0;
+	assign tx_mac_strobe_l = 0;
+	assign tx_mac_data = 0;
+	assign tx_mac_done = 0;
+end endgenerate
+
+// Slide data from Tx MAC in here
+// XXX no cross-checking that the MAC is avoiding collisions
+// using precog the way it's supposed to.
+wire xraw2_s = xraw_s | tx_mac_strobe_s;
+wire xraw2_l = xraw_l | tx_mac_strobe_l;
+wire [7:0] raw2_d = tx_mac_strobe_s ? tx_mac_data : raw_d;
+
+// Finally, add Ethernet CRC and GMII preamble
+wire opack_s;  wire [7:0] opack_d;
+ethernet_crc_add e_crc(.clk(tx_clk),
+	.raw_s(xraw2_s), .raw_l(xraw2_l), .raw_d(raw2_d),
+	.opack_s(opack_s), .opack_d(opack_d)
+);
+
+// Make sure these outputs can be put into an IOB
+reg [7:0] eth_out_r=0;
+reg eth_out_s_r=0;
+always @(posedge tx_clk) begin
+	eth_out_r <= opack_d;
+	eth_out_s_r <= opack_s;
+end
+assign txd = eth_out_r;
+assign tx_en = eth_out_s_r;
+
+// Has to be distinct from the IOBs
+assign rx_mon = eth_in_s_r;
+assign tx_mon = opack_s;
+
+// Hook for testing; not intended to be connected in hardware
+reg [paw-1:0] in_use_timer=0;
+assign in_use = |in_use_timer;
+always @(posedge rx_clk) begin
+	if (in_use) in_use_timer <= in_use_timer - 1;
+	if (rx_mon) in_use_timer <= {paw{1'b1}};
+end
+
+// Memory for MAC/IP addresses
+reg [7:0] ip_mem[0:15];
+always @(posedge config_clk) if (config_s) ip_mem[config_a] <= config_d;
+always @(posedge rx_clk) ip_d <= ip_mem[ip_a];
+always @(posedge tx_clk) ip_mem_d_tx <= ip_mem[ip_mem_a_tx];
+initial begin
+	// Matches packets in at least arp3.dat, icmp3.dat, udp3.dat.
+	ip_mem[0] = mac[47:40];  // Start of MAC
+	ip_mem[1] = mac[39:32];
+	ip_mem[2] = mac[31:24];
+	ip_mem[3] = mac[23:16];
+	ip_mem[4] = mac[15:8];
+	ip_mem[5] = mac[7:0];  // End of MAC
+	ip_mem[6] = ip[31:24];  // Start of IP
+	ip_mem[7] = ip[23:16];
+	ip_mem[8] = ip[15:8];
+	ip_mem[9] = ip[7:0];  // End of IP
+end
+
+// Memory for UDP port numbers
+reg [7:0] pno_mem[0:15];
+always @(posedge config_clk) if (config_p) pno_mem[config_a] <= config_d;
+always @(posedge rx_clk) pno_d <= pno_mem[pno_a];
+initial begin
+	pno_mem[0] = udp_port0[15:8];
+	pno_mem[1] = udp_port0[7:0];
+	pno_mem[2] = udp_port1[15:8];
+	pno_mem[3] = udp_port1[7:0];
+	pno_mem[4] = udp_port2[15:8];
+	pno_mem[5] = udp_port2[7:0];
+	pno_mem[6] = udp_port3[15:8];
+	pno_mem[7] = udp_port3[7:0];
+	pno_mem[8] = udp_port4[15:8];
+	pno_mem[9] = udp_port4[7:0];
+	pno_mem[10] = udp_port5[15:8];
+	pno_mem[11] = udp_port5[7:0];
+	pno_mem[12] = udp_port6[15:8];
+	pno_mem[13] = udp_port6[7:0];
+	pno_mem[14] = udp_port7[15:8];
+	pno_mem[15] = udp_port7[7:0];
+end
+
+endmodule

BerkeleyLab_Bedrock/badger/rtefi_notes.txt

@@ -0,0 +1,95 @@
+Real-Time Ethernet Fabric Infrastructure (building on PSPEPS experience)
+(work-in-progress)
+
+Also see rtefi.eps
+
+Keep core success of PSPEPS that it can support self-throttled full-rate
+communications to unbuffered clients.  Supporting UDP rather than raw
+Ethernet is (still) worth the effort in order to align with the security
+model of typical host computers; an application doesn't need root privileges
+to communicate over UDP.
+
+Hardware support limited to IP, ARP, ICMP echo, UDP.  TCP support (if any)
+would be relegated to the soft-core.  IPv4 only, no IP options or
+fragmentation.  Supporting jumbo packets is easy in theory, but balloons the
+latency and amount of storage needed; just don't do it.
+
+A major defect in PSPEPS was the side-channel handling of source IP and MAC,
+which was easily confused when handling communication from multiple hosts.
+That info is correctly handled per-packet in RTEFI.
+
+Even clients that have to buffer their data need to be shoehorned into the
+unbuffered paradigm.  Expect this will happen by making them respond to each
+input packet with a status message that includes their (possibly incomplete)
+output buffer.  Known possible sub-clients include flash programming,
+microcontroller bridge, and JTAG.  Those sub-clients could share (time-slice
+access) their input and output buffers.  Work on such clients has not started.
+
+A common packet structure for the buffered clients can include at least one
+nonce, a flag for reply-buffer complete, and a time estimate for when that
+buffer will be complete.  Plus optional authentication components, see below.
+
+We hope eventually to include PTP/White Rabbit IEEE-1588 capability somewhere,
+maybe with the assistance of a soft-core.
+
+The input scanner transcribes packets with a fixed latency of about 20 cycles.
+Status bits written to badge include, among other things, a check that the
+UDP payload length is consistent with the actual packet length; a packet that
+fails that test is considered not UDP.
+
+The badge added to packet by the input scanner is necessarily less than 12
+octets, the minimum IFG.  Actually one less than that, due to the potential
+Tx/Rx 100ppm clock mismatch.  The actual length now is five octets.
+
+The mem_gateway client could eventually have two UDP port numbers, one with
+and one without authentication.
+
+Output signature insertion must have a fixed latency, maybe around 16 cycles.
+This contrasts with the one-cycle latency of CRC32 insertion.
+
+Plan to write a self-diagnostic client, capable of reporting things like packet
+counts, byte counts, error counts, Rx/Tx frequency ratio, and which hosts
+are communicating.  Of course it will be optional, but attempt to make it
+small and non-intrusive enough that it will practically be kept in most builds.
+It's an interesting question whether reports should be public or require
+authentication.  Not sure if it is better handled as as a buffered or
+unbuffered client.
+
+Rx MAC for soft-core should be run-time configurable by the soft-core; nominal
+is to accept all packets with our dest MAC and IP, but not handled by hardware
+clients.  It will inherently receive packets with IP options or fragmentation
+set.  Include promiscuous mode option.
+
+Precog (precognition) module leverages the 1 MTU shift register to look ahead
+for a prescribed gap in the input.  That will become an available slot in the
+Tx channel into which the output buffer of the soft-core MAC can be inserted.
+
+PSPEPS claimed to fit in 1000 LUTs minimum; this base structure hasn't
+changed that much.  Prototyping indicates authentication will likely add over
+1000 more LUT.  We could still come in at under 10% of a 7A35T.
+
+Minimum DPRAM usage is one, without authentication or any buffered clients.
+Add two for authentication key memory, two for buffered clients, two for a
+soft-core MAC, and two typical overhead internal to mem_gateway (config_romx
+and mirror), total could reach nine.  All DPRAM instances should be useful
+at 2K x 8, the minimum size in 7-series Xilinx chips.
+
+UDP checksums are always disabled now.  We could also provide the option for
+a client to fake its checksum.  A true checksum is not possible for causality
+reasons.
+
+Flash-program and JTAG buffered sub-clients will demand authentication.
+
+People do ask about DHCP.  This is likely a job for the soft-core.
+
+UDP echo on port 7 is included in the baseline, no netlist overhead, but
+can be disabled.  No ICMP port unreachable responses are ever generated
+(unless by some future soft core and its software).  At some point we need
+to probe/fingerprint this code with nmap, zmap, arp-scan, p0f, prads, others.
+
+For maximum clarity and applicability, the implementation is (and needs
+to be kept) 100% portable Verilog, properly testable with both Icarus and
+Verilator.  Some of that Verilog may be machine-generated by open-source
+tools.
+
+LBNL think tank props:  Larry Doolittle, Vamsi Vytla, Eric Norum, Gang Huang

BerkeleyLab_Bedrock/badger/rtefi_preblob.v

@@ -0,0 +1,129 @@
+// rtefi_blob.v is normally a preprocessed version of rtefi_preblob.v with
+// definitions from the include file expressed/expanded.  That include file
+// is itself machine-generated based on the desired clients.
+//
+// TL;DR: if this file is named rtefi_blob.v, it's probably a mistake to
+// hand-edit it!
+//
+`include "rtefi_preblob.vh"
+module rtefi_blob #(
+	parameter paw = 11,  // packet (memory) address width, nominal 11
+	parameter n_lat = 8,  // latency of client pipeline
+	parameter mac_aw = 10,  // sets size (in 16-bit words) of DPRAM in Tx MAC
+	// See comments in rtefi_center.v
+	parameter [31:0] ip = {8'd192, 8'd168, 8'd7, 8'd4},  // 192.168.7.4
+	parameter [47:0] mac = 48'h12555500012d,
+`BLOB_PARAMS
+	parameter udp_port0 = 7,
+	parameter udp_port1 = 801,
+	parameter udp_port2 = 802,
+	parameter udp_port3 = 803,
+	parameter udp_port4 = 804,
+	parameter udp_port5 = 0,
+	parameter udp_port6 = 0,
+	parameter udp_port7 = 0
+) (
+	// GMII Input (Rx)
+	input rx_clk,
+	input [7:0] rxd,
+	input rx_dv,
+	input rx_er,
+	// GMII Output (Tx)
+	input tx_clk,
+	output [7:0] txd,
+	output tx_en,
+	output tx_er,
+	// Configuration
+	input enable_rx,
+	input config_clk,
+	input [3:0] config_a,
+	input [7:0] config_d,
+	input config_s,  // MAC/IP address write
+	input config_p,  // UDP port number write
+	// Host side of Tx MAC
+	// connect the 2 below to an external 16 bit dual port ram
+	output [mac_aw - 1: 0] host_raddr,
+	input [15:0] host_rdata,
+	// address where we should start transmitting from
+	input [mac_aw - 1: 0] buf_start_addr,
+	// set start to trigger transmission, wait for done, reset start
+	input tx_mac_start,
+	output tx_mac_done,
+	// port to Rx MAC memory
+	output [7:0] rx_mac_d,
+	output [11:0] rx_mac_a,
+	output rx_mac_wen,
+	// port to Rx MAC handshake
+	input rx_mac_hbank,
+	output [1:0] rx_mac_buf_status,
+	// port to Rx MAC packet selector
+	output [7:0] rx_mac_status_d,
+	output rx_mac_status_s,
+	input rx_mac_accept,
+	// Debugging
+	output [3:0] scanner_debug,
+	output ibadge_stb,
+	output [7:0] ibadge_data,
+	output obadge_stb,
+	output [7:0] obadge_data,
+	output xdomain_fault,
+	// Pass-through to user modules
+`BLOB_PORTS
+	// Dumb stuff to get LEDs blinking
+	output rx_mon,
+	output tx_mon,
+	// Simulation-only
+	output in_use
+);
+
+wire [10:0] len_c;
+wire [6:0] raw_l;
+wire [6:0] raw_s;
+wire [7:0] idata;
+wire [7*8-1:0] mux_data_in;
+
+rtefi_center #(
+	.ip(ip), .mac(mac), .paw(paw), .n_lat(n_lat),
+	.mac_aw(mac_aw),
+	.udp_port0(udp_port0),
+	.udp_port1(udp_port1),
+	.udp_port2(udp_port2),
+	.udp_port3(udp_port3),
+	.udp_port4(udp_port4),
+	.udp_port5(udp_port5),
+	.udp_port6(udp_port6),
+	.udp_port7(udp_port7)
+) center(
+	.rx_clk(rx_clk), .rxd(rxd),
+	.rx_dv(rx_dv), .rx_er(rx_er),
+	.tx_clk(tx_clk) , .txd(txd),
+	.tx_en(tx_en),
+	.enable_rx(enable_rx),
+	.config_clk(config_clk), .config_s(config_s), .config_p(config_p),
+	.config_a(config_a), .config_d(config_d),
+	.len_c(len_c), .raw_l(raw_l), .raw_s(raw_s),
+	.idata(idata), .mux_data_in(mux_data_in),
+	.host_raddr(host_raddr),
+	.host_rdata(host_rdata),
+	.buf_start_addr(buf_start_addr),
+	.tx_mac_start(tx_mac_start),
+	.tx_mac_done(tx_mac_done),
+	.rx_mac_d(rx_mac_d), .rx_mac_a(rx_mac_a), .rx_mac_wen(rx_mac_wen),
+	.rx_mac_hbank(rx_mac_hbank), .rx_mac_buf_status(rx_mac_buf_status),
+	.rx_mac_accept(rx_mac_accept),
+	.rx_mac_status_d(rx_mac_status_d), .rx_mac_status_s(rx_mac_status_s),
+	.scanner_debug(scanner_debug),
+	.ibadge_stb(ibadge_stb), .ibadge_data(ibadge_data),
+	.obadge_stb(obadge_stb), .obadge_data(obadge_data),
+	.xdomain_fault(xdomain_fault),
+	.rx_mon(rx_mon), .tx_mon(tx_mon), .in_use(in_use)
+);
+
+wire clk = tx_clk;
+wire [7:0] odata_p7, odata_p6, odata_p5, odata_p4, odata_p3, odata_p2, odata_p1;
+assign mux_data_in = {odata_p7, odata_p6, odata_p5, odata_p4, odata_p3, odata_p2, odata_p1};
+assign tx_er = 1'b0;
+
+`BLOB_INSTANCES
+
+endmodule

BerkeleyLab_Bedrock/badger/scanner.v

@@ -0,0 +1,526 @@
+// scans input packet
+
+// status_vec key:
+// assign status_vec = {port_p, pass_ip, pass_ethmac, crc_zero, category};
+//  bit 0-1  category: 3=UDP, 2=ICMP, 1=ARP, 0=other
+//  bit 2  CRC32 passed
+//  bit 3  Destination MAC matched our configuration
+//  bit 4  valid IP packet of some kind
+//  bit 5-7  UDP virtual port number, output of CAM
+
+// I haven't yet started trying to handle authentication here.
+// That can wait; we have the architecture ready.
+
+// This is a relatively long file, but it helps that it is broken down
+// into smaller modules:
+//   scanner   top level, see doc/rtefi.eps
+//    - arp_patt
+//    - ip_patt
+//    - icmp_patt
+//    - udp_patt
+// The four submodules have relatively consistent ports and semantics.
+
+module scanner (
+	input clk,  // timespec 6.8 ns
+	input [7:0] eth_in,
+	input eth_in_s,
+	input eth_in_e,  // error flag from PHY
+	// PSPEPS didn't do anything with eth_in_e, which is certainly
+	// a mistake, but did work in practice.  Ditto for this version,
+	// and it's proven to be very robust.  Presumably the 32-bit CRC
+	// makes the RX_ER bit effectively redundant?
+	//
+	// New port: async input to allow packet reception
+	// Lets someone turn off the Ethernet subsystem during maintenance,
+	// e.g., changing IP address.
+	input enable_rx,
+	// port to MAC/IP config, single-cycle latency
+	output [3:0] ip_a,
+	input [7:0] ip_d,
+	// port to UDP port number config memory, single-cycle latency
+	output [3:0] pno_a,
+	input [7:0] pno_d,
+	// Access to a single-cycle-latency RAM holding keys and masks,
+	// necessarily also in the Rx clock domain.
+	// output [9:0] key_addr,
+	// input [15:0] key_data,
+	//
+	// Two-bit summary info available to precog
+	// For a kept packet, busy has the full width of odata_s,
+	// but is delayed one cycle.  Non-keep packets can have the busy
+	// line de-asserted as soon as the dropping condition is detected.
+	// When an incoming packet is categorized as causing a response,
+	// the keep line is asserted one cycle before busy falls.
+	// Also see doc/precog_upg.eps
+	output busy,
+	output keep,
+	output [3:0] debug,
+	//
+	// Simple flow of data to the next processing stage (pbuf_writer).
+	// somewhat conforms to AXI-stream-lite, if I adjust the names?
+	output [7:0] odata,
+	output odata_s,
+	output odata_f,
+	output status_valid,
+	output [7:0] status_vec,
+	output [10:0] pack_len
+);
+// Configuration
+parameter handle_arp = 1;
+parameter handle_icmp = 1;
+
+// We need enable_rx in our own clk domain
+wire enable_rx_r;
+reg_tech_cdc enable_rx_cdc(.I(enable_rx), .C(clk), .O(enable_rx_r));
+
+// Ethernet frame state machine, primarily based on eth_strobe from PHY
+wire [7:0] eth_octet = eth_in;
+wire eth_strobe = eth_in_s;
+// exactly four states, one-hot encoded
+reg h_idle=1, h_preamble=0, h_data=0, h_drop=0;
+// The exact start of frame (transition from h_preamble to h_data)
+// is controlled by a traditional Ethernet synchronization preamble and SFD.
+// That old-school bit-pattern of 10101010 10101010 10101011
+// looks like 55 55 d5 when read over the 8-bit GMII port.  See
+// https://en.wikipedia.org/wiki/Ethernet_frame#Preamble_and_start_frame_delimiter
+wire drop_packet;
+reg [3:0] ifg_count=0;  // Inter-frame gap counter
+wire ifg_inc = ~(&ifg_count[3:2]);  // saturate at 12
+wire ifg_ok = ifg_count >= 10;  // slightly relaxed from spec of 12,
+// this configuration guarantees 11 non-data cycles between frames
+always @(posedge clk) begin
+	if (h_idle | h_preamble) ifg_count <= ifg_count + ifg_inc;
+	else ifg_count <= 0;
+	if (h_idle & eth_strobe) begin
+		h_idle <= 0;
+		if (eth_octet==8'h55 && enable_rx_r) h_preamble <= 1;
+		else h_drop <= 1;
+	end
+	if (h_preamble) begin
+		if (eth_strobe & (eth_octet==8'hd5)) begin
+			h_preamble <= 0;
+			if (ifg_ok) h_data <= 1;
+			else h_drop <= 1;  // IFG too small.
+		end else if (eth_strobe & (eth_octet!=8'h55)) begin
+			h_preamble <= 0; h_drop <= 1;
+		end else if (~eth_strobe) begin
+			h_preamble <= 0; h_idle <= 1;
+		end
+	end
+	if (h_data) begin
+		if (~eth_strobe) begin
+			h_data <= 0; h_idle <= 1;
+		end else if (drop_packet) begin   // poorly tested
+			h_data <= 0; h_drop <= 1;
+		end
+	end
+	if (h_drop & ~eth_strobe) begin
+		h_drop <= 0; h_idle <= 1;
+	end
+end
+
+// Debug helper
+reg [1:0] debug1_r=0;
+always @(posedge clk) begin
+	if (h_idle) debug1_r <= 0;
+	if (h_preamble) debug1_r <= 1;
+	if (h_data) debug1_r <= 3;
+	if (h_drop) debug1_r <= 2;
+end
+
+// Synchronization and pipelining step
+// Squelch data that isn't being considered
+reg h_data_d1=0, h_data_d2=0, data_first=0;
+reg [7:0] data_d1=0, data_d2=0;
+always @(posedge clk) begin
+	h_data_d1 <= h_data;
+	h_data_d2 <= h_data & h_data_d1;  // XXX horrible hack
+	// Why does h_data last one octet past last Ethernet octet in data?
+	data_first <= h_data & ~h_data_d1;
+	data_d1 <= eth_strobe ? eth_octet : 8'b0;
+	data_d2 <= data_d1;
+end
+
+// Unified handling of MAC/IP addresses via external config memory
+//
+// Ethernet
+// Dest    MAC:  octets 0-5    match me (might be FF for broadcast)
+// Source  MAC:  octets 6-11
+//
+// ARP (RFC 826)
+// Sender  MAC:  octets 22-27
+// Sender   IP:  octets 28-31
+// Placeholder:  octets 32-37
+// Dest     IP:  octets 38-41  match me
+//
+// IP (RFC 791)
+// Source   IP:  octets 26-29
+// Dest     IP:  octets 30-33  match me
+//
+// ICMP (RFC 792)
+// UDP (RFC 768)
+//
+reg [10:0] pack_cnt=0;
+always @(posedge clk) begin
+	pack_cnt <= h_data ? pack_cnt+1 : 0;
+end
+assign drop_packet = pack_cnt >= 1536;
+assign ip_a = pack_cnt > 36 || pack_cnt < 16 ? pack_cnt[3:0] : pack_cnt[3:0]+8;
+wire ip_m = ip_d == data_d1;
+// This pack_cnt decoding is synthesizable as is; we can make it more gate-
+// efficient later, using synthesis measurements and good regression tests.
+reg want_c_eth=0, want_c_arp=0, want_c_ip=0;
+always @(posedge clk) begin
+	want_c_eth <= pack_cnt < 6;
+	want_c_arp <= pack_cnt >= 38 && pack_cnt < 42;
+	want_c_ip  <= pack_cnt >= 30 && pack_cnt < 34;
+end
+// Accumulate state
+wire pz = pack_cnt == 0;
+reg pass_ethmac=0;  always @(posedge clk) begin if (want_c_eth & ~ip_m) pass_ethmac <= 0; if (pz) pass_ethmac <= 1; end
+reg pass_arpip=0;   always @(posedge clk) begin if (want_c_arp & ~ip_m) pass_arpip  <= 0; if (pz) pass_arpip  <= 1; end
+reg pass_ipdst=0;   always @(posedge clk) begin if (want_c_ip  & ~ip_m) pass_ipdst  <= 0; if (pz) pass_ipdst  <= 1; end
+
+// Specific protocols; IP is a component of both ICMP and UDP
+wire [15:0] ip_length, udp_length;
+
+// ARP handling is optional, chosen by the handle_arp parameter.
+wire pass_arp0;
+generate if (handle_arp) begin : find_arp
+	arp_patt arp_p (.clk(clk), .cnt(pack_cnt), .data(data_d1), .pass(pass_arp0));
+end else begin : no_find_arp
+	assign pass_arp0 = 0;
+end endgenerate
+
+// ICMP handling is optional, chosen by the handle_icmp parameter.
+wire pass_icmp0;
+generate if (handle_icmp) begin : find_icmp
+	icmp_patt icmp_p(.clk(clk), .cnt(pack_cnt), .data(data_d1), .pass(pass_icmp0));
+end else begin : no_find_icmp
+	assign pass_icmp0 = 0;
+end endgenerate
+
+// IP, UDP, and checksum handling are given, but see note below about UDP checksums.
+wire pass_ip0;   ip_patt   ip_p  (.clk(clk), .cnt(pack_cnt), .data(data_d1), .pass(pass_ip0), .length(ip_length));
+wire pass_udp0;  udp_patt  udp_p (.clk(clk), .cnt(pack_cnt), .data(data_d1), .pass(pass_udp0), .length(udp_length));
+wire pass_sum;   cksum_chk chk_p (.clk(clk), .cnt(pack_cnt), .data(data_d1), .pass(pass_sum), .length(ip_length));
+
+// CRC32
+wire crc_zero;
+crc8e_guts crc8e(.clk(clk), .gate(h_data_d1), .first(data_first),
+	.d_in(data_d1), .zero(crc_zero));
+wire final_octet = h_data_d1 & ~h_data;
+
+// UDP port number
+reg udp_port_stb=0;
+always @(posedge clk) udp_port_stb <= pack_cnt == 36;
+wire [2:0] port_p0;  wire port_h, port_v;
+udp_port_cam #(.naw(3)) cam(.clk(clk),
+	.port_s(udp_port_stb), .data(data_d1),
+	.pno_a(pno_a), .pno_d(pno_d),
+	.port_p(port_p0), .port_h(port_h), .port_v(port_v)
+);
+
+// Packet length (doesn't count GMII preamble)
+reg [10:0] pack_len_r=0;
+always @(posedge clk) if (h_data) pack_len_r <= pack_cnt;
+
+// Weird place for this
+reg ip_len_check=0, udp_len_check=0;
+always @(posedge clk) if (h_data) begin
+	ip_len_check <= pack_cnt >= ip_length + 18; // 18 = 14 Ethernet header + 4 CRC
+	udp_len_check <= ip_length >= udp_length + 20; // 20 = IP header length
+end
+
+// One more oddball
+reg unicast_src_mac=0;
+always @(posedge clk) begin
+	if (pack_cnt==1) unicast_src_mac <= 1;  // optimistic, needed to make busy flag work
+	if (pack_cnt==7) unicast_src_mac <= ~data_d1[0];
+end
+
+// Summary bits (mostly) don't leak irrelevant state
+wire pass_arp  = unicast_src_mac & crc_zero & pass_arp0 & pass_arpip;
+wire pass_ip   = unicast_src_mac & crc_zero & pass_ethmac & pass_ip0 & pass_ipdst & ip_len_check;
+wire pass_icmp = pass_ip & pass_icmp0 & pass_sum;
+wire pass_udp  = pass_ip & pass_udp0 & udp_len_check & port_h;
+wire [1:0] category = pass_udp ? 3 : pass_icmp ? 2 : pass_arp ? 1 : 0;
+wire [2:0] port_p = pass_udp ? port_p0 : 3'd0;
+
+// Summary output
+assign status_vec = {port_p, pass_ip, pass_ethmac, crc_zero, category};
+assign status_valid = final_octet;
+assign pack_len = pack_len_r;
+
+// Other summary output
+wire busy_with_arp = unicast_src_mac & pass_arp0;
+wire busy_with_udp = unicast_src_mac & pass_ethmac & pass_ip0 & pass_udp0;
+wire busy_with_icmp = unicast_src_mac & pass_ethmac & pass_ip0 & pass_icmp0;
+reg busy_r=0, keep_r=0;
+always @(posedge clk) begin
+	busy_r <= odata_s & (busy_with_arp | busy_with_udp | busy_with_icmp);
+	keep_r <= odata_s & (category != 0);
+end
+assign busy = busy_r;
+assign keep = keep_r;
+
+// Debug helper
+reg [1:0] debug2_r=0;
+always @(posedge clk) begin
+	if (status_valid) debug2_r <= category;
+end
+assign debug = {debug2_r, debug1_r};
+
+// Output ports
+assign odata = data_d2;
+assign odata_s = h_data_d2;
+assign odata_f = final_octet;
+
+endmodule
+
+// New modules to get new name spaces
+
+// =====
+// UDP/ICMP Checksum checker
+// Calculation structure for UDP and ICMP is about the same, so it
+// superficially looks like we just need a little stream selection logic
+// based on the protocol, and then a single one's-complement accumulator
+// could handle both cases.
+// This rosy scenario is stymied by UDP's pathological inclusion of
+// _two_ copies of the UDP length.  At the moment, therefore, this
+// module doesn't handle UDP.
+module cksum_chk(
+	input clk,
+	input [10:0] cnt,
+	input [7:0] data,
+	input [15:0] length,  // IP length
+	output pass
+);
+
+wire chksum_zero = cnt == 22;  // or earlier
+wire icmp_gate = cnt >= 35;
+// wire udp_gate = cnt >= 23;
+wire chksum_gate = icmp_gate;
+
+// Make sure length is known before using it
+wire end_of_ip = cnt>32 && cnt == (length+14);
+
+// Standard one's-complement checksum
+wire ones;
+ones_chksum ck(.clk(clk), .clear(chksum_zero), .gate(chksum_gate),
+	.din(data), .all_ones(ones));
+
+// Final state, should find FF FF at end of IP packet
+reg eof=0, state=0;
+always @(posedge clk) begin
+	if (chksum_zero) state <= 0;
+	if (end_of_ip) state <= ones;
+	eof <= end_of_ip;
+	if (eof) state <= state & ones;
+end
+assign pass = state;
+
+endmodule // UDP/ICMP Checksum checker
+
+// =====
+// ARP pattern checker
+module arp_patt(
+	input clk,
+	input [10:0] cnt,
+	input [7:0] data,
+	output pass
+);
+
+reg [7:0] template=0;
+always @(posedge clk) case(cnt[3:0])
+	// template starts at 12th byte of Ethernet packet,
+	// after the two MAC addresses.
+	4'd12: template <= 8'h08;
+	4'd13: template <= 8'h06;
+	4'd14: template <= 8'h00;   // ARP Ethernet hardware, octet 1
+	4'd15: template <= 8'h01;   // ARP Ethernet hardware, octet 2
+	4'd00: template <= 8'h08;   // ARP Protocol IP
+	4'd01: template <= 8'h00;   // ARP Protocol IP
+	4'd02: template <= 8'h06;   // ARP protocol address length
+	4'd03: template <= 8'h04;   // ARP protocol address length
+	4'd04: template <= 8'h00;   // ARP protocol operation
+	4'd05: template <= 8'h01;   // ARP protocol operation (request)
+	default: template <= 8'h00;
+endcase
+
+reg want=0, pass_r=0;
+wire match = data == template;
+always @(posedge clk) begin
+	want <= cnt >= 12 && cnt < 22;
+	if (cnt == 0) pass_r <= 1;
+	if (want & ~match) pass_r <= 0;
+end
+assign pass = pass_r;
+
+endmodule  // ARP pattern checker
+
+// =====
+// IP pattern checker
+module ip_patt(
+	input clk,
+	input [10:0] cnt,
+	input [7:0] data,
+	output pass,
+	output [15:0] length
+);
+
+reg [7:0] template=0;
+always @(posedge clk) case(cnt[4:0])
+	// template starts at 12th byte of Ethernet packet,
+	// after the two MAC addresses.
+	5'd12: template <= 8'h08;  // Bytes 12 and 13 are Ethertype IPv4
+	5'd13: template <= 8'h00;  // https://en.wikipedia.org/wiki/Ethertype
+
+	// Start of IPv4 header [https://en.wikipedia.org/wiki/IPv4#Header]
+	5'd14: template <= 8'h45;  // Vers (4 for ipv4) / IHL (> 5 is a weird case)
+	// 15  ignore  TOS (later changed to DSCP and ECN)
+	// 16  ignore  length msb
+	// 17  ignore  length lsb
+	// 18  ignore  identification msb
+	// 19  ignore  identification lsb
+	5'd20: template <= 8'h00;  // Flags/Fragment
+	5'd21: template <= 8'h00;
+	// 22  ignore  TTL (but see below)
+	// 23  ignore  Protocol
+	// 24-33  header checksum, source address, destination address
+	default: template <= 8'h00;
+endcase
+
+// Packet has expired when TTL hits zero
+reg ttl_flag=0;
+wire zero_ttl = ttl_flag & ~(|data);
+
+reg want=0, mask_df_bit=0, pass_r=0;
+wire [7:0] df_mask = {1'b1, ~mask_df_bit, 6'h3f};
+wire match = (data&df_mask) == template;
+always @(posedge clk) begin
+	want <= cnt >= 12 && cnt < 15 || cnt >= 20 && cnt < 22;
+	mask_df_bit <= cnt == 20;
+	ttl_flag <= cnt == 22;
+	if (cnt == 0) pass_r <= 1;
+	if (want & ~match) pass_r <= 0;
+	if (zero_ttl) pass_r <= 0;
+end
+
+// IP packet total length
+// Quoting RFC 791, Total Length is the length of the datagram,
+// measured in octets, including internet header and data.
+reg [7:0] data_d=0;
+reg [15:0] length_r=0;
+always @(posedge clk) begin
+	data_d <= data;
+	if (cnt==18) length_r <= {data_d, data};
+end
+assign length = length_r;
+
+// IP header checksum
+reg out_chksum_gate=0, out_chksum_zero=0;
+always @(posedge clk) begin
+	out_chksum_gate <= cnt >= 14 && cnt < 34;
+	out_chksum_zero <= cnt == 0;
+end
+wire chksum_all_ones;
+ones_chksum ck(.clk(clk), .clear(out_chksum_zero), .gate(out_chksum_gate),
+	.din(data), .all_ones(chksum_all_ones));
+reg chksum_all_ones_d=0;
+reg chksum_fail=0;
+always @(posedge clk) begin
+	chksum_all_ones_d <= chksum_all_ones;
+	if (cnt==0) chksum_fail <= 0;
+	if (cnt==35) chksum_fail <= ~chksum_all_ones | ~chksum_all_ones_d;
+end
+assign pass = pass_r & ~chksum_fail;
+
+endmodule  // IP header
+
+// =====
+// ICMP pattern checker
+// For ICMP checksum see module cksum_chk
+module icmp_patt(
+	input clk,
+	input [10:0] cnt,
+	input [7:0] data,
+	output pass
+);
+
+reg [7:0] template=0;
+always @(posedge clk) case(cnt[2:0])
+	// Ethernet/IP header is not in our scope
+	// template starts at 23rd byte of Ethernet packet,
+	// after the two MAC addresses.
+	3'd7: template <= 8'h01;  // cnt==23, Proto (ICMP)
+	3'd2: template <= 8'h08;  // cnt==34, ICMP echo request
+	3'd3: template <= 8'h00;  // cnt==35, ICMP code
+	default: template <= 8'h00;
+endcase
+
+reg want=0, pass_r=0;
+wire match = data == template;
+always @(posedge clk) begin
+	want <= cnt == 23 || cnt==34 || cnt==35;
+	if (cnt == 0) pass_r <= 1;
+	if (want & ~match) pass_r <= 0;
+end
+assign pass = pass_r;
+
+endmodule  // ICMP pattern checker
+
+// =====
+// UDP pattern checker
+module udp_patt(
+	input clk,
+	input [10:0] cnt,
+	input [7:0] data,
+	output pass,
+	output [15:0] length
+);
+
+// Degenerate form of template ROM
+// Moving this template and comparison to ip_patt would save 2 LUTs.
+wire [7:0] template = 8'h11;  // cnt==23, Proto (UDP)
+
+// Reject packets from source port number < 1024,
+// as they come from "trusted" sources.
+// This is part of the strategy to resist echo loops.
+wire reject_low = cnt==35 & ~|data[7:2];
+
+// Reject packets to destination port number 0
+reg pzero_d=0, pzero_d1=0, pzero_t=0;
+always @(posedge clk) begin
+	pzero_d <= data == 8'h00;
+	pzero_d1 <= pzero_d;
+	pzero_t <= cnt == 36;
+end
+wire discard_port0 = pzero_t & pzero_d & pzero_d1;
+
+reg want=0, pass_r=0;
+wire match = data == template;
+always @(posedge clk) begin
+	want <= cnt == 23;
+	if (cnt == 0) pass_r <= 1;
+	if (want & ~match) pass_r <= 0;
+	if (reject_low) pass_r <= 0;
+	if (discard_port0) pass_r <= 0;
+end
+assign pass = pass_r;
+
+// UDP packet length
+// Length is the length in octets of this user datagram including [UDP]
+// header and the data.
+reg [7:0] data_d=0;
+reg [15:0] length_r=0;
+always @(posedge clk) begin
+	data_d <= data;
+	if (cnt==40) length_r <= {data_d, data};
+end
+assign length = length_r;
+
+// XXX We don't yet compute the UDP checksum.
+// That may not be a practical problem.
+
+endmodule  // UDP pattern checker

BerkeleyLab_Bedrock/badger/speed_test.v

@@ -0,0 +1,32 @@
+// Speed test client
+// A lot like a UDP echo, but more satisfying because it actually
+// changes the data that flows through it.
+// Compatible with ethernet-core/core/client_thru.v
+// and ethernet-core/runtime/udprtx.c
+module speed_test(
+	input clk,
+	input nomangle,  // software settable
+	// client interface with RTEFI, see doc/clients.eps
+	input [10:0] len_c,
+	input [7:0] idata,
+	input raw_l,
+	input raw_s,
+	output [7:0] odata
+);
+
+parameter n_lat=2;  // minimum value is 1
+
+// len_c counts down to 9, but we need something that counts up from 0
+reg [7:0] count=0;
+reg [7:0] processed=0;
+always @(posedge clk) begin
+	count <= raw_s ? count+1 : 0;
+	processed <= idata ^ (count & {8{~nomangle}});
+end
+
+// 13 bits input, 8 bits output, choose to pipeline output
+reg_delay #(.len(n_lat-1), .dw(8)) align(.clk(clk), .gate(1'b1), .reset(1'b0),
+	.din(processed), .dout(odata));
+
+
+endmodule

BerkeleyLab_Bedrock/badger/spi_flash.v

@@ -0,0 +1,136 @@
+// Mechanism to reprogram boot flash
+module spi_flash(
+	input clk,
+	// client interface with RTEFI, see doc/clients.eps
+	input [10:0] len_c,
+	input [7:0] idata,
+	input raw_l,
+	input raw_s,
+	output [7:0] odata,
+	// 4-wire to e.g., Winbond W25X16
+	output spi_clk,
+	output spi_cs,
+	output spi_mosi,
+	input spi_miso,
+	output busy   // only intended for simulation
+);
+
+parameter n_lat = 8;  // latency of client pipeline
+
+// Try really hard to be non-fancy here, just the obvious way of
+// gatewaying the previously functioning spi_flash_engine into
+// the RTEFI scheme.
+
+// Longer term it would be nice if this could be re-written to
+// allow more resource sharing, say between Rx and Tx buffers,
+// and code sharing with other buffered clients, like the SPI
+// slave gateway to a microcontroller, as was done in PSPEPS.
+
+// This module cries out to be a customer of an authentication
+// mechanism, whenever that becomes available.
+
+parameter aw=9;  // nominal/minimal 512 x 8
+reg [7:0] rx_mem[0:(1<<aw)-1];
+reg [7:0] tx_mem[0:(1<<aw)-1];
+
+reg pack_read_ready=0;
+reg [8:0] rx_packet_len;
+wire pack_read_strobe;
+reg [7:0] pack_data_rx=0;
+
+wire pack_read_done;
+wire pack_write;
+wire pack_write_ack=pack_read_ready;
+wire pack_write_strobe;
+wire [7:0] pack_data_tx;
+
+spi_flash_engine engine(
+	.clk(clk),
+	.spi_clk(spi_clk),
+	.spi_cs(spi_cs),
+	.spi_mosi(spi_mosi),
+	.spi_miso(spi_miso),
+	//
+	.pack_read_ready(pack_read_ready),
+	.input_packet_len(rx_packet_len),
+	.pack_read_strobe(pack_read_strobe),
+	.pack_data_in(pack_data_rx),
+	.pack_read_done(pack_read_done),
+	//
+	.pack_write(pack_write),
+	.pack_write_ack(pack_write_ack),
+	.pack_write_strobe(pack_write_strobe),
+	.pack_data_out(pack_data_tx)
+);
+
+// Adapt the RTEFI control lines into what we need;
+// shared between Rx writer and Tx reader.
+reg [1:0] raw_sr=0;
+reg [aw-1:0] eth_point=0;
+always @(posedge clk) begin
+	raw_sr <= {raw_sr[0:0], raw_s};
+	eth_point <= raw_sr[1] ? eth_point+1 : 0;
+end
+
+// Logic for writing Rx memory
+// Note the decoding of the first byte as a packet-global op-code:
+//  0x52   write buffer
+// The write command will fail if the buffer is not empty, and that
+// failure  gets reported in the status message, below, right?
+reg rx_for_us=0, write_pack_flag=0;
+wire rx_mem_write = raw_s & raw_sr[1] & write_pack_flag;
+wire pre_write_pack_flag = rx_for_us & idata[0];
+always @(posedge clk) begin
+	if (raw_s & ~raw_sr[0]) rx_for_us <= (idata == 8'h52) && ~pack_read_ready;
+	if (raw_sr[0] & ~raw_sr[1]) write_pack_flag <= pre_write_pack_flag;
+	if (rx_mem_write) rx_mem[eth_point] <= idata;
+	if (raw_sr[0] & ~raw_s & write_pack_flag) pack_read_ready <= 1;
+	if (raw_sr[0] & ~raw_s & write_pack_flag) rx_packet_len <= eth_point;
+	if (pack_read_done) pack_read_ready <= 0;
+end
+
+// Logic for reading Rx memory
+reg [aw-1:0] rx_rpoint=0;
+always @(posedge clk) begin
+	if (pack_read_done) rx_rpoint <= 0;
+	if (pack_read_strobe & pack_read_ready) rx_rpoint <= rx_rpoint+1;
+	pack_data_rx <= rx_mem[rx_rpoint];
+end
+
+// Logic for writing Tx memory
+reg [aw-1:0] tx_wpoint=0;
+always @(posedge clk) begin
+	if (pack_write_strobe) begin
+		tx_mem[tx_wpoint] <= pack_data_tx;
+		tx_wpoint <= tx_wpoint+1;
+	end
+	if (~pack_write) tx_wpoint <= 0;
+end
+
+// Logic for reading Tx memory
+// len_c counts down to 9, but we need something that counts up from 0
+wire [7:0] tx_status = {pre_write_pack_flag, ~pack_read_ready};
+reg [7:0] tx_rdata=0, odata1=0;
+always @(posedge clk) begin
+	tx_rdata <= tx_mem[eth_point];
+	odata1 <= raw_sr[1] ? tx_rdata : raw_sr[0] ? tx_status : 8'h51;
+end
+
+// Internal-only for viewing in simulation
+reg [7:0] status_report;
+wire status_capture_tick = ~raw_sr[1] & raw_sr[0];
+always @(posedge clk) if (status_capture_tick) status_report <= tx_status;
+
+// output packet:
+//   message type
+//   status byte
+//   buffer memory
+// how about buffer length, i.e., tx_wpoint before it got erased?
+
+// choose to pipeline output
+reg_delay #(.len(n_lat-1), .dw(8)) align(.clk(clk), .gate(1'b1), .reset(1'b0),
+	.din(odata1), .dout(odata));
+
+assign busy = pack_read_ready;
+
+endmodule

BerkeleyLab_Bedrock/badger/spi_flash_engine.v

@@ -0,0 +1,146 @@
+module spi_flash_engine(
+	input clk,
+	// 4-wire to e.g., Winbond W25X16
+	output spi_clk,
+	output spi_cs,
+	output spi_mosi,
+	input spi_miso,
+	// port to read packet memory
+	input pack_read_ready,
+	input [8:0] input_packet_len,
+	output pack_read_strobe,
+	input [7:0] pack_data_in,
+	output pack_read_done,   // marks memory as empty
+	// port to write packet memory
+	output pack_write,   // high for whole transaction
+	input pack_write_ack,  // see below
+	output pack_write_strobe,  // single-cycle for each data byte
+	output [7:0] pack_data_out
+);
+
+parameter xc6slx = 0;  // Include gateway to an ICAP_SPARTAN6
+parameter seven = 0;  // Include gateway to an ICAPE2 on Xilinx 7-series
+
+// packet write, and indeed the whole engine, will stall until
+// pack_write_ack is received.  The ack will often happen immediately,
+// but can be substantially delayed if the output packet buffer is busy
+// handling a microcontroller output packet.
+
+// spi_clk is rated to 50 MHz, but we have no real reason to push this.
+// Most of the clock time will be spent after the write or erase SPI
+// transactions, waiting for the busy flag to go away.
+// Use 32 ns high / 32 ns low, 15.6 MBit/s.
+
+// Abstract spi_mosi is valid 4 cycles before and 4 cycles after the rising
+// edge of spi_clk.  The real W25Xxx requires the real data pin valid 2ns
+// before and 5ns after the rising edge of the real clock pin.
+
+// The real X25Xxx specifies its data is output 0ns to 7ns after the falling
+// edge of its clock.  This module samples spi_miso on the rising edge
+// of spi_clk.
+
+// Encode length byte as
+//   256 4 2 1
+// Allows likely lengths 1, 2, 4, 6, 260, and 261.
+// Leaves additional control bits to possibly encode a special
+// "read status register repeatedly until done" mode.
+
+reg running=0;
+reg [8:0] block_len=0;
+reg [8:0] bytes_remaining=0;
+reg word=0;
+reg icap_en=0;
+reg word2=0, word3=0, word4=0;
+always @(posedge clk) begin
+	if (pack_write_ack & word & ~running) begin
+		running<=1;
+		bytes_remaining<=input_packet_len;
+	end else begin
+		if (~pack_read_ready | (bytes_remaining==0)) running<=0;
+	end
+	if (running & word2) begin
+		block_len <= (|block_len) ? (block_len-1) : {pack_data_in[3],5'b0,pack_data_in[2:0]};
+		if (~(|block_len)) icap_en <= pack_data_in[7];
+		bytes_remaining <= bytes_remaining-1;
+	end
+	if (running & word3 & ~(|block_len)) icap_en <= 0;
+	if (!running) icap_en <= 0;
+end
+
+reg [6:0] subtick=0;
+reg [7:0] sr=0;
+reg tick=0, tick2=0, tick3=0, tick4=0;
+reg spi_clk_r=0, spi_clk_rr=0, spi_miso_r=0, spi_cs_pre=0, spi_cs_r=0, in_bit=0;
+wire [7:0] sr_next = {sr[6:0], in_bit};
+always @(posedge clk) begin
+	subtick <= subtick+1;
+	tick <= subtick[3:0]==13;
+	tick2 <= tick;
+	tick3 <= tick2;
+	tick4 <= tick3;
+	word <= subtick==125;
+	word2 <= word;
+	word3 <= word2;
+	word4 <= word3;
+	spi_clk_r <= subtick[3]&running&~icap_en&(|block_len);
+	spi_clk_rr <= spi_clk_r;
+	spi_miso_r <= spi_miso;  // IOB
+	if (subtick[3:0]==11) in_bit <= spi_cs_r ? spi_miso_r : 1'b0;
+	spi_cs_pre <= running&~icap_en&(|block_len)&(|bytes_remaining);
+	spi_cs_r <= spi_cs_pre;
+	if (tick4 & running) sr <= (word4&(|block_len)) ? pack_data_in : sr_next;
+end
+
+assign spi_clk=spi_clk_rr;
+assign spi_cs=~spi_cs_r;
+assign spi_mosi=sr[7]&spi_cs_r;
+
+// Optional support for ICAP_SPARTAN6
+// Keep the same basic timing engine as SPI.
+// Bit-reverse bytes per UG380 Table 2-5
+wire [7:0] pack_data_in_rev={
+	pack_data_in[0], pack_data_in[1], pack_data_in[2], pack_data_in[3],
+	pack_data_in[4], pack_data_in[5], pack_data_in[6], pack_data_in[7]};
+reg odd=0, icap_clk=0;
+// reg icap_we=0, icap_en2=0;  // when were these used?
+reg [7:0] icap_upper_data=0;
+always @(posedge clk) begin
+	// if (word2) icap_en2 <= icap_en;
+	// if (word3) icap_we <= icap_en2 & odd;
+	if (word3) icap_upper_data <= pack_data_in_rev;
+	if (word & icap_en) odd <= ~odd;
+	icap_clk <= subtick[6] & odd & ~word2;
+end
+wire [15:0] icap_wdata = {icap_upper_data,pack_data_in_rev};
+wire [15:0] icap_result;
+wire icap_busy;
+
+generate if (xc6slx == 1) begin : ICAP6
+    // 16-bit I port (for writing) and O port (for reading)
+    ICAP_SPARTAN6 intern(.CLK(icap_clk),
+	.CE(~icap_en), // icap_en is active high, CE "pin" is active low
+	.WRITE(1'b0), // funny name for a pin where "0" means write
+	.I(icap_wdata),
+	.O(icap_result), .BUSY(icap_busy));
+end else if (seven == 1) begin : ICAP7
+    // see UG953 and
+    // https://opencores.org/projects/wbicapetwo by Dan Gisselquist
+    wire [15:0] o_padding;  // half of the O port not used, since we configure width as X16
+    ICAPE2 #(.ICAP_WIDTH("X16")) reconfig(.CLK(icap_clk),
+	.CSIB(~icap_en), .RDWRB(1'b0),
+	.I(icap_wdata), .O({o_padding, icap_result}));
+    assign icap_busy=0;
+end else begin : no_ICAP
+    assign icap_result=0;
+    assign icap_busy=0;
+end endgenerate
+wire [7:0] icap_result_byte={7'b1010000,icap_busy};  // XXX useless for actually reading data
+
+assign pack_read_strobe=word2&running;
+assign pack_read_done=running&(bytes_remaining==0);
+
+assign pack_write=pack_read_ready;
+assign pack_write_strobe=word&running;
+assign pack_data_out = icap_en ? icap_result_byte : sr_next;
+
+endmodule

BerkeleyLab_Bedrock/badger/status.md

@@ -0,0 +1,69 @@
+# Packet Badger Status / Progress
+
+* 2018-11-02:  Input scanner (scanner.v) can properly detect
+  Ethernet, ARP, IP, ICMP, and UDP.  Makefile includes useful regression tests.
+* 2018-11-13:  Simulation constructs working ARP and ICMP echo
+  (ping) replies, verified with Linux tap interface.
+* 2018-11-15:  Simulation (Linux tap) also gives UDP echo.
+* 2018-11-18:  Hardware (SP605) responds to ARP and ICMP echo.
+* 2018-11-20:  ARP, ICMP echo, and UDP all work reliably with tap
+  using either Icarus or Verilator, and on SP605.
+* 2018-11-23:  Responds only to configured set of UDP ports
+* 2018-11-24:  Multiplexes between (trivial) UDP port sources
+* 2018-11-28:  Documented, tested, and used client interface
+* 2018-12-05:  Working mem_gateway, with regression test, confirmed on SP605
+* 2018-12-10:  Fixed dropped-packets problem, tested with > 10^8 packets
+* 2018-12-20:  Demonstrated functional on AC701/RGMII, synthesizing with XST
+* 2018-12-21:  Demonstrated functional on AC701 when synthesizing with Vivado
+* 2019-01-15:  Merged into bedrock
+* 2019-03-26:  Refactored udp-vpi.c to enable Verilator test of mem_gateway.v
+* 2019-04-29:  Demonstrated Tx MAC working on hardware
+* 2019-05-31:  MAC supporting TFTP works in simulation
+
+Synthesized by XST 14.7 for Spartan-6:
+
+| **module**         |**LUTs**|**RAMB16**|
+|:-------------------:|:-----:|:--------:|
+|  scanner.v          |  271  |     |
+|  construct.v        |  192  |     |
+|  xformer.v          |   93  |     |
+|  ethernet_crc_add.v |   94  |     |
+|  udp_port_cam_v     |   31  |     |
+|  rtefi_blob.v       | 1044  |  2  |
+|  gmii_hw_test.v     | 1582  | 6.5 |
+
+This Verilog code is intentionally portable and standards-based.
+It has been tested using:
+
+* verilator 3.900 through 5.032 (including 5.006 in stock Debian 12 bookworm)
+* iverilog 10.1 through 12.0 (including 11.0 in stock Debian 12 bookworm)
+* yosys 0.23 through 0.52 (including 0.23 in stock Debian 12 bookworm)
+* Xilinx XST 14.7
+* Xilinx Vivado 2015.3, 2017.4, 2018.1, 2020.2
+
+All the .eps files here are created with and editable by xcircuit.
+
+Files in tests/sp605/, tests/ac701/, and tests/kc705/ are only here temporarily;
+eventually they should be constructed by the LBNL/ATG project infrastructure.
+
+Next steps, pretty much unordered:
+
+* Rename modules, signals, and project
+* Create an instantiation template along with rtefi_blob.v
+* Update documentation
+* Analyze, test, and document limits on p_offset
+* Better force or test that all GMII signals are latched in IOBs
+* Do something with GMII_RX_ER, test
+* Decrement TTL as part of echo loop mitigation strategy?
+* Consider dropping UDP packets with zero data length
+* UDP Rx checksum?
+* Add SPI clients
+* Find help to exercise this on an Altera board
+* Increase minimum number of 0x55 in Tx preamble
+* Hook to allow use of TAP device other than tap0
+* Add monitoring hooks, like packet, byte, and error counts
+* Add authentication option
+* Refactor and rewrite for clarity and reduced LUT count
+* Attach Tx and Rx MAC to a soft core
+* Add IEEE-1588 (PTP) feature to MAC
+* Make optional based on parameters: ARP and ICMP echo

BerkeleyLab_Bedrock/badger/test_tx_mac.v

@@ -0,0 +1,77 @@
+module test_tx_mac #(
+	parameter mac_aw=10,  // 16-bit words
+	parameter big_endian=0
+) (
+	input clk,
+	// There is an implied DPRAM _not_ included in this module.
+	// These ports access its read port, with assumed 1-cycle latency
+	// The packet length is stored as the first word of a buffer.
+	// Endian-ness is configurable.
+	output [mac_aw-1:0] host_addr,
+	input [15:0] host_d,
+	// Request from host to transmit a packet, already converted to
+	// (or at least usable in) our clk domain.
+	// OK to just latch buf_start_addr on one host clock cycle,
+	// and raise the start signal on the next.
+	// Also OK to construct buf_start_addr with a handful of
+	// static 0 at the lsb (representing granularity of buffer starts),
+	// could save a few registers in that clock domain crossing.
+	input start,
+	input [mac_aw-1:0] buf_start_addr,
+	output done,  // 4-phase handshake with start signal
+	// Connection to precog module
+	output req,
+	output [10:0] len_req,  // can represent 1 MTU, in octets
+	// Connection to output multiplexer (xformer.v)
+	input strobe,
+	output [7:0] mac_data
+);
+
+reg [mac_aw-1:0] buffer_point;  // in words
+reg [2:0] mode=0;
+reg [10:0] len_req_r=0;
+reg req_r=0, done_r=0;
+reg odd_octet=0;
+wire even_octet = ~odd_octet;
+// There's a total of two cycles latency from setting buffer_point
+// to being able to use the result of reading that DPRAM entry.
+always @(posedge clk) case (mode)
+	0: if (start) begin
+		mode <= 1;
+		buffer_point <= buf_start_addr;
+	end
+	1: begin
+		mode <= 2;
+		buffer_point <= buffer_point + 1;
+	end
+	2: begin
+		mode <= 3;
+		len_req_r <= host_d[10:0];
+		odd_octet <= 0;
+		req_r <= 1;
+	end
+	3: if (strobe) begin
+		odd_octet <= ~odd_octet;
+		buffer_point <= buffer_point + even_octet;
+		len_req_r <= len_req_r-1;
+		if (len_req_r == 1) begin
+			mode <= 4;
+			done_r <= 1;
+			req_r <= 0;
+		end
+	end
+	4: begin
+		if (~start) begin
+			mode <= 0;
+			done_r <= 0;
+		end
+	end
+endcase
+
+assign host_addr = buffer_point;
+assign len_req = len_req_r;
+assign mac_data = (odd_octet^big_endian) ? host_d[15:8] : host_d[7:0];
+assign done = done_r;
+assign req = req_r;
+
+endmodule

BerkeleyLab_Bedrock/badger/tests/ac701_rgmii_test.tcl

@@ -0,0 +1,6 @@
+source "badger.tcl"
+set build_id "ac701_rgmii_test"
+set chip_id "xc7a200t-fbg676-2"
+set top_module "rgmii_hw_test"
+set verilog_defines [list "CHIP_FAMILY_7SERIES" ]
+badger_build $build_id $chip_id $top_module $verilog_defines