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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
like
0
Dataset card
Files
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xet
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main
verilog_data-1
/
MiSTer-devel_Minimig-AGA_MiSTer
/
rtl
/
sim
132 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 7 with 10 repos
24bce15
verified
4 days ago
akiko
Add Batch 7 with 10 repos
4 days ago
cache
Add Batch 7 with 10 repos
4 days ago
cdtv
Add Batch 7 with 10 repos
4 days ago
chipset
Add Batch 7 with 10 repos
4 days ago
sdram
Add Batch 7 with 10 repos
4 days ago
