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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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0
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Files
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xet
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main
verilog_data-1
/
MiSTer-devel_Minimig-AGA_MiSTer
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 7 with 10 repos
24bce15
verified
3 days ago
doc
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3 days ago
extra
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3 days ago
rtl
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3 days ago
sys
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3 days ago
Minimig.sdc
5.85 kB
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3 days ago
Minimig.sv
35.6 kB
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3 days ago
README.md
10.4 kB
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3 days ago
gpl.txt
Safe
35.1 kB
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3 days ago
hps_ext.v
7.31 kB
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3 days ago
