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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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0
Dataset card
Files
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xet
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27be9c5
verilog_data-1
/
WangXuan95_FPGA-UART
/
SIM
16.7 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
c22be57
verified
7 days ago
tb_axis_inc_source.v
Safe
2.09 kB
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
7 days ago
tb_uart.v
Safe
6.41 kB
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
7 days ago
tb_uart2axi4.v
Safe
7.86 kB
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
7 days ago
tb_uart2axi4_run_iverilog.bat
158 Bytes
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
7 days ago
tb_uart_run_iverilog.bat
155 Bytes
Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
7 days ago
