Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
c22be57 verified | del sim.out dump.vcd | |
| iverilog -g2001 -o sim.out tb_uart.v tb_axis_inc_source.v ../RTL/uart_tx.v ../RTL/uart_rx.v | |
| vvp -n sim.out | |
| del sim.out | |
| pause |