Add Batch 4 with 10 repos

MIPSfpga_schoolMIPS/README.md

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+# schoolMIPS
+
+A small MIPS CPU core originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris). The first version of schoolMIPS was written for [Young Russian Chip Architects](http://www.silicon-russia.com/2017/06/09/arduino-and-fpga/) summer school.
+
+Next version of schoolMIPS is based on RISC-V architecture: [schoolRISCV](https://github.com/zhelnio/schoolRISCV)
+
+The CPU have several versions (from simple to complex). Each of them is placed in the separate git branch:
+- **00_simple** - the simplest CPU without data memory, programs compiled with GNU gcc;
+- **01_mmio** - the same but with data memory, simple system bus and peripherals (pwm, gpio, als);
+- **01_mmio_sv_dpi** - the same but with data memory, simple system bus and peripherals (pwm, gpio, als);   
+- **02_irq** - data memory, system timer, interrupts and exceptions (CP0 coprocessor);
+- **03_pipeline** - the pipelined version of the simplest core with data memory 
+- **04_pipeline_irq** - the pipelined version of 02_irq
+
+Examples of using this kernel as an element of a multiprocessor system:   
+1. A.E. Ryazanova, A.A. Amerikanov, E. V Lezhnev, Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS, J. Phys. Conf. Ser. 1163 (2019) 012026. [doi:10.1088/1742-6596/1163/1/012026](https://iopscience.iop.org/article/10.1088/1742-6596/1163/1/012026).
+2. [Innovate FPGA 2019 project: EM028 » NoC-based multiprocessing system prototype](http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=EM028)
+
+For docs and CPU diagrams please visit the project [wiki](https://github.com/MIPSfpga/schoolMIPS/wiki)
+
+![CPU diagram](../../wiki/img/schoolMIPS_diagram.gif) 

MIPSfpga_schoolMIPS/board/de0/de0_top.sdc

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+
+create_clock -period "50.0 MHz" [get_ports CLOCK_50]
+create_clock -period "50.0 MHz" [get_ports CLOCK_50_2]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDG[*]}]
+set_false_path -from * -to [get_ports {HEX0_D[*]}]
+set_false_path -from * -to [get_ports {HEX1_D[*]}]
+set_false_path -from * -to [get_ports {HEX2_D[*]}]
+set_false_path -from * -to [get_ports {HEX3_D[*]}]
+set_false_path -from * -to [get_ports {HEX0_DP}]
+set_false_path -from * -to [get_ports {HEX1_DP}]
+set_false_path -from * -to [get_ports {HEX2_DP}]
+set_false_path -from * -to [get_ports {HEX3_DP}]
+
+set_false_path -from [get_ports {BUTTON[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/de0/de0_top.v

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+
+module de0_top
+    (
+        input           CLOCK_50,       //    Clock 50 MHz
+        input           CLOCK_50_2,     //    Clock 50 MHz
+
+        input    [ 2:0] BUTTON,         //    Pushbutton[2:0]
+
+        input    [ 9:0] SW,             //    Toggle Switch[9:0]
+
+        output   [ 6:0] HEX0_D,         //    Seven Segment Digit 0
+        output          HEX0_DP,        //    Seven Segment Digit DP 0
+        output   [ 6:0] HEX1_D,         //    Seven Segment Digit 1
+        output          HEX1_DP,        //    Seven Segment Digit DP 1
+        output   [ 6:0] HEX2_D,         //    Seven Segment Digit 2
+        output          HEX2_DP,        //    Seven Segment Digit DP 2
+        output   [ 6:0] HEX3_D,         //    Seven Segment Digit 3
+        output          HEX3_DP,        //    Seven Segment Digit DP 3
+
+        output   [ 9:0] LEDG,           //    LED Green[9:0]
+
+        output          UART_TXD,       //    UART Transmitter
+        input           UART_RXD,       //    UART Receiver
+        output          UART_CTS,       //    UART Clear To Send
+        input           UART_RTS,       //    UART Request To Send
+
+        inout    [15:0] DRAM_DQ,        //    SDRAM Data bus 16 Bits
+        output   [12:0] DRAM_ADDR,      //    SDRAM Address bus 13 Bits
+        output          DRAM_LDQM,      //    SDRAM Low-byte Data Mask
+        output          DRAM_UDQM,      //    SDRAM High-byte Data Mask
+        output          DRAM_WE_N,      //    SDRAM Write Enable
+        output          DRAM_CAS_N,     //    SDRAM Column Address Strobe
+        output          DRAM_RAS_N,     //    SDRAM Row Address Strobe
+        output          DRAM_CS_N,      //    SDRAM Chip Select
+        output          DRAM_BA_0,      //    SDRAM Bank Address 0
+        output          DRAM_BA_1,      //    SDRAM Bank Address 1
+        output          DRAM_CLK,       //    SDRAM Clock
+        output          DRAM_CKE,       //    SDRAM Clock Enable
+
+        inout    [14:0] FL_DQ,          //    FLASH Data bus 15 Bits
+        inout           FL_DQ15_AM1,    //    FLASH Data bus Bit 15 or Address A-1
+        output   [21:0] FL_ADDR,        //    FLASH Address bus 22 Bits
+        output          FL_WE_N,        //    FLASH Write Enable
+        output          FL_RST_N,       //    FLASH Reset
+        output          FL_OE_N,        //    FLASH Output Enable
+        output          FL_CE_N,        //    FLASH Chip Enable
+        output          FL_WP_N,        //    FLASH Hardware Write Protect
+        output          FL_BYTE_N,      //    FLASH Selects 8/16-bit mode
+        input           FL_RY,          //    FLASH Ready/Busy
+
+        inout    [ 7:0] LCD_DATA,       //    LCD Data bus 8 bits
+        output          LCD_BLON,       //    LCD Back Light ON/OFF
+        output          LCD_RW,         //    LCD Read/Write Select, 0 = Write, 1 = Read
+        output          LCD_EN,         //    LCD Enable
+        output          LCD_RS,         //    LCD Command/Data Select, 0 = Command, 1 = Data
+
+        inout           SD_DAT0,        //    SD Card Data 0
+        inout           SD_DAT3,        //    SD Card Data 3
+        inout           SD_CMD,         //    SD Card Command Signal
+        output          SD_CLK,         //    SD Card Clock
+        input           SD_WP_N,        //    SD Card Write Protect
+
+        inout           PS2_KBDAT,      //    PS2 Keyboard Data
+        inout           PS2_KBCLK,      //    PS2 Keyboard Clock
+        inout           PS2_MSDAT,      //    PS2 Mouse Data
+        inout           PS2_MSCLK,      //    PS2 Mouse Clock
+
+        output          VGA_HS,         //    VGA H_SYNC
+        output          VGA_VS,         //    VGA V_SYNC
+        output   [3:0]  VGA_R,          //    VGA Red[3:0]
+        output   [3:0]  VGA_G,          //    VGA Green[3:0]
+        output   [3:0]  VGA_B,          //    VGA Blue[3:0]
+
+        input    [ 1:0] GPIO0_CLKIN,    //    GPIO Connection 0 Clock In Bus
+        output   [ 1:0] GPIO0_CLKOUT,   //    GPIO Connection 0 Clock Out Bus
+        inout    [31:0] GPIO0_D,        //    GPIO Connection 0 Data Bus
+        input    [ 1:0] GPIO1_CLKIN,    //    GPIO Connection 1 Clock In Bus
+        output   [ 1:0] GPIO1_CLKOUT,   //    GPIO Connection 1 Clock Out Bus
+        inout    [31:0] GPIO1_D         //    GPIO Connection 1 Data Bus
+    );
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLOCK_50;
+    wire          rst_n     =  BUTTON[0];
+    wire          clkEnable =  SW [9] | ~BUTTON[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDG[0]   = clk;
+    assign LEDG[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    assign HEX0_DP = 1'b1;
+    assign HEX0_DP = 1'b1;
+    assign HEX0_DP = 1'b1;
+    assign HEX0_DP = 1'b1;
+
+    sm_hex_display digit_3 ( h7segment [15:12] , HEX3_D [6:0] );
+    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2_D [6:0] );
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1_D [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0_D [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/de0_cv/de0_cv.sdc

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+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+create_clock -period 20 [get_ports CLOCK4_50]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDR[*]}]
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+set_false_path -from * -to [get_ports {HEX2[*]}]
+set_false_path -from * -to [get_ports {HEX3[*]}]
+set_false_path -from * -to [get_ports {HEX4[*]}]
+set_false_path -from * -to [get_ports {HEX5[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]
+set_false_path -from [get_ports {RESET_N}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/de0_cv/de0_cv.v

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+
+module de0_cv
+(
+    input           CLOCK2_50,
+    input           CLOCK3_50,
+    inout           CLOCK4_50,
+    input           CLOCK_50,
+                   
+    input           RESET_N,
+
+    input   [ 3:0]  KEY,
+    input   [ 9:0]  SW,
+
+    output  [ 9:0]  LEDR,
+
+    output  [ 6:0]  HEX0,
+    output  [ 6:0]  HEX1,
+    output  [ 6:0]  HEX2,
+    output  [ 6:0]  HEX3,
+    output  [ 6:0]  HEX4,
+    output  [ 6:0]  HEX5,
+                   
+    output  [12:0]  DRAM_ADDR,
+    output  [ 1:0]  DRAM_BA,
+    output          DRAM_CAS_N,
+    output          DRAM_CKE,
+    output          DRAM_CLK,
+    output          DRAM_CS_N,
+    inout   [15:0]  DRAM_DQ,
+    output          DRAM_LDQM,
+    output          DRAM_RAS_N,
+    output          DRAM_UDQM,
+    output          DRAM_WE_N,
+                   
+    output  [ 3:0]  VGA_B,
+    output  [ 3:0]  VGA_G,
+    output          VGA_HS,
+    output  [ 3:0]  VGA_R,
+    output          VGA_VS,
+
+    inout           PS2_CLK,
+    inout           PS2_CLK2,
+    inout           PS2_DAT,
+    inout           PS2_DAT2,
+                   
+    output          SD_CLK,
+    inout           SD_CMD,
+    inout   [ 3:0]  SD_DATA,
+                   
+    inout   [35:0]  GPIO_0,
+    inout   [35:0]  GPIO_1
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLOCK_50;
+    wire          rst_n     =  KEY[0] & RESET_N;
+    wire          clkEnable =  SW [9] | ~KEY[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDR[0]   = clk;
+    assign LEDR[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
+    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
+    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
+    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/de0_nano/README.md

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+# Terasic DE0-Nano (Altera Cyclone IV)
+
+Thanks to [@dbkudryavtsevEduHSE](https://github.com/dbkudryavtsevEduHSE) for this port.
+
+## Used pins
+
+Pin | Name | Description
+--- | ---- | -----------
+pin_r8 | FPGA_CLK1_50 | system clock
+pin_j15 | KEY0 | system reset
+pin_e1 | KEY1 | clock enable
+pin_a15, a13, b13, a11, s1, f3, b1, l3 | LED0-LED7 | system output
+pin_m1, t8, b9, m15|SW0-SW3|
+
+## Board photo
+
+![photo](/board/de0_nano/doc/photo.jpg)
+
+## Board pinout
+
+![pinout](/board/de0_nano/doc/pins.jpg)
+![pinout](/board/de0_nano/doc/pins_.jpg)

MIPSfpga_schoolMIPS/board/de0_nano/de0_nano.sdc

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+
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+
+# for enhancing USB BlasterII to be reliable, 25MHz
+create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
+
+derive_pll_clocks
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {FPGA_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]
+

MIPSfpga_schoolMIPS/board/de0_nano/de0_nano.v

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+
+module de0_nano
+(
+    input           FPGA_CLK1_50,
+    input   [ 1:0]  KEY,
+    output  [ 7:0]  LED,
+    input   [ 3:0]  SW
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  FPGA_CLK1_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  ~KEY[1];
+    wire [  3:0 ] clkDevide =  4'b1000;
+    wire [  4:0 ] regAddr   =  { 1'b0, SW [3:0] };
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[7:1] = regData[6:0];
+
+endmodule

MIPSfpga_schoolMIPS/board/de10_lite/de10_lite.sdc

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+
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {MAX10_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDR[*]}]
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+set_false_path -from * -to [get_ports {HEX2[*]}]
+set_false_path -from * -to [get_ports {HEX3[*]}]
+set_false_path -from * -to [get_ports {HEX4[*]}]
+set_false_path -from * -to [get_ports {HEX5[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/de10_lite/de10_lite.v

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+
+
+module de10_lite(
+
+    input               ADC_CLK_10,
+    input               MAX10_CLK1_50,
+    input               MAX10_CLK2_50,
+
+    output  [  7:0 ]    HEX0,
+    output  [  7:0 ]    HEX1,
+    output  [  7:0 ]    HEX2,
+    output  [  7:0 ]    HEX3,
+    output  [  7:0 ]    HEX4,
+    output  [  7:0 ]    HEX5,
+
+    input   [  1:0 ]    KEY,
+
+    output  [  9:0 ]    LEDR,
+
+    input   [  9:0 ]    SW,
+
+    inout   [ 35:0 ]    GPIO
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  MAX10_CLK1_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  SW [9] | ~KEY[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDR[0]   = clk;
+    assign LEDR[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    assign HEX0 [7] = 1'b1;
+    assign HEX1 [7] = 1'b1;
+    assign HEX2 [7] = 1'b1;
+    assign HEX3 [7] = 1'b1;
+    assign HEX4 [7] = 1'b1;
+    assign HEX5 [7] = 1'b1;
+
+    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
+    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
+    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
+    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/de10_nano/de10_nano.sdc

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+
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
+
+# for enhancing USB BlasterII to be reliable, 25MHz
+create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
+
+derive_pll_clocks
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {FPGA_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]
+

MIPSfpga_schoolMIPS/board/de10_nano/de10_nano.v

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+
+module de10_nano
+(
+    output          ADC_CONVST,
+    output          ADC_SCK,
+    output          ADC_SDI,
+    input           ADC_SDO,
+
+    inout   [15:0]  ARDUINO_IO,
+    inout           ARDUINO_RESET_N,
+
+    input           FPGA_CLK1_50,
+    input           FPGA_CLK2_50,
+    input           FPGA_CLK3_50,
+
+    inout           HDMI_I2C_SCL,
+    inout           HDMI_I2C_SDA,
+    inout           HDMI_I2S,
+    inout           HDMI_LRCLK,
+    inout           HDMI_MCLK,
+    inout           HDMI_SCLK,
+    output          HDMI_TX_CLK,
+    output          HDMI_TX_DE,
+    output  [23:0]  HDMI_TX_D,
+    output          HDMI_TX_HS,
+    input           HDMI_TX_INT,
+    output          HDMI_TX_VS,
+
+    input   [ 1:0]  KEY,
+    output  [ 7:0]  LED,
+    input   [ 3:0]  SW,
+
+    inout   [35:0]  GPIO_0,
+    inout   [35:0]  GPIO_1
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  FPGA_CLK1_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  ~KEY[1];
+    wire [  3:0 ] clkDevide =  4'b1000;
+    wire [  4:0 ] regAddr   =  { 1'b0, SW [3:0] };
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[7:1] = regData[6:0];
+
+endmodule

MIPSfpga_schoolMIPS/board/de10_standard/de10_standard.sdc

@@ -0,0 +1,27 @@
+
+create_clock -period "50.000000 MHz" [get_ports CLOCK2_50]
+create_clock -period "50.000000 MHz" [get_ports CLOCK3_50]
+create_clock -period "50.000000 MHz" [get_ports CLOCK4_50]
+create_clock -period "50.000000 MHz" [get_ports CLOCK_50]
+
+# for enhancing USB BlasterII to be reliable, 25MHz
+create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDR[*]}]
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+set_false_path -from * -to [get_ports {HEX2[*]}]
+set_false_path -from * -to [get_ports {HEX3[*]}]
+set_false_path -from * -to [get_ports {HEX4[*]}]
+set_false_path -from * -to [get_ports {HEX5[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]
+
+

MIPSfpga_schoolMIPS/board/de10_standard/de10_standard.v

@@ -0,0 +1,58 @@
+
+
+module de10_standard
+(
+    input                       CLOCK2_50,
+    input                       CLOCK3_50,
+    input                       CLOCK4_50,
+    input                       CLOCK_50,
+
+    input            [3:0]      KEY,
+
+    input            [9:0]      SW,
+
+    output           [9:0]      LEDR,
+
+    output           [6:0]      HEX0,
+    output           [6:0]      HEX1,
+    output           [6:0]      HEX2,
+    output           [6:0]      HEX3,
+    output           [6:0]      HEX4,
+    output           [6:0]      HEX5
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLOCK_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  SW [9] | ~KEY[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDR[0]   = clk;
+    assign LEDR[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
+    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
+    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
+    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/de1_soc/de1_soc.sdc

@@ -0,0 +1,16 @@
+
+create_clock -period "50.0 MHz" [get_ports CLOCK_50]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDR[*]}]
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+set_false_path -from * -to [get_ports {HEX2[*]}]
+set_false_path -from * -to [get_ports {HEX3[*]}]
+set_false_path -from * -to [get_ports {HEX4[*]}]
+set_false_path -from * -to [get_ports {HEX5[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/de1_soc/de1_soc.v

@@ -0,0 +1,226 @@
+
+//`define ENABLE_ADC
+//`define ENABLE_AUD
+//`define ENABLE_CLOCK2
+//`define ENABLE_CLOCK3
+//`define ENABLE_CLOCK4
+`define ENABLE_CLOCK
+//`define ENABLE_DRAM
+//`define ENABLE_FAN
+`define ENABLE_FPGA
+`define ENABLE_GPIO
+`define ENABLE_HEX
+//`define ENABLE_HPS
+//`define ENABLE_IRDA
+`define ENABLE_KEY
+`define ENABLE_LEDR
+//`define ENABLE_PS2
+//`define ENABLE_TD
+//`define ENABLE_VGA
+`define ENABLE_SW
+
+module de1_soc(
+
+      `ifdef ENABLE_ADC
+      output             ADC_CONVST,
+      output             ADC_DIN,
+      input              ADC_DOUT,
+      output             ADC_SCLK,
+      `endif
+
+      `ifdef ENABLE_AUD
+      input              AUD_ADCDAT,
+      inout              AUD_ADCLRCK,
+      inout              AUD_BCLK,
+      output             AUD_DACDAT,
+      inout              AUD_DACLRCK,
+      output             AUD_XCK,
+      `endif
+
+      `ifdef ENABLE_CLOCK2
+      input              CLOCK2_50,
+      `endif
+
+      `ifdef ENABLE_CLOCK3
+      input              CLOCK3_50,
+      `endif
+
+      `ifdef ENABLE_CLOCK4
+      input              CLOCK4_50,
+      `endif
+
+      `ifdef ENABLE_CLOCK
+      input              CLOCK_50,
+      `endif
+
+      `ifdef ENABLE_DRAM
+      output      [12:0] DRAM_ADDR,
+      output      [1:0]  DRAM_BA,
+      output             DRAM_CAS_N,
+      output             DRAM_CKE,
+      output             DRAM_CLK,
+      output             DRAM_CS_N,
+      inout       [15:0] DRAM_DQ,
+      output             DRAM_LDQM,
+      output             DRAM_RAS_N,
+      output             DRAM_UDQM,
+      output             DRAM_WE_N,
+      `endif
+
+      `ifdef ENABLE_FAN
+      output             FAN_CTRL,
+      `endif
+
+      `ifdef ENABLE_FPGA
+      output             FPGA_I2C_SCLK,
+      inout              FPGA_I2C_SDAT,
+      `endif
+
+      `ifdef ENABLE_GPIO
+      inout     [35:0]         GPIO_0,
+      inout     [35:0]         GPIO_1,
+      `endif
+
+      `ifdef ENABLE_HEX
+      output      [6:0]  HEX0,
+      output      [6:0]  HEX1,
+      output      [6:0]  HEX2,
+      output      [6:0]  HEX3,
+      output      [6:0]  HEX4,
+      output      [6:0]  HEX5,
+      `endif
+
+      `ifdef ENABLE_HPS
+      inout              HPS_CONV_USB_N,
+      output      [14:0] HPS_DDR3_ADDR,
+      output      [2:0]  HPS_DDR3_BA,
+      output             HPS_DDR3_CAS_N,
+      output             HPS_DDR3_CKE,
+      output             HPS_DDR3_CK_N,
+      output             HPS_DDR3_CK_P,
+      output             HPS_DDR3_CS_N,
+      output      [3:0]  HPS_DDR3_DM,
+      inout       [31:0] HPS_DDR3_DQ,
+      inout       [3:0]  HPS_DDR3_DQS_N,
+      inout       [3:0]  HPS_DDR3_DQS_P,
+      output             HPS_DDR3_ODT,
+      output             HPS_DDR3_RAS_N,
+      output             HPS_DDR3_RESET_N,
+      input              HPS_DDR3_RZQ,
+      output             HPS_DDR3_WE_N,
+      output             HPS_ENET_GTX_CLK,
+      inout              HPS_ENET_INT_N,
+      output             HPS_ENET_MDC,
+      inout              HPS_ENET_MDIO,
+      input              HPS_ENET_RX_CLK,
+      input       [3:0]  HPS_ENET_RX_DATA,
+      input              HPS_ENET_RX_DV,
+      output      [3:0]  HPS_ENET_TX_DATA,
+      output             HPS_ENET_TX_EN,
+      inout       [3:0]  HPS_FLASH_DATA,
+      output             HPS_FLASH_DCLK,
+      output             HPS_FLASH_NCSO,
+      inout              HPS_GSENSOR_INT,
+      inout              HPS_I2C1_SCLK,
+      inout              HPS_I2C1_SDAT,
+      inout              HPS_I2C2_SCLK,
+      inout              HPS_I2C2_SDAT,
+      inout              HPS_I2C_CONTROL,
+      inout              HPS_KEY,
+      inout              HPS_LED,
+      inout              HPS_LTC_GPIO,
+      output             HPS_SD_CLK,
+      inout              HPS_SD_CMD,
+      inout       [3:0]  HPS_SD_DATA,
+      output             HPS_SPIM_CLK,
+      input              HPS_SPIM_MISO,
+      output             HPS_SPIM_MOSI,
+      inout              HPS_SPIM_SS,
+      input              HPS_UART_RX,
+      output             HPS_UART_TX,
+      input              HPS_USB_CLKOUT,
+      inout       [7:0]  HPS_USB_DATA,
+      input              HPS_USB_DIR,
+      input              HPS_USB_NXT,
+      output             HPS_USB_STP,
+      `endif
+
+      `ifdef ENABLE_IRDA
+      input              IRDA_RXD,
+      output             IRDA_TXD,
+      `endif
+
+      `ifdef ENABLE_KEY
+      input       [3:0]  KEY,
+      `endif
+
+      `ifdef ENABLE_LEDR
+      output      [9:0]  LEDR,
+      `endif
+
+      `ifdef ENABLE_PS2
+      inout              PS2_CLK,
+      inout              PS2_CLK2,
+      inout              PS2_DAT,
+      inout              PS2_DAT2,
+      `endif
+
+      `ifdef ENABLE_TD
+      input             TD_CLK27,
+      input      [7:0]  TD_DATA,
+      input             TD_HS,
+      output            TD_RESET_N,
+      input             TD_VS,
+      `endif
+
+      `ifdef ENABLE_VGA
+      output      [7:0]  VGA_B,
+      output             VGA_BLANK_N,
+      output             VGA_CLK,
+      output      [7:0]  VGA_G,
+      output             VGA_HS,
+      output      [7:0]  VGA_R,
+      output             VGA_SYNC_N,
+      output             VGA_VS,
+      `endif
+
+      `ifdef ENABLE_SW
+      input       [9:0]  SW
+      `endif
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLOCK_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  SW [9] | ~KEY[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDR[0]   = clk;
+    assign LEDR[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
+    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
+    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
+    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/de4_230/DE4_230.sdc

@@ -0,0 +1,25 @@
+
+create_clock -period 20 [get_ports OSC_50_BANK2]
+create_clock -period 20 [get_ports OSC_50_BANK3]
+create_clock -period 20 [get_ports OSC_50_BANK4]
+create_clock -period 20 [get_ports OSC_50_BANK5]
+create_clock -period 20 [get_ports OSC_50_BANK6]
+create_clock -period 20 [get_ports OSC_50_BANK7]
+
+derive_pll_clocks
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+set_false_path -from * -to [get_ports {SEG0_D[*]}]
+set_false_path -from * -to [get_ports {SEG1_D[*]}]
+set_false_path -from * -to [get_ports {SEG0_DP}]
+set_false_path -from * -to [get_ports {SEG1_DP}]
+set_false_path -from * -to [get_ports {HEX4[*]}]
+set_false_path -from * -to [get_ports {HEX5[*]}]
+
+set_false_path -from [get_ports {SLIDE_SW[*]}] -to [all_clocks]
+set_false_path -from [get_ports {BUTTON[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]
+set_false_path -from [get_ports {CPU_RESET_n}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/de4_230/de4_230.v

@@ -0,0 +1,59 @@
+
+module de4_230
+(
+    input          	GCLKIN,
+    output          GCLKOUT_FPGA,
+    input          	OSC_50_BANK2,
+    input          	OSC_50_BANK3,
+    input          	OSC_50_BANK4,
+    input          	OSC_50_BANK5,
+    input          	OSC_50_BANK6,
+    input          	OSC_50_BANK7,
+    input          	PLL_CLKIN_p,
+
+    output  [7:0]   LED,
+    input   [3:0]   BUTTON,
+    input           CPU_RESET_n, // CPU Reset Push Button
+    inout           EXT_IO,
+    input   [7:0]   SW,          // DIP Switches
+    input   [3:0]   SLIDE_SW,    // Slide switches
+    output  [6:0]   SEG0_D,
+    output          SEG0_DP,
+    output  [6:0]   SEG1_D,
+    output          SEG1_DP
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  OSC_50_BANK2;
+    wire          rst_n     =  CPU_RESET_n;
+    wire          clkEnable =  SW [7] | ~BUTTON[0];
+    wire [  3:0 ] clkDevide =  SW [3:0];
+    wire [  4:0 ] regAddr   =  { ~BUTTON[1], SLIDE_SW };
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[7:1] = regData[6:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    assign SEG0_DP = 1'b1;
+    assign SEG1_DP = 1'b1;
+
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , SEG1_D );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , SEG0_D );
+
+endmodule

MIPSfpga_schoolMIPS/board/marsohod_3/help.txt

@@ -0,0 +1,4 @@
+0-й светодиод отсчитывает такты работы процессора
+1 - 7 светодиод: вывод малдших 7 бит регистра $v0
+ нопка разрешени¤ работы процессора: KEY1.
+ нопка сброса процессора: KEY0.

MIPSfpga_schoolMIPS/board/marsohod_3/marsohod_3.sdc

@@ -0,0 +1,10 @@
+
+create_clock -period "100.0 MHz" [get_ports CLK100MHZ]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+
+set_false_path -from [get_ports {KEY0}] -to [all_clocks]
+set_false_path -from [get_ports {KEY1}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/marsohod_3/marsohod_3.v

@@ -0,0 +1,33 @@
+
+module marsohod_3(
+      input       CLK100MHZ,
+      input       KEY0,
+      input       KEY1,
+      output      [7:0]  LED
+
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLK100MHZ;
+    wire          rst_n     =  KEY0;
+    wire          clkEnable =  ~KEY1;
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( 4'b1000   ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( 4'b0010   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[7:1] = regData[6:0];
+
+endmodule

MIPSfpga_schoolMIPS/board/marsohod_3b/help.txt

@@ -0,0 +1,4 @@
+0-й светодиод отсчитывает такты работы процессора
+1 - 7 светодиод: вывод младших 7 бит регистра $v0
+Кнопка разрешения работы процессора: KEY1.
+Кнопка сброса процессора: KEY0.

MIPSfpga_schoolMIPS/board/marsohod_3b/marsohod_3b.sdc

@@ -0,0 +1,10 @@
+
+create_clock -period "100.0 MHz" [get_ports CLK100MHZ]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+
+set_false_path -from [get_ports {KEY0}] -to [all_clocks]
+set_false_path -from [get_ports {KEY1}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/marsohod_3b/marsohod_3b.v

@@ -0,0 +1,33 @@
+
+module marsohod_3b(
+      input       CLK100MHZ,
+      input       KEY0,
+      input       KEY1,
+      output      [7:0]  LED
+
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLK100MHZ;
+    wire          rst_n     =  KEY0;
+    wire          clkEnable =  ~KEY1;
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( 4'b1000   ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( 4'b0010   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[7:1] = regData[6:0];
+
+endmodule

MIPSfpga_schoolMIPS/board/max_10_evkit/README.md

@@ -0,0 +1,28 @@
+# MAX 10 FPGA Evaluation Kit
+## Описание платы
+Max 10 FPGA Evaluation Kit отладочная плата компании Intel начального уровня. В плате используется микросхема 10M08SAE144C8G серии MAX 10.
+
+![board](images/max_10_eval_board.jpg)
+
+Плата включает следующие компоненты:
+
+- Микросхема серии MAX10 FPGA
+- Intel Enpirion® EP5388QI DC-DC понижающий преобразователь
+- JTAG разъем для программирования платы
+- Тактовый генератор на 50МГц
+- АЦП встроенный в микросхему MAX 10 
+- Переключатели, кнопки, перемычки и сигнальные светодиоды
+- Пробная точка для измерения питания микросхемы
+- Разъемы формата Arduino UNO для подключения переферии
+- Отверстия GPIO для подключения переферии
+- Mini-USB разъем для питания платы 
+![board](images/sch.jpg)
+
+Для программирования платы используется внешний программатор, подключаемый через JTAG разъем.
+
+![board](images/blaster.jpg)
+
+## Ссылки
+1. [Страница с описание платы MAX 10 FPGA Evaluation Kit на сайте Intel](https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html#Contents)
+2. [Руководство пользователя платы MAX 10 FPGA Evaluation Kit](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_max10_eval_10m80.pdf)
+

MIPSfpga_schoolMIPS/board/max_10_evkit/max_10_evkit.v

@@ -0,0 +1,32 @@
+module max_10_evkit(
+      input       CLK,
+      input       SW3_1,
+      input       SW3_2,
+      output      [4:0]  LED
+
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLK;
+    wire          rst_n     =  SW3_1;
+    wire          clkEnable =  ~SW3_2;
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( 4'b1010   ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( 4'b0010   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[4:1] = ~{regData[0], regData[1], regData[2], regData[3]};
+
+endmodule

MIPSfpga_schoolMIPS/board/max_10_neek/max_10_neek.sdc

@@ -0,0 +1,14 @@
+
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK3_50]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {MAX10_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LEDR[*]}]
+set_false_path -from * -to [get_ports {HEX0[*]}]
+set_false_path -from * -to [get_ports {HEX1[*]}]
+
+set_false_path -from [get_ports {KEY[*]}] -to [all_clocks]
+set_false_path -from [get_ports {SW[*]}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/max_10_neek/max_10_neek.v

@@ -0,0 +1,280 @@
+
+`define ENABLE_ADC
+`define ENABLE_AUDIO
+`define ENABLE_CAMERA
+`define ENABLE_DAC
+// `define ENABLE_DDR3
+`define ENABLE_FLASH
+`define ENABLE_GPIO
+`define ENABLE_GSENSOR
+`define ENABLE_HDMI
+`define ENABLE_HEX0
+`define ENABLE_HEX1
+`define ENABLE_KEY
+`define ENABLE_LEDR
+`define ENABLE_LSENSOR
+`define ENABLE_MAX10
+`define ENABLE_MIPI
+`define ENABLE_MTL2
+`define ENABLE_NET
+`define ENABLE_PM
+`define ENABLE_PS2
+`define ENABLE_RH
+`define ENABLE_SD
+`define ENABLE_SW
+`define ENABLE_UART
+
+module golden_top(
+
+`ifdef ENABLE_ADC
+      ///////// ADC 3.3 V /////////
+      input              ADC_CLK_10,
+`endif	  
+        
+`ifdef ENABLE_AUDIO
+      ///////// AUDIO 2.5 V /////////
+      inout              AUDIO_BCLK,
+      output             AUDIO_DIN_MFP1,
+      input              AUDIO_DOUT_MFP2,
+      inout              AUDIO_GPIO_MFP5,
+      output             AUDIO_MCLK,
+      input              AUDIO_MISO_MFP4,
+      inout              AUDIO_RESET_n,
+      output             AUDIO_SCLK_MFP3,
+      output             AUDIO_SCL_SS_n,
+      inout              AUDIO_SDA_MOSI,
+      output             AUDIO_SPI_SELECT,
+      inout              AUDIO_WCLK,
+`endif
+        
+`ifdef ENABLE_CAMERA	
+      // 2.5 V
+      output             CAMERA_I2C_SCL,
+      inout              CAMERA_I2C_SDA,
+      // 3.3 V LVTTL
+      output             CAMERA_PWDN_n,
+`endif
+        
+`ifdef ENABLE_DAC	  
+      ///////// DAC 3.3 V LVTTL /////////
+      inout              DAC_DATA,
+      output             DAC_SCLK,
+      output             DAC_SYNC_n,
+`endif
+        
+`ifdef ENABLE_DDR3
+      // "SSTL-15 CLASS I"
+      output      [14:0] DDR3_A,
+      output      [2:0]  DDR3_BA,
+      output             DDR3_CKE, 
+      output             DDR3_CAS_n,
+      output             DDR3_CS_n,
+      output      [2:0]  DDR3_DM,
+      inout       [23:0] DDR3_DQ,
+      output             DDR3_ODT,
+      output             DDR3_RAS_n,
+      output             DDR3_RESET_n,
+      output             DDR3_WE_n,
+      // "DIFFERENTIAL 1.5-V SSTL CLASS I"
+      inout              DDR3_CK_n,
+      inout              DDR3_CK_p,
+      inout       [2:0]  DDR3_DQS_n,
+      inout       [2:0]  DDR3_DQS_p,
+`endif 
+
+`ifdef ENABLE_FLASH
+      // "3.3-V LVTTL"
+      inout       [3:0]  FLASH_DATA,
+      output             FLASH_DCLK,
+      output             FLASH_NCSO,
+      output             FLASH_RESET_n,
+`endif
+       
+      `ifdef ENABLE_GPIO
+      // "3.3-V LVTTL"
+      inout       [7:0]  GPIO,	 
+      `endif	
+       
+`ifdef ENABLE_GSENSOR  
+      // 2.5 V
+      output             GSENSOR_CS_n,
+      input       [2:1]  GSENSOR_INT,
+      inout              GSENSOR_SCLK,
+      inout              GSENSOR_SDI,
+      inout              GSENSOR_SDO,
+`endif  
+        
+`ifdef ENABLE_HDMI  
+      // "3.3-V LVTTL"
+      input              HDMI_AP,
+      inout              HDMI_I2C_SCL,
+      inout              HDMI_I2C_SDA,
+      inout              HDMI_LRCLK,
+      inout              HDMI_MCLK,
+      input              HDMI_RX_CLK,
+      input       [23:0] HDMI_RX_D,
+      input              HDMI_RX_DE,
+      inout              HDMI_RX_HS,
+      input              HDMI_RX_INT1,
+      inout              HDMI_RX_RESET_n,
+      input              HDMI_RX_VS,
+      inout              HDMI_SCLK,
+`endif
+        
+`ifdef ENABLE_HEX0	  
+      // "3.3-V LVTTL"
+      output      [6:0]  HEX0,
+`endif
+
+`ifdef ENABLE_HEX1
+      // "3.3-V LVTTL"
+      output      [6:0]  HEX1,
+`endif
+        
+`ifdef ENABLE_KEY
+      // "1.5 V SCHMITT TRIGGER" 
+      input       [4:0]  KEY,
+`endif
+        
+`ifdef ENABLE_LEDR	  
+      // "3.3-V LVTTL"
+      output      [9:0]  LEDR,
+`endif
+        
+`ifdef ENABLE_LSENSOR	  
+      // "3.3-V LVTTL"
+      inout              LSENSOR_INT,
+      output             LSENSOR_SCL,
+      inout              LSENSOR_SDA,
+`endif
+        
+`ifdef ENABLE_MAX10	 
+      //  "3.3-V LVTTL"
+      input              MAX10_CLK1_50,
+      input              MAX10_CLK2_50,
+      input              MAX10_CLK3_50,
+`endif
+        
+`ifdef ENABLE_MIPI
+      // "3.3-V LVTTL"
+      output             MIPI_CS_n,
+      output             MIPI_I2C_SCL,
+      inout              MIPI_I2C_SDA,
+      input              MIPI_PIXEL_CLK,
+      input       [23:0] MIPI_PIXEL_D,
+      input              MIPI_PIXEL_HS,
+      input              MIPI_PIXEL_VS,
+      output             MIPI_REFCLK,
+      output             MIPI_RESET_n,
+`endif
+
+`ifdef ENABLE_MTL2	  
+      // "3.3-V LVTTL"
+      output      [7:0]  MTL2_B,
+      inout              MTL2_BL_ON_n,
+      output             MTL2_DCLK,
+      output      [7:0]  MTL2_G,
+      output             MTL2_HSD,
+      output             MTL2_I2C_SCL,
+      inout              MTL2_I2C_SDA,
+      input              MTL2_INT,
+      output      [7:0]  MTL2_R,
+      output             MTL2_VSD,
+`endif
+        
+`ifdef ENABLE_NET
+      // 2.5 V 
+      output             NET_GTX_CLK,
+      input              NET_INT_n,
+      input              NET_LINK100,
+      output             NET_MDC,
+      inout              NET_MDIO,
+      output             NET_RST_N,
+      input              NET_RX_CLK,
+      input              NET_RX_COL,
+      input              NET_RX_CRS,
+      input       [3:0]  NET_RX_D,
+      input              NET_RX_DV,
+      input              NET_RX_ER,
+      input              NET_TX_CLK,
+      output      [3:0]  NET_TX_D,
+      output             NET_TX_EN,
+      output             NET_TX_ER,
+`endif
+        
+`ifdef ENABLE_PM	  
+      //  "3.3-V LVTTL"
+      output             PM_I2C_SCL,
+      inout              PM_I2C_SDA,
+`endif
+
+`ifdef ENABLE_PS2
+      // "3.3-V LVTTL"
+      inout              PS2_CLK,
+      inout              PS2_CLK2,
+      inout              PS2_DAT,
+      inout              PS2_DAT2,
+`endif
+
+`ifdef ENABLE_RH
+      // "3.3-V LVTTL"
+      input              RH_TEMP_DRDY_n,
+      output             RH_TEMP_I2C_SCL,
+      inout              RH_TEMP_I2C_SDA,
+`endif
+        
+`ifdef ENABLE_SD
+      // 2.5 V  
+      output             SD_CLK,
+      inout              SD_CMD,
+      inout       [3:0]  SD_DATA,
+`endif
+
+`ifdef ENABLE_SW
+      // 1.5 V 
+      input       [9:0]  SW,
+`endif
+        
+`ifdef ENABLE_UART
+      // 2.5 V 
+      output             UART_RESET_n,
+      input              UART_RX,
+      output             UART_TX,
+`endif
+
+      ///////// FPGA /////////
+      input              FPGA_RESET_n
+
+);
+
+  // wires & inputs
+    wire          clk;
+    wire          clkIn     =  MAX10_CLK1_50;
+    wire          rst_n     =  KEY[0];
+    wire          clkEnable =  SW [9] | ~KEY[1];
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LEDR[0]   = clk;
+    assign LEDR[9:1] = regData[8:0];
+
+    wire [ 31:0 ] h7segment = regData;
+
+    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
+    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_schoolMIPS/board/nexys4/nexys4.v

@@ -0,0 +1,89 @@
+
+module nexys4
+(
+    input         clk,
+    input         btnCpuReset,
+
+    input         btnC,
+    input         btnU,
+    input         btnL,
+    input         btnR,
+    input         btnD,
+
+    input  [15:0] sw,
+
+    output [15:0] led,
+
+    output        RGB1_Red,
+    output        RGB1_Green,
+    output        RGB1_Blue,
+    output        RGB2_Red,
+    output        RGB2_Green,
+    output        RGB2_Blue,
+
+    output [ 6:0] seg,
+    output        dp,
+    output [ 7:0] an,
+
+    inout  [ 7:0] JA,
+    inout  [ 7:0] JB,
+
+    input         RsRx
+);
+    // wires & inputs
+    wire          clkCpu;
+    wire          clkIn     =  clk;
+    wire          rst_n     =  btnCpuReset;
+    wire          clkEnable =  sw [9] | btnU;
+    wire [  3:0 ] clkDevide =  sw [8:5];
+    wire [  4:0 ] regAddr   =  sw [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clkCpu    ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign led[0]    = clkCpu;
+    assign led[15:1] = regData[14:0];
+
+    //hex out
+    wire [ 31:0 ] h7segment = regData;
+    wire clkHex;
+
+    sm_clk_divider hex_clk_divider
+    (
+        .clkIn   ( clkIn  ),
+        .rst_n   ( rst_n  ),
+        .devide  ( 4'b1   ),
+        .enable  ( 1'b1   ),
+        .clkOut  ( clkHex )
+    );
+
+    sm_hex_display_8 sm_hex_display_8
+    (
+        .clock          ( clkHex    ),
+        .resetn         ( rst_n     ),
+        .number         ( h7segment ),
+
+        .seven_segments ( seg       ),
+        .dot            ( dp        ),
+        .anodes         ( an        )
+    );
+
+    assign RGB1_Red   = 1'b0; 
+    assign RGB1_Green = 1'b0; 
+    assign RGB1_Blue  = 1'b0; 
+    assign RGB2_Red   = 1'b0; 
+    assign RGB2_Green = 1'b0; 
+    assign RGB2_Blue  = 1'b0;
+
+endmodule

MIPSfpga_schoolMIPS/board/nexys4_ddr/nexys4_ddr.v

@@ -0,0 +1,97 @@
+
+module nexys4_ddr
+(
+    input         CLK100MHZ,
+    input         CPU_RESETN,
+
+    input         BTNC,
+    input         BTNU,
+    input         BTNL,
+    input         BTNR,
+    input         BTND,
+
+    input  [15:0] SW, 
+
+    output [15:0] LED,
+
+    output        LED16_B,
+    output        LED16_G,
+    output        LED16_R,
+    output        LED17_B,
+    output        LED17_G,
+    output        LED17_R,
+
+    output        CA,
+    output        CB,
+    output        CC,
+    output        CD,
+    output        CE,
+    output        CF,
+    output        CG,
+    output        DP,
+
+    output [ 7:0] AN,
+
+    inout  [12:1] JA,
+    inout  [12:1] JB,
+
+    input         UART_TXD_IN
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLK100MHZ;
+    wire          rst_n     =  CPU_RESETN;
+    wire          clkEnable =  SW [9] | BTNU;
+    wire [  3:0 ] clkDevide =  SW [8:5];
+    wire [  4:0 ] regAddr   =  SW [4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]    = clk;
+    assign LED[15:1] = regData[14:0];
+
+    //hex out
+    wire [ 31:0 ] h7segment = regData;
+    wire clkHex;
+
+    sm_clk_divider hex_clk_divider
+    (
+        .clkIn   ( clkIn  ),
+        .rst_n   ( rst_n  ),
+        .devide  ( 4'b1   ),
+        .enable  ( 1'b1   ),
+        .clkOut  ( clkHex )
+    );
+
+    sm_hex_display_8 sm_hex_display_8
+    (
+        .clock          ( clkHex                         ),
+        .resetn         ( rst_n                          ),
+        .number         ( h7segment                      ),
+
+        .seven_segments ( { CG, CF, CE, CD, CC, CB, CA } ),
+        .dot            ( DP                             ),
+        .anodes         ( AN                             )
+    );
+
+    assign LED16_B = 1'b0;
+    assign LED16_G = 1'b0;
+    assign LED16_R = 1'b0;
+    assign LED17_B = 1'b0;
+    assign LED17_G = 1'b0;
+    assign LED17_R = 1'b0;
+
+endmodule

MIPSfpga_schoolMIPS/board/rz_easyFPGA_A2.1/README.md

@@ -0,0 +1,20 @@
+# RZ-EasyFPGA A2.1 (Altera Cyclone IV)
+
+Thanks to [@woodywitch](https://github.com/woodywitch) and [@Dluzhnevsky](https://github.com/Dluzhnevsky) for this port.
+
+## Used pins
+
+Pin | Name | Description
+--- | ---- | -----------
+pin_23 | CLK100MHZ | system clock
+pin_25 | KEY0 | system reset
+pin_88 | KEY1 | clock enable
+pin_87:84 | LED1-LED4 | system output
+
+## Board photo
+
+![photo](/board/rz_easyFPGA_A2.1/doc/photo.jpg)
+
+## Board pinout
+
+![pinout](/board/rz_easyFPGA_A2.1/doc/pins.jpg)

MIPSfpga_schoolMIPS/board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.sdc

@@ -0,0 +1,11 @@
+
+
+create_clock -period "100.0 MHz" [get_ports CLK100MHZ]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+
+set_false_path -from * -to [get_ports {LED[*]}]
+
+set_false_path -from [get_ports {KEY0}] -to [all_clocks]
+set_false_path -from [get_ports {KEY1}] -to [all_clocks]

MIPSfpga_schoolMIPS/board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.v

@@ -0,0 +1,31 @@
+module rz_easyFPGA_A21(
+	input       CLK100MHZ,
+	input       KEY0,
+	input       KEY1,
+	output      [3:0]  LED
+);
+
+    // wires & inputs
+    wire          clk;
+    wire          clkIn     =  CLK100MHZ;
+    wire          rst_n     =  KEY0;
+    wire          clkEnable =  ~KEY1;
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( 4'b1000   ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clk       ),
+        .regAddr    ( 4'b0010   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign LED[0]   = clk;
+    assign LED[3:1] = regData[2:0];
+
+endmodule

MIPSfpga_schoolMIPS/board/zeowaa/zeowaa.sdc

@@ -0,0 +1,13 @@
+create_clock -period "50.0 MHz" [get_ports clk_50]
+
+derive_clock_uncertainty
+create_generated_clock -name {clk}     -divide_by 2 -source [get_ports {clk_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}]
+create_generated_clock -name {clk_hex} -divide_by 2 -source [get_ports {clk_50}] [get_registers {sm_clk_divider:hex_clk_divider|sm_register_we:r_cntr|q[16]}]
+
+set_false_path -from [get_ports {key[*]}] -to [all_clocks]
+set_false_path -from [get_ports {sw[*]}]  -to [all_clocks]
+
+set_false_path -from * -to [get_ports {led[*]}]
+set_false_path -from * -to [get_ports {hex[*]}]
+set_false_path -from * -to [get_ports {digit[*]}]
+set_false_path -from * -to buzzer

MIPSfpga_schoolMIPS/board/zeowaa/zeowaa.v

@@ -0,0 +1,62 @@
+
+module zeowaa
+(
+    input         clk_50,
+    input  [ 5:2] key,
+    input  [ 7:0] sw,
+    output [11:0] led,
+    output [ 7:0] hex,
+    output [ 7:0] digit,
+    output        buzzer
+);
+    // wires & inputs
+    wire          clkCpu;
+    wire          clkIn     =  clk_50;
+    wire          rst_n     =  key[4];
+    wire          clkEnable =   ~sw[  7] | ~key[5];
+    wire [  3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
+    wire [  4:0 ] regAddr   =   ~sw[4:0];
+    wire [ 31:0 ] regData;
+
+    //cores
+    sm_top sm_top
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .clkDevide  ( clkDevide ),
+        .clkEnable  ( clkEnable ),
+        .clk        ( clkCpu    ),
+        .regAddr    ( regAddr   ),
+        .regData    ( regData   )
+    );
+
+    //outputs
+    assign led[0]    = ~clkCpu;
+    assign led[11:1] = ~regData[11:0];
+
+    //hex out
+    wire [ 31:0 ] h7segment = regData;
+    wire clkHex;
+
+    sm_clk_divider hex_clk_divider
+    (
+        .clkIn   ( clkIn  ),
+        .rst_n   ( rst_n  ),
+        .devide  ( 4'b0   ),
+        .enable  ( 1'b1   ),
+        .clkOut  ( clkHex )
+    );
+
+    sm_hex_display_8 sm_hex_display_8
+    (
+        .clock          ( clkHex    ),
+        .resetn         ( rst_n     ),
+        .number         ( h7segment ),
+        .seven_segments ( hex[6:0]  ),
+        .dot            ( hex[7]    ),
+        .anodes         ( digit     )
+    );
+
+    assign buzzer = 1'b1;
+
+endmodule

MIPSfpga_schoolMIPS/doc/README.md

@@ -0,0 +1,2 @@
+
+For docs and CPU diagrams please visit the project [wiki](https://github.com/MIPSfpga/schoolMIPS/wiki)

MIPSfpga_schoolMIPS/program/00_counter/modelsim_script.tcl

@@ -0,0 +1,24 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../src
+set i1 +incdir+../../../testbench
+
+set s0 ../../../src/*.v
+set s1 ../../../testbench/*.v
+
+vlog $p0 $p1  $i0 $i1  $s0 $s1
+
+vsim work.sm_testbench
+
+# add wave -radix hex sim:/sm_testbench/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf
+
+run -all
+
+wave zoom full

MIPSfpga_schoolMIPS/program/01_fibonacci/modelsim_script.tcl

@@ -0,0 +1,24 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../src
+set i1 +incdir+../../../testbench
+
+set s0 ../../../src/*.v
+set s1 ../../../testbench/*.v
+
+vlog $p0 $p1  $i0 $i1  $s0 $s1
+
+vsim work.sm_testbench
+
+# add wave -radix hex sim:/sm_testbench/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf
+
+run -all
+
+wave zoom full

MIPSfpga_schoolMIPS/program/02_sqrt/modelsim_script.tcl

@@ -0,0 +1,25 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../src
+set i1 +incdir+../../../testbench
+
+set s0 ../../../src/*.v
+set s1 ../../../testbench/*.v
+
+vlog $p0 $p1  $i0 $i1  $s0 $s1
+
+vsim work.sm_testbench
+
+# add wave -radix hex sim:/sm_testbench/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/*
+add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf
+add wave            sim:/sm_testbench/cycle
+
+run -all
+
+wave zoom full

MIPSfpga_schoolMIPS/src/sm_cpu.v

@@ -0,0 +1,184 @@
+/*
+ * schoolMIPS - small MIPS CPU for "Young Russian Chip Architects" 
+ *              summer school ( yrca@googlegroups.com )
+ *
+ * originally based on Sarah L. Harris MIPS CPU 
+ * 
+ * Copyright(c) 2017 Stanislav Zhelnio 
+ *                   Aleksandr Romanov 
+ */ 
+
+`include "sm_cpu.vh"
+
+module sm_cpu
+(
+    input           clk,        // clock
+    input           rst_n,      // reset
+    input   [ 4:0]  regAddr,    // debug access reg address
+    output  [31:0]  regData,    // debug access reg data
+    output  [31:0]  imAddr,     // instruction memory address
+    input   [31:0]  imData      // instruction memory data
+);
+    //control wires
+    wire        pcSrc;
+    wire        regDst;
+    wire        regWrite;
+    wire        aluSrc;
+    wire        aluZero;
+    wire [ 2:0] aluControl;
+
+    //program counter
+    wire [31:0] pc;
+    wire [31:0] pcBranch;
+    wire [31:0] pcNext  = pc + 1;
+    wire [31:0] pc_new   = ~pcSrc ? pcNext : pcBranch;
+    sm_register r_pc(clk ,rst_n, pc_new, pc);
+
+    //program memory access
+    assign imAddr = pc;
+    wire [31:0] instr = imData;
+
+    //debug register access
+    wire [31:0] rd0;
+    assign regData = (regAddr != 0) ? rd0 : pc;
+
+    //register file
+    wire [ 4:0] a3  = regDst ? instr[15:11] : instr[20:16];
+    wire [31:0] rd1;
+    wire [31:0] rd2;
+    wire [31:0] wd3;
+
+    sm_register_file rf
+    (
+        .clk        ( clk          ),
+        .a0         ( regAddr      ),
+        .a1         ( instr[25:21] ),
+        .a2         ( instr[20:16] ),
+        .a3         ( a3           ),
+        .rd0        ( rd0          ),
+        .rd1        ( rd1          ),
+        .rd2        ( rd2          ),
+        .wd3        ( wd3          ),
+        .we3        ( regWrite     )
+    );
+
+    //sign extension
+    wire [31:0] signImm = { {16 { instr[15] }}, instr[15:0] };
+    assign pcBranch = pcNext + signImm;
+
+    //alu
+    wire [31:0] srcB = aluSrc ? signImm : rd2;
+
+    sm_alu alu
+    (
+        .srcA       ( rd1          ),
+        .srcB       ( srcB         ),
+        .oper       ( aluControl   ),
+        .shift      ( instr[10:6 ] ),
+        .zero       ( aluZero      ),
+        .result     ( wd3          ) 
+    );
+
+    //control
+    sm_control sm_control
+    (
+        .cmdOper    ( instr[31:26] ),
+        .cmdFunk    ( instr[ 5:0 ] ),
+        .aluZero    ( aluZero      ),
+        .pcSrc      ( pcSrc        ), 
+        .regDst     ( regDst       ), 
+        .regWrite   ( regWrite     ), 
+        .aluSrc     ( aluSrc       ),
+        .aluControl ( aluControl   )
+    );
+
+endmodule
+
+module sm_control
+(
+    input      [5:0] cmdOper,
+    input      [5:0] cmdFunk,
+    input            aluZero,
+    output           pcSrc, 
+    output reg       regDst, 
+    output reg       regWrite, 
+    output reg       aluSrc,
+    output reg [2:0] aluControl
+);
+    reg          branch;
+    reg          condZero;
+    assign pcSrc = branch & (aluZero == condZero);
+
+    always @ (*) begin
+        branch      = 1'b0;
+        condZero    = 1'b0;
+        regDst      = 1'b0;
+        regWrite    = 1'b0;
+        aluSrc      = 1'b0;
+        aluControl  = `ALU_ADD;
+
+        casez( {cmdOper,cmdFunk} )
+            default               : ;
+
+            { `C_SPEC,  `F_ADDU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD;  end
+            { `C_SPEC,  `F_OR   } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR;   end
+            { `C_SPEC,  `F_SRL  } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL;  end
+            { `C_SPEC,  `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
+            { `C_SPEC,  `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
+
+            { `C_ADDIU, `F_ANY  } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;  end
+            { `C_LUI,   `F_ANY  } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI;  end
+
+            { `C_BEQ,   `F_ANY  } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
+            { `C_BNE,   `F_ANY  } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
+        endcase
+    end
+endmodule
+
+
+module sm_alu
+(
+    input  [31:0] srcA,
+    input  [31:0] srcB,
+    input  [ 2:0] oper,
+    input  [ 4:0] shift,
+    output        zero,
+    output reg [31:0] result
+);
+    always @ (*) begin
+        case (oper)
+            default   : result = srcA + srcB;
+            `ALU_ADD  : result = srcA + srcB;
+            `ALU_OR   : result = srcA | srcB;
+            `ALU_LUI  : result = (srcB << 16);
+            `ALU_SRL  : result = srcB >> shift;
+            `ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
+            `ALU_SUBU : result = srcA - srcB;
+        endcase
+    end
+
+    assign zero   = (result == 0);
+endmodule
+
+module sm_register_file
+(
+    input         clk,
+    input  [ 4:0] a0,
+    input  [ 4:0] a1,
+    input  [ 4:0] a2,
+    input  [ 4:0] a3,
+    output [31:0] rd0,
+    output [31:0] rd1,
+    output [31:0] rd2,
+    input  [31:0] wd3,
+    input         we3
+);
+    reg [31:0] rf [31:0];
+
+    assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
+    assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
+    assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
+
+    always @ (posedge clk)
+        if(we3) rf [a3] <= wd3;
+endmodule

MIPSfpga_schoolMIPS/src/sm_cpu.vh

@@ -0,0 +1,41 @@
+/*
+ * schoolMIPS - small MIPS CPU for "Young Russian Chip Architects" 
+ *              summer school ( yrca@googlegroups.com )
+ *
+ * originally based on Sarah L. Harris MIPS CPU 
+ * 
+ * Copyright(c) 2017 Stanislav Zhelnio 
+ *                   Aleksandr Romanov 
+ */ 
+
+//ALU commands
+`define ALU_ADD     3'b000
+`define ALU_OR      3'b001
+`define ALU_LUI     3'b010
+`define ALU_SRL     3'b011
+`define ALU_SLTU    3'b100
+`define ALU_SUBU    3'b101
+
+//instruction operation code
+`define C_SPEC      6'b000000 // Special instructions (depends on function field)
+`define C_ADDIU     6'b001001 // I-type, Integer Add Immediate Unsigned
+                              //         Rd = Rs + Immed
+`define C_BEQ       6'b000100 // I-type, Branch On Equal
+                              //         if (Rs == Rt) PC += (int)offset
+`define C_LUI       6'b001111 // I-type, Load Upper Immediate
+                              //         Rt = Immed << 16
+`define C_BNE       6'b000101 // I-type, Branch on Not Equal
+                              //         if (Rs != Rt) PC += (int)offset
+
+//instruction function field
+`define F_ADDU      6'b100001 // R-type, Integer Add Unsigned
+                              //         Rd = Rs + Rt
+`define F_OR        6'b100101 // R-type, Logical OR
+                              //         Rd = Rs | Rt
+`define F_SRL       6'b000010 // R-type, Shift Right Logical
+                              //         Rd = Rs∅ >> shift
+`define F_SLTU      6'b101011 // R-type, Set on Less Than Unsigned
+                              //         Rd = (Rs∅ < Rt∅) ? 1 : 0
+`define F_SUBU      6'b100011 // R-type, Unsigned Subtract
+                              //         Rd = Rs – Rt
+`define F_ANY       6'b??????

MIPSfpga_schoolMIPS/src/sm_hex_display.v

@@ -0,0 +1,88 @@
+
+module sm_hex_display
+(
+    input      [3:0] digit,
+    output reg [6:0] seven_segments
+);
+
+    always @*
+        case (digit)
+        'h0: seven_segments = 'b1000000;  // g f e d c b a
+        'h1: seven_segments = 'b1111001;
+        'h2: seven_segments = 'b0100100;  //   --a--
+        'h3: seven_segments = 'b0110000;  //  |     |
+        'h4: seven_segments = 'b0011001;  //  f     b
+        'h5: seven_segments = 'b0010010;  //  |     |
+        'h6: seven_segments = 'b0000010;  //   --g--
+        'h7: seven_segments = 'b1111000;  //  |     |
+        'h8: seven_segments = 'b0000000;  //  e     c
+        'h9: seven_segments = 'b0011000;  //  |     |
+        'ha: seven_segments = 'b0001000;  //   --d-- 
+        'hb: seven_segments = 'b0000011;
+        'hc: seven_segments = 'b1000110;
+        'hd: seven_segments = 'b0100001;
+        'he: seven_segments = 'b0000110;
+        'hf: seven_segments = 'b0001110;
+        endcase
+
+endmodule
+
+//--------------------------------------------------------------------
+
+module sm_hex_display_8
+(
+    input             clock,
+    input             resetn,
+    input      [31:0] number,
+
+    output reg [ 6:0] seven_segments,
+    output reg        dot,
+    output reg [ 7:0] anodes
+);
+
+    function [6:0] bcd_to_seg (input [3:0] bcd);
+
+        case (bcd)
+        'h0: bcd_to_seg = 'b1000000;  // g f e d c b a
+        'h1: bcd_to_seg = 'b1111001;
+        'h2: bcd_to_seg = 'b0100100;  //   --a--
+        'h3: bcd_to_seg = 'b0110000;  //  |     |
+        'h4: bcd_to_seg = 'b0011001;  //  f     b
+        'h5: bcd_to_seg = 'b0010010;  //  |     |
+        'h6: bcd_to_seg = 'b0000010;  //   --g--
+        'h7: bcd_to_seg = 'b1111000;  //  |     |
+        'h8: bcd_to_seg = 'b0000000;  //  e     c
+        'h9: bcd_to_seg = 'b0011000;  //  |     |
+        'ha: bcd_to_seg = 'b0001000;  //   --d-- 
+        'hb: bcd_to_seg = 'b0000011;
+        'hc: bcd_to_seg = 'b1000110;
+        'hd: bcd_to_seg = 'b0100001;
+        'he: bcd_to_seg = 'b0000110;
+        'hf: bcd_to_seg = 'b0001110;
+        endcase
+
+    endfunction
+
+    reg [2:0] i;
+
+    always @ (posedge clock or negedge resetn)
+    begin
+        if (! resetn)
+        begin
+            seven_segments <=   bcd_to_seg (0);
+            dot            <= ~ 0;
+            anodes         <= ~ 8'b00000001;
+
+            i <= 0;
+        end
+        else
+        begin
+            seven_segments <=   bcd_to_seg (number [i * 4 +: 4]);
+            dot            <= ~ 0;
+            anodes         <= ~ (1 << i);
+
+            i <= i + 1;
+        end
+    end
+
+endmodule

MIPSfpga_schoolMIPS/src/sm_register.v

@@ -0,0 +1,31 @@
+
+
+module sm_register
+(
+    input                 clk,
+    input                 rst,
+    input      [ 31 : 0 ] d,
+    output reg [ 31 : 0 ] q
+);
+    always @ (posedge clk or negedge rst)
+        if(~rst)
+            q <= 32'b0;
+        else
+            q <= d;
+endmodule
+
+
+module sm_register_we
+(
+    input                 clk,
+    input                 rst,
+    input                 we,
+    input      [ 31 : 0 ] d,
+    output reg [ 31 : 0 ] q
+);
+    always @ (posedge clk or negedge rst)
+        if(~rst)
+            q <= 32'b0;
+        else
+            if(we) q <= d;
+endmodule

MIPSfpga_schoolMIPS/src/sm_rom.v

@@ -0,0 +1,17 @@
+
+module sm_rom
+#(
+    parameter SIZE = 64
+)
+(
+    input  [31:0] a,
+    output [31:0] rd
+);
+    reg [31:0] rom [SIZE - 1:0];
+    assign rd = rom [a];
+
+    initial begin
+        $readmemh ("program.hex", rom);
+    end
+
+endmodule

MIPSfpga_schoolMIPS/src/sm_top.v

@@ -0,0 +1,88 @@
+
+//hardware top level module
+module sm_top
+(
+    input           clkIn,
+    input           rst_n,
+    input   [ 3:0 ] clkDevide,
+    input           clkEnable,
+    output          clk,
+    input   [ 4:0 ] regAddr,
+    output  [31:0 ] regData
+);
+    //metastability input filters
+    wire    [ 3:0 ] devide;
+    wire            enable;
+    wire    [ 4:0 ] addr;
+
+    sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
+    sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
+    sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr,   addr  );
+
+    //cores
+    //clock devider
+    sm_clk_divider sm_clk_divider
+    (
+        .clkIn      ( clkIn     ),
+        .rst_n      ( rst_n     ),
+        .devide     ( devide    ),
+        .enable     ( enable    ),
+        .clkOut     ( clk       )
+    );
+
+    //instruction memory
+    wire    [31:0]  imAddr;
+    wire    [31:0]  imData;
+    sm_rom reset_rom(imAddr, imData);
+
+    sm_cpu sm_cpu
+    (
+        .clk        ( clk       ),
+        .rst_n      ( rst_n     ),
+        .regAddr    ( addr      ),
+        .regData    ( regData   ),
+        .imAddr     ( imAddr    ),
+        .imData     ( imData    )
+    );
+
+endmodule
+
+//metastability input debouncer module
+module sm_debouncer
+#(
+    parameter SIZE = 1
+)
+(
+    input                      clk,
+    input      [ SIZE - 1 : 0] d,
+    output reg [ SIZE - 1 : 0] q
+);
+    reg        [ SIZE - 1 : 0] data;
+
+    always @ (posedge clk) begin
+        data <= d;
+        q    <= data;
+    end
+
+endmodule
+
+//tunable clock devider
+module sm_clk_divider
+#(
+    parameter shift  = 16,
+              bypass = 0
+)
+(
+    input           clkIn,
+    input           rst_n,
+    input   [ 3:0 ] devide,
+    input           enable,
+    output          clkOut
+);
+    wire [31:0] cntr;
+    wire [31:0] cntrNext = cntr + 1;
+    sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
+
+    assign clkOut = bypass ? clkIn 
+                           : cntr[shift + devide];
+endmodule

MIPSfpga_schoolMIPS/testbench/testbench.v

@@ -0,0 +1,137 @@
+
+`timescale 1 ns / 100 ps
+
+`include "sm_cpu.vh"
+
+`ifndef SIMULATION_CYCLES
+    `define SIMULATION_CYCLES 120
+`endif
+
+module sm_testbench;
+
+    // simulation options
+    parameter Tt     = 20;
+
+    reg         clk;
+    reg         rst_n;
+    reg  [ 4:0] regAddr;
+    wire [31:0] regData;
+    wire        cpuClk;
+
+    // ***** DUT start ************************
+
+    sm_top sm_top
+    (
+        .clkIn     ( clk     ),
+        .rst_n     ( rst_n   ),
+        .clkDevide ( 4'b0    ),
+        .clkEnable ( 1'b1    ),
+        .clk       ( cpuClk  ),
+        .regAddr   ( regAddr ),
+        .regData   ( regData )
+    );
+
+    defparam sm_top.sm_clk_divider.bypass = 1;
+
+    // ***** DUT  end  ************************
+
+`ifdef ICARUS
+    //iverilog memory dump init workaround
+    initial $dumpvars;
+    genvar k;
+    for (k = 0; k < 32; k = k + 1) begin
+        initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
+    end
+`endif
+
+    // simulation init
+    initial begin
+        clk = 0;
+        forever clk = #(Tt/2) ~clk;
+    end
+
+    initial begin
+        rst_n   = 0;
+        repeat (4)  @(posedge clk);
+        rst_n   = 1;
+    end
+
+    //register file reset
+    integer i;
+    initial begin
+        for (i = 0; i < 32; i = i + 1)
+            sm_top.sm_cpu.rf.rf[i] = 0;
+    end
+
+    task disasmInstr
+    (
+        input [31:0] instr
+    );
+        reg        [ 5:0] cmdOper;
+        reg        [ 5:0] cmdFunk;
+        reg        [ 4:0] cmdRs;
+        reg        [ 4:0] cmdRt;
+        reg        [ 4:0] cmdRd;
+        reg        [ 4:0] cmdSa;
+        reg        [15:0] cmdImm;
+        reg signed [15:0] cmdImmS;
+
+        begin
+            cmdOper = instr[31:26];
+            cmdFunk = instr[ 5:0 ];
+            cmdRs   = instr[25:21];
+            cmdRt   = instr[20:16];
+            cmdRd   = instr[15:11];
+            cmdSa   = instr[10:6 ];
+            cmdImm  = instr[15:0 ];
+            cmdImmS = instr[15:0 ];
+
+            $write("   ");
+
+            casez( {cmdOper,cmdFunk} )
+                default               : if (instr == 32'b0) 
+                                            $write ("nop");
+                                        else
+                                            $write ("new/unknown");
+
+                { `C_SPEC,  `F_ADDU } : $write ("addu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                { `C_SPEC,  `F_OR   } : $write ("or    $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+
+                { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
+                { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);
+
+                { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
+                { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
+            endcase
+        end
+
+    endtask
+
+
+    //simulation debug output
+    integer cycle; initial cycle = 0;
+
+    initial regAddr = 0; // get PC
+
+    always @ (posedge clk)
+    begin
+        $write ("%5d  pc = %2d  pcaddr = %h  instr = %h   v0 = %1d", 
+                  cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);
+
+        disasmInstr(sm_top.sm_cpu.instr);
+
+        $write("\n");
+
+        cycle = cycle + 1;
+
+        if (cycle > `SIMULATION_CYCLES)
+        begin
+            $display ("Timeout");
+            $stop;
+        end
+    end
+
+endmodule

ShawnHymel_introduction-to-fpga/02-install-apio/solution-turn-off-led/leds.v

@@ -0,0 +1,18 @@
+//------------------------------------------------------------------
+//-- Hello world example for the iCEstick board
+//-- Turn on all the leds
+//------------------------------------------------------------------
+
+module leds(output wire D1,
+            output wire D2,
+            output wire D3,
+            output wire D4,
+            output wire D5);
+
+assign D1 = 1'b1;
+assign D2 = 1'b1;
+assign D3 = 1'b1;
+assign D4 = 1'b1;
+assign D5 = 1'b0;
+
+endmodule

ShawnHymel_introduction-to-fpga/02-install-apio/solution-turn-off-led/leds_tb.v

@@ -0,0 +1,45 @@
+//-------------------------------------------------------------------
+//-- leds_tb.v
+//-- Testbench
+//-------------------------------------------------------------------
+//-- Juan Gonzalez (Obijuan)
+//-- Jesus Arroyo Torrens
+//-- GPL license
+//-------------------------------------------------------------------
+`default_nettype none
+`define DUMPSTR(x) `"x.vcd`"
+`timescale 100 ns / 10 ns
+
+module leds_tb();
+
+//-- Simulation time: 1us (10 * 100ns)
+parameter DURATION = 10;
+
+//-- Clock signal. It is not used in this simulation
+reg clk = 0;
+always #0.5 clk = ~clk;
+
+//-- Leds port
+wire d1, d2, d3, d4, d5;
+
+//-- Instantiate the unit to test
+leds UUT (
+           .D1(d1),
+           .D2(d2),
+           .D3(d3),
+           .D4(d4),
+           .D5(d5)
+         );
+
+
+initial begin
+
+  //-- File were to store the simulation results
+  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
+  $dumpvars(0, leds_tb);
+
+   #(DURATION) $display("End of simulation");
+  $finish;
+end
+
+endmodule

ShawnHymel_introduction-to-fpga/03-verilog-gate-logic/example-01-and-gate/and_gate.v

@@ -0,0 +1,29 @@
+// AND gate example
+//
+// Inputs:
+//      pmod_0  - pushbutton
+//      pmod_1  - pushbutton
+// Outputs:
+//      led_0   - LED
+//
+// LED will turn on if both pushbuttons are pressed (~pmod_0 & ~pmod_1).
+//
+// Date: October 13, 2021
+// Author: Shawn Hymel
+// License: 0BSD
+
+// Module: when buttons 1 and 2 are pressed, turn on LED
+module and_gate (
+
+    // Inputs
+    input   pmod_0,
+    input   pmod_1,
+    
+    // Outputs
+    output  led_0
+);
+
+    // Continuous assignment: NOT and AND operators
+    assign led_0 = ~pmod_0 & ~pmod_1;
+    
+endmodule

ShawnHymel_introduction-to-fpga/03-verilog-gate-logic/example-02-vectors/vectors.v

@@ -0,0 +1,36 @@
+// Vector and intermediate (wire) value example
+//
+// Inputs:
+//      pmod[1:0]   - pushbuttons (x2)
+//
+// Outputs:
+//      led[2:0]    - LEDs (x3)
+//
+// LEDs 0 and 1 turn on if pmod[0] button is pressed. LED 2 turns on if pmod[0]
+// and pmod[1] are pressed together.
+//
+// Date: October 13, 2021
+// Author: Shawn Hymel
+// License: 0BSD
+
+// Module: button 0 lights up 2 LEDs, button 0 and 1 light up another LED
+module and_gate (
+
+    // Inputs
+    input   [1:0]   pmod,
+    
+    // Output
+    output  [2:0]   led
+);
+
+    // Wire (net) declarations (internal to module)
+    wire not_pmod_0;
+
+    // Continuous assignment: replicate 1 wire to 2 outputs
+    assign not_pmod_0 = ~pmod[0];
+    assign led[1:0] = {2{not_pmod_0}};
+    
+    // Continuous assignment: NOT and AND operators
+    assign led[2] = not_pmod_0 & ~pmod[1];
+    
+endmodule