Add Batch 3 with 10 repos

.gitattributes

@@ -1157,3 +1157,4 @@ openasic-org_xk265/sw/testVector/rec.yuv filter=lfs diff=lfs merge=lfs -text
 efabless_caravel_user_project/verilog/gl/user_proj_example.v filter=lfs diff=lfs merge=lfs -text
 soDLA-publishment_soDLA/sodla-wrapper/src/main/resources/SO_small.v filter=lfs diff=lfs merge=lfs -text
 soDLA-publishment_soDLA/sodla.v filter=lfs diff=lfs merge=lfs -text
+wuxx_icesugar-pro/src/litex_linux/top.json filter=lfs diff=lfs merge=lfs -text

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/LICENSE.md

@@ -0,0 +1,196 @@
+Some of the files provided with the Opencores.org files contain thier own licenses. 
+Those licenses continue and you must respect them. 
+
+This license below is only for the files which are NOT covered by those licences. 
+IE : All the examples in the Book_EXAMPLES directory and sub directories
+and all examples in the soc/tb/uvm/* directories.
+
+Permission is granted as per the Apache license below With an Additional restriction.  Please respect our copyrights and not 
+remove any notices or alter the copyright in any way. The examples are meant for your own
+study and to further your knowledge of UVM. 
+
+Please DO NOT POST the contents of these examples on any other website. 
+
+
+
+(c) Srivatsa Vasudevan 2011-2016. All rights reserved.
+
+
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
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+   END OF TERMS AND CONDITIONS
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/README.md

@@ -0,0 +1,41 @@
+Note: 
+There were some typos in the code for the uvm_utilities in the BOOK print COPY.
+These were actually  fixed in the code. The wrong files got picked up.
+
+
+------------------------------------
+
+The examples for Part 1 of the book are in the subdirectories below this directory.
+There are 3 makefiles in the run directory. One for each simulator. 
+
+Please note that I have not provided log files for the other two simulators in the run directory for a number of reasons. 
+The makefiles for the Questa and IUS simulators were provided by Srinivasan Venkataraman of CVC Bangalore.  srini@cvcblr.com
+I am grateful to him for making the contribution. 
+
+The make files for  the VCS simulator have been validated and provided in the run directory along with log files. 
+
+I appeal to the community at large to run these examples, make any necessary tweaks for the other simulators and share thier log files.
+The contribution of the log files will be gratefully appreciated.
+
+
+
+Please note: 
+For IUS and Questa:
+You may need to set the environment variable UVM_HOME to an area where you have the UVM tarball downloaded.  That is NOT in the makefile
+The simulator may provide a setting and I invite you to check on that in the documentation. 
+If you are not sure, you can download the tarball from: http://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz
+explode it and set UVM_HOME to the location of the src/ subdirectory.
+
+For the VCS simulator, it is set to the inbuilt copy of UVM bundled with VCS. 
+
+Please let me know of any problems with these files so that I can correct them.
+if anything is wrong with these instructions for Questa and IUS, and you figure it out, please let me know what the changes are and I will incorporate them
+into the main repository.
+
+Thanks!
+Srivatsa 
+July 2018
+
+
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/run/vc_hdrs.h

@@ -0,0 +1,81 @@
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+#include <stdio.h>
+#include <dlfcn.h>
+#include "svdpi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _VC_TYPES_
+#define _VC_TYPES_
+/* common definitions shared with DirectC.h */
+
+typedef unsigned int U;
+typedef unsigned char UB;
+typedef unsigned char scalar;
+typedef struct { U c; U d;} vec32;
+
+#define scalar_0 0
+#define scalar_1 1
+#define scalar_z 2
+#define scalar_x 3
+
+extern long long int ConvUP2LLI(U* a);
+extern void ConvLLI2UP(long long int a1, U* a2);
+extern long long int GetLLIresult();
+extern void StoreLLIresult(const unsigned int* data);
+typedef struct VeriC_Descriptor *vc_handle;
+
+#ifndef SV_3_COMPATIBILITY
+#define SV_STRING const char*
+#else
+#define SV_STRING char*
+#endif
+
+#endif /* _VC_TYPES_ */
+
+
+ extern int uvm_hdl_check_path(/* INPUT */const char* path);
+
+ extern int uvm_hdl_deposit(/* INPUT */const char* path, const /* INPUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_force(/* INPUT */const char* path, const /* INPUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_release_and_read(/* INPUT */const char* path, /* INOUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_release(/* INPUT */const char* path);
+
+ extern int uvm_hdl_read(/* INPUT */const char* path, /* OUTPUT */svLogicVecVal *value);
+
+ extern SV_STRING uvm_hdl_read_string(/* INPUT */const char* path);
+
+ extern int uvm_memory_load(/* INPUT */const char* nid, /* INPUT */const char* scope, /* INPUT */const char* fileName, /* INPUT */const char* radix, /* INPUT */const char* startaddr, /* INPUT */const char* endaddr, /* INPUT */const char* types);
+
+ extern SV_STRING uvm_dpi_get_next_arg_c(/* INPUT */int init);
+
+ extern SV_STRING uvm_dpi_get_tool_name_c();
+
+ extern SV_STRING uvm_dpi_get_tool_version_c();
+
+ extern void* uvm_dpi_regcomp(/* INPUT */const char* regex);
+
+ extern int uvm_dpi_regexec(/* INPUT */void* preg, /* INPUT */const char* str);
+
+ extern void uvm_dpi_regfree(/* INPUT */void* preg);
+
+ extern int uvm_re_match(/* INPUT */const char* re, /* INPUT */const char* str);
+
+ extern void uvm_dump_re_cache();
+
+ extern SV_STRING uvm_glob_to_re(/* INPUT */const char* glob);
+
+ extern void m__uvm_report_dpi(/* INPUT */int severity, /* INPUT */const char* id, /* INPUT */const char* message, /* INPUT */int verbosity, /* INPUT */const char* filename, /* INPUT */int line);
+void SdisableFork();
+
+#ifdef __cplusplus
+}
+#endif
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/class.sv

@@ -0,0 +1,129 @@
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+        longint	unsigned logic_data[*];
+
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON)
+			`uvm_field_string(cl_string,UVM_ALL_ON)
+			`uvm_field_array_int(cl_int_arr,UVM_ALL_ON)
+			`uvm_field_aa_int_longint_unsigned(logic_data,UVM_ALL_ON)
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			int idx = 1;
+			super.new(name);	
+			cl_string = name;
+			cl_int = 10;
+	 		cl_int_arr = new[cl_int];
+			for(int i = 0; i < cl_int; i++) begin
+				cl_int_arr[i] = i + 1;
+			end
+			repeat (16) begin
+				logic_data[idx] = idx;
+				idx = idx << 1;
+			end
+		endfunction
+
+endclass
+
+		
+class  class_P extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_P)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON  )
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON|UVM_NOCOPY)
+		`uvm_field_object(cl3,UVM_ALL_ON|UVM_REFERENCE)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name )	;
+	par_string  = name;
+  endfunction
+	
+
+    function void do_copy(uvm_object rhs);
+	class_P rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+   endfunction
+
+     virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer);
+
+
+	endfunction
+endclass
+
+class  class_Pass2 extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_Pass2)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON | UVM_NOCOPY)
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON)
+		`uvm_field_object(cl3,UVM_ALL_ON|UVM_SHALLOW)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name );
+	par_string  = name;
+  endfunction
+	
+
+    function void do_copy(uvm_object rhs);
+	class_Pass2 rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+     par_int = rhs_.par_int;
+     par_address = rhs_.par_address;
+     par_string = rhs_.par_string;
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+   endfunction
+	
+     virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer);
+	class_P rhs_;	
+	do_compare = super.do_compare(rhs,comparer);
+	$cast(rhs_,rhs);
+	do_compare &= comparer.compare_field_int("par_int",par_int,rhs_.par_int,32,UVM_NORADIX);
+	do_compare &= comparer.compare_field_int("par_address",par_int,rhs_.par_int,32,UVM_NORADIX);
+	do_compare &= comparer.compare_string("par_string",par_string,rhs_.par_string);
+	do_compare &= comparer.compare_object("cl1",cl1,rhs_.cl1);
+	do_compare &= comparer.compare_object("cl1",cl3,rhs_.cl3);
+	endfunction
+
+
+endclass
+
+	

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/clone.sv

@@ -0,0 +1,41 @@
+module top;
+import uvm_pkg::*;
+typedef class class_A;
+
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON);
+			`uvm_field_string(cl_string,UVM_ALL_ON);
+			`uvm_field_array_int(cl_int_arr,UVM_ALL_ON);
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			super.new(name);	
+			cl_string = name;
+			cl_int = 11;
+	 		cl_int_arr = new[cl_int];
+			for(int i = 0; i < cl_int; i++) begin
+				cl_int_arr[i] = i + 1;
+			end
+		endfunction
+
+endclass
+
+ class_A    class_A_inst1;
+ class_A    class_A_inst2;
+initial begin
+	// free children
+	class_A_inst1 = new("child_inst1",1);
+
+	class_A_inst1.randomize();
+	class_A_inst1.print();
+	$cast(class_A_inst2,class_A_inst1.clone());
+	class_A_inst1.print();
+
+ end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/compare2.sv

@@ -0,0 +1,44 @@
+module top;
+`include "uvm_macros.svh"
+   import uvm_pkg::*;
+
+`include "class2_1.sv"
+   
+
+   class_B  class_B_inst1;
+   class_B  class_B_inst2;
+   class_A    class_A_inst1;
+   class_A    class_A_inst2;
+
+class custom_comparer extends uvm_comparer;
+
+   int 	   unsigned show_max = 10;
+   int 	   unsigned verbosity = UVM_WARNING;
+   string  miscompares  = "srivatsa %m";
+   
+endclass
+
+   custom_comparer c_comp = new();
+   initial begin
+      // free children
+      class_A_inst1 = new("A_inst1");
+      class_A_inst2 = new("A_inst2");
+
+      // Custom Comparison:
+
+      class_A_inst1.randomize();
+      
+      class_A_inst2.randomize();
+      class_A_inst2.copy(class_A_inst1);
+      `uvm_info("Compare 1","comparison of identical classes",UVM_LOW)
+      class_A_inst1.compare(class_A_inst2, c_comp);
+      
+      class_A_inst1.logic_data[16 ] = 2;
+      class_A_inst1.logic_data[32 ] = 2;
+      // class_A_inst1.logic_data[64] = 2;
+      class_A_inst1.logic_data[128] = 1;
+      `uvm_info("Compare 2","comparison of nonidentical classes",UVM_LOW)
+      class_A_inst1.compare(class_A_inst2, c_comp);
+
+   end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/compare_ex.sv

@@ -0,0 +1,69 @@
+/* This example illustrates a custom comparer
+ * and the copy operation 
+ */
+
+module top;
+`include "uvm_macros.svh"
+import uvm_pkg::*;
+	
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+        longint	unsigned logic_data[*];
+
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON)
+			`uvm_field_string(cl_string,UVM_ALL_ON)
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			int idx = 1;
+			super.new(name);	
+			cl_string = name;
+		endfunction
+
+endclass
+
+		
+
+ class_A    class_A_inst1;
+ class_A    class_A_inst2;
+
+class custom_comparer extends uvm_comparer;
+
+	int unsigned show_max = 10;
+        int unsigned verbosity = UVM_WARNING;
+	string miscompares  = "srivatsa %m";
+	
+endclass
+
+custom_comparer c_comp = new();
+initial begin
+	// free children
+	//class_A_inst1 = new("child_inst1");
+//	class_A_inst2 = new("child_inst2");
+
+	class_A_inst1 = class_A::type_id::create("child_inst1");
+	class_A_inst2 = class_A::type_id::create("child_inst2");
+	// Custom Comparison:
+
+	class_A_inst1.randomize();
+	
+	class_A_inst2.randomize();
+	class_A_inst2.copy(class_A_inst1);
+	
+	class_A_inst1.logic_data[16 ] = 2;
+	class_A_inst1.logic_data[32 ] = 2;
+	class_A_inst1.logic_data[64] = 2;
+	class_A_inst1.logic_data[128] = 1;
+	 class_A_inst1.print();
+	 class_A_inst2.print();
+      class_A_inst1.compare(class_A_inst2, c_comp);
+
+
+
+ end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/completed_class.sv

@@ -0,0 +1,140 @@
+
+module top;
+   import uvm_pkg::*;
+
+   // Class definition
+class class_A extends uvm_object;
+
+   int cl_int;
+   string cl_string;
+   int 	  cl_int_arr[];
+   int 	  logic_data[int];
+
+   `uvm_object_utils_begin(class_A)
+      `uvm_field_int(cl_int,UVM_ALL_ON)
+      `uvm_field_string(cl_string,UVM_ALL_ON)
+      `uvm_field_array_int(cl_int_arr,UVM_ALL_ON)
+      `uvm_field_aa_int_int(logic_data,UVM_ALL_ON)
+   `uvm_object_utils_end
+   
+   function new(string name="");
+      int idx = 1;
+      super.new(name);	
+      cl_string = name;
+      cl_int = 10;
+      cl_int_arr = new[cl_int];
+      for(int i = 0; i < cl_int; i++) begin
+	 cl_int_arr[i] = i + 1;
+      end
+      repeat (16) begin
+	 logic_data[idx] = idx;
+	 idx = idx << 1;
+      end
+   endfunction
+
+endclass
+
+class  class_B extends uvm_object;
+
+   // basic datatypes
+   rand int par_int;  int inst_id = 10;
+   rand byte par_address;
+   string par_string;
+   logic [3:0] bits_field;
+
+   // Some objects to demonstrate the copy recursion policy
+
+   class_A cl1; // UVM_SHALLOW
+   class_A cl3; // UVM_DEEP
+
+   `uvm_object_utils_begin(class_B)
+      `uvm_field_int(par_int,UVM_ALL_ON|UVM_NOPACK)
+      `uvm_field_int(par_address,UVM_ALL_ON | UVM_NOCOPY|UVM_NOPACK)
+      `uvm_field_string(par_string,UVM_NOCOPY|UVM_NOPACK)
+      `uvm_field_object(cl1,UVM_ALL_ON|UVM_NOPACK)
+      `uvm_field_object(cl3,UVM_ALL_ON|UVM_SHALLOW|UVM_NOPACK)
+      `uvm_field_int(bits_field,UVM_ALL_ON|UVM_NOPACK)
+   `uvm_object_utils_end
+
+   function new(string name="");
+      super.new(name);
+
+      cl1 = new(name,10);
+      cl3 = new(name,11 )	;
+      par_string  = name;
+      bits_field = inst_id;
+   endfunction
+   
+
+   function void do_copy(uvm_object rhs);
+      class_B rhs_;
+      super.do_copy(rhs);
+      $cast(rhs_,rhs);
+      par_int = rhs_.par_int;
+      par_address = rhs_.par_address;
+      par_string = rhs_.par_string;
+      cl1 = new rhs_.cl1;
+      cl3 = new rhs_.cl3;
+      bits_field = rhs_.bits_field;
+   endfunction
+   
+   virtual     function bit do_compare(uvm_object rhs, uvm_comparer comparer);
+      class_B rhs_;	
+      do_compare = super.do_compare(rhs,comparer);
+      $cast(rhs_,rhs);
+      do_compare &= comparer.compare_field_int("par_int",par_int,rhs_.par_int,32,UVM_NORADIX);
+      do_compare &= comparer.compare_field_int("par_address",par_int,rhs_.par_int,32,UVM_NORADIX);
+      do_compare &= comparer.compare_string("par_string",par_string,rhs_.par_string);
+      do_compare &= comparer.compare_object("cl1",cl1,rhs_.cl1);
+      do_compare &= comparer.compare_object("cl1",cl3,rhs_.cl3);
+      do_compare &= comparer.compare_field("bits_field",bits_field,rhs_.bits_field,$bits(bits_field),UVM_NORADIX);
+   endfunction
+
+   function void do_pack (uvm_packer packer);
+      super.do_pack(packer);
+      packer.pack_field_int(par_int,32);
+      packer.pack_field_int(par_address,8);
+      packer.pack_string(par_string);
+      packer.pack_object(cl1);
+      packer.pack_object(cl3);
+      packer.pack_field(bits_field,$bits(bits_field));
+   endfunction
+
+   function void do_unpack (uvm_packer packer);
+      super.do_unpack(packer);
+      par_int = packer.unpack_field_int(32);
+      par_address = packer.unpack_field_int(8);
+      par_string = packer.unpack_string(-1);
+      packer.unpack_object(cl1);
+      packer.unpack_object(cl3);
+      bits_field = packer.unpack_field($bits(bits_field));
+   endfunction
+endclass
+
+   bit 	       pack_bytes[];
+   class_B  class_B_inst1;
+   class_B  class_B_inst2;
+   initial begin
+      // free children
+
+      class_B_inst1 = new("first_inst");
+      class_B_inst1.randomize();
+      `uvm_info("top", "Printing class_B_inst1",UVM_LOW)	
+      class_B_inst1.print();
+
+      uvm_default_packer.use_metadata = 1;
+      class_B_inst1.pack(pack_bytes);
+
+      class_B_inst2 = new("second_inst");
+      //      class_B_inst2.randomize();
+      `uvm_info("top", "Printing class_B_inst2",UVM_LOW)	
+      class_B_inst2.print();
+
+      class_B_inst2.unpack(pack_bytes);
+      `uvm_info("top", "Printing class_B_inst2 after unpack",UVM_LOW)	
+      class_B_inst2.print();
+
+   end
+endmodule
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/copy.sv

@@ -0,0 +1,99 @@
+module top;
+import uvm_pkg::*;
+typedef class class_A;
+
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON);
+			`uvm_field_string(cl_string,UVM_ALL_ON);
+			`uvm_field_array_int(cl_int_arr,UVM_ALL_ON);
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			super.new(name);	
+			cl_string = name;
+			cl_int = 10;
+	 		cl_int_arr = new[cl_int];
+			for(int i = 0; i < cl_int; i++) begin
+				cl_int_arr[i] = i + 1;
+			end
+		endfunction
+
+endclass
+
+		
+class  class_P extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_P)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON | UVM_NOCOPY)
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON|UVM_NOCOPY)
+		`uvm_field_object(cl3,UVM_ALL_ON | UVM_NOCOPY)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name )	;
+	par_string  = name;
+  endfunction
+	
+    function void do_copy(uvm_object rhs);
+	class_P rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+     par_int = rhs_.par_int;
+     par_address = rhs_.par_address;
+     par_string = rhs_.par_string;
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+	cl1.copy(rhs_.cl1);
+        cl3.copy(rhs_.cl3);
+   endfunction
+
+
+endclass
+
+	
+
+ class_P  class_P_inst1;
+ class_P  class_P_inst2;
+ class_A    class_A_inst1;
+ class_A    class_A_inst2;
+initial begin
+	// free children
+	class_A_inst1 = new("child_inst1");
+	class_A_inst2 = new("child_inst3");
+
+
+
+ 	class_P_inst1 = new("first_inst");
+	class_P_inst1.randomize();
+	class_P_inst1.print();
+	
+ 	class_P_inst2 = new("second_inst");
+	class_P_inst2.randomize();
+	class_P_inst2.print();
+
+
+	class_P_inst2.copy(class_P_inst1);
+	class_P_inst2.print();
+
+ end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/copy_ex.sv

@@ -0,0 +1,109 @@
+module top;
+`include "uvm_macros.svh"
+import uvm_pkg::*;
+typedef class class_A;
+
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON);
+			`uvm_field_string(cl_string,UVM_ALL_ON);
+			`uvm_field_array_int(cl_int_arr,UVM_ALL_ON);
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			super.new(name);	
+			cl_string = name;
+			cl_int = 10;
+	 		cl_int_arr = new[cl_int];
+			for(int i = 0; i < cl_int; i++) begin
+				cl_int_arr[i] = i + 1;
+			end
+		endfunction
+
+endclass
+
+		
+class  class_P extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_P)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON | UVM_NOCOPY)
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON|UVM_NOCOPY)
+		`uvm_field_object(cl3,UVM_ALL_ON | UVM_NOCOPY)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name);
+	par_string  = name;
+  endfunction
+	
+    function void do_copy(uvm_object rhs);
+	class_P rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+     par_int = rhs_.par_int;
+     par_address = rhs_.par_address;
+     par_string = rhs_.par_string;
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+	cl1.copy(rhs_.cl1);
+        cl3.copy(rhs_.cl3);
+   endfunction
+
+
+endclass
+
+	
+
+ class_P  class_P_inst1;
+ class_P  class_P_inst2;
+ class_A    class_A_inst1;
+ class_A    class_A_inst2;
+initial begin
+	// free children
+	class_A_inst1 = new("child_inst1");
+	class_A_inst2 = new("child_inst3");
+
+
+
+ 	class_P_inst1 = new("first_inst");
+	class_P_inst1.randomize();
+	class_P_inst1.print();
+	
+ 	class_P_inst2 = new("second_inst");
+	class_P_inst2.randomize();
+	class_P_inst2.print();
+
+
+	class_P_inst2.copy(class_P_inst1);
+	class_P_inst2.print();
+
+/*	
+	class_A_inst1.randomize();
+	class_A_inst1.print();
+	class_A_inst2.randomize();
+	class_A_inst2.print();
+	class_A_inst2.copy(class_A_inst1);
+	class_A_inst1.print();
+*/	 
+
+ end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/copy_obj.sv

@@ -0,0 +1,41 @@
+module top;
+`include "uvm_macros.svh"
+import uvm_pkg::*;
+typedef class class_A;
+
+`include "class4.sv"
+	
+
+ class_P  class_P_inst1;
+ class_P  class_P_inst2;
+ class_A    class_A_inst1;
+ class_A    class_A_inst2;
+
+class custom_comparer extends uvm_comparer;
+
+	int unsigned show_max = 10;
+	int unsigned  verbosity = UVM_MEDIUM;
+	uvm_severity sev = UVM_FATAL;
+	string miscompares  = " this is a extended miscompare:";
+endclass
+
+custom_comparer c_comp = new();
+initial begin
+	// free children
+
+
+	 class_P_inst1 = new ("class_Pass1",1);
+	 class_P_inst2 = new ("class_Pass2",3);
+
+	// Custom Comparison:
+
+	class_P_inst1.randomize();
+	class_P_inst2.randomize();
+
+	class_P_inst2.copy(class_P_inst1);
+	
+ 	class_P_inst2.compare(class_P_inst1);
+
+
+ end 
+endmodule

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/listing_2.1.sv

@@ -0,0 +1,17 @@
+class classA_cl extends uvm_object;
+
+   int addr;
+   int cl_int;
+   string cl_string;
+   int 	  cl_int_arr[];
+   
+   function new(string name="");
+      super.new(name);	
+      cl_string = name;
+      cl_int = 10;
+      cl_int_arr = new[cl_int];
+      for(int i = 0; i < cl_int; i++) begin
+	 cl_int_arr[i] = i + 1;
+      end
+   endfunction
+endclass

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/listing_2.10.sv

@@ -0,0 +1,51 @@
+class  class_B2 extends uvm_object;
+
+   // basic datatypes
+   rand int par_int; 
+   rand byte par_address;
+   string par_string;
+   logic [3:0] bits_field;
+
+   // Some objects to demonstrate the copy recursion policy
+
+   child_cl cl1; // UVM_SHALLOW
+   child_cl cl3; // UVM_DEEP
+
+   `uvm_object_utils_begin(class_B2)
+      `uvm_field_int(par_int,UVM_DEFAULT|UVM_NOPACK)
+      `uvm_field_int(par_address,UVM_DEFAULT | UVM_NOCOPY|UVM_NOPACK)
+      `uvm_field_string(par_string,UVM_NOCOPY|UVM_NOPACK)
+      `uvm_field_object(cl1,UVM_DEFAULT|UVM_NOPACK)
+      `uvm_field_object(cl3,UVM_DEFAULT|UVM_SHALLOW|UVM_NOPACK)
+      `uvm_field_int(bits_field,UVM_DEFAULT|UVM_NOPACK)
+   `uvm_object_utils_end
+
+   function new(string name="");
+      super.new(name);
+      cl1 = new(name);
+      cl3 = new(name )	;
+      par_string  = name;
+      bits_field = inst_id;
+   endfunction
+
+   function void do_pack (uvm_packer packer);
+      super.do_pack(packer);
+      packer.pack_field_int(par_int,32);
+      packer.pack_field_int(par_address,8);
+      packer.pack_string(par_string);
+      packer.pack_object(cl1);
+      packer.pack_object(cl3);
+      packer.pack_field(bits_field,$bits(bits_field));
+   endfunction
+
+   function void do_unpack (uvm_packer packer);
+      super.do_unpack(packer);
+      par_int = packer.unpack_field_int(32);
+      par_address = packer.unpack_field_int(8);
+      par_string = packer.unpack_string(-1);
+      packer.unpack_object(cl1);
+      packer.unpack_object(cl3);
+      bits_field = packer.unpack_field($bits(bits_field));
+   endfunction
+endclass
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/listing_2.2.sv

@@ -0,0 +1,22 @@
+class  classB_cl extends uvm_object;
+
+   // basic datatypes
+   rand int par_int; 
+   rand byte par_address;
+   string par_string;
+
+   // Some objects to demonstrate the copy recursion policy
+
+   classA_cl cl1; // UVM_SHALLOW
+   classA_cl cl3; // UVM_DEEP
+
+   function new(string name="");
+      super.new(name);
+      cl1 = new("cl1_inst");
+      cl3 = new("cl3_inst")	;
+      par_string  = name;
+   endfunction
+   
+endclass
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/new_packer.sv

@@ -0,0 +1,176 @@
+
+module top;
+import uvm_pkg::*;
+
+// Class definition
+class class_A extends uvm_object;
+
+ 	int cl_int;
+	string cl_string;
+	int cl_int_arr[];
+        longint	unsigned logic_data[*];
+
+	 `uvm_object_utils_begin(class_A)
+			`uvm_field_int(cl_int,UVM_ALL_ON)
+			`uvm_field_string(cl_string,UVM_ALL_ON)
+			`uvm_field_array_int(cl_int_arr,UVM_ALL_ON)
+			`uvm_field_aa_int_longint_unsigned(logic_data,UVM_ALL_ON)
+	`uvm_object_utils_end
+		
+		function new(string name="");
+			int idx = 1;
+			super.new(name);	
+			cl_string = name;
+			cl_int = 10;
+	 		cl_int_arr = new[cl_int];
+			for(int i = 0; i < cl_int; i++) begin
+				cl_int_arr[i] = i + 1;
+			end
+			repeat (16) begin
+				logic_data[idx] = idx;
+				idx = idx << 1;
+			end
+		endfunction
+
+endclass
+
+		
+class  class_P extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_P)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON  )
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON|UVM_NOCOPY)
+		`uvm_field_object(cl3,UVM_ALL_ON|UVM_REFERENCE)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name )	;
+	par_string  = name;
+  endfunction
+	
+
+    function void do_copy(uvm_object rhs);
+	class_P rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+   endfunction
+
+     virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer);
+
+
+	endfunction
+endclass
+
+class  class_Pass2 extends uvm_object;
+
+// basic datatypes
+rand int par_int; 
+rand byte par_address;
+string par_string;
+
+// Some objects to demonstrate the copy recursion policy
+
+class_A cl1; // UVM_SHALLOW
+class_A cl3; // UVM_DEEP
+
+	`uvm_object_utils_begin(class_Pass2)
+		`uvm_field_int(par_int,UVM_ALL_ON)
+		`uvm_field_int(par_address,UVM_ALL_ON | UVM_NOCOPY)
+		`uvm_field_string(par_string,UVM_NOCOPY)
+		 `uvm_field_object(cl1,UVM_ALL_ON)
+		`uvm_field_object(cl3,UVM_ALL_ON|UVM_SHALLOW)
+        `uvm_object_utils_end
+
+ function new(string name="");
+	super.new(name);
+	cl1 = new(name);
+  	cl3 = new(name )	;
+	par_string  = name;
+  endfunction
+	
+
+    function void do_copy(uvm_object rhs);
+	class_Pass2 rhs_;
+     super.do_copy(rhs);
+	$cast(rhs_,rhs);
+     par_int = rhs_.par_int;
+     par_address = rhs_.par_address;
+     par_string = rhs_.par_string;
+	cl1 = new rhs_.cl1;
+	cl3 = new rhs_.cl3;
+   endfunction
+	
+     virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer);
+	class_P rhs_;	
+	do_compare = super.do_compare(rhs,comparer);
+	$cast(rhs_,rhs);
+	do_compare &= comparer.compare_field_int("par_int",par_int,rhs_.par_int,32,UVM_NORADIX);
+	do_compare &= comparer.compare_field_int("par_address",par_int,rhs_.par_int,32,UVM_NORADIX);
+	do_compare &= comparer.compare_string("par_string",par_string,rhs_.par_string);
+	do_compare &= comparer.compare_object("cl1",cl1,rhs_.cl1);
+	do_compare &= comparer.compare_object("cl1",cl3,rhs_.cl3);
+	endfunction
+
+    function void do_pack (uvm_packer packer);
+	super.do_pack(packer);
+	packer.pack_field_int(par_int,32);
+	packer.pack_field_int(par_address,8);
+	packer.pack_string(par_string);
+	packer.pack_object(cl1);
+	packer.pack_object(cl3);
+    endfunction
+
+
+    function void do_unpack (uvm_packer packer);
+	super.do_unpack(packer);
+	par_int = packer.unpack_field_int(32);
+	par_address = packer.unpack_field_int(8);
+	par_string = packer.unpack_string(par_string);
+	packer.unpack_object(cl1);
+	packer.unpack_object(cl3);
+    endfunction
+endclass
+
+
+bit pack_bytes[];
+class_P  class_P_inst1;
+class_P  class_P_inst2;
+initial begin
+        // free children
+
+        class_P_inst1 = new("first_inst");
+        class_P_inst1.randomize();
+        class_P_inst1.print();
+
+        uvm_default_packer.use_metadata = 1;
+        class_P_inst1.pack(pack_bytes);
+
+
+        class_P_inst2 = new("second_inst");
+//      class_P_inst2.randomize();
+        class_P_inst2.print();
+
+        class_P_inst2.unpack(pack_bytes);
+        class_P_inst2.print();
+
+
+ end
+endmodule
+
+	

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_1/uvm_core_utilities/src/print.sv

@@ -0,0 +1,28 @@
+
+module top;
+import uvm_pkg::*;
+`include "class.sv"
+
+	uvm_line_printer local_line_printer = new;
+	uvm_tree_printer local_tree_printer = new;
+	uvm_table_printer local_table_printer = new;
+	UVM_FILE myfile;
+
+	class_A cl1 = new("Child Class");
+	initial begin
+		myfile = $fopen("Data","w");
+		//uvm_default_printer = uvm_default_table_printer; //default, so not needed.
+		cl1.print();
+		uvm_default_printer = uvm_default_line_printer;
+		cl1.print();
+		uvm_default_printer = uvm_default_tree_printer;
+		cl1.print();
+		local_table_printer.knobs.type_width = 20;
+		local_table_printer.knobs.header = 1;
+		local_table_printer.knobs.value_width = 20;
+		local_table_printer.knobs.mcd = myfile;
+		cl1.print(local_table_printer);
+	end
+endmodule
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/README.md

@@ -0,0 +1,64 @@
+This example is the main example upon which all the files are patterned. 
+So I have marked all the files in this example as being important.
+
+
+
+*************************************************************
+STEPS TO COMPILE AND RUN EXAMPLE
+*************************************************************
+
+Note: 
+  1) To include the UVM1.2 inbuilt source from VCS installation:
+     Inclusion of UVM_HOME can be replaced by -ntb_opts uvm command in Makefile
+  2) To use the UVM source other than VCS installation directory:
+     Set environment variable VCS_UVM_HOME to the uvm-1.2 installation directory
+
+*************************************************************
+Directory Structure of environment generated by UVMGEN
+*************************************************************
+-EXAMPLE
+  	|
+       -README.md ( This file)
+       |
+       -hdl/        ---> includes top module and inclusion of all environment files.
+       |
+       | - wb_env_top.sv  -- Top level file that instantiates everything
+       | - dut.v     -- Dummy DUT
+       |
+       -env/        ---> includes environment related files (environment, ralenv)
+       |  
+       | - wb_slave_agent.sv  -- top level slave agent file
+       | - wb_master_agent.sv -- top level master agent file
+       | - wb_env_env.sv      -- the complete environment
+       |
+       -include/
+       |
+       -src/        ---> includes Transaction, configurations, driver, monitor, master/slave subenv, scoreboard, coverage related files.
+       |  
+       | - wb_slave.sv     --- Slave driver
+       | - wb_slave_mon.sv  -- Slave monitor
+       | - wb_slave_if.sv   -- slave interface
+       | - wb_transaction.sv  -- transaction class
+       | - wb_slave_seqr.sv   -- Slave Sequencer. This is not used in this example
+       | - wb_master.sv     -- master driver
+       | - wb_master_seqr.sv  -- master sequencer
+       | - wb_master_agent_sequence_library.sv -- All the sequences for the master are HERE
+       | - wb_master_if.sv  -- master interface
+       | - wb_master_mon.sv  -- master monitor 
+       | - wb_env_cov.sv   -- coverage
+       | - wb_env_cfg.sv   -- env config class as an example. Not used much in the example
+       |
+       -tests/      ---> includes testbench module and testcases 
+       |
+       | - wb_env_tb_mod.sv 
+       | - wb_env_test.sv --- This is the actual test you need to look at 
+       |
+       -run/        ---> Makefile
+       | - Makefile   
+       | - simv.log -- run log file
+       | - vcs.log  -- compile log file
+
+
+
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/env/wb_env_env.sv

@@ -0,0 +1,50 @@
+`ifndef WB_ENV_ENV__SV
+`define WB_ENV_ENV__SV
+`include "wb_env.sv"
+class wb_env_env extends uvm_env;
+   wb_master_agent master_agent;
+   wb_slave_agent slave_agent;
+    wb_env_cov cov;
+   
+   wb_master_mon_2cov_connect mon2cov;
+   wb_scoreboard sb;
+   `uvm_component_utils(wb_env_env)
+
+   extern function new(string name="wb_env_env", uvm_component parent=null);
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual function void report_phase(uvm_phase phase);
+
+endclass: wb_env_env
+
+function wb_env_env::new(string name= "wb_env_env",uvm_component parent=null);
+   super.new(name,parent);
+endfunction:new
+
+function void wb_env_env::build_phase(uvm_phase phase);
+   super.build_phase(phase);
+   master_agent = wb_master_agent::type_id::create("master_agent",this); 
+   slave_agent = wb_slave_agent::type_id::create("slave_agent",this);
+ 
+    cov = wb_env_cov::type_id::create("cov",this); //Instantiating the coverage class
+
+    mon2cov  = wb_master_mon_2cov_connect::type_id::create("mon2cov", this);
+    mon2cov.cov = cov;
+	 sb = wb_scoreboard::type_id::create("sb",this);
+
+endfunction: build_phase
+
+function void wb_env_env::connect_phase(uvm_phase phase);
+   super.connect_phase(phase);
+   master_agent.mast_mon.mon_analysis_port.connect(cov.cov_export);
+  master_agent.mast_mon.mon_analysis_port.connect(sb.expected_wb_transaction_fifo.analysis_export);
+   slave_agent.slv_mon.mon_analysis_port.connect(sb.actual_wb_transaction_fifo.analysis_export);
+
+endfunction: connect_phase
+
+function void wb_env_env::report_phase(uvm_phase phase);
+   super.report_phase(phase);
+endfunction:report_phase
+
+`endif // WB_ENV_ENV__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/env/wb_master_agent.sv

@@ -0,0 +1,80 @@
+//
+// Template for UVM-compliant generic master agent
+//
+
+`ifndef WB_MASTER_AGENT__SV
+ `define WB_MASTER_AGENT__SV
+
+
+class wb_master_agent extends uvm_agent;
+   // ToDo: add uvm agent properties here
+   protected uvm_active_passive_enum is_active = UVM_ACTIVE;
+   wb_master_seqr mast_sqr;
+   wb_master mast_drv;
+   wb_master_mon mast_mon;
+   typedef virtual wb_master_if vif;
+   vif mast_agt_if; 
+   wb_config mstr_agent_cfg;
+
+
+   `uvm_component_utils_begin(wb_master_agent)
+      `uvm_field_object(mast_sqr, UVM_DEFAULT)
+      `uvm_field_object(mast_drv, UVM_DEFAULT)
+      `uvm_field_object(mast_mon, UVM_DEFAULT)
+      `uvm_field_object (mstr_agent_cfg,UVM_DEFAULT)
+   `uvm_component_utils_end
+
+   // ToDo: Add required short hand override method
+
+   function new(string name = "mast_agt", uvm_component parent = null);
+      super.new(name, parent);
+   endfunction
+
+   virtual function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      uvm_config_db #(wb_config)::get(this, "", "config", mstr_agent_cfg);
+
+      mast_mon = wb_master_mon::type_id::create("mast_mon", this);
+      if (is_active == UVM_ACTIVE) begin
+         mast_sqr = wb_master_seqr::type_id::create("mast_sqr", this);
+         mast_drv = wb_master::type_id::create("mast_drv", this);
+	 mast_drv.mstr_drv_cfg = mstr_agent_cfg;
+         mast_sqr.cfg = mstr_agent_cfg;
+	 mast_mon.mstr_mon_cfg = mstr_agent_cfg;
+
+      end
+      if (!uvm_config_db#(vif)::get(this, "", "mst_if", mast_agt_if)) begin
+         `uvm_fatal("AGT/NOVIF", "No virtual interface specified for this agent instance Master Agent")
+      end
+      uvm_config_db# (vif)::set(this,"mast_drv","mst_if",mast_agt_if);
+      uvm_config_db# (vif)::set(this,"mast_mon","mon_if",mast_agt_if);
+
+      // Now getting the configuration
+   endfunction: build_phase
+
+   virtual function void connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if (is_active == UVM_ACTIVE) begin
+   	 mast_drv.seq_item_port.connect(mast_sqr.seq_item_export);
+      end
+   endfunction
+
+   virtual task run_phase(uvm_phase phase);
+      super.run_phase(phase);
+      phase.raise_objection(this,"master_agt_run");
+
+      //ToDo :: Implement here
+
+      phase.drop_objection(this);
+   endtask
+
+   virtual function void report_phase(uvm_phase phase);
+      super.report_phase(phase);
+
+
+   endfunction
+
+endclass: wb_master_agent
+
+`endif // WB_MASTER_AGENT__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/env/wb_slave_agent.sv

@@ -0,0 +1,67 @@
+`ifndef WB_SLAVE_AGENT__SV
+ `define WB_SLAVE_AGENT__SV
+
+typedef class wb_slave_seqr;
+class wb_slave_agent extends uvm_agent;
+   protected uvm_active_passive_enum is_active = UVM_ACTIVE;
+   wb_slave slv_drv;
+   wb_slave_mon slv_mon;
+   wb_slave_seqr slv_seqr;
+   typedef virtual wb_slave_if vif;
+   vif slv_agt_if;
+
+   wb_config slv_agent_cfg;
+
+   `uvm_component_utils_begin(wb_slave_agent)
+      `uvm_field_object(slv_seqr, UVM_DEFAULT)
+      `uvm_field_object(slv_drv, UVM_DEFAULT)
+      `uvm_field_object(slv_mon, UVM_DEFAULT)
+   `uvm_component_utils_end
+
+
+   function new(string name = "slv_agt", uvm_component parent = null);
+      super.new(name, parent);
+   endfunction
+
+   virtual function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      uvm_config_db #(wb_config)::get(this, "", "config", slv_agent_cfg);
+
+      slv_mon = wb_slave_mon::type_id::create("slv_mon", this);
+      if (is_active == UVM_ACTIVE) begin
+         slv_seqr = wb_slave_seqr::type_id::create("slv_seqr",this);
+         slv_drv = wb_slave::type_id::create("slv_drv", this);
+ 	 slv_drv.wb_slave_cfg  = slv_agent_cfg;
+	 slv_mon.slv_mon_cfg = slv_agent_cfg;
+      end
+      if (!uvm_config_db#(vif)::get(this, "", "slv_if", slv_agt_if)) begin
+         `uvm_fatal("AGT/NOVIF", "No virtual interface specified for this agent instance")
+      end
+      uvm_config_db# (vif)::set(this,"slv_drv","slv_if",slv_agt_if);
+      uvm_config_db# (vif)::set(this,"slv_mon","mon_if",slv_agt_if);
+   endfunction: build_phase
+
+   virtual function void connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if (is_active == UVM_ACTIVE) begin
+	 slv_drv.seq_item_port.connect(slv_seqr.seq_item_export);
+	 slv_seqr.m_getp.connect(slv_drv.getp);
+      end
+   endfunction
+
+
+   virtual task run_phase(uvm_phase phase);
+      super.run_phase(phase);
+      phase.raise_objection(this,"slv_agt_main");
+
+
+      phase.drop_objection(this);
+   endtask
+
+   virtual function void report_phase(uvm_phase phase);
+      super.report_phase(phase);
+   endfunction
+
+endclass: wb_slave_agent
+
+`endif // WB_SLAVE_AGENT__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/hdl/design.sv

@@ -0,0 +1,71 @@
+/*
+`include "wb_master_if.sv"
+`include "wb_slave_if.sv"
+`ifndef WB_ENV_TOP__SV
+ `define WB_ENV_TOP__SV
+
+module wb_env_top_mod();
+
+   logic clk;
+   logic rst;
+
+   // Clock Generation
+   parameter sim_cycle = 10;
+   // Reset Delay Parameter
+   parameter rst_delay = 5;
+   initial begin 
+      clk  = 0;
+      forever clk = #(sim_cycle/2) ~clk;
+      #10000 $finish;
+   end 
+
+   wb_master_if mast_if(clk,rst);
+   wb_slave_if slave_if(clk,rst);
+
+   wb_env_tb_mod test(); 
+
+   dut dut(mast_if,slave_if);
+
+   //Driver reset depending on rst_delay
+   initial
+     begin
+        clk = 0;
+        rst = 0;
+	#1 rst = 1;
+        repeat (rst_delay) @(clk);
+        rst = 1'b0;
+        @(clk);
+     end
+
+endmodule: wb_env_top_mod
+
+`endif // WB_ENV_TOP__SV
+
+module dut(wb_master_if mast_if, wb_slave_if slave_if);
+
+   assign slave_if.CYC_I = mast_if.CYC_O;
+
+   assign slave_if.DAT_I = mast_if.DAT_O;
+   assign mast_if.DAT_I = slave_if.DAT_O;
+
+   assign slave_if.TGD_I = mast_if.TGD_O;
+   assign mast_if.TGD_I = slave_if.TGD_O;
+
+   assign mast_if.ACK_I = slave_if.ACK_O;
+
+   assign slave_if.ADR_I = mast_if.ADR_O;
+   assign mast_if.ERR_I = slave_if.ERR_O;
+   assign slave_if.LOCK_I = mast_if.LOCK_O;
+   assign slave_if.SEL_I = mast_if.SEL_O;
+   assign slave_if.STB_I = mast_if.STB_O;
+   assign slave_if.TGA_I = mast_if.TGA_O;
+   assign slave_if.TGC_I = mast_if.TGC_O;
+   assign slave_if.WE_I = mast_if.WE_O;
+   assign mast_if.RTY_I = slave_if.RTY_O;
+   assign mast_if.RST_I = 1;
+   assign slave_if.RST_I = 1;
+
+
+endmodule
+*/
+// Code your design here

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/hdl/dut2.sv

@@ -0,0 +1,27 @@
+module dut(wb_master_if mast_if, wb_slave_if slave_if);
+
+   assign slave_if.CYC_I = mast_if.CYC_O;
+
+   assign slave_if.DAT_I = mast_if.DAT_O;
+   assign mast_if.DAT_I = slave_if.DAT_O;
+
+   assign slave_if.TGD_I = mast_if.TGD_O;
+   assign mast_if.TGD_I = slave_if.TGD_O;
+
+   assign mast_if.ACK_I = slave_if.ACK_O;
+
+   assign slave_if.ADR_I = mast_if.ADR_O;
+   assign mast_if.ERR_I = slave_if.ERR_O;
+   assign slave_if.LOCK_I = mast_if.LOCK_O;
+   assign slave_if.SEL_I = mast_if.SEL_O;
+   assign slave_if.STB_I = mast_if.STB_O;
+   assign slave_if.TGA_I = mast_if.TGA_O;
+   assign slave_if.TGC_I = mast_if.TGC_O;
+   assign slave_if.WE_I = mast_if.WE_O;
+   assign mast_if.RTY_I = slave_if.RTY_O;
+   assign mast_if.RST_I = 1;
+   assign slave_if.RST_I = 1;
+
+
+endmodule
+// Code your design here

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/hdl/wb_env_top.sv

@@ -0,0 +1,42 @@
+`include "wb_master_if.sv"
+`include "wb_slave_if.sv"
+`ifndef WB_ENV_TOP__SV
+ `define WB_ENV_TOP__SV
+
+module wb_env_top_mod();
+
+   logic clk;
+   logic rst;
+
+   // Clock Generation
+   parameter sim_cycle = 10;
+   // Reset Delay Parameter
+   parameter rst_delay = 5;
+   initial begin 
+      clk  = 0;
+      forever clk = #(sim_cycle/2) ~clk;
+      #10000 $finish;
+   end 
+
+   wb_master_if mast_if(clk,rst);
+   wb_slave_if slave_if(clk,rst);
+
+   wb_env_tb_mod test(); 
+
+   dut dut(mast_if,slave_if);
+
+   //Driver reset depending on rst_delay
+   initial
+     begin
+        clk = 0;
+        rst = 0;
+	#1 rst = 1;
+        repeat (rst_delay) @(clk);
+        rst = 1'b0;
+        @(clk);
+     end
+
+endmodule: wb_env_top_mod
+
+`endif // WB_ENV_TOP__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/include/wb_env.sv

@@ -0,0 +1,25 @@
+//
+// Template for UVM-compliant verification environment
+//
+
+`ifndef WB_ENV__SV
+`define WB_ENV__SV
+
+
+
+
+`include "mstr_slv_src.incl"
+
+`include "wb_env_cfg.sv"
+
+
+
+`include "wb_env_cov.sv"
+
+`include "mon_2cov.sv"
+`include "wb_scoreboard.sv"
+
+
+// ToDo: Add additional required `include directives
+
+`endif // WB_ENV__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/run/vc_hdrs.h

@@ -0,0 +1,77 @@
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+#include <stdio.h>
+#include <dlfcn.h>
+#include "svdpi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _VC_TYPES_
+#define _VC_TYPES_
+/* common definitions shared with DirectC.h */
+
+typedef unsigned int U;
+typedef unsigned char UB;
+typedef unsigned char scalar;
+typedef struct { U c; U d;} vec32;
+
+#define scalar_0 0
+#define scalar_1 1
+#define scalar_z 2
+#define scalar_x 3
+
+extern long long int ConvUP2LLI(U* a);
+extern void ConvLLI2UP(long long int a1, U* a2);
+extern long long int GetLLIresult();
+extern void StoreLLIresult(const unsigned int* data);
+typedef struct VeriC_Descriptor *vc_handle;
+
+#ifndef SV_3_COMPATIBILITY
+#define SV_STRING const char*
+#else
+#define SV_STRING char*
+#endif
+
+#endif /* _VC_TYPES_ */
+
+
+ extern int uvm_hdl_check_path(/* INPUT */const char* path);
+
+ extern int uvm_hdl_deposit(/* INPUT */const char* path, const /* INPUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_force(/* INPUT */const char* path, const /* INPUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_release_and_read(/* INPUT */const char* path, /* INOUT */svLogicVecVal *value);
+
+ extern int uvm_hdl_release(/* INPUT */const char* path);
+
+ extern int uvm_hdl_read(/* INPUT */const char* path, /* OUTPUT */svLogicVecVal *value);
+
+ extern SV_STRING uvm_dpi_get_next_arg_c(/* INPUT */int init);
+
+ extern SV_STRING uvm_dpi_get_tool_name_c();
+
+ extern SV_STRING uvm_dpi_get_tool_version_c();
+
+ extern void* uvm_dpi_regcomp(/* INPUT */const char* regex);
+
+ extern int uvm_dpi_regexec(/* INPUT */void* preg, /* INPUT */const char* str);
+
+ extern void uvm_dpi_regfree(/* INPUT */void* preg);
+
+ extern int uvm_re_match(/* INPUT */const char* re, /* INPUT */const char* str);
+
+ extern void uvm_dump_re_cache();
+
+ extern SV_STRING uvm_glob_to_re(/* INPUT */const char* glob);
+
+ extern void m__uvm_report_dpi(/* INPUT */int severity, /* INPUT */const char* id, /* INPUT */const char* message, /* INPUT */int verbosity, /* INPUT */const char* filename, /* INPUT */int line);
+void SdisableFork();
+
+#ifdef __cplusplus
+}
+#endif
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/mon_2cov.sv

@@ -0,0 +1,21 @@
+//
+// Template for UVM-compliant Monitor to Coverage Connector Callbacks
+//
+
+`ifndef WB_MASTER_MON_2COV_CONNECT
+`define WB_MASTER_MON_2COV_CONNECT
+class wb_master_mon_2cov_connect extends uvm_component;
+   wb_env_cov cov;
+   uvm_analysis_export # (wb_transaction) an_exp;
+   `uvm_component_utils(wb_master_mon_2cov_connect)
+   function new(string name="", uvm_component parent=null);
+   	super.new(name, parent);
+   endfunction: new
+
+   virtual function void write(wb_transaction tr);
+      cov.tr = tr;
+      -> cov.cov_event;
+   endfunction:write 
+endclass: wb_master_mon_2cov_connect
+
+`endif // WB_MASTER_MON_2COV_CONNECT

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_config.sv

@@ -0,0 +1,53 @@
+`ifndef WB_CONFIG
+ `define WB_CONFIG
+class wb_config extends uvm_object;
+
+   bit enable_coverage;  // Enable coverage from monitor
+
+   typedef enum {BYTE, WORD, DWORD, QWORD} sizes_e;
+   rand sizes_e port_size;
+   rand sizes_e granularity;
+
+   typedef enum {CLASSIC, REGISTERED} cycle_types_e;
+   rand cycle_types_e cycles;
+
+   rand integer max_n_wss;
+
+   rand bit [63:0] min_addr;
+   rand bit [63:0] max_addr;
+
+   constraint wb_slave_cfg_valid {
+      max_addr >= min_addr;
+
+   }
+
+   constraint wb_cfg_valid {
+      granularity <= port_size;
+      max_n_wss >= 0;
+   }
+
+   constraint reasonable_max_n_wss {
+      max_n_wss == 10;
+   }
+
+   constraint supported {
+      port_size   == DWORD;
+      granularity == BYTE; 
+      cycles      == CLASSIC;
+   }
+   `uvm_object_utils_begin(wb_config); // All we need is it registerd with factory
+      `uvm_field_enum(sizes_e,port_size,UVM_DEFAULT)
+      `uvm_field_enum(sizes_e,granularity,UVM_DEFAULT)
+      `uvm_field_enum(cycle_types_e,cycles,UVM_DEFAULT)
+      `uvm_field_int(max_n_wss,UVM_DEFAULT)
+      `uvm_field_int(min_addr,UVM_DEFAULT)
+      `uvm_field_int(max_addr,UVM_DEFAULT)
+   `uvm_object_utils_end
+
+
+   function new(string name = "");
+      super.new(name);
+   endfunction
+
+endclass
+`endif

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_env_cfg.sv

@@ -0,0 +1,30 @@
+`ifndef WB_ENV_CFG__SV
+ `define WB_ENV_CFG__SV
+
+class wb_env_cfg extends uvm_object; 
+
+   // Define test configuration parameters (e.g. how long to run)
+   rand int num_trans;
+   rand int num_scen;
+   // ToDo: Add other environment configuration varaibles
+
+   constraint cst_num_trans_default {
+      num_trans inside {[1:7]};
+   }
+   constraint cst_num_scen_default {
+      num_scen inside {[1:2]};
+   }
+   // ToDo: Add constraint blocks to prevent error injection
+
+   `uvm_object_utils_begin(wb_env_cfg)
+      `uvm_field_int(num_trans,UVM_DEFAULT) 
+      `uvm_field_int(num_scen,UVM_DEFAULT)
+      // ToDo: add properties using macros here
+   `uvm_object_utils_end
+   function new(string name = "wb_env_cfg") ;
+      super.new(name);
+   endfunction
+   
+endclass: wb_env_cfg
+
+`endif // WB_ENV_CFG__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_env_cov.sv

@@ -0,0 +1,41 @@
+`ifndef WB_ENV_COV__SV
+ `define WB_ENV_COV__SV
+typedef class wb_transaction;
+
+class wb_env_cov  extends uvm_subscriber #(wb_transaction);
+   event cov_event;
+   wb_transaction tr;
+   `uvm_component_utils(wb_env_cov)
+   
+   covergroup cg_trans @(cov_event);
+      coverpoint tr.kind;
+      coverpoint tr.address {
+         bins low = {[0:10]};
+         bins mid = {[10:100]};
+         bins high = {[100:$]};
+      }
+      coverpoint tr.lock ;
+      coverpoint tr.status;
+      coverpoint tr.num_wait_states {
+         bins legal[] = {[0:15]};
+         illegal_bins ib = {[16:$]};
+
+      }
+
+   endgroup: cg_trans
+
+
+   function new(string name, uvm_component parent);
+      super.new(name,parent);
+      cg_trans = new;
+   endfunction: new
+
+   virtual function void write(wb_transaction t);
+      this.tr = t;
+      -> cov_event;
+   endfunction: write
+
+endclass: wb_env_cov
+
+`endif // WB_ENV_COV__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_master.sv

@@ -0,0 +1,273 @@
+`ifndef WB_MASTER__SV
+ `define WB_MASTER__SV
+
+typedef class wb_transaction;
+   typedef class wb_config;
+   typedef class wb_master;
+   typedef class wb_config;
+ //`include "wb_master_if.sv"
+
+class wb_master_callbacks extends uvm_callback;
+
+   // Called before a transaction is executed
+   virtual task pre_tx( wb_master xactor,
+                        wb_transaction tr);
+      
+      `uvm_info("WB_MASTER_CALLBACKS"," This is in the pre-callback phase",UVM_LOW)
+      tr.print();
+
+   endtask: pre_tx
+
+
+   // Called after a transaction has been executed
+   virtual task post_tx( wb_master xactor,
+                         wb_transaction tr);
+
+   endtask: post_tx
+
+endclass: wb_master_callbacks
+
+class wb_master extends uvm_driver # (wb_transaction);
+
+   wb_config mstr_drv_cfg;
+
+   
+   typedef virtual wb_master_if v_if; 
+   v_if drv_if;
+   `uvm_register_cb(wb_master,wb_master_callbacks); 
+   
+   extern function new(string name = "wb_master",
+                       uvm_component parent = null); 
+   
+   `uvm_component_utils_begin(wb_master)
+   `uvm_component_utils_end
+
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void end_of_elaboration_phase(uvm_phase phase);
+   extern virtual function void start_of_simulation_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual task reset_phase(uvm_phase phase); // See Note near implementation of this phase.
+   extern virtual task run_phase(uvm_phase phase);
+   extern protected virtual task main_driver();
+
+
+   extern protected virtual task read(wb_transaction trans);
+   extern protected virtual task write(wb_transaction trans);
+   extern protected virtual task blockRead(wb_transaction trans);
+   extern protected virtual task blockWrite( wb_transaction trans);  
+   extern protected virtual task ReadModifyWrite(wb_transaction trans);
+
+endclass: wb_master
+
+
+   function wb_master::new(string name = "wb_master",
+			   uvm_component parent = null);
+      super.new(name, parent);
+
+      
+   endfunction: new
+
+
+   function void wb_master::build_phase(uvm_phase phase);
+      super.build_phase(phase);
+   endfunction: build_phase
+
+   function void wb_master::connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      uvm_config_db#(v_if)::get(this, "", "mst_if", drv_if);
+
+   endfunction: connect_phase
+
+   function void wb_master::end_of_elaboration_phase(uvm_phase phase);
+      super.end_of_elaboration_phase(phase);
+      if (drv_if == null)
+	`uvm_fatal("NO_CONN", "Virtual port not connected to the actual interface instance");   
+   endfunction: end_of_elaboration_phase
+
+   function void wb_master::start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+   endfunction: start_of_simulation_phase
+
+   //This reset_phase task implementation really isn't the recommended way to do use the reset_phase task.   
+   // However, I provided this to simplify the example simply to allow you to follow along.
+   // See Book for reasons why you should do it a different way.
+   
+   task wb_master::reset_phase(uvm_phase phase);
+      super.reset_phase(phase);
+      phase.raise_objection(this,"");
+      // Driving the signals as per the spec.
+      this.drv_if.master_cb.DAT_O <= 'bz;
+      this.drv_if.master_cb.TGD_O <= 'bz;
+      this.drv_if.master_cb.ADR_O  <= 'bz;
+      this.drv_if.master_cb.WE_O   <= 'bz;
+      this.drv_if.master_cb.CYC_O <= 'bz;
+      this.drv_if.master_cb.LOCK_O <= 'bz;
+      this.drv_if.master_cb.SEL_O <= 'bz;
+      this.drv_if.master_cb.STB_O <= 'bz;
+      this.drv_if.master_cb.TGA_O <= 'bz;
+      this.drv_if.master_cb.TGC_O <= 'bz;
+
+      repeat (4) @(this.drv_if.master_cb);
+      // Done setting signals. Now we can drop objections and move on.
+      phase.drop_objection(this);
+   endtask: reset_phase
+   
+
+   task wb_master::run_phase(uvm_phase phase);
+      super.run_phase(phase);
+      phase.raise_objection(this,"");
+      fork 
+	 main_driver();
+      join_none
+      phase.drop_objection(this);
+   endtask: run_phase
+
+
+   task wb_master::main_driver();
+      int count;
+      count = 0;
+      forever begin
+	 wb_transaction tr;
+	 bit drop = 0;
+	 // Set output signals to their idle state
+
+	 this.drv_if.master_cb.DAT_O <= 'bz; 
+         this.drv_if.master_cb.TGD_O <= 'bz;
+         this.drv_if.master_cb.ADR_O <= 'bz;
+         this.drv_if.master_cb.CYC_O <= 'bz;
+         this.drv_if.master_cb.LOCK_O <= 'bz;
+         this.drv_if.master_cb.SEL_O <= 'bz;
+         this.drv_if.master_cb.STB_O <= 'b0;
+         this.drv_if.master_cb.TGA_O <= 'bz;
+         this.drv_if.master_cb.TGC_O <= 'bz;
+
+	 seq_item_port.get_next_item(tr);
+	 `uvm_info("wb_env_DRIVER", "Starting transaction...",UVM_LOW)
+	 `uvm_do_callbacks(wb_master,wb_master_callbacks, pre_tx(this, tr))
+	 // Since we are just beginning the transaction, we dont know what kind it's yet. 
+
+         tr.status = wb_transaction::UNKNOWN;
+
+	 case (tr.kind)  
+           wb_transaction::READ: begin
+	      read(tr);
+           end
+           wb_transaction::WRITE: begin
+              // ToDo: Implement DISPLAY transaction
+	      write(tr);
+           end
+           wb_transaction::BLK_RD: begin
+              // ToDo: Implement BLK_RD transaction
+           end
+           wb_transaction::BLK_WR: begin
+              // ToDo: Implement BLK_RD transaction
+           end
+           wb_transaction::RMW: begin
+              // ToDo: Implement RMW transaction
+           end
+	 endcase
+	 
+	 seq_item_port.item_done();
+	 `uvm_info("wb_env_DRIVER", tr.sprint(),UVM_LOW)
+
+	 `uvm_do_callbacks(wb_master,wb_master_callbacks, post_tx(this, tr))
+	 `uvm_info("wb_env_DRIVER", "Completed transaction...",UVM_LOW)
+	 count = count + 1;
+      end
+   endtask : main_driver
+
+
+   task wb_master::read(wb_transaction trans);
+      @(this.drv_if.master_cb);
+
+      `uvm_info("Wb master","Got a read transaction",UVM_LOW)
+
+      // Edge 0
+      this.drv_if.master_cb.ADR_O <= trans.address;
+      this.drv_if.master_cb.TGA_O <= trans.tga;
+      this.drv_if.master_cb.WE_O  <= 1'b0;
+      this.drv_if.master_cb.SEL_O <= trans.sel;
+      this.drv_if.master_cb.CYC_O <= 1'b1;
+      this.drv_if.master_cb.TGC_O <= trans.tgc;
+      this.drv_if.master_cb.STB_O <= 1'b1;
+
+      // Edge 1
+      trans.status = wb_transaction::TIMEOUT ;
+      repeat (this.mstr_drv_cfg.max_n_wss + 1) begin
+	 // Wait states
+	 @(this.drv_if.master_cb);
+
+	 case (1'b1)
+	   this.drv_if.master_cb.ERR_I: trans.status = wb_transaction::ERR ;
+	   this.drv_if.master_cb.RTY_I: trans.status = wb_transaction::RTY ;
+	   this.drv_if.master_cb.ACK_I: trans.status = wb_transaction::ACK ;
+	   default: continue;
+	 endcase
+
+	 break;
+      end
+      trans.data = this.drv_if.master_cb.DAT_I;
+      trans.tgd  = this.drv_if.master_cb.TGD_I;
+
+      this.drv_if.master_cb.LOCK_O <= trans.lock;
+      this.drv_if.master_cb.CYC_O  <= 1'bz;
+
+   endtask	
+   
+   task wb_master::write( wb_transaction trans);
+
+
+      // Section 3.2.2 of Wishbone B3 Specification
+      @(this.drv_if.master_cb);
+      `uvm_info("Wb master","Got a write transaction",UVM_LOW)
+
+      // Edge 0
+      this.drv_if.master_cb.ADR_O <= trans.address;
+      this.drv_if.master_cb.TGA_O  <= trans.tga;
+      this.drv_if.master_cb.DAT_O <= trans.data;
+      this.drv_if.master_cb.TGD_O <= trans.tgd;
+      this.drv_if.master_cb.WE_O    <= 1'b1;
+      this.drv_if.master_cb.SEL_O  <= trans.sel;
+      this.drv_if.master_cb.CYC_O  <= 1'b1;
+      this.drv_if.master_cb.TGC_O  <= trans.tgc;
+      this.drv_if.master_cb.STB_O  <= 1'b1;
+
+      // Edge 1
+      trans.status = wb_transaction::TIMEOUT ;
+      repeat (this.mstr_drv_cfg.max_n_wss + 1) begin
+	 // Wait states
+	 @(this.drv_if.master_cb);
+	 case (1'b1)
+      	   this.drv_if.master_cb.ERR_I: trans.status = wb_transaction::ERR ;
+     	   this.drv_if.master_cb.RTY_I: trans.status = wb_transaction::RTY ;
+      	   this.drv_if.master_cb.ACK_I: trans.status = wb_transaction::ACK ;
+      	   default: continue;
+	 endcase
+
+	 break;
+      end
+
+      if (trans.status == wb_transaction::TIMEOUT ) begin
+	 `uvm_info("wb_master_driver: ", "Timeout waiting for ACK_I, RTY_I or ERR_I",UVM_HIGH);
+      end 
+
+      this.drv_if.master_cb.LOCK_O <= trans.lock;
+      this.drv_if.master_cb.CYC_O  <= 1'bz;
+
+   endtask	
+
+   task wb_master::blockRead(wb_transaction trans);
+      `uvm_error("WB_MASTER","blockRead not implemented yet")
+   endtask
+
+   task wb_master::blockWrite(wb_transaction trans);
+      `uvm_error("WB_MASTER","blockWrite not implemented yet")
+   endtask
+
+   task wb_master::ReadModifyWrite(wb_transaction trans);
+
+      `uvm_error("WB_MASTER","ReadModifyWrite not implemented yet")
+   endtask
+`endif // WB_MASTER__SV
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_master_agent_sequence_library.sv

@@ -0,0 +1,101 @@
+//
+// Template for UVM-compliant sequence library
+//
+
+typedef class wb_transaction;
+
+class wb_master_seqr_sequence_library extends uvm_sequence_library # (wb_transaction);
+   `uvm_sequence_library_utils(wb_master_seqr_sequence_library)
+
+   function new(string name = "simple_seq_lib");
+      super.new(name);
+      init_sequence_library();
+   endfunction
+
+endclass  
+
+class base_sequence extends uvm_sequence #(wb_transaction);
+   `uvm_object_utils(base_sequence)
+
+   function new(string name = "base_seq");
+      super.new(name);
+     set_automatic_phase_objection(1);
+   endfunction:new
+/*
+   virtual task pre_body(); 
+      uvm_phase phase_=get_starting_phase();
+      if (phase_ != null)
+	phase_.raise_objection(this);
+   endtask:pre_body
+   virtual task post_body(); 
+
+      uvm_phase phase_=get_starting_phase();
+
+      if (phase_ != null)
+	phase_.drop_objection(this);
+   endtask:post_body
+*/
+endclass
+
+class sequence_0 extends base_sequence;
+   `uvm_object_utils(sequence_0)
+   `uvm_add_to_seq_lib(sequence_0,wb_master_seqr_sequence_library)
+   function new(string name = "seq_0");
+      super.new(name);
+   endfunction:new
+   virtual task body();
+      
+      repeat(2) begin
+	 `uvm_do(req);
+      end
+      start_item(req);
+      finish_item(req);
+   endtask 
+   virtual task pre_body(); 
+	// Provided as an example. See above comment DONT USE THIS.
+
+      uvm_phase phase_=get_starting_phase();
+
+      if (phase_!=null) begin
+	 `uvm_info(get_type_name(),
+                   $sformatf("%s pre_body() raising %s objection",
+                             get_sequence_path(),
+                             phase_.get_name()), UVM_MEDIUM);
+	 phase_.raise_objection(this);
+      end
+   endtask
+
+   // Drop the objection in the post_body so the objection is removed when
+   // the root sequence is complete.   Provided as an example. See above comment. DONT USE THIS.
+   virtual task post_body(); 
+      uvm_phase phase_=get_starting_phase();
+
+      if (phase_!=null) begin
+	 `uvm_info(get_type_name(),
+                   $sformatf("%s post_body() dropping %s objection",
+                             get_sequence_path(),
+                             phase_.get_name()), UVM_MEDIUM);
+	 phase_.drop_objection(this);
+      end
+   endtask
+
+endclass
+
+class sequence_1 extends base_sequence;
+   byte sa;
+   `uvm_object_utils(sequence_1)
+   `uvm_add_to_seq_lib(sequence_1, wb_master_seqr_sequence_library)
+   function new(string name = "seq_1");
+      super.new(name);
+   endfunction:new
+   virtual task body();
+      `uvm_do_with(req, {address == 3; kind == wb_transaction::WRITE; data == 63'hdeadbeef;} )
+      `uvm_do_with(req,{address == 4; kind == wb_transaction::WRITE; data == 63'hbeefdead;} )
+      `uvm_do_with(req, {address == 5; kind == wb_transaction::WRITE; data == 63'h0123456678;} )
+
+      `uvm_do_with(req, {address == 6; kind == wb_transaction::READ ;} )
+      `uvm_do_with(req, {address == 6; kind == wb_transaction::READ;} )
+      `uvm_do_with(req, {address == 7; kind == wb_transaction::READ;} ) 
+   endtask
+endclass
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_master_if.sv

@@ -0,0 +1,102 @@
+`ifndef WB_MASTER_IF__SV
+ `define WB_MASTER_IF__SV
+
+interface wb_master_if (input wire clk,input bit rst);
+
+   // ToDo: Define default setup & hold times
+
+   parameter setup_time = 5/*ns*/;
+   parameter hold_time  = 3/*ns*/;
+
+
+   // Common Signals
+   wire  [63:0] DAT_I;
+   wire [63:0] 	DAT_O;
+   wire 	RST_I;
+   wire [15:0] 	TGD_I;
+   wire [15:0] 	TGD_O;
+   
+
+   // Master signals
+   logic 	ACK_I;
+   logic [63:0] ADR_O;
+   logic 	CYC_O;
+   logic 	ERR_I;
+   logic 	LOCK_O;
+
+   logic 	RTY_I ;
+   logic [7:0] 	SEL_O;	
+   logic 	STB_O;	
+   logic [15:0] TGA_O;	
+   logic [15:0] TGC_O;	
+   logic 	WE_O;	
+
+
+   clocking master_cb @(posedge clk);
+
+      // Common Signals
+      input 	clk;
+      input 	rst;
+
+      input 	DAT_I;
+      output 	DAT_O;
+      input 	RST_I;
+      input 	TGD_I;
+      output 	TGD_O;
+      
+
+      // Master signals
+      input 	ACK_I;
+      output 	ADR_O;
+      output 	CYC_O;
+      input 	ERR_I;
+      output 	LOCK_O;
+
+      input 	RTY_I ;
+      output 	SEL_O;	
+      output 	STB_O;	
+      output 	TGA_O;	
+      output 	TGC_O;	
+      output 	WE_O;
+   endclocking
+
+
+
+
+   clocking monitor_cb @(posedge clk);
+      // Common Signals
+      input 	clk;
+      input 	rst;
+
+      input 	DAT_I;
+      input 	DAT_O;
+      input 	RST_I;
+      input 	TGD_I;
+      input 	TGD_O;
+      
+
+      // Master signals
+      input 	ACK_I;
+      input 	ADR_O;
+      input 	CYC_O;
+      input 	ERR_I;
+      input 	LOCK_O;
+
+      input 	RTY_I ;
+      input 	SEL_O;	
+      input 	STB_O;	
+      input 	TGA_O;	
+      input 	TGC_O;	
+      input 	WE_O;
+   endclocking
+
+
+   modport master (clocking master_cb);
+
+
+   modport monitor (clocking monitor_cb);
+
+
+endinterface: wb_master_if
+
+`endif // WB_MASTER_IF__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_master_mon.sv

@@ -0,0 +1,192 @@
+`ifndef WB_MASTER_MON__SV
+ `define WB_MASTER_MON__SV
+
+
+typedef class wb_transaction;
+   typedef class wb_master_mon;
+   typedef class wb_config;
+
+
+class wb_master_mon_callbacks extends uvm_callback;
+
+   // ToDo: Add additional relevant callbacks
+   // ToDo: Use a task if callbacks can be blocking
+
+
+   // Called at start of observed transaction
+   virtual function void pre_trans(wb_master_mon xactor,
+                                   wb_transaction tr);
+   endfunction: pre_trans
+
+
+   // Called before acknowledging a transaction
+   virtual function pre_ack(wb_master_mon xactor,
+                            wb_transaction tr);
+   endfunction: pre_ack
+   
+
+   // Called at end of observed transaction
+   virtual function void post_trans(wb_master_mon xactor,
+                                    wb_transaction tr);
+   endfunction: post_trans
+
+   
+   // Callback method post_cb_trans can be used for coverage
+   virtual task post_cb_trans(wb_master_mon xactor,
+                              wb_transaction tr);
+   endtask: post_cb_trans
+
+endclass: wb_master_mon_callbacks
+
+   
+
+class wb_master_mon extends uvm_monitor;
+
+   uvm_analysis_port #(wb_transaction) mon_analysis_port;  //TLM analysis port
+   typedef virtual wb_master_if v_if;
+   v_if mon_if;
+   // ToDo: Add another class property if required
+
+   wb_config mstr_mon_cfg;
+
+   extern function new(string name = "wb_master_mon",uvm_component parent);
+   `uvm_register_cb(wb_master_mon,wb_master_mon_callbacks);
+   `uvm_component_utils_begin(wb_master_mon)
+      // ToDo: Add uvm monitor member if any class property added later through field macros
+
+   `uvm_component_utils_end
+   // ToDo: Add required short hand override method
+
+
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void end_of_elaboration_phase(uvm_phase phase);
+   extern virtual function void start_of_simulation_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual task reset_phase(uvm_phase phase);
+   extern virtual task configure_phase(uvm_phase phase);
+   extern virtual task run_phase(uvm_phase phase);
+   extern protected virtual task master_monitor_task();
+
+endclass: wb_master_mon
+
+
+   function wb_master_mon::new(string name = "wb_master_mon",uvm_component parent);
+      super.new(name, parent);
+      mon_analysis_port = new ("mon_analysis_port",this);
+   endfunction: new
+
+   function void wb_master_mon::build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      //ToDo : Implement this phase here
+
+   endfunction: build_phase
+
+   function void wb_master_mon::connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      uvm_config_db#(v_if)::get(this, "", "mon_if", mon_if);
+   endfunction: connect_phase
+
+   function void wb_master_mon::end_of_elaboration_phase(uvm_phase phase);
+      super.end_of_elaboration_phase(phase); 
+      if (mon_if == null)
+	`uvm_fatal("NO_CONN", "Virtual port not connected to the actual interface instance");
+
+
+   endfunction: end_of_elaboration_phase
+
+
+   function void wb_master_mon::start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+   endfunction: start_of_simulation_phase
+
+
+   task wb_master_mon::reset_phase(uvm_phase phase);
+      super.reset_phase(phase);
+
+   endtask: reset_phase
+
+
+   task wb_master_mon::configure_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      phase.raise_objection(this,"");
+      //ToDo: Configure your component here
+      phase.drop_objection(this);
+
+   endtask:configure_phase
+
+
+   task wb_master_mon::run_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      phase.raise_objection(this,"");
+      fork
+	 master_monitor_task();
+      join_none
+      phase.drop_objection(this);
+      `uvm_info("wb_env_MONITOR", "Droppoimg all objectsion...",UVM_HIGH)
+
+   endtask: run_phase
+
+
+   task wb_master_mon::master_monitor_task();
+
+      forever begin
+	 wb_transaction tr;
+
+	 do begin
+
+            @(this.mon_if.CYC_O or
+              this.mon_if.STB_O or
+              this.mon_if.ADR_O or
+              this.mon_if.SEL_O or
+              this.mon_if.WE_O  or
+              this.mon_if.TGA_O or
+              this.mon_if.TGC_O);
+	 end while (this.mon_if.CYC_O !== 1'b1 ||
+                    this.mon_if.STB_O !== 1'b1);
+	 tr= wb_transaction::type_id::create("tr", this);
+	 tr.address = this.mon_if.ADR_O;
+	 // Are we supposed to respond to this cycle?
+	 if(this.mstr_mon_cfg.min_addr <= tr.address  && tr.address <=this.mstr_mon_cfg.max_addr )
+	   begin
+	      `uvm_do_callbacks(wb_master_mon,wb_master_mon_callbacks,
+				pre_trans(this, tr))
+
+	      tr.tga = this.mon_if.TGA_O;
+	      if(this.mon_if.WE_O) begin
+		 tr.kind = wb_transaction::WRITE;
+	   	 `uvm_info("WB master Monitor","got a write transaction  from Master ",UVM_LOW)
+		 tr.data  = this.mon_if.DAT_I;
+	         tr.tgd  = this.mon_if.TGD_O;
+		 tr.status = wb_transaction::ACK;
+              end
+	      else begin
+		 tr.kind = wb_transaction::READ ;
+   		 `uvm_info("Wb_master Monitor","got a read transaction  ",UVM_LOW)
+
+		 tr.status = wb_transaction::ACK;
+      	      end
+
+	      `uvm_do_callbacks(wb_master_mon,wb_master_mon_callbacks,
+				pre_ack(this, tr))
+
+	      wait(this.mon_if.master_cb.ACK_I);
+	      tr.data  = this.mon_if.DAT_O;
+	      tr.tgd  = this.mon_if.TGD_O;
+
+	      tr.sel = this.mon_if.SEL_O;
+	      tr.tgc  = this.mon_if.TGC_O;
+	      @(this.mon_if.monitor_cb);
+	   end
+	 `uvm_do_callbacks(wb_master_mon,wb_master_mon_callbacks,
+			   post_trans(this, tr))
+	 mon_analysis_port.write(tr);
+      end
+
+   endtask: master_monitor_task
+
+
+
+
+
+
+`endif // WB_MASTER_MON__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_master_seqr.sv

@@ -0,0 +1,15 @@
+`ifndef WB_MASTER_SEQR
+ `define WB_MASTER_SEQR
+typedef class wb_transaction;
+   typedef class wb_config;
+class wb_master_seqr extends uvm_sequencer # (wb_transaction);
+
+   wb_config cfg;
+
+   `uvm_component_utils(wb_master_seqr)
+   function new (string name,
+                 uvm_component parent);
+      super.new(name,parent);
+   endfunction:new 
+endclass:wb_master_seqr
+`endif

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_scoreboard.sv

@@ -0,0 +1,64 @@
+`ifndef WB_SCOREBOARD__SV
+ `define WB_SCOREBOARD__SV
+
+class wb_scoreboard extends uvm_scoreboard;
+   `uvm_component_utils( wb_scoreboard)
+   
+   uvm_tlm_analysis_fifo#( wb_transaction ) expected_wb_transaction_fifo;
+   uvm_tlm_analysis_fifo#( wb_transaction ) actual_wb_transaction_fifo;
+   
+   // Constructor
+
+   function new( string name, uvm_component parent );
+      super.new( name, parent );
+   endfunction: new
+
+   extern virtual function void build_phase( uvm_phase phase );
+   extern virtual function void connect_phase( uvm_phase phase );
+   extern virtual task run_phase( uvm_phase phase );
+
+endclass: wb_scoreboard
+
+// Build all the components ..
+
+function void wb_scoreboard::build_phase( uvm_phase phase );
+   super.build_phase( phase );
+   expected_wb_transaction_fifo = new( "expected_wb_transaction_fifo", this );
+   actual_wb_transaction_fifo  = new(   "actual_wb_transaction_fifo", this );
+endfunction: build_phase
+
+// Function: connect_phase
+// Connect the components
+
+function void wb_scoreboard::connect_phase( uvm_phase phase );
+   super.connect_phase( phase );
+endfunction: connect_phase
+
+// Task: run_phase. All the heavy lifting takes place here.
+
+task wb_scoreboard::run_phase( uvm_phase phase );
+   wb_transaction expected_transaction;
+   wb_transaction   actual_transaction;
+   
+   super.run_phase( phase ); // THis should do nothing
+   forever begin
+      expected_wb_transaction_fifo.get_peek_export.get( expected_transaction);
+      actual_wb_transaction_fifo.get_peek_export.get(actual_transaction);
+      `uvm_info("SCOREBOARD","EXPECTED TRANSACTION",UVM_LOW)
+      expected_transaction.print();
+      `uvm_info("SCOREBOARD","ACTUAL TRANSACTION",UVM_LOW)
+      actual_transaction.print();
+      
+      if ( !expected_transaction.compare( actual_transaction)  ) begin
+         `uvm_error( "WB Scoreboard", "wb_transaction mismatch") 
+	 //expected_transaction.print();
+	 //actual_transaction.print();
+      end
+      else begin
+	 `uvm_info("WB SCOREBOARD", "TRANSACTIONS MATCH", UVM_LOW)
+      end
+   end
+endtask: run_phase
+
+
+`endif // WB_SCOREBOARD__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave.my.sv

@@ -0,0 +1,220 @@
+//
+// Template for UVM-compliant physical-level transactor
+//
+
+`ifndef WB_SLAVE__SV
+`define WB_SLAVE__SV
+
+typedef class wb_transaction;
+typedef class wb_slave;
+
+class wb_slave_callbacks extends uvm_callback;
+
+   // Called before a transaction is executed
+   virtual task pre_tx( wb_slave xactor, wb_transaction tr);
+	$display("pre tx slave Not implemented yet");
+   endtask: pre_tx
+
+
+   // Called after a transaction has been executed
+   virtual task post_tx( wb_slave xactor,
+                         wb_transaction tr);
+     $display("post tx slave Not implemented yet");
+
+   endtask: post_tx
+
+endclass: wb_slave_callbacks
+
+
+class wb_slave extends uvm_driver # (wb_transaction);
+
+protected wb_transaction m_tr; // This is what is captured
+event send_to_get;
+
+ uvm_blocking_get_imp #(wb_transaction,wb_slave) get_export;
+// uvm_blocking_put_port #(wb_transaction,wb_slave) addr_ph_imp;
+
+wb_config wb_slave_cfg;
+ 
+   typedef virtual wb_slave_if v_if; 
+   v_if drv_if;
+   `uvm_register_cb(wb_slave,wb_slave_callbacks); 
+   
+   extern function new(string name = "wb_slave",
+                       uvm_component parent = null); 
+ 
+      `uvm_component_utils_begin(wb_slave)
+      `uvm_component_utils_end
+
+
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void end_of_elaboration_phase(uvm_phase phase);
+   extern virtual function void start_of_simulation_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual task reset_phase(uvm_phase phase);
+   extern virtual task configure_phase(uvm_phase phase);
+   extern virtual task main_phase(uvm_phase phase);
+   extern protected virtual task slave_driver();
+
+
+task get(output wb_transaction transaction);
+         wait(send_to_get.triggered)
+	$display("Got transaction in get task\n");
+	m_tr.print();
+  	transaction = m_tr;
+	m_tr = null;
+	send_to_get = null;
+endtask: get
+endclass: wb_slave
+
+
+
+
+
+function wb_slave::new(string name = "wb_slave",
+                   uvm_component parent = null);
+  	 super.new(name, parent);
+	get_export = new("slv_get_export",this);
+   
+endfunction: new
+
+
+function void wb_slave::build_phase(uvm_phase phase);
+   super.build_phase(phase);
+endfunction: build_phase
+
+function void wb_slave::connect_phase(uvm_phase phase);
+   super.connect_phase(phase);
+  if(!uvm_config_db#(v_if)::get(this, "", "slv_if", drv_if))
+       `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".v_if"}); 
+endfunction: connect_phase
+
+function void wb_slave::end_of_elaboration_phase(uvm_phase phase);
+   super.end_of_elaboration_phase(phase);
+   if (drv_if == null)
+       `uvm_fatal("NO_CONN", "Virtual port not connected to the actual interface instance");   
+endfunction: end_of_elaboration_phase
+
+function void wb_slave::start_of_simulation_phase(uvm_phase phase);
+   super.start_of_simulation_phase(phase);
+endfunction: start_of_simulation_phase
+
+ 
+task wb_slave::reset_phase(uvm_phase phase);
+   super.reset_phase(phase);
+   phase.raise_objection(this,"");
+   this.drv_if.DAT_O <= 64'bz;
+   this.drv_if.TGD_O <= 16'bz;
+   this.drv_if.ACK_O <=  1'bz;
+   this.drv_if.RTY_O  <=  1'bz;
+   this.drv_if.ERR_O <=  1'bz;
+   phase.drop_objection(this);
+endtask: reset_phase
+
+task wb_slave::configure_phase(uvm_phase phase);
+   super.configure_phase(phase);
+   phase.raise_objection(this,"");
+   //ToDo: Configure your component here
+   phase.drop_objection(this);
+endtask:configure_phase
+
+
+task wb_slave::main_phase(uvm_phase phase);
+   super.configure_phase(phase);
+   phase.raise_objection(this,"");
+   fork 
+      slave_driver();
+   join_none
+   phase.drop_objection(this);
+endtask: main_phase
+
+
+
+
+task wb_slave::slave_driver();
+ forever begin
+	wb_transaction tr;
+        process proc;
+
+	    do begin
+         if (this.drv_if.CYC_I !== 1'b1 || this.drv_if.STB_I !== 1'b1) begin
+            this.drv_if.DAT_O    <= 64'bz;
+            this.drv_if.TGD_O    <= 16'bz;
+            this.drv_if.ACK_O    <=  1'bz;
+            this.drv_if.RTY_O    <=  1'bz;
+            this.drv_if.ERR_O     <=  1'bz;
+         end
+
+         @(this.drv_if.CYC_I or
+           this.drv_if.STB_I or
+           this.drv_if.ADR_I or
+           this.drv_if.SEL_I or
+           this.drv_if.WE_I  or
+           this.drv_if.TGA_I or
+           this.drv_if.TGC_I);
+      end while (this.drv_if.CYC_I !== 1'b1 ||
+                 this.drv_if.STB_I !== 1'b1);
+$display(" creating a new transatciopmn");
+	tr= wb_transaction::type_id::create("tr", this);
+	tr.address = this.drv_if.ADR_I;
+	// Are we supposed to respond to this cycle?
+	if(this.wb_slave_cfg.min_addr <= tr.address  && tr.address <=this.wb_slave_cfg.max_addr )
+	begin
+	  	tr.tga = this.drv_if.TGA_I;
+		if(this.drv_if.WE_I) begin
+			tr.kind = wb_transaction::WRITE;
+	   		`uvm_info("Wb_slave","got a write transaction  from Master ",UVM_LOW)
+			tr.data  = this.drv_if.DAT_I;
+	        	tr.tgd  = this.drv_if.TGD_I;
+                end
+		else begin
+		 	tr.kind = wb_transaction::READ ;
+   			`uvm_info("Wb_slave","got a read transaction  ",UVM_LOW)
+      		end
+
+      tr.sel = this.drv_if.SEL_I;
+      tr.tgc  = this.drv_if.TGC_I;
+     // Send back an ack .. 
+      m_tr = tr;
+	 -> send_to_get;
+     	this.drv_if.ACK_O <= 1;
+	$display("Troggeriing");
+	@(this.drv_if.slave_cb);
+      end
+      `uvm_do_callbacks(wb_slave,wb_slave_callbacks, pre_tx(this, tr))
+ 	tr = null;
+/*
+            begin
+               proc = process::self();
+      		seq_item_port.get_next_item(tr);
+		      case (tr.kind) 
+         		wb_transaction::READ: begin
+				$display("responding to a read transaction\n");
+            			// ToDo: Implement READ transaction
+
+         			end
+         		wb_transaction::WRITE: begin
+				$display("responding to a write transaction\n");
+            			// ToDo: Implement READ transaction
+         			end
+      			endcase
+      		seq_item_port.item_done();
+      		`uvm_info("SLAVE_DRIVER", "Completed transaction...",UVM_LOW)
+      		`uvm_do_callbacks(wb_slave,wb_slave_callbacks, post_tx(this, tr))
+
+   		end 
+
+
+*/
+
+   end
+
+endtask : slave_driver
+
+
+
+
+
+`endif // WB_SLAVE__SV
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave.sv

@@ -0,0 +1,188 @@
+`ifndef WB_SLAVE__SV
+ `define WB_SLAVE__SV
+
+typedef class wb_transaction;
+   typedef class wb_slave;
+
+class wb_slave_callbacks extends uvm_callback;
+
+   // Called before a transaction is executed
+   virtual task pre_tx( wb_slave xactor, wb_transaction tr);
+      `uvm_info("WB_SLAVE",$sformatf("pre tx slave Not implemented yet"),UVM_LOW)
+   endtask: pre_tx
+
+   // Called after a transaction has been executed
+   virtual task post_tx( wb_slave xactor,
+                         wb_transaction tr);
+      `uvm_info("WB_SLAVE",$sformatf("post tx slave Not implemented yet"),UVM_LOW)
+
+   endtask: post_tx
+
+endclass: wb_slave_callbacks
+
+
+class wb_slave extends uvm_driver # (wb_transaction);
+
+   wb_transaction m_tr; // This is what is captured
+   local bit [63:0] ram [*];
+
+   uvm_blocking_get_imp #(wb_transaction,wb_slave) getp;
+
+   wb_config wb_slave_cfg;
+   
+   typedef virtual  wb_slave_if v_if; 
+   v_if drv_if;
+   `uvm_register_cb(wb_slave,wb_slave_callbacks); 
+   
+   extern function new(string name = "wb_slave",
+                       uvm_component parent = null); 
+   
+   `uvm_component_utils(wb_slave)
+
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void end_of_elaboration_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual task reset_phase(uvm_phase phase);
+   extern virtual task configure_phase(uvm_phase phase);
+   extern virtual task run_phase(uvm_phase phase);
+   extern protected virtual task slave_driver();
+
+   task get(output wb_transaction transaction);
+      wait(m_tr != null )
+  	transaction = m_tr;
+      m_tr = null;
+   endtask: get
+
+endclass: wb_slave
+
+
+
+
+
+   function wb_slave::new(string name = "wb_slave",
+			  uvm_component parent = null);
+      super.new(name, parent);
+      getp= new("slv_get_export",this);
+      
+   endfunction: new
+
+
+   function void wb_slave::build_phase(uvm_phase phase);
+      super.build_phase(phase);
+   endfunction: build_phase
+
+   function void wb_slave::connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      if(!uvm_config_db#(v_if)::get(this, "", "slv_if", drv_if))
+	`uvm_fatal("NOVIF SLV DRIVER",{"virtual interface must be set for: ","WB_SLAVE",".v_if"}); 
+   endfunction: connect_phase
+
+   function void wb_slave::end_of_elaboration_phase(uvm_phase phase);
+      super.end_of_elaboration_phase(phase);
+      if (drv_if == null)
+	`uvm_fatal("NO_CONN", "Virtual port not connected to the actual interface instance");   
+   endfunction: end_of_elaboration_phase
+
+
+   
+   task wb_slave::reset_phase(uvm_phase phase);
+      super.reset_phase(phase);
+      phase.raise_objection(this,"");
+      this.drv_if.DAT_O <= 64'bz;
+      this.drv_if.TGD_O <= 16'bz;
+      this.drv_if.ACK_O <=  1'bz;
+      this.drv_if.RTY_O  <=  1'bz;
+      this.drv_if.ERR_O <=  1'bz;
+      phase.drop_objection(this);
+   endtask: reset_phase
+
+   task wb_slave::configure_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      phase.raise_objection(this,"");
+
+      phase.drop_objection(this);
+   endtask:configure_phase
+
+
+   task wb_slave::run_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      //phase.raise_objection(this,"");
+      fork 
+	 slave_driver();
+      join_none
+      //phase.drop_objection(this);
+   endtask: run_phase
+
+
+
+
+   task wb_slave::slave_driver();
+      bit [63:0] read_data;
+      wb_slave_cfg.print();
+      forever begin
+	 wb_transaction tr;
+
+	 do begin
+            if (this.drv_if.CYC_I !== 1'b1 || this.drv_if.STB_I !== 1'b1) begin
+               this.drv_if.DAT_O    <= 64'bz;
+               this.drv_if.TGD_O    <= 16'bz;
+               this.drv_if.ACK_O    <=  1'bz;
+               this.drv_if.RTY_O    <=  1'bz;
+               this.drv_if.ERR_O     <=  1'bz;
+            end
+
+            @(this.drv_if.CYC_I or
+              this.drv_if.STB_I or
+              this.drv_if.ADR_I or
+              this.drv_if.SEL_I or
+              this.drv_if.WE_I  or
+              this.drv_if.TGA_I or
+              this.drv_if.TGC_I);
+	 end while (this.drv_if.CYC_I !== 1'b1 ||
+                    this.drv_if.STB_I !== 1'b1);
+	 tr= wb_transaction::type_id::create("tr", this);
+	 tr.address = this.drv_if.ADR_I;
+	 // Are we supposed to respond to this cycle?
+	 if(this.wb_slave_cfg.min_addr <= tr.address  && tr.address <=this.wb_slave_cfg.max_addr )
+	   begin
+	      tr.sel = this.drv_if.SEL_I;
+	      tr.tgc  = this.drv_if.TGC_I;
+	      `uvm_do_callbacks(wb_slave,wb_slave_callbacks, pre_tx(this, tr))
+	      tr.tga = this.drv_if.TGA_I;
+	      if(this.drv_if.WE_I) begin
+		 tr.kind = wb_transaction::WRITE;
+	   	 `uvm_info("Wb_slave","got a write transaction  from Master ",UVM_LOW)
+		 tr.data  = this.drv_if.DAT_I;
+	         tr.tgd  = this.drv_if.TGD_I;
+	      end
+	      else  begin
+		 tr.kind = wb_transaction::READ ;
+   		 `uvm_info("Wb_slave","got a read transaction  ",UVM_LOW)
+	      end
+	      m_tr = tr;
+	      seq_item_port.get_next_item(tr);
+              this.drv_if.DAT_O    = 64'bz;
+ 	      if(tr.kind == wb_transaction::READ) begin
+		 this.drv_if.DAT_O = tr.data;
+	      end
+
+	      repeat (this.wb_slave_cfg.max_n_wss) begin
+		 @ (this.drv_if.slave_cb);
+              end
+	      this.drv_if.ACK_O <= 1'b1;
+  	      this.drv_if.RTY_O <= 1'b0;
+	      this.drv_if.ERR_O <= 1'b0;
+	      @ (this.drv_if.slave_cb);
+	      this.drv_if.ACK_O <= 1'b0;
+	      @(this.drv_if.slave_cb);
+              this.drv_if.DAT_O    <= 64'bz;
+	      `uvm_do_callbacks(wb_slave,wb_slave_callbacks, post_tx(this, tr))
+      	      `uvm_info("SLAVE_DRIVER", "Completed transaction...",UVM_LOW)
+	      seq_item_port.item_done(tr);
+	   end // if 
+      end //forever
+   endtask : slave_driver
+
+`endif // WB_SLAVE__SV
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave_agent_sequence_library.sv

@@ -0,0 +1,62 @@
+//
+// Template for UVM-compliant sequence library
+//
+
+typedef class wb_transaction;
+
+class wb_slave_seqr_sequence_library extends uvm_sequence_library # (wb_transaction);
+   `uvm_sequence_library_utils(wb_slave_seqr_sequence_library)
+
+   function new(string name = "slave_seq_lib");
+      super.new(name);
+      init_sequence_library();
+   endfunction
+
+endclass  
+
+class slv_base_sequence extends uvm_sequence #(wb_transaction);
+
+   `uvm_object_utils(slv_base_sequence)
+
+   `uvm_declare_p_sequencer(wb_slave_seqr)
+
+
+   function new(string name = "base_seq");
+      super.new(name);
+   endfunction:new
+   virtual task pre_body();
+      uvm_phase phase_ = get_starting_phase();
+      if (phase_ != null)
+	phase_.raise_objection(this);
+   endtask:pre_body
+   virtual task post_body();
+      uvm_phase phase_ = get_starting_phase();
+      if (phase_ != null)
+	phase_.drop_objection(this);
+   endtask:post_body
+endclass
+
+class ram_sequence extends uvm_sequence #(wb_transaction);
+   `uvm_object_utils(ram_sequence)
+   `uvm_declare_p_sequencer(wb_slave_seqr)
+   `uvm_add_to_seq_lib(ram_sequence,wb_slave_seqr_sequence_library)
+   function new(string name = "seq_0");
+      super.new(name);
+   endfunction:new
+   virtual task body();
+      wb_transaction tr;
+      forever begin
+	 p_sequencer.wait_for_req(this, tr);
+	 `uvm_info(get_full_name(),$sformatf("In SLAVE SEQUENCER, Transaction address = %h   kind = %s",tr.address,tr.kind.name()),UVM_LOW)
+	 case (tr.kind)
+	   wb_transaction::WRITE: p_sequencer.write(tr.address, tr.data);
+	   wb_transaction::READ: tr.data = p_sequencer.read(tr.address);
+	 endcase
+	 tr.status = wb_transaction::ACK;
+	 `uvm_info(get_full_name(),$sformatf("SLAVE SEQUENCER OUTPUT, Transaction address = %h   kind = %s data = %h",tr.address,tr.kind.name(), tr.data),UVM_LOW)
+	 p_sequencer.send_rsp(this, tr);
+      end
+   endtask
+
+endclass
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave_if.sv

@@ -0,0 +1,82 @@
+`ifndef WB_SLAVE_IF__SV
+ `define WB_SLAVE_IF__SV
+
+interface wb_slave_if (input bit clk, input bit rst);
+
+
+   parameter setup_time = 5/*ns*/;
+   parameter hold_time  = 3/*ns*/;
+
+   // Common Signals
+   wire CYC_I;
+   wire [63:0] DAT_I;
+   logic [63:0] DAT_O;
+   wire        RST_I;
+   wire [15:0] TGD_I;
+   logic [15:0] TGD_O;
+   // Slave Signals
+   logic       ACK_O	;
+   logic [63:0] ADR_I;	
+   logic 	ERR_O	;
+   logic 	LOCK_I	;
+   logic 	RTY_O	;
+   logic [7:0] 	SEL_I	;
+   logic 	STB_I	;
+   logic [15:0] TGA_I	;
+   logic [15:0] TGC_I	;
+   logic 	WE_I	;
+
+   clocking slave_cb @(posedge clk);
+      default input #setup_time output #hold_time;
+
+      // Common Signals
+      input 	CYC_I;
+      input 	DAT_I;
+      output 	DAT_O;
+      input 	RST_I;
+      input 	TGD_I;
+      output 	TGD_O;
+      // Slave Signals
+      output 	ACK_O	;
+      input 	ADR_I;	
+      output 	ERR_O	;
+      input 	LOCK_I	;
+      output 	RTY_O	;
+      input 	SEL_I	;
+      input 	STB_I	;
+      input 	TGA_I	;
+      input 	TGC_I	;
+      input 	WE_I	;
+
+   endclocking: slave_cb
+
+   clocking slave_mon_cb @(posedge clk);
+      default input #setup_time output #hold_time;
+
+      // Common Signals
+      input 	CYC_I;
+      input 	DAT_I;
+      input 	DAT_O;
+      input 	RST_I;
+      input 	TGD_I;
+      input 	TGD_O;
+      // Slave Signals
+      input 	ACK_O	;
+      input 	ADR_I;	
+      input 	ERR_O	;
+      input 	LOCK_I	;
+      input 	RTY_O	;
+      input 	SEL_I	;
+      input 	STB_I	;
+      input 	TGA_I	;
+      input 	TGC_I	;
+      input 	WE_I;
+
+   endclocking: slave_mon_cb
+   modport slave (clocking slave_cb);
+
+   modport slave_mon (clocking slave_mon_cb);
+
+endinterface: wb_slave_if
+
+`endif // WB_SLAVE_IF__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave_mon.sv

@@ -0,0 +1,185 @@
+`ifndef WB_SLAVE_MON__SV
+ `define WB_SLAVE_MON__SV
+
+
+typedef class wb_transaction;
+   typedef class wb_slave_mon;
+   typedef class wb_config;
+
+class wb_slave_mon_callbacks extends uvm_callback;
+
+   // ToDo: Add additional relevant callbacks
+   // ToDo: Use a task if callbacks can be blocking
+
+
+   // Called at start of observed transaction
+   virtual function void pre_trans(wb_slave_mon xactor,
+                                   wb_transaction tr);
+   endfunction: pre_trans
+
+
+   // Called before acknowledging a transaction
+   virtual function pre_ack(wb_slave_mon xactor,
+                            wb_transaction tr);
+   endfunction: pre_ack
+   
+
+   // Called at end of observed transaction
+   virtual function void post_trans(wb_slave_mon xactor,
+                                    wb_transaction tr);
+   endfunction: post_trans
+
+   
+   // Callback method post_cb_trans can be used for coverage
+   virtual task post_cb_trans(wb_slave_mon xactor,
+                              wb_transaction tr);
+   endtask: post_cb_trans
+
+endclass: wb_slave_mon_callbacks
+
+   
+
+class wb_slave_mon extends uvm_monitor;
+
+   uvm_analysis_port #(wb_transaction) mon_analysis_port;  //TLM analysis port
+   typedef virtual wb_slave_if v_if;
+   v_if mon_if;
+
+   // ToDo: Add another class property if required
+
+   wb_config slv_mon_cfg;
+   extern function new(string name = "wb_slave_mon",uvm_component parent);
+   `uvm_register_cb(wb_slave_mon,wb_slave_mon_callbacks);
+
+   `uvm_component_utils_begin(wb_slave_mon)
+      // ToDo: Add uvm monitor member if any class property added later through field macros
+
+   `uvm_component_utils_end
+   // ToDo: Add required short hand override method
+
+
+   extern virtual function void build_phase(uvm_phase phase);
+   extern virtual function void connect_phase(uvm_phase phase);
+   extern virtual task reset_phase(uvm_phase phase);
+   extern virtual task configure_phase(uvm_phase phase);
+   extern virtual task run_phase(uvm_phase phase);
+   extern protected virtual task slave_monitor_task();
+
+endclass: wb_slave_mon
+
+
+   function wb_slave_mon::new(string name = "wb_slave_mon",uvm_component parent);
+      super.new(name, parent);
+      mon_analysis_port = new ("mon_analysis_port",this);
+   endfunction: new
+
+   function void wb_slave_mon::build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      //ToDo : Implement this phase here
+
+   endfunction: build_phase
+
+   function void wb_slave_mon::connect_phase(uvm_phase phase);
+      super.connect_phase(phase);
+      uvm_config_db#(v_if)::get(this, "", "mon_if", mon_if);
+   endfunction: connect_phase
+
+
+
+   task wb_slave_mon::reset_phase(uvm_phase phase);
+      super.reset_phase(phase);
+      phase.raise_objection(this,"");
+      // ToDo: Implement reset here
+      phase.drop_objection(this);
+
+   endtask: reset_phase
+
+
+   task wb_slave_mon::configure_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      phase.raise_objection(this,"");
+      //ToDo: Configure your component here
+      phase.drop_objection(this);
+
+   endtask:configure_phase
+
+
+   task wb_slave_mon::run_phase(uvm_phase phase);
+      super.configure_phase(phase);
+      phase.raise_objection(this,"");
+      fork
+	 slave_monitor_task();
+      join_none
+      phase.drop_objection(this);
+      `uvm_info("wb_env_SLAVE MONITOR", "Dropped objections ...",UVM_HIGH)
+
+   endtask: run_phase
+
+
+   task wb_slave_mon::slave_monitor_task();
+
+      forever begin
+	 wb_transaction tr;
+
+	 do begin
+
+            @(this.mon_if.CYC_I or
+              this.mon_if.STB_I or
+              this.mon_if.ADR_I or
+              this.mon_if.SEL_I or
+              this.mon_if.WE_I  or
+              this.mon_if.TGA_I or
+              this.mon_if.TGC_I);
+	 end while (this.mon_if.CYC_I !== 1'b1 ||
+                    this.mon_if.STB_I !== 1'b1);
+	 tr= wb_transaction::type_id::create("tr", this);
+	 tr.address = this.mon_if.ADR_I;
+	 // Are we supposed to respond to this cycle?
+	 if(this.slv_mon_cfg.min_addr <= tr.address  && tr.address <=this.slv_mon_cfg.max_addr )
+	   begin
+	      `uvm_do_callbacks(wb_slave_mon,wb_slave_mon_callbacks,
+				pre_trans(this, tr))
+
+	      tr.tga = this.mon_if.TGA_I;
+	      if(this.mon_if.WE_I) begin
+		 tr.kind = wb_transaction::WRITE;
+	   	 `uvm_info("WB slave Monitor","got a write transaction  from Master ",UVM_LOW)
+		 tr.data  = this.mon_if.DAT_I;
+	         tr.tgd  = this.mon_if.TGD_I;
+		 tr.status = wb_transaction::ACK;
+              end
+	      else begin
+		 tr.kind = wb_transaction::READ ;
+   		 `uvm_info("Wb_slave Monitor","got a read transaction  ",UVM_LOW)
+		 tr.data  = this.mon_if.DAT_I;
+	         tr.tgd  = this.mon_if.TGD_I;
+
+		 tr.status = wb_transaction::ACK;
+      	      end
+
+	      `uvm_do_callbacks(wb_slave_mon,wb_slave_mon_callbacks,
+				pre_ack(this, tr))
+
+	      repeat (this.slv_mon_cfg.max_n_wss) begin
+		 @ (this.mon_if.slave_mon_cb);
+              end
+
+
+
+	      tr.sel = this.mon_if.SEL_I;
+	      tr.tgc  = this.mon_if.TGC_I;
+	      @(this.mon_if.slave_mon_cb);
+	   end
+	 `uvm_do_callbacks(wb_slave_mon,wb_slave_mon_callbacks,
+			   post_trans(this, tr))
+	 mon_analysis_port.write(tr);
+      end
+
+   endtask: slave_monitor_task
+
+
+
+
+
+
+`endif // WB_SLAVE_MON__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_slave_seqr.sv

@@ -0,0 +1,51 @@
+`ifndef WB_SLAVE_SEQR
+ `define WB_SLAVE_SEQR
+typedef class wb_transaction;
+class wb_slave_seqr extends uvm_sequencer # (wb_transaction);
+
+   uvm_blocking_get_port #(wb_transaction) m_getp;
+
+   local bit [63:0] ram [*];
+   `uvm_component_utils(wb_slave_seqr)
+   function new (string name,
+                 uvm_component parent);
+      super.new(name,parent);
+      m_getp = new("slave_get_port",this);
+      set_arbitration(UVM_SEQ_ARB_STRICT_FIFO);
+
+   endfunction:new 
+
+   task wait_for_req(uvm_sequence_base seq, output wb_transaction req);
+      wait_for_grant(seq);
+      m_getp.get(req);
+   endtask
+
+
+   task send_rsp(uvm_sequence_base seq, wb_transaction rsp);
+      rsp.set_item_context(seq);
+      seq.finish_item(rsp);
+   endtask
+
+   function bit [63:0] read(bit [63:0] addr);
+      read = (this.ram.exists(addr)) ? this.ram[addr] : 64'bx;
+   endfunction: read
+
+
+   function void write(bit [63:0] addr,
+                       bit [63:0] data);
+      this.ram[addr] = data;
+   endfunction: write
+
+   function void start_of_simulation_phase(uvm_phase phase);
+      integer 			  i;
+      super.start_of_simulation_phase(phase);
+      `uvm_info("WB_SLAVE_SEQR","Initializing memory",UVM_MEDIUM)
+      for(i = 0; i < 1000; i++) begin
+	 write(i,i * 10);
+      end
+
+      
+   endfunction
+
+endclass:wb_slave_seqr
+`endif

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_transaction.sv

@@ -0,0 +1,84 @@
+/*
+ * Template for UVM-compliant transaction descriptor
+ * this class provides the basic transaction required 
+ * by the WB Master and WB Slave Agents
+ */
+
+
+`ifndef WB_TRANSACTION__SV
+ `define WB_TRANSACTION__SV
+
+typedef class wb_config;
+class wb_transaction extends uvm_sequence_item;
+
+   // Different types of read and Write cycles.
+   typedef enum {READ, WRITE, BLK_RD, BLK_WR, RMW} kinds_e;
+   rand kinds_e kind;
+
+   // This is the status of the transaction
+   typedef enum {OK, ACK, RTY, ERR, TIMEOUT ,INFLIGHT , UNKNOWN } status_e;
+   wb_config cfg;  // Must be non-NULL to randomize
+
+   rand status_e status;
+
+   typedef enum {CLASSIC, CONSTANT,
+                 LINEAR, WRAP4, WRAP8, WRAP16,
+                 EOB} pipelining_e;
+   rand pipelining_e next_cycle;
+
+   rand bit [63:0] address;
+   rand bit [63:0] data;
+   rand bit [ 7:0] sel;
+   rand bit [15:0] tgc;
+   rand bit [15:0] tga;
+   rand bit [15:0] tgd;
+   rand bit        lock;
+   rand bit [15:0] tag;
+
+   int 		num_wait_states;
+
+   constraint supported {
+      next_cycle == CLASSIC;
+      kind == READ || kind == WRITE;
+   }
+
+   constraint valid_address {
+      if (cfg.port_size - cfg.granularity == 1) address[0:0] == 1'b0;
+      if (cfg.port_size - cfg.granularity == 2) address[1:0] == 2'b00;
+      if (cfg.port_size - cfg.granularity == 3) address[2:0] == 3'b000;
+   }
+
+   constraint valid_sel {
+      sel inside {8'h01, 8'h03, 8'h07, 8'h0F, 8'h1F, 8'h3F, 8'h7F, 8'hFF};
+      if (cfg.port_size - cfg.granularity == 0) sel[7:1] == 7'h00;
+      if (cfg.port_size - cfg.granularity == 1) sel[7:2] == 6'h00;
+      if (cfg.port_size - cfg.granularity == 2) sel[7:4] == 4'h0;
+   }
+
+
+   constraint wb_transaction_valid {
+      status == OK;
+      if (cfg.cycles == wb_config::CLASSIC ) next_cycle == CLASSIC;
+
+   }
+   `uvm_object_utils_begin(wb_transaction) 
+      `uvm_field_int(address,UVM_DEFAULT)
+      `uvm_field_int(data,UVM_DEFAULT)
+      `uvm_field_int(sel,UVM_DEFAULT)
+      `uvm_field_int(tga,UVM_DEFAULT)
+      `uvm_field_int(tgc,UVM_DEFAULT)
+      `uvm_field_int(lock,UVM_DEFAULT)
+      `uvm_field_int(num_wait_states,UVM_DEFAULT)
+      `uvm_field_enum(kinds_e,kind,UVM_DEFAULT)
+      `uvm_field_enum(status_e,status, UVM_DEFAULT)
+      `uvm_field_enum(pipelining_e,next_cycle, UVM_DEFAULT)
+   `uvm_object_utils_end
+
+   function new(string name="" );
+      super.new(name);
+      cfg = new();
+   endfunction: new
+
+endclass: wb_transaction
+
+`endif // WB_TRANSACTION__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/src/wb_transaction_extended.sv

@@ -0,0 +1,18 @@
+`ifndef WB_TRANSACTION_EXTENDED__SV
+ `define WB_TRANSACTION_EXTENDED__SV
+
+class wb_transaction_extended extends wb_transaction;
+
+   constraint my_new_constraint {
+      address  inside {32'h01, 32'h03, 32'h07, 32'h0F, 32'h1F, 32'h3F, 32'h7F, 32'hFF};
+   }
+
+   `uvm_object_utils(wb_transaction_extended) 
+
+   function new(string name="" );
+      super.new(name);
+   endfunction: new
+
+endclass: wb_transaction_extended
+
+`endif // WB_TRANSACTION_EXTENDED__SV

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/tests/wb_env_base_test.sv

@@ -0,0 +1,49 @@
+`ifndef BASE_TEST__SV
+ `define BASE_TEST__SV
+
+typedef class wb_env;
+
+class wb_env_base_test extends uvm_test;
+   bit test_pass = 1;
+
+   wb_config wb_master_config;
+   wb_config wb_slave_config;
+
+   `uvm_component_utils(wb_env_base_test)
+
+   wb_env env;
+
+   function new(string name, uvm_component parent);
+      super.new(name, parent);
+   endfunction
+
+   virtual function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      env = wb_env::type_id::create("env", this);
+      wb_master_config = new("wb_master_config");
+      wb_slave_config = new("wb_slave_config");
+
+      wb_master_config.max_n_wss = 10;
+      wb_master_config.min_addr = 0;
+      wb_master_config.max_addr = 10000000;
+
+      wb_slave_config.max_n_wss = 10;
+      wb_slave_config.min_addr = 0;
+      wb_slave_config.max_addr = 10000000;
+
+      begin: configure
+	 uvm_config_db #(uvm_object_wrapper)::set(this, "env.master_agent.mast_sqr.run_phase", "default_sequence", sequence_1::get_type()); 
+	 uvm_config_db #(uvm_object_wrapper)::set(this, "env.slave_agent.slv_seqr.run_phase", "default_sequence", ram_sequence::get_type()); 
+
+	 uvm_config_db #(wb_config)::set(this, "env.master_agent", "config", wb_master_config); 
+	 uvm_config_db #(wb_config)::set(this, "env.slave_agent", "config", wb_slave_config); 
+      end 
+   endfunction
+   task run_phase(uvm_phase phase);
+      //    obj_.set_drain_time(this, 50);  Dont use this. Use Objections in Sequence
+   endtask : run_phase
+
+endclass : wb_env_base_test
+
+`endif //BASE_TEST__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/tests/wb_env_tb_mod.sv

@@ -0,0 +1,30 @@
+// Code your testbench here
+// or browse Examples
+
+`ifndef WB_ENV_TB_MOD__SV
+ `define WB_ENV_TB_MOD__SV
+`include "uvm_macros.svh"
+
+ //`include "mstr_slv_intfs.incl"
+ `include "wb_test.pkg"
+
+module wb_env_tb_mod;
+
+   import uvm_pkg::*;
+   import wb_tests::*;
+
+   typedef virtual wb_master_if v_if1;
+   typedef virtual wb_slave_if v_if2;
+   initial begin
+      uvm_config_db #(v_if1)::set(null,"uvm_test_top.env.master_agent","mst_if",wb_env_top_mod.mast_if); 
+      uvm_config_db #(v_if2)::set(null,"uvm_test_top.env.slave_agent","slv_if",wb_env_top_mod.slave_if);
+      uvm_config_db #(bit) :: set(null,"env.slave_agent","is_active",1);
+      uvm_config_db #(bit) :: set(null,"env.master_agent","is_active",1);
+
+      run_test();
+   end
+
+endmodule: wb_env_tb_mod
+
+`endif // WB_ENV_TB_MOD__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/tests/wb_env_test.sv

@@ -0,0 +1,54 @@
+`ifndef WB_ENV_TEST
+`define WB_ENV_TEST
+typedef class wb_env_env;
+
+class wb_env_test extends uvm_test;
+bit test_pass = 1;
+wb_config master_config;
+wb_config slave_config;
+int slave_adr_max ;
+int slave_adr_min;
+
+
+
+  `uvm_component_utils(wb_env_test)
+
+  wb_env_env env;
+
+  function new(string name, uvm_component parent);
+    super.new(name, parent);
+  endfunction
+
+  virtual function void build_phase(uvm_phase phase);
+    super.build_phase(phase);
+    slave_adr_min = 32'h0;
+    slave_adr_max = 32'h0fffffe;
+
+// Create and Build the configuration
+	master_config = wb_config::type_id::create("master_configuration");
+	slave_config = wb_config::type_id::create("slave_configuration");
+// Randomize the configuration
+	  slave_config.randomize with {min_addr == slave_adr_min; max_addr == slave_adr_max; max_n_wss == 2; };
+	  master_config.randomize with {min_addr == slave_adr_min; max_addr == slave_adr_max; max_n_wss == 2; };
+// Set in Config DB
+      uvm_config_db #(wb_config)::set(null,"uvm_test_top.env.master_agent","mstr_agent_cfg",master_config);
+      uvm_config_db #(wb_config)::set(null,"uvm_test_top.env.slave_agent","mstr_agent_cfg",slave_config);
+    env = wb_env_env::type_id::create("env", this);
+
+    uvm_config_db #(uvm_object_wrapper)::set(this, "env.master_agent.mast_sqr.main_phase", "default_sequence", sequence_1::get_type()); 
+  endfunction
+
+  function void report_phase(uvm_phase phase);
+    if(test_pass) begin
+      `uvm_info(get_type_name(), "** UVM TEST PASSED **", UVM_NONE)
+    end
+    else begin
+      `uvm_error(get_type_name(), "** UVM TEST FAIL **")
+    end
+  endfunction
+
+
+endclass : wb_env_test
+
+`endif //TEST__SV
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_2-Putting_it_all_Together/tests/wb_env_test_extended.sv

@@ -0,0 +1,16 @@
+
+class wb_env_test_extended extends wb_env_base_test;
+
+   `uvm_component_utils(wb_env_test_extended)
+
+   virtual function void build_phase(uvm_phase phase);
+      super.build_phase(phase);
+      wb_transaction::type_id::set_type_override(wb_transaction_extended::get_type());
+      uvm_config_db #(uvm_object_wrapper)::set(this, "env.master_agent.mast_sqr.main_phase", "default_sequence", sequence_0::get_type());
+   endfunction
+
+   function new(string name="wb_env_test_extended",uvm_component parent);
+      super.new(name,parent);
+   endfunction
+
+endclass

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_3_Stimulus_Generation/README.md

@@ -0,0 +1,10 @@
+
+There are 2 files in this directory and 2 Directories.
+
+The grab_ungrab.sv shows a simple sequence which can be used in the example from Part2.
+The priority shows how to handle priority in sequences. 
+
+To have a complete example, use the examples in the 2 directories. These are FULLY 
+ working environments.  The ONLY file that has changed in both xamples 
+
+

Practical-UVM-Step-By-Step_Practical-UVM-Step-By-Step/Part_3_Stimulus_Generation/grab.sv

@@ -0,0 +1,16 @@
+class grab_sequence extends base_sequence;
+  byte sa;
+  `uvm_object_utils(grab_sequence)
+  `uvm_add_to_seq_lib(grab_sequence, wb_master_seqr_sequence_library)
+  function new(string name = "int_seq");
+    super.new(name);
+  endfunction:new
+  virtual task body();
+`uvm_info(get_type_name(),"STARTING INTERRUPT SEQUENCE",UVM_LOW)		
+grab();
+      `uvm_do_with(req, {address == 15; kind == wb_transaction::READ ;} )
+       `uvm_do_with(req,{address == 14; kind == wb_transaction::WRITE; data == 63'hbeefdead;} )
+      `uvm_do_with(req, {address == 13; kind == wb_transaction::READ;} ) 
+ungrab();
+  endtask
+endclass