Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)
23d354c verified | module sdf_test1 (clk, d, q); | |
| input clk, d; | |
| output q; | |
| wire n1; | |
| BUF_X1 buf1 (.A(d), .Z(n1)); | |
| DFF_X1 reg1 (.D(n1), .CK(clk), .Q(q)); | |
| endmodule | |