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Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)
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# Test SDF read and annotation
source ../../test/helpers.tcl
set test_name sdf_read_write
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdf_test1.v
link_design sdf_test1
create_clock -name clk -period 10 [get_ports clk]
# Read SDF
read_sdf sdf_test1.sdf
# Write SDF
set sdf_out [make_result_file $test_name.sdf]
write_sdf $sdf_out
diff_files $test_name.sdfok $sdf_out {\(DATE|\(VERSION}