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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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verilog_data-1
/
The-OpenROAD-Project_OpenSTA
/
sdc
/
test
/
sdc_design_rules_limits.ok
SAIFIINDUSTRIES
Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)
23d354c
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5 days ago
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