The-OpenROAD-Project_OpenSTA/sdc/test/sdc_derate_disable_deep.ok

Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00 ^ reg1/CK (DFF_X1)
   0.08   10.08 v reg1/Q (DFF_X1)
   0.00   10.08 v reg3/D (DFF_X1)
          10.08   data arrival time

  20.00   20.00   clock clk2 (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg3/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
         -10.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00 ^ reg1/CK (DFF_X1)
   0.08   10.08 v reg1/Q (DFF_X1)
   0.00   10.08 v reg3/D (DFF_X1)
          10.08   data arrival time

  20.00   20.00   clock clk2 (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg3/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
         -10.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00 ^ reg1/CK (DFF_X1)
   0.08   10.08 v reg1/Q (DFF_X1)
   0.00   10.08 v reg3/D (DFF_X1)
          10.08   data arrival time

  20.00   20.00   clock clk2 (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg3/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
         -10.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00 ^ reg1/CK (DFF_X1)
   0.08   10.08 v reg1/Q (DFF_X1)
   0.00   10.08 v reg3/D (DFF_X1)
          10.08   data arrival time

  20.00   20.00   clock clk2 (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg3/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
         -10.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)


No differences found.
No differences found.
disabled_edges_sorted count = 1
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk1 (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg2/CK (DFF_X1)
   0.08    0.08 ^ reg2/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  10.00   10.00   clock clk1 (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00 ^ reg1/CK (DFF_X1)
   0.08   10.08 v reg1/Q (DFF_X1)
   0.00   10.08 v reg3/D (DFF_X1)
          10.08   data arrival time

  20.00   20.00   clock clk2 (rise edge)
   0.00   20.00   clock network delay (ideal)
   0.00   20.00   clock reconvergence pessimism
          20.00 ^ reg3/CK (DFF_X1)
  -0.04   19.96   library setup time
          19.96   data required time
---------------------------------------------------------
          19.96   data required time
         -10.08   data arrival time
---------------------------------------------------------
           9.88   slack (MET)