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Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)
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module graph_test1 (clk, d, q);
input clk, d;
output q;
wire n1;
DFF_X1 reg1 (.D(d), .CK(clk), .Q(n1));
DFF_X1 reg2 (.D(n1), .CK(clk), .Q(q));
endmodule