Add batch 10 (abdelazeem201_Systolic-array-implementation-in-RTL-for-TPU, MiSTer-devel_ao486_MiSTer, pulp-platform_cheshire, WangXuan95_FPGA-ftdi245fifo, wuxx_Colorlight-FPGA-Projects)
ed7714b verified | set_global_assignment -name SYNTHESIS_ONLY_QIP ON | |
| set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"] | |
| set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"] | |
| set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"] | |
| set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"] | |