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verilog_data-1 / The-OpenROAD-Project_OpenSTA /test /get_is_buffer.v

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Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)

23d354c verified 6 days ago

123 Bytes

	module dut (
	input A,
	output Y
	);

	sky130_fd_sc_hd__buf_2 buf_inst (
	.A(A),
	.X(Y)
	);

	endmodule