ZipCPU_wbuart32/wbuart32.core

CAPI=1
[main]
description = A full featured UART with Simulator
simulators = verilator

[fileset rtl]
files =
  rtl/rxuartlite.v
  rtl/txuartlite.v
  rtl/rxuart.v
  rtl/txuart.v
  rtl/ufifo.v
  rtl/wbuart.v
file_type = verilogSource

[verilator]
verilator_options =
tb_toplevel = bench/cpp/linetest.cpp
top_module  = linetest
source_type = CPP
src_files = bench/cpp/linetest.cpp bench/cpp/uartsim.cpp
include_files = bench/cpp/uartsim.h

[fileset tb_files]
files = bench/verilog/linetest.v
usage = verilator
file_type = verilogSource
scope = private