SAIFIINDUSTRIES's picture
Add batch 11 (FPGAwars_icezum, WangXuan95_FPGA-CAN, TILOS-AI-Institute_MacroPlacement, ZipCPU_wbuart32, WangXuan95_FPGA-SDcard-Reader)
e990697 verified
Raw
History Blame
383 Bytes
[tasks]
prf
cvr
[options]
prf: mode prove
cvr: mode cover
multiclock on
prf: depth 110
cvr: depth 720
[engines]
smtbmc yices
[script]
prf: read -formal -DRXUARTLITE -D PHASE_TWO rxuartlite.v
cvr: read -formal -DRXUARTLITE -D PHASE_TWO rxuartlite.v
hierarchy -top rxuartlite -chparam CLOCKS_PER_BAUD 16
prep -top rxuartlite
# opt_merge -share_all
[files]
../../rtl/rxuartlite.v