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Add batch 1 (tiny-tpu-v2_tiny-tpu, chili-chips-ba_wireguard-fpga, ultraembedded_biriscv, EttusResearch_uhd, circuitvalley_USB_C_Industrial_Camera_FPGA_USB3)
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#
# Copyright 2010 Ettus Research LLC
#
##################################################
# Timing Sources
##################################################
TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../timing/, \
time_64bit.v \
time_compare.v \
time_receiver.v \
time_sender.v \
time_sync.v \
timer.v \
simple_timer.v \
))