Add batch 1 (tiny-tpu-v2_tiny-tpu, chili-chips-ba_wireguard-fpga, ultraembedded_biriscv, EttusResearch_uhd, circuitvalley_USB_C_Industrial_Camera_FPGA_USB3)
7b1962c verified | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $ | |
| /////////////////////////////////////////////////////////////////////////////// | |
| // Copyright (c) 1995/2004 Xilinx, Inc. | |
| // All Right Reserved. | |
| /////////////////////////////////////////////////////////////////////////////// | |
| // ____ ____ | |
| // / /\/ / | |
| // /___/ \ / Vendor : Xilinx | |
| // \ \ \/ Version : 8.1i (I.13) | |
| // \ \ Description : Xilinx Functional Simulation Library Component | |
| // / / Global Clock Buffer | |
| // /___/ /\ Filename : BUFG.v | |
| // \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 | |
| // \___\/\___\ | |
| // | |
| // Revision: | |
| // 03/23/04 - Initial version. | |
| // End Revision | |
| module BUFG (O, I); | |
| output O; | |
| input I; | |
| buf B1 (O, I); | |
| endmodule | |