verilog_data-1 / EttusResearch_uhd /.ci /utils /requirements.txt
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Add batch 1 (tiny-tpu-v2_tiny-tpu, chili-chips-ba_wireguard-fpga, ultraembedded_biriscv, EttusResearch_uhd, circuitvalley_USB_C_Industrial_Camera_FPGA_USB3)
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labgrid==24.0.3
fabric==3.2.2
pyroute2==0.8.1
pottery==3.0.0
py3tftp==1.3.0