verilog_data-1 / EttusResearch_uhd /.ci /uhd-pipeline-pr.yml
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Add batch 1 (tiny-tpu-v2_tiny-tpu, chili-chips-ba_wireguard-fpga, ultraembedded_biriscv, EttusResearch_uhd, circuitvalley_USB_C_Industrial_Camera_FPGA_USB3)
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
parameters:
# Force enable/disable modules, examples:
#
# Force-enable/disable UHD builds...
# ... for all OS: uhd.build.all
# ... for Linux: uhd.build.linux
# ... for Windows: uhd.build.windows
# ... for macOS: uhd.build.mac
#
# Force-enable/disable MPM builds...
# ... for all devs: mpm.build.all
#
# Force-enable/disable FPGA images builds...
# ... all FPGAs: fpga.usrp3.all
# ... E31X FPGAs: fpga.usrp3.e31x
# ... E320 FPGAs: fpga.usrp3.e320
# ... N3XX FPGAs: fpga.usrp3.n3xx
# ... X4XX FPGAs: fpga.usrp3.x4xx
# ... X410 FPGAs: fpga.usrp3.x410
# ... X440 FPGAs: fpga.usrp3.x440
#
# Force-enable/disable tests...
# ... Devtests: devtest.all
# ... Streaming tests: hw.streaming.all
# ... RF tests: hw.rf.all
#
# For more examples, see tools/changeset_testlist.yaml
- name: add_tests
displayName: Force-enable modules
type: string
default: "none"
- name: remove_tests
displayName: Force-disable modules
type: string
default: "none"
- name: skip_rule_checking
displayName: Skip rule checking (execute "Force-enable modules" only)
type: boolean
default: False
- name: custom_boost_version
type: boolean
displayName: Use custom boost version
default: false
- name: custom_boost_version_url
type: string
displayName: Custom Boost URL
default: 'https://boostorg.jfrog.io/artifactory/main/release/1.76.0/source/boost_1_76_0.tar.bz2'
- name: release_binaries
type: boolean
displayName: Set release mode for installers
default: false
- name: testLength
type: string
values:
- 'smoke'
- 'full'
- 'stress'
displayName: Test Length
default: 'smoke'
- name: create_sbom
type: boolean
displayName: Create SBOM for filesystem images
default: false
- name: build_sdk
type: boolean
displayName: Build embedded image SDKs
default: false
- name: cache_sstate
type: boolean
displayName: Use sstate cache for embedded builds
default: true
- name: build_e310_sg1
type: boolean
displayName: Build e310_sg1 filesystem image
default: true
- name: build_e310_sg3
type: boolean
displayName: Build e310_sg3 filesystem image
default: true
- name: build_e320
type: boolean
displayName: Build e320 filesystem image
default: true
- name: build_n3xx
type: boolean
displayName: Build n3xx filesystem image
default: true
- name: build_x4xx
type: boolean
displayName: Build x4xx filesystem image
default: true
- name: ext_fpga
type: boolean
displayName: Use pipeline FPGA build
default: true
- name: cmake_args
type: string
displayName: Additional CMake arguments (optional)
default: ' '
- name: fpga_imgs_source
type: string
values:
- 'files.ettus.com (Public)'
- 'Internal Repo'
- 'Mono Pipeline'
- 'Mono Pipeline PR'
- 'FPGA Pipeline'
displayName: FPGA Images Source
default: 'Mono Pipeline'
# FPGA Parameters
- name: clean_ip_build
type: boolean
displayName: Clean IP Build
default: false
- name: num_ip_jobs
type: number
default: 5
displayName: Number of parallel IP jobs
- name: package_and_publish_images
type: boolean
displayName: Package & Publish Images
default: false
# Package access: This controls from where we download the FPGA images, if we
# are not building them.
- name: package_access
type: string
values:
- 'Internal'
- 'files.ettus.com (Public)'
displayName: Published Package Access
default: 'Internal'
- name: use_low_success_fpga_targets
type: boolean
displayName: Force use of FPGA with low-success compile rates
default: false
- name: selected_streaming_tests
type: string
displayName: Streaming Tests Multi-Select (comma-separated)
default: 'B206,B210,B310,X310_XG,X410_CG_400,X410_UC_200,X440_CG_400,X440_CG_1600'
trigger: none
pr:
branches:
include:
- master
- UHD-*
paths:
include:
- host
- mpm
- fpga
- .ci
- images/manifest.txt
exclude:
- .ci/docker
- host/LICENSE
- host/README.md
drafts: false
extends:
template: templates/stages-uhd-pipeline.yml
parameters:
add_tests: ${{ parameters.add_tests }}
remove_tests: ${{ parameters.remove_tests }}
skip_rule_checking: ${{ parameters.skip_rule_checking }}
custom_boost_version: ${{ parameters.custom_boost_version }}
custom_boost_version_url: ${{ parameters.custom_boost_version_url }}
release_binaries: ${{ parameters.release_binaries }}
testLength: ${{ parameters.testLength }}
create_sbom: ${{ parameters.create_sbom }}
build_sdk: ${{ parameters.build_sdk }}
cache_sstate: ${{ parameters.cache_sstate }}
build_e310_sg1: ${{ parameters.build_e310_sg1 }}
build_e310_sg3: ${{ parameters.build_e310_sg3 }}
build_e320: ${{ parameters.build_e320 }}
build_n3xx: ${{ parameters.build_n3xx }}
build_x4xx: ${{ parameters.build_x4xx }}
cmake_args: ${{ parameters.cmake_args }}
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
# FPGA parameters
clean_ip_build: ${{ parameters.clean_ip_build }}
publish_int_files: true
package_and_publish_images: ${{ parameters.package_and_publish_images }}
package_access: ${{ parameters.package_access }}
use_low_success_fpga_targets: ${{ parameters.use_low_success_fpga_targets }}
# Test parameters
selected_streaming_tests: ${{ parameters.selected_streaming_tests }}