File size: 19,446 Bytes
23d354c | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 | --- read_sdf with timing checks ---
--- report_checks with SDF ---
Startpoint: d1 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.13 0.69 v nor1/ZN (NOR2_X1)
0.03 0.72 v reg3/D (DFF_X1)
0.72 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.72 data arrival time
---------------------------------------------------------
9.25 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ en (in)
0.02 0.02 v nand1/ZN (NAND2_X1)
0.01 0.03 v reg2/D (DFF_X1)
0.03 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.05 0.05 library hold time
0.05 data required time
---------------------------------------------------------
0.05 data required time
-0.03 data arrival time
---------------------------------------------------------
-0.02 slack (VIOLATED)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.13 0.69 v nor1/ZN (NOR2_X1)
0.03 0.72 v reg3/D (DFF_X1)
0.72 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.72 data arrival time
---------------------------------------------------------
9.25 slack (MET)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.13 0.69 v nor1/ZN (NOR2_X1)
0.03 0.72 v reg3/D (DFF_X1)
0.72 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.72 data arrival time
---------------------------------------------------------
9.25 slack (MET)
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
--- report_annotated_delay ---
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
internal net arcs 11 11 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 3 0 3
----------------------------------------------------------------
37 28 9
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
----------------------------------------------------------------
17 17 0
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
internal net arcs 11 11 0
----------------------------------------------------------------
11 11 0
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
net arcs from primary inputs 6 0 6
----------------------------------------------------------------
6 0 6
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
net arcs to primary outputs 3 0 3
----------------------------------------------------------------
3 0 3
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
internal net arcs 11 11 0
----------------------------------------------------------------
28 28 0
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
internal net arcs 11 11 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 3 0 3
----------------------------------------------------------------
37 28 9
Annotated Arcs
delay and1/A1 -> and1/ZN
delay and1/A2 -> and1/ZN
internal net and1/ZN -> or1/A2
delay buf1/A -> buf1/Z
internal net buf1/Z -> inv1/A
internal net buf1/Z -> and1/A1
delay buf2/A -> buf2/Z
internal net buf2/Z -> and1/A2
delay inv1/A -> inv1/ZN
internal net inv1/ZN -> or1/A1
internal net inv1/ZN -> nor1/A1
delay nand1/A1 -> nand1/ZN
delay nand1/A2 -> nand1/ZN
internal net nand1/ZN -> nor1/A2
internal net nand1/ZN -> reg2/D
delay nor1/A1 -> nor1/ZN
delay nor1/A2 -> nor1/ZN
internal net nor1/ZN -> reg3/D
delay or1/A1 -> or1/ZN
delay or1/A2 -> or1/ZN
internal net or1/ZN -> nand1/A1
internal net or1/ZN -> reg1/D
delay reg1/CK -> reg1/QN
delay reg1/CK -> reg1/Q
delay reg2/CK -> reg2/QN
delay reg2/CK -> reg2/Q
delay reg3/CK -> reg3/QN
delay reg3/CK -> reg3/Q
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
internal net arcs 11 11 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 3 0 3
----------------------------------------------------------------
37 28 9
Unannotated Arcs
primary input net clk -> reg1/CK
primary input net clk -> reg2/CK
primary input net clk -> reg3/CK
primary input net d1 -> buf1/A
primary input net d2 -> buf2/A
primary input net en -> nand1/A2
primary output net reg1/Q -> q1
primary output net reg2/Q -> q2
primary output net reg3/Q -> q3
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
constant arcs 0 0
internal net arcs 11 11 0
constant arcs 0 0
net arcs from primary inputs 6 0 6
constant arcs 0 0
net arcs to primary outputs 3 0 3
constant arcs 0 0
----------------------------------------------------------------
37 28 9
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 17 17 0
internal net arcs 11 11 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 3 0 3
----------------------------------------------------------------
37 28 9
--- report_annotated_check ---
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
----------------------------------------------------------------
3 3 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell hold arcs 3 3 0
----------------------------------------------------------------
3 3 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell width arcs 3 3 0
----------------------------------------------------------------
3 3 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
----------------------------------------------------------------
6 6 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
----------------------------------------------------------------
6 6 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell width arcs 3 3 0
----------------------------------------------------------------
3 3 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
cell width arcs 3 3 0
----------------------------------------------------------------
9 9 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
cell width arcs 3 3 0
----------------------------------------------------------------
9 9 0
Annotated Arcs
width reg1/CK -> reg1/CK
setup reg1/CK -> reg1/D
hold reg1/CK -> reg1/D
width reg2/CK -> reg2/CK
setup reg2/CK -> reg2/D
hold reg2/CK -> reg2/D
width reg3/CK -> reg3/CK
setup reg3/CK -> reg3/D
hold reg3/CK -> reg3/D
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
cell width arcs 3 3 0
----------------------------------------------------------------
9 9 0
Unannotated Arcs
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
constant arcs 0 0
cell hold arcs 3 3 0
constant arcs 0 0
cell width arcs 3 3 0
constant arcs 0 0
----------------------------------------------------------------
9 9 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 3 3 0
cell hold arcs 3 3 0
cell width arcs 3 3 0
----------------------------------------------------------------
9 9 0
--- write_sdf ---
--- re-read SDF ---
Startpoint: d1 (input port clocked by clk)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.13 0.69 v nor1/ZN (NOR2_X1)
0.03 0.72 v reg3/D (DFF_X1)
0.72 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg3/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.72 data arrival time
---------------------------------------------------------
9.25 slack (MET)
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