File size: 20,813 Bytes
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Warning 192: sdf_cond_pathpulse.sdf line 97, cell DFF_X1 CK -> D skew check not found.
--- Test 2: timing paths ---
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.58 data arrival time
---------------------------------------------------------
9.39 slack (MET)
Startpoint: sel (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ sel (in)
0.02 0.02 v nand1/ZN (NAND2_X1)
0.01 0.03 v reg2/D (DFF_X1)
0.03 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.03 0.03 library hold time
0.03 data required time
---------------------------------------------------------
0.03 data required time
-0.03 data arrival time
---------------------------------------------------------
0.00 slack (VIOLATED)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.58 data arrival time
---------------------------------------------------------
9.39 slack (MET)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.58 data arrival time
---------------------------------------------------------
9.39 slack (MET)
No paths found.
No paths found.
No paths found.
No paths found.
No paths found.
--- Test 3: annotated reports ---
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 12 11 1
internal net arcs 6 6 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 2 0 2
----------------------------------------------------------------
26 17 9
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 12 11 1
----------------------------------------------------------------
12 11 1
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
internal net arcs 6 6 0
----------------------------------------------------------------
6 6 0
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
net arcs from primary inputs 6 0 6
----------------------------------------------------------------
6 0 6
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
net arcs to primary outputs 2 0 2
----------------------------------------------------------------
2 0 2
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 12 11 1
internal net arcs 6 6 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 2 0 2
----------------------------------------------------------------
26 17 9
Annotated Arcs
delay and1/A1 -> and1/ZN
delay and1/A2 -> and1/ZN
internal net and1/ZN -> or1/A2
delay buf1/A -> buf1/Z
internal net buf1/Z -> and1/A1
delay inv1/A -> inv1/ZN
internal net inv1/ZN -> or1/A1
delay nand1/A1 -> nand1/ZN
delay nand1/A2 -> nand1/ZN
internal net nand1/ZN -> reg2/D
delay or1/A1 -> or1/ZN
delay or1/A2 -> or1/ZN
internal net or1/ZN -> nand1/A1
internal net or1/ZN -> reg1/D
delay reg1/CK -> reg1/QN
delay reg1/CK -> reg1/Q
delay reg2/CK -> reg2/Q
Not
Delay type Total Annotated Annotated
----------------------------------------------------------------
cell arcs 12 11 1
internal net arcs 6 6 0
net arcs from primary inputs 6 0 6
net arcs to primary outputs 2 0 2
----------------------------------------------------------------
26 17 9
Unannotated Arcs
primary input net clk -> reg1/CK
primary input net clk -> reg2/CK
primary input net d1 -> buf1/A
primary input net d2 -> inv1/A
primary input net sel -> and1/A2
primary input net sel -> nand1/A2
primary output net reg1/Q -> q1
delay reg2/CK -> reg2/QN
primary output net reg2/Q -> q2
--- Test 4: annotated checks ---
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 2 2 0
----------------------------------------------------------------
2 2 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell hold arcs 2 2 0
----------------------------------------------------------------
2 2 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell width arcs 2 1 1
----------------------------------------------------------------
2 1 1
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
----------------------------------------------------------------
0 0 0
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 2 2 0
cell hold arcs 2 2 0
cell width arcs 2 1 1
----------------------------------------------------------------
6 5 1
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 2 2 0
cell hold arcs 2 2 0
cell width arcs 2 1 1
----------------------------------------------------------------
6 5 1
Annotated Arcs
width reg1/CK -> reg1/CK
setup reg1/CK -> reg1/D
hold reg1/CK -> reg1/D
setup reg2/CK -> reg2/D
hold reg2/CK -> reg2/D
Not
Check type Total Annotated Annotated
----------------------------------------------------------------
cell setup arcs 2 2 0
cell hold arcs 2 2 0
cell width arcs 2 1 1
----------------------------------------------------------------
6 5 1
Unannotated Arcs
width reg2/CK -> reg2/CK
--- Test 5: write SDF ---
--- Test 6: detailed reports ---
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
1 0.88 0.10 0.00 0.00 v d1 (in)
d1 (net)
0.10 0.00 0.00 v buf1/A (BUF_X1)
1 0.87 0.01 0.14 0.14 v buf1/Z (BUF_X1)
n1 (net)
0.01 0.03 0.17 v and1/A1 (AND2_X1)
1 0.90 0.01 0.13 0.30 v and1/ZN (AND2_X1)
n3 (net)
0.01 0.03 0.33 v or1/A2 (OR2_X1)
2 2.59 0.01 0.10 0.43 v or1/ZN (OR2_X1)
n4 (net)
0.01 0.03 0.46 v nand1/A1 (NAND2_X1)
1 1.14 0.02 0.10 0.56 ^ nand1/ZN (NAND2_X1)
n5 (net)
0.02 0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
-----------------------------------------------------------------------------
9.97 data required time
-0.58 data arrival time
-----------------------------------------------------------------------------
9.39 slack (MET)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
-----------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
0.000000 0.000000 clock network delay (ideal)
0.000000 0.000000 v input external delay
0.000000 0.000000 v d1 (in)
0.140000 0.140000 v buf1/Z (BUF_X1)
0.160000 0.300000 v and1/ZN (AND2_X1)
0.130000 0.430000 v or1/ZN (OR2_X1)
0.130000 0.560000 ^ nand1/ZN (NAND2_X1)
0.020000 0.580000 ^ reg2/D (DFF_X1)
0.580000 data arrival time
10.000000 10.000000 clock clk (rise edge)
0.000000 10.000000 clock network delay (ideal)
0.000000 10.000000 clock reconvergence pessimism
10.000000 ^ reg2/CK (DFF_X1)
-0.030000 9.970000 library setup time
9.970000 data required time
-----------------------------------------------------------------
9.970000 data required time
-0.580000 data arrival time
-----------------------------------------------------------------
9.390000 slack (MET)
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.58 data arrival time
---------------------------------------------------------
9.39 slack (MET)
Startpoint: sel (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ sel (in)
0.02 0.02 v nand1/ZN (NAND2_X1)
0.01 0.03 v reg2/D (DFF_X1)
0.03 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.03 0.03 library hold time
0.03 data required time
---------------------------------------------------------
0.03 data required time
-0.03 data arrival time
---------------------------------------------------------
0.00 slack (VIOLATED)
No paths found.
No paths found.
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg1/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
0.60 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.40 slack (MET)
Pin: reg1/CK
10.00 period
-1.00 min period
---------------------------------------------------------
9.00 slack (MET)
--- Test 7: re-read SDF ---
Warning 192: sdf_cond_pathpulse.sdf line 97, cell DFF_X1 CK -> D skew check not found.
Startpoint: d1 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v d1 (in)
0.14 0.14 v buf1/Z (BUF_X1)
0.16 0.30 v and1/ZN (AND2_X1)
0.13 0.43 v or1/ZN (OR2_X1)
0.13 0.56 ^ nand1/ZN (NAND2_X1)
0.02 0.58 ^ reg2/D (DFF_X1)
0.58 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.58 data arrival time
---------------------------------------------------------
9.39 slack (MET)
--- Test 8: combined write ---
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