File size: 442 Bytes
ed7714b | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 | `timescale 1ns / 1ps
`default_nettype none
module synchronizer #(
parameter DATA_WIDTH = 1
) (
input wire clk, // clock domain of out
input wire [DATA_WIDTH-1:0] in,
output logic [DATA_WIDTH-1:0] out
);
logic [1:0] [DATA_WIDTH-1:0] sync_regs = 0;
always_ff @(posedge clk)
{sync_regs[1], sync_regs[0]} <= {sync_regs[0], in};
always_comb out = sync_regs[1];
endmodule
`default_nettype wire |