File size: 1,885 Bytes
54c34c9 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 | #ifndef SRC_DEFINES_H_
#define SRC_DEFINES_H_
#include "xparameters.h"
#define CACHE_LINE_SIZE 32
#define MM_ADDR XPAR_MM_ULTRA_TOP_0_BASEADDR
#define SHIFT_ADDR MM_ADDR
#define FL_ADDR (MM_ADDR + 0x04)
#define FWBN_ADDR (MM_ADDR +0x08)
#define WWBN_ADDR (MM_ADDR +0x0c)
#define WEIGHT_DMA_ADDR XPAR_AXI_DMA_1_BASEADDR
#define WEIGHT_MM2S_DMACR (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
#define WEIGHT_MM2S_DMASR (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
#define WEIGHT_MM2S_SA (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
#define WEIGHT_MM2S_LENGTH (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
#define FEATURE_DMA_ADDR XPAR_AXI_DMA_0_BASEADDR
#define FEATURE_MM2S_DMACR (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
#define FEATURE_MM2S_DMASR (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
#define FEATURE_MM2S_SA (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
#define FEATURE_MM2S_LENGTH (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
#define RESULT_DMA_ADDR XPAR_AXI_DMA_2_BASEADDR
#define RESULT_S2MM_DMACR (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET) //S2MM DMA Control register
#define RESULT_S2MM_DMASR (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET) //S2MM DMA Status register
#define RESULT_S2MM_DA (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //S2MM Destination Address
#define RESULT_S2MM_LENGTH (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //S2MM Transfer Length (Bytes)
#define A_SIZE 24
#endif /* SRC_DEFINES_H_ */
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