Add repo: Buck008_Transformer-Accelerator-Based-on-FPGA

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/sim/Softmax_top_tb.sv

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+`timescale 1ns / 1ps
+`define length 197
+`define scale_in 6
+`define scale_out 7
+//scale_in and scale_out must be kept during the valid_in, min =-1, max =10
+//scale_out min = 7,max  = 12
+module Softmax_top_tb;
+reg                           clk;
+reg                           rst_n;
+
+reg [9:0]                     length;
+reg signed [4:0]              scale_in;
+reg [3:0]                     scale_out;
+
+wire signed [7:0]             top_data_in;
+reg                           top_valid_in;
+wire                          top_ready_in;
+reg                           top_last_in;
+
+wire    [7:0]                 top_data_out;
+wire                          top_valid_out;
+wire                          top_last_out;
+
+Softmax_control u_Softmax_control(
+    .clk(clk),
+    .length_input(length),
+    .rst_n(rst_n),
+    .scale_in_input(scale_in),
+    .scale_out_input(scale_out),
+
+    .top_data_in(top_data_in),
+    .top_valid_in(top_valid_in),
+    .top_ready_in(top_ready_in),
+    .top_last_in(top_last_in),
+
+    .top_data_out(top_data_out),
+    .top_valid_out(top_valid_out),    
+    .top_last_out(top_last_out)
+);
+
+task Softmax_task(input real x[`length-1:0], output real y[`length-1:0] );
+begin
+    automatic int Scnt = 0;
+    automatic real in_max = 0;
+    automatic real exp[`length];
+    automatic real exp_sum = 0;
+    
+    for(Scnt = 0;Scnt<`length;Scnt++)begin
+        if(in_max<x[Scnt])
+            in_max = x[Scnt];
+    end
+    
+    for(Scnt = 0;Scnt<`length;Scnt++)begin
+        x[Scnt] = x[Scnt] - in_max;
+        exp[Scnt] = $exp(x[Scnt]);
+        exp_sum = exp_sum + exp[Scnt];
+    end
+    
+    for(Scnt = 0;Scnt<`length;Scnt++)begin
+        y[Scnt] = exp[Scnt]/exp_sum;
+    end
+end
+endtask
+
+reg [9:0] cnt;
+reg [9:0] cnt_valid;
+reg [9:0] y_cnt;
+
+real x_real [`length - 1:0];
+real y_real [`length - 1:0];
+reg [31:0] time_cnt;
+reg signed [7:0] x_hard [`length-1:0];
+reg signed [7:0] y_hard [`length-1:0];
+reg control_valid;
+
+
+real differ;
+real temp1;
+real temp2;
+real hard_max;
+real real_max;
+real error_cnt;
+
+always @(posedge clk) begin
+    if(u_Softmax_control.u_Softmax.out_last | (!top_ready_in))
+        control_valid = 0;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        time_cnt<=0;
+    else
+        time_cnt<=time_cnt+1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        cnt_valid<=0;
+    else 
+        cnt_valid <= cnt_valid +1;
+end
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        cnt<=0;
+    else if(cnt == length)
+        cnt<=0;
+    else if(top_valid_in & top_ready_in)
+        cnt <= cnt+1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        y_cnt<=0;
+    else if(y_cnt == length-1)
+        y_cnt<=0;
+    else if(top_valid_out)
+        y_cnt <= y_cnt+1;
+    else
+        y_cnt <= y_cnt;
+end
+
+always @(posedge clk ) begin
+    if(top_valid_out)
+        y_hard[y_cnt] <= top_data_out;
+end
+
+assign top_data_in = x_hard[cnt];
+assign top_valid_in =(cnt <= `length-1)&(~cnt_valid[1])&control_valid;
+assign top_last_in = (cnt == `length - 1) ;
+
+initial begin
+    clk = 1;
+end
+
+always  begin
+    #50 clk = ~clk;
+end
+
+
+integer i;
+initial begin
+    control_valid = 0;
+    rst_n = 0;
+
+    length = `length;
+    scale_in = `scale_in;
+    scale_out = `scale_out;
+    for(i=0;i<`length;i++)begin
+        x_hard[i] = 100;
+//        x_hard[i] = $random % 176;
+//        if(i==`length/2)
+//            x_hard[i] = 110;
+//        if(i==`length/3)
+//            x_hard[i] = 10;
+//        if(i==`length/4)
+//            x_hard[i] = 60;
+//        if(i==`length/5)
+//            x_hard[i] = 40; 
+        x_real[i] = $itor($signed(x_hard[i])) * $pow(2, -$itor(scale_in));
+    end
+    Softmax_task(x_real,y_real);
+    control_valid = 1;
+    #350 rst_n = 1;
+    for (i=0;i<5*`length;i++)begin
+        #100;
+    end
+    
+    
+    
+    error_cnt = 0;
+    real_max = 0;
+    hard_max = 0;
+    for (i=0;i<`length;i++)begin
+        temp1 = $itor($signed(y_hard[i])) * $pow(2,-$itor(scale_out));
+        temp2 = y_real[i];
+        if (temp1 >hard_max)
+            hard_max = temp1;
+        if(temp2>real_max)
+            real_max = temp2;
+        differ =  temp1- temp2;
+        if( differ >  $pow(2,-$itor(scale_out)) |differ < -$pow(2,-$itor(scale_out))) begin
+            error_cnt++;
+            $display("%d: differ percentile = %6.4f%%, differ = %6.4f, real = %6.4f, hard = %6.4f",i,differ/y_real[i]*100,differ,temp2,temp1);
+        end
+    end
+    $display("The ratio of error greater than the minimum precision: %6.4f%%",100 *error_cnt / `length);
+    $display("real_max = %6.4f, hard_max = %6.4f",real_max, hard_max);
+    
+    
+    
+    
+    for(i=0;i<`length;i++)begin
+//        x_hard[i] = i;
+        x_hard[i] = $random % 256;
+//        if(i==`length/2)
+//            x_hard[i] = 110;
+//        if(i==`length/3)
+//            x_hard[i] = 10;
+//        if(i==`length/4)
+//            x_hard[i] = 60;
+//        if(i==`length/5)
+//            x_hard[i] = 40; 
+        x_real[i] = $itor($signed(x_hard[i])) * $pow(2, -$itor(scale_in));
+    end
+    Softmax_task(x_real,y_real);
+    control_valid = 1;
+    for (i=0;i<5*`length;i++)begin
+        #100;
+    end
+
+    
+    error_cnt = 0;
+    real_max = 0;
+    hard_max = 0;
+    for (i=0;i<`length;i++)begin
+        temp1 = $itor($signed(y_hard[i])) * $pow(2,-$itor(scale_out));
+        temp2 = y_real[i];
+        if (temp1 >hard_max)
+            hard_max = temp1;
+        if(temp2>real_max)
+            real_max = temp2;
+        differ =  temp1- temp2;
+        if( differ >  $pow(2,-$itor(scale_out)) |differ < -$pow(2,-$itor(scale_out))) begin
+            error_cnt++;
+            $display("%d: differ percentile = %6.5f%%, differ = %6.5f, real = %6.5f, hard = %6.5f, y_hard = %0d",i,differ/y_real[i]*100,differ,temp2,temp1,y_hard[i]);
+        end
+    end
+    $display("The ratio of error greater than the minimum precision: %6.5f%%",100 *error_cnt / `length);
+    $display("real_max = %6.5f, hard_max = %6.5f",real_max, hard_max);
+    #100 $finish();
+end
+
+
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/sim/gelu_tb.sv

@@ -0,0 +1,107 @@
+`timescale 1ns / 1ps
+
+
+module gelu_tb();
+reg [2:0] in_scale;
+reg [7:0] x;
+reg clk;
+reg [127:0] cnt;
+wire [7:0] y;
+
+gelu u_gelu(
+	.clk(clk),
+    .in_scale(in_scale),
+    .x(x),
+    .y_reg1(y)
+);
+
+task gelu_task(input real x, output real y );
+begin
+    automatic real tanh_o;
+    automatic real tanh_i;
+    automatic real pi = 3.1415926535897932;
+    automatic real cst_1;
+    automatic real cst_2 = 0.044715;
+    cst_1 = $sqrt(2/pi);
+    tanh_i = cst_1 * (x + cst_2 * $pow(x,3));
+    tanh_o= $tanh(tanh_i);
+    y= 0.5 * x * (1 + tanh_o);
+end
+endtask
+
+always begin
+	#50 clk=~clk;
+end
+initial begin
+clk=1;
+#20000$display("cnt = %1d",cnt); $display("END");$finish;
+end
+
+initial cnt = 0;
+real y_soft_reg8;
+real y_hard;
+real x_soft;
+real x_soft_reg8;
+real x_hard;
+real temp;
+genvar i;
+//real y_soft_reg_array [7:0];
+//always @(posedge clk ) begin
+//    y_soft_reg_array[0] <= y_soft;
+//end
+
+//generate
+//    for(i=1;i<8;i++)begin
+//        always @(posedge clk ) begin
+//            y_soft_reg_array[i] <= y_soft_reg_array[i-1];
+//        end
+//    end
+//endgenerate
+
+real x_soft_reg_array [7:0];
+always @(posedge clk ) begin
+    x_soft_reg_array[0] <= x_soft;
+end
+
+generate
+    for(i=1;i<8;i++)begin
+        always @(posedge clk ) begin
+            x_soft_reg_array[i] <= x_soft_reg_array[i-1];
+        end
+    end
+endgenerate
+
+reg[2:0] in_scale_reg_array [7:0];
+always @(posedge clk ) begin
+    in_scale_reg_array[0] <= in_scale;
+end
+
+generate
+    for(i=1;i<8;i++)begin
+        always @(posedge clk ) begin
+            in_scale_reg_array[i] <= in_scale_reg_array[i-1];
+        end
+    end
+endgenerate
+assign x_soft_reg8 = x_soft_reg_array[7];
+real differ;
+always begin
+    #50;
+//    x=1;in_scale=2;
+    x = $random % 128;in_scale = {$random}%7;
+    cnt = cnt +1;
+    x_soft = $itor($signed(x)) / $pow(2, $itor(in_scale)) ;
+    gelu_task(x_soft_reg8,y_soft_reg8);
+    y_hard = $itor($signed(y))/$pow(2, $itor(in_scale_reg_array[7]));
+    differ = $pow(2, -$itor(in_scale_reg_array[7]));
+    temp=y_hard-y_soft_reg8;
+    if(temp>differ || temp < -differ)begin
+         $display("diff = %6.3f, y_hard=%6.3f, y_soft=%6.3f, x_soft=%6.3f, cnt = %1d",temp,y_hard,y_soft_reg8,x_soft_reg8,cnt);
+    end
+    
+    #50;
+end
+
+
+
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/EightGelus.v

@@ -0,0 +1,118 @@
+`timescale 1ns / 1ps
+
+module EightGelus
+#(
+    parameter num_gelu  = 4
+)
+(
+    input clk,
+    input rst_n,
+    
+    // input [63:0]  in_data,
+    input [num_gelu*8 -1: 0] in_data,
+    input         in_valid,
+    output        in_ready,
+    input         in_last,
+    // input [7:0]   in_keep,
+    input [num_gelu-1:0]   in_keep,
+    
+    // output [63:0] out_data,
+    output [num_gelu*8 -1: 0]  out_data,
+    output        out_valid,
+    input         out_ready,
+    output        out_last,
+    // output [7:0]  out_keep,
+    output [num_gelu-1:0] out_keep,
+
+    
+    input  [2:0]  scale
+    );
+
+assign in_ready = out_ready;
+reg [8:0] valid_reg;
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        valid_reg[0]<=0;
+    else
+        valid_reg[0] <= in_valid;
+end
+
+genvar i;
+generate
+for(i=1;i<9;i=i+1)begin
+    always@(posedge clk or negedge rst_n)begin
+        if(~rst_n)
+            valid_reg[i]<=0;
+        else           
+            valid_reg[i]<=valid_reg[i-1];
+       
+    end
+end
+endgenerate
+assign out_valid = valid_reg[8];
+
+reg [8:0] last_reg;
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        last_reg[0]<=0;
+    else
+        last_reg[0] <= in_last;
+end
+
+generate
+for(i=1;i<9;i=i+1)begin
+    always@(posedge clk or negedge rst_n)begin
+        if(~rst_n)
+            last_reg[i]<=0;
+        else           
+            last_reg[i]<=last_reg[i-1];
+       
+    end
+end
+endgenerate
+assign out_last = last_reg[8];
+
+
+reg [num_gelu*8-1:0]  in_data_delay1;
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        in_data_delay1<=0;
+    else
+        in_data_delay1<=in_data;
+end
+ 
+reg [num_gelu-1:0] keep_reg [8:0];
+assign out_keep = keep_reg[8];
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        keep_reg[0] <=0;
+    else
+        keep_reg[0] <= in_keep;
+end
+
+generate 
+    for(i=1;i<9;i=i+1)begin
+        always@(posedge clk or negedge rst_n)begin
+            if(~rst_n)
+                keep_reg[i] <=0;
+            else
+                keep_reg[i] <= keep_reg[i-1];
+        end
+    end
+endgenerate
+
+generate
+    for(i=0;i<num_gelu;i=i+1)begin
+        gelu u_gelu(
+            .clk(clk),        
+            .in_scale(scale),
+            .x(in_data_delay1[i*8+7 : i*8]),       
+            .y_reg1(out_data[i*8+7 : i*8])  
+        );
+    end
+endgenerate
+
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Exp_module.v

@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+module Exp_module(//latency = 3
+	input 					clk,      
+    input  signed [19:0]    x_S9Q10, //signed
+    output reg signed [24:0]    y_U0Q25_reg1 //unsigned
+);
+
+wire signed [24:0] x_log2e_S10Q14; //signed��less or equal 0
+reg  signed [24:0] x_log2e_S10Q14_reg1; //signed��less or equal 0
+assign x_log2e_S10Q14  = x_S9Q10 * 6'sd23;
+
+always@(posedge clk)begin
+	x_log2e_S10Q14_reg1 <= x_log2e_S10Q14;
+end
+
+wire [23:0] x_log2e_U10Q14_abs; 
+assign x_log2e_U10Q14_abs = ~x_log2e_S10Q14_reg1+1;
+
+wire [9:0] x_int_10Q0 = x_log2e_U10Q14_abs[23:14];
+
+wire [13:0] x_decimal_0Q14 = x_log2e_U10Q14_abs[13:0];
+
+wire [14:0] temp_1Q14 = 15'b100_0000_0000_0000 - {2'b0,x_decimal_0Q14[13:1]};//1+0.5*x_decimal,unsigned
+reg  [14:0] temp_1Q14_reg1;
+wire [3:0] x_int_4Q0;//unsigned
+assign x_int_4Q0 = (x_int_10Q0 > 12)? 4'd12 : x_int_10Q0;//to 12bits
+
+wire [11:0] temp_2_int_1Q11; 
+reg  [11:0] temp_2_int_1Q11_reg1; 
+assign temp_2_int_1Q11 = 12'b1000_0000_0000 >> x_int_4Q0;
+always@(posedge clk)begin
+	temp_2_int_1Q11_reg1<=temp_2_int_1Q11;
+	temp_1Q14_reg1<=temp_1Q14;
+end
+
+wire [26:0] temp_y_2Q25 = temp_2_int_1Q11_reg1 * temp_1Q14_reg1;//unsigned
+
+
+// wire signed [11:0] y_U0Q12;
+// assign y_U0Q12 = temp_y_2Q25[25] == 1'b1 ? 12'b1111_1111_1111:temp_y_2Q25[24:13];
+wire signed [24:0] y_U0Q25;
+assign y_U0Q25 = temp_y_2Q25[25] == 1'b1 ? 25'h1FF_FFFF:temp_y_2Q25[24:0];
+
+always@(posedge clk)begin 
+	y_U0Q25_reg1<=y_U0Q25;
+end
+
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Gelus_axi.v

@@ -0,0 +1,440 @@
+
+`timescale 1 ns / 1 ps
+
+	module Gelus_axi #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+        parameter integer num_gelu = 4,
+		// Do not modify the parameters beyond this line
+
+		// Width of S_AXI data bus
+		parameter integer C_S_AXI_DATA_WIDTH	= 32,
+		// Width of S_AXI address bus
+		parameter integer C_S_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+		input 										axis_aclk,
+    	input 										aresetn,
+	
+    	input [num_gelu*8-1:0] 	                    s_axis_tdata,
+    	input       								s_axis_tvalid,
+    	output      								s_axis_tready,
+    	input       								s_axis_tlast,
+    	input [num_gelu-1:0]                        s_axis_tkeep,
+	
+    	output [num_gelu*8-1:0] 	                m_axis_tdata,
+    	output       								m_axis_tvalid,
+    	input        								m_axis_tready,
+    	output      			 					m_axis_tlast,
+    	output [num_gelu-1:0]                         m_axis_tkeep,
+
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+		// Global Clock Signal
+		input wire  S_AXI_ACLK,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  S_AXI_ARESETN,
+		// Write address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+		// Write channel Protection type. This signal indicates the
+    		// privilege and security level of the transaction, and whether
+    		// the transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_AWPROT,
+		// Write address valid. This signal indicates that the master signaling
+    		// valid write address and control information.
+		input wire  S_AXI_AWVALID,
+		// Write address ready. This signal indicates that the slave is ready
+    		// to accept an address and associated control signals.
+		output wire  S_AXI_AWREADY,
+		// Write data (issued by master, acceped by Slave) 
+		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+		// Write strobes. This signal indicates which byte lanes hold
+    		// valid data. There is one write strobe bit for each eight
+    		// bits of the write data bus.    
+		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+		// Write valid. This signal indicates that valid write
+    		// data and strobes are available.
+		input wire  S_AXI_WVALID,
+		// Write ready. This signal indicates that the slave
+    		// can accept the write data.
+		output wire  S_AXI_WREADY,
+		// Write response. This signal indicates the status
+    		// of the write transaction.
+		output wire [1 : 0] S_AXI_BRESP,
+		// Write response valid. This signal indicates that the channel
+    		// is signaling a valid write response.
+		output wire  S_AXI_BVALID,
+		// Response ready. This signal indicates that the master
+    		// can accept a write response.
+		input wire  S_AXI_BREADY,
+		// Read address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+		// Protection type. This signal indicates the privilege
+    		// and security level of the transaction, and whether the
+    		// transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_ARPROT,
+		// Read address valid. This signal indicates that the channel
+    		// is signaling valid read address and control information.
+		input wire  S_AXI_ARVALID,
+		// Read address ready. This signal indicates that the slave is
+    		// ready to accept an address and associated control signals.
+		output wire  S_AXI_ARREADY,
+		// Read data (issued by slave)
+		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+		// Read response. This signal indicates the status of the
+    		// read transfer.
+		output wire [1 : 0] S_AXI_RRESP,
+		// Read valid. This signal indicates that the channel is
+    		// signaling the required read data.
+		output wire  S_AXI_RVALID,
+		// Read ready. This signal indicates that the master can
+    		// accept the read data and response information.
+		input wire  S_AXI_RREADY
+	);
+
+	// AXI4LITE signals
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+	reg  	axi_awready;
+	reg  	axi_wready;
+	reg [1 : 0] 	axi_bresp;
+	reg  	axi_bvalid;
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+	reg  	axi_arready;
+	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+	reg [1 : 0] 	axi_rresp;
+	reg  	axi_rvalid;
+
+	// Example-specific design signals
+	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	// ADDR_LSB is used for addressing 32/64 bit registers/memories
+	// ADDR_LSB = 2 for 32 bits (n downto 2)
+	// ADDR_LSB = 3 for 64 bits (n downto 3)
+	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+	localparam integer OPT_MEM_ADDR_BITS = 1;
+	//----------------------------------------------
+	//-- Signals for user logic register space example
+	//------------------------------------------------
+	//-- Number of Slave Registers 4
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+	wire	 slv_reg_rden;
+	wire	 slv_reg_wren;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+	integer	 byte_index;
+	reg	 aw_en;
+
+	// I/O Connections assignments
+
+	assign S_AXI_AWREADY	= axi_awready;
+	assign S_AXI_WREADY	= axi_wready;
+	assign S_AXI_BRESP	= axi_bresp;
+	assign S_AXI_BVALID	= axi_bvalid;
+	assign S_AXI_ARREADY	= axi_arready;
+	assign S_AXI_RDATA	= axi_rdata;
+	assign S_AXI_RRESP	= axi_rresp;
+	assign S_AXI_RVALID	= axi_rvalid;
+	// Implement axi_awready generation
+	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	// de-asserted when reset is low.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awready <= 1'b0;
+	      aw_en <= 1'b1;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // slave is ready to accept write address when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_awready <= 1'b1;
+	          aw_en <= 1'b0;
+	        end
+	        else if (S_AXI_BREADY && axi_bvalid)
+	            begin
+	              aw_en <= 1'b1;
+	              axi_awready <= 1'b0;
+	            end
+	      else           
+	        begin
+	          axi_awready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_awaddr latching
+	// This process is used to latch the address when both 
+	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awaddr <= 0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // Write Address latching 
+	          axi_awaddr <= S_AXI_AWADDR;
+	        end
+	    end 
+	end       
+
+	// Implement axi_wready generation
+	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	// de-asserted when reset is low. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_wready <= 1'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+	        begin
+	          // slave is ready to accept write data when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_wready <= 1'b1;
+	        end
+	      else
+	        begin
+	          axi_wready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement memory mapped register select and write logic generation
+	// The write data is accepted and written to memory mapped registers when
+	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	// select byte enables of slave registers while writing.
+	// These registers are cleared when reset (active low) is applied.
+	// Slave register write enable is asserted when valid address and data are available
+	// and the slave is ready to accept the write address and write data.
+	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      slv_reg0 <= 0;
+	      slv_reg1 <= 0;
+	      slv_reg2 <= 0;
+	      slv_reg3 <= 0;
+	    end 
+	  else begin
+	    if (slv_reg_wren)
+	      begin
+	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	          2'h0:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 0
+	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h1:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 1
+	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h2:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 2
+	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h3:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 3
+	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          default : begin
+	                      slv_reg0 <= slv_reg0;
+	                      slv_reg1 <= slv_reg1;
+	                      slv_reg2 <= slv_reg2;
+	                      slv_reg3 <= slv_reg3;
+	                    end
+	        endcase
+	      end
+	  end
+	end    
+
+	// Implement write response logic generation
+	// The write response and response valid signals are asserted by the slave 
+	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	// This marks the acceptance of address and indicates the status of 
+	// write transaction.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_bvalid  <= 0;
+	      axi_bresp   <= 2'b0;
+	    end 
+	  else
+	    begin    
+	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+	        begin
+	          // indicates a valid write response is available
+	          axi_bvalid <= 1'b1;
+	          axi_bresp  <= 2'b0; // 'OKAY' response 
+	        end                   // work error responses in future
+	      else
+	        begin
+	          if (S_AXI_BREADY && axi_bvalid) 
+	            //check if bready is asserted while bvalid is high) 
+	            //(there is a possibility that bready is always asserted high)   
+	            begin
+	              axi_bvalid <= 1'b0; 
+	            end  
+	        end
+	    end
+	end   
+
+	// Implement axi_arready generation
+	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	// S_AXI_ARVALID is asserted. axi_awready is 
+	// de-asserted when reset (active low) is asserted. 
+	// The read address is also latched when S_AXI_ARVALID is 
+	// asserted. axi_araddr is reset to zero on reset assertion.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_arready <= 1'b0;
+	      axi_araddr  <= 32'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_arready && S_AXI_ARVALID)
+	        begin
+	          // indicates that the slave has acceped the valid read address
+	          axi_arready <= 1'b1;
+	          // Read address latching
+	          axi_araddr  <= S_AXI_ARADDR;
+	        end
+	      else
+	        begin
+	          axi_arready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_arvalid generation
+	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	// data are available on the axi_rdata bus at this instance. The 
+	// assertion of axi_rvalid marks the validity of read data on the 
+	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	// cleared to zero on reset (active low).  
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rvalid <= 0;
+	      axi_rresp  <= 0;
+	    end 
+	  else
+	    begin    
+	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+	        begin
+	          // Valid read data is available at the read data bus
+	          axi_rvalid <= 1'b1;
+	          axi_rresp  <= 2'b0; // 'OKAY' response
+	        end   
+	      else if (axi_rvalid && S_AXI_RREADY)
+	        begin
+	          // Read data is accepted by the master
+	          axi_rvalid <= 1'b0;
+	        end                
+	    end
+	end    
+
+	// Implement memory mapped register select and read logic generation
+	// Slave register read enable is asserted when valid address is available
+	// and the slave is ready to accept the read address.
+	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+	always @(*)
+	begin
+	      // Address decoding for reading registers
+	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	        2'h0   : reg_data_out <= slv_reg0;
+	        2'h1   : reg_data_out <= slv_reg1;
+	        2'h2   : reg_data_out <= slv_reg2;
+	        2'h3   : reg_data_out <= slv_reg3;
+	        default : reg_data_out <= 0;
+	      endcase
+	end
+
+	// Output register or memory read data
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rdata  <= 0;
+	    end 
+	  else
+	    begin    
+	      // When there is a valid read address (S_AXI_ARVALID) with 
+	      // acceptance of read address by the slave (axi_arready), 
+	      // output the read dada 
+	      if (slv_reg_rden)
+	        begin
+	          axi_rdata <= reg_data_out;     // register read data
+	        end   
+	    end
+	end    
+
+	// Add user logic here
+    EightGelus 
+	#(
+		.num_gelu(num_gelu)
+	)u_EightGelus
+	(
+        .clk(axis_aclk),
+        .rst_n(aresetn),
+
+        .in_data(s_axis_tdata),
+        .in_valid(s_axis_tvalid),
+        .in_ready(s_axis_tready),
+        .in_last(s_axis_tlast),
+        .in_keep(s_axis_tkeep),
+
+        .out_data(m_axis_tdata),
+        .out_valid(m_axis_tvalid),
+        .out_ready(m_axis_tready),
+        .out_last(m_axis_tlast),
+        .out_keep(m_axis_tkeep),
+        
+        .scale(slv_reg0)
+    );
+	// User logic ends
+
+	endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Gelus_top.v

@@ -0,0 +1,107 @@
+
+`timescale 1 ns / 1 ps
+
+	module Gelus_top #
+	(
+		// Users to add parameters here
+		parameter integer num_gelu = 4,
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		localparam integer C_S00_AXI_DATA_WIDTH	= 32,
+		localparam integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+		input 										axis_aclk,
+    	input 										aresetn,
+	
+    	input [num_gelu*8-1:0] 	                    s_axis_tdata,
+    	input       								s_axis_tvalid,
+    	output      								s_axis_tready,
+    	input       								s_axis_tlast,
+    	input [num_gelu-1:0]                        s_axis_tkeep,
+	
+    	output [num_gelu*8-1:0] 	                m_axis_tdata,
+    	output       								m_axis_tvalid,
+    	input        								m_axis_tready,
+    	output      			 					m_axis_tlast,
+    	output [num_gelu-1:0]                         m_axis_tkeep,
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire  s00_axi_aclk,
+		input wire  s00_axi_aresetn,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	Gelus_axi # ( 
+		.num_gelu(num_gelu),
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+	) Gelus_axi (
+        .axis_aclk(axis_aclk),
+        .aresetn(aresetn),
+
+        .s_axis_tdata(s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tready(s_axis_tready),
+        .s_axis_tlast(s_axis_tlast),
+        .s_axis_tkeep(s_axis_tkeep),
+
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tready(m_axis_tready),
+        .m_axis_tlast(m_axis_tlast),
+        .m_axis_tkeep(m_axis_tkeep),
+
+		.S_AXI_ACLK(s00_axi_aclk),
+		.S_AXI_ARESETN(s00_axi_aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready)
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Ln_module.v

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps 
+module Ln_module(//latency=2
+	input clk,
+    input [15:0]    x_U8Q8,    
+    output [12:0]   y_U3Q10    
+);
+
+reg [2:0] w; 
+
+reg [14:0] k_1_0Q15;
+
+
+
+always @(*) begin
+    if (x_U8Q8[15]==1'b1)begin 
+        w = 7;
+        k_1_0Q15 = x_U8Q8[14:0];
+    end
+    else if (x_U8Q8[14]==1'b1)begin
+        w = 6;
+        k_1_0Q15 = {x_U8Q8[13:0],1'b0};
+    end
+    else if (x_U8Q8[13]==1'b1)begin
+        w = 5;
+        k_1_0Q15 = {x_U8Q8[12:0],2'b00};
+    end
+    else if (x_U8Q8[12]==1'b1)begin
+        w = 4;
+        k_1_0Q15 = {x_U8Q8[11:0],3'b000};
+    end
+    else if (x_U8Q8[11]==1'b1)begin
+        w = 3;
+        k_1_0Q15 = {x_U8Q8[10:0],4'b0000};
+    end
+    else if (x_U8Q8[10]==1'b1)begin
+        w = 2;
+        k_1_0Q15 = {x_U8Q8[9:0],5'b00000};
+    end
+    else if (x_U8Q8[9]==1'b1)begin
+        w = 1;
+        k_1_0Q15 = {x_U8Q8[8:0],6'b000000};
+    end
+    else begin
+        w = 0;
+        k_1_0Q15 = {x_U8Q8[7:0],7'b0000000};
+    end
+end
+
+
+wire [17:0] k_1_w_3Q15 = {w,k_1_0Q15};
+reg  [17:0] k_1_w_3Q15_reg1;
+always@(posedge clk)begin
+	k_1_w_3Q15_reg1<=k_1_w_3Q15;
+end
+wire [21:0] P_3Q19;
+reg  [21:0] P_3Q19_reg1;
+assign P_3Q19 = k_1_w_3Q15_reg1 * 4'b1011; 
+always@(posedge clk)begin
+	P_3Q19_reg1<=P_3Q19;
+end
+assign y_U3Q10 = P_3Q19_reg1[21:9];
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Softmax.v

@@ -0,0 +1,234 @@
+`timescale 1ns / 1ps
+
+module Softmax(
+    input                   clk,
+    input                   rst_n,
+    
+    input [9:0]             length_input,
+    input [10:0]            lengthX2,
+    input [11:0]            lengthX3,
+    input signed [4:0]      scale_in,//scale_in and scale_out must be kept during the valid_in, min =-1, max =10
+    input [3:0]             scale_out,//min = 7,max  = 14
+    input signed [7:0]      data_in,
+    input                   valid_in,
+    
+    output reg [7:0]        data_out,
+    // output reg [15:0]       data_out,
+    output                  valid_out,
+    output                  out_last
+);
+
+
+(*MAX_FANOUT = 25 *)  reg [9:0] length;
+reg valid_in_delay1;
+reg valid_in_delay2;
+reg valid_in_delay3;
+reg valid_in_delay4;
+reg valid_in_delay5;
+reg valid_in_delay6;
+reg valid_in_delay7;
+reg valid_in_delay8;
+reg valid_in_delay9;
+reg valid_in_delay10;
+reg [15:0] cnt;
+reg signed [7:0] data_in_max;
+reg signed [19:0] x_max_S9Q10;
+reg signed [19:0] x_max_S9Q10_delay1;
+reg signed [19:0] x_max_S9Q10_delay2;
+reg signed [19:0] x_max_S9Q10_delay3;
+reg signed [19:0] x_max_S9Q10_delay4;
+reg signed [19:0] x_max_S9Q10_delay5;
+reg signed [19:0] x_max_S9Q10_delay6;
+reg  [19:0] e_sum_U8Q12;
+reg [1:0] stage_delay1;
+reg [1:0] stage_delay2;
+reg [1:0] stage_delay3;
+reg [1:0] stage_delay4;
+reg [1:0] stage_delay5;
+reg [1:0] stage_delay6;
+reg [1:0] stage_delay7;
+reg [1:0] stage_delay8;
+reg [1:0] stage_delay9;
+reg [1:0] stage_delay10;
+reg [3:0] scale_out_delay1;
+reg [3:0] scale_out_delay2;
+reg [3:0] scale_out_delay3;
+reg [3:0] scale_out_delay4;
+reg [3:0] scale_out_delay5;
+reg [3:0] scale_out_delay6;
+reg [3:0] scale_out_delay7;
+reg [3:0] scale_out_delay8;
+reg [3:0] scale_out_delay9;
+reg   [7:0] exp_out;
+// reg   [15:0] exp_out;
+
+wire [1:0] stage;// 1:first input, 2:second input, 3:third input
+wire signed [8:0] x_max_9b;
+wire  [11:0] exp_U0Q12;
+wire  [13:0] exp_U0Q14_out;
+wire [15:0] e_sum_U8Q8;
+wire [15:0] e_sum_U8Q8_temp;
+wire [12:0] ln_U3Q10;
+wire signed [20:0] x_max_ln_S10Q10;
+wire signed [19:0] x_max_ln_S9Q10;
+
+assign x_max_ln_S10Q10 = x_max_S9Q10_delay6-$signed({7'b000_0000,ln_U3Q10}); 
+assign x_max_ln_S9Q10 = x_max_ln_S10Q10[20] == 0 ? 0:(x_max_ln_S10Q10 < -524288) ? 20'b1000_0000_0000_0000_0000:x_max_ln_S10Q10;
+//assign stage = cnt<=(length -1) ? 1 : (length- 1<cnt && cnt <=length*2-1 ? 2 : 3);
+assign stage = cnt<=(length -1) ? 1 : (length- 1<cnt && cnt <=lengthX2-1 ? 2 : 3);
+assign x_max_9b = data_in-data_in_max;
+assign e_sum_U8Q8_temp = e_sum_U8Q12[19:4] + (e_sum_U8Q12[3]?1:0);
+assign e_sum_U8Q8 =  e_sum_U8Q8_temp> 256 ? e_sum_U8Q8_temp: 256;
+assign valid_out = (stage_delay10==3 & valid_in_delay10)?1:0;
+assign out_last = (stage_delay10 == 3) & (stage_delay9==1);
+
+always @(*) begin
+    case(scale_out_delay9)
+        14:begin exp_out = (|exp_U0Q14_out[13:7]) ? 8'b0111_1111 : {1'b0,exp_U0Q14_out[6:0]}; end
+
+        13:begin exp_out = (|exp_U0Q14_out[13:8]) ? 8'b0111_1111 : {1'b0,exp_U0Q14_out[7:1]}; end
+
+        12:begin exp_out = (|exp_U0Q14_out[13:9]) ? 8'b0111_1111 : {1'b0,exp_U0Q14_out[8:2]}; end
+        
+        11:begin exp_out = (|exp_U0Q14_out[13:10]) ? 8'b0111_1111 : {1'b0,exp_U0Q14_out[9:3]};end
+
+        10:begin exp_out = (|exp_U0Q14_out[13:11]) ? 8'b0111_1111 : {1'b0,exp_U0Q14_out[10:4]};end
+
+         9:begin exp_out = (|exp_U0Q14_out[13:12]) ? 8'b0111_1111 : {1'b0, exp_U0Q14_out[11:5]};end
+
+         8:begin exp_out = (exp_U0Q14_out[13]) ? 8'b0111_1111 : {1'b0, exp_U0Q14_out[12:6]};end
+
+         7:begin exp_out = {1'b0, exp_U0Q14_out[13:7]}; end  
+
+         default: begin exp_out = {1'b0, exp_U0Q14_out[13:7]}; end 
+    endcase                                                                                                                                                                                                    
+end                                                                                                              
+
+always@(posedge clk)begin
+    data_out<=exp_out;
+end
+
+always @(posedge clk ) begin
+    length <= length_input;
+end
+
+always@(posedge clk)begin
+    stage_delay1<=stage;
+    stage_delay2<=stage_delay1;
+    stage_delay3<=stage_delay2;
+    stage_delay4<=stage_delay3;
+    stage_delay5<=stage_delay4;
+    stage_delay6<=stage_delay5;
+    stage_delay7<=stage_delay6;
+    stage_delay8<=stage_delay7;
+    stage_delay9<=stage_delay8;
+    stage_delay10<=stage_delay9;
+end
+
+always@(posedge clk)begin
+    scale_out_delay1<=scale_out;
+    scale_out_delay2<=scale_out_delay1;
+    scale_out_delay3<=scale_out_delay2;
+    scale_out_delay4<=scale_out_delay3;
+    scale_out_delay5<=scale_out_delay4;
+    scale_out_delay6<=scale_out_delay5;
+    scale_out_delay7<=scale_out_delay6;
+    scale_out_delay8<=scale_out_delay7;
+    scale_out_delay9<=scale_out_delay8;
+end
+
+always@(posedge clk)begin
+    valid_in_delay1<=valid_in;
+    valid_in_delay2<=valid_in_delay1;
+    valid_in_delay3<=valid_in_delay2;
+    valid_in_delay4<=valid_in_delay3;
+    valid_in_delay5<=valid_in_delay4;
+    valid_in_delay6<=valid_in_delay5;
+    valid_in_delay7<=valid_in_delay6;
+    valid_in_delay8<=valid_in_delay7;
+    valid_in_delay9<=valid_in_delay8;
+    valid_in_delay10<=valid_in_delay9;
+end
+
+initial begin  cnt=0;  end
+always@(posedge clk or negedge rst_n)begin
+    if (~rst_n)
+        cnt<=0;
+    else begin
+        if(cnt==0&valid_in)
+            cnt<=1;
+        else if(cnt==0)
+            cnt<=cnt;
+        else if(cnt==lengthX3-1)
+            cnt<=0;
+        else if(valid_in)
+            cnt<=cnt+1;
+        else
+            cnt<=cnt;
+    end
+end
+
+// initial begin data_in_max=8'b11111111;end
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        data_in_max<=8'b11111111;
+    else if(cnt==lengthX3-1)
+        data_in_max<=8'b11111111;
+    else if(valid_in&stage==1)
+        data_in_max<=(data_in_max>data_in)?data_in_max:data_in;
+end
+
+always @(*) begin
+    if (scale_in == -1)
+        x_max_S9Q10 =  $signed(x_max_9b) <<< 11;
+    else if (scale_in < 10) begin
+        x_max_S9Q10 = $signed(x_max_9b) <<< (5'd10- scale_in[3:0]);
+    end
+    else begin // in_scale == 10
+        x_max_S9Q10 = x_max_9b;
+    end
+end
+
+always@(posedge clk)begin
+    x_max_S9Q10_delay1<=x_max_S9Q10;
+    x_max_S9Q10_delay2<=x_max_S9Q10_delay1;
+    x_max_S9Q10_delay3<=x_max_S9Q10_delay2;
+    x_max_S9Q10_delay4<=x_max_S9Q10_delay3;
+    x_max_S9Q10_delay5<=x_max_S9Q10_delay4;
+    x_max_S9Q10_delay6<=x_max_S9Q10_delay5;
+end
+
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        e_sum_U8Q12<=0;
+    else if(stage_delay4==2 & valid_in_delay4)
+        e_sum_U8Q12<=exp_U0Q12+e_sum_U8Q12;
+    else if(stage_delay4==1)
+        e_sum_U8Q12<=0;
+end
+
+wire [24:0] exp_U0Q25;
+assign exp_U0Q12 = exp_U0Q25[24:13];
+
+Exp_module u_Exp_module_1(
+	.clk(clk),
+    .x_S9Q10(x_max_S9Q10_delay1), 
+    .y_U0Q25_reg1(exp_U0Q25) 
+);
+
+Ln_module u_Ln_module(//latency=2
+	.clk(clk),
+    .x_U8Q8(e_sum_U8Q8),    
+    .y_U3Q10(ln_U3Q10)  
+);
+
+wire [24:0] exp_U0Q25_out;
+assign exp_U0Q14_out = exp_U0Q25_out[24:11];
+
+Exp_module u_Exp_module_2(
+	.clk(clk),
+    .x_S9Q10(x_max_ln_S9Q10), 
+    .y_U0Q25_reg1(exp_U0Q25_out) 
+);
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Softmax_control.v

@@ -0,0 +1,194 @@
+`timescale 1ns / 1ps
+
+
+module Softmax_control(
+    input                           clk,
+    input                           rst_n,
+
+    input [9:0]                     length_input,
+    input signed [4:0]              scale_in_input,
+    input [3:0]                     scale_out_input,
+    
+    
+    input signed [7:0]              top_data_in,
+    input                           top_valid_in,
+    output                          top_ready_in,
+    input                           top_last_in,
+    
+    output     [7:0]                top_data_out,
+    output                          top_valid_out,
+    output                          top_last_out
+
+);
+
+reg [9:0] length;
+reg [11:0] lengthX3;
+reg [10:0] lengthX2;
+reg signed [4:0] scale_in;
+reg [3:0] scale_out;
+reg [15:0] cnt_in;
+reg [15:0] cnt_stage;
+reg Softmax_valid_in;
+reg Softmax_valid_in_delay1;
+reg top_valid_in_delay1;
+reg [9:0] out_addr;
+reg top_last_in_reg;
+reg top_ready_in_delay1;
+reg [7:0] Softmax_data_in_delay1;
+reg signed [7:0] in_data_buffer [1023:0];
+
+wire valid_input_flag;
+//wire [7:0] Softmax_data_in;
+wire [7:0] Softmax_data_out;
+wire buffer_wen;
+wire Softmax_valid_out;
+wire [9:0] in_addr;
+wire Softmax_out_last;
+wire length1_flag;
+wire length2_flag;
+wire length3_flag;
+
+assign length1_flag = cnt_stage<=length;
+assign length2_flag = cnt_stage<=lengthX2;
+assign length3_flag = cnt_stage<=lengthX3;
+assign in_addr = (cnt_in < length)? cnt_in:0;
+assign valid_input_flag = top_valid_in&top_ready_in;
+assign buffer_wen = top_valid_in&top_ready_in;
+assign top_data_out = Softmax_data_out;
+assign top_valid_out = Softmax_valid_out;
+assign top_last_out = Softmax_out_last & top_last_in_reg;
+assign top_ready_in = cnt_in < length;
+//assign Softmax_data_in = in_data_buffer[out_addr];
+
+always @(posedge clk ) begin
+//    Softmax_data_in_delay1<=Softmax_data_in;
+    Softmax_data_in_delay1<=in_data_buffer[out_addr]; //block mem
+end
+
+always @(posedge clk ) begin
+    Softmax_valid_in_delay1<=Softmax_valid_in;
+end
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        top_last_in_reg<=0;
+    else if (top_last_in)
+        top_last_in_reg<=1;
+    else if (top_last_out)
+        top_last_in_reg<=0;
+    else
+        top_last_in_reg<=top_last_in_reg;
+end
+
+always@(posedge clk)begin
+    top_ready_in_delay1<=top_ready_in;
+end
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        cnt_in <= 0;
+    else if(cnt_stage == lengthX3)//(cnt_stage == length * 3)
+        cnt_in <= 0;
+    else if(valid_input_flag)
+        cnt_in <= cnt_in + 1;
+    else
+        cnt_in <= cnt_in;
+end
+
+always@(posedge clk or negedge rst_n)begin
+    if(~rst_n)
+        cnt_stage<=0;
+    else if (cnt_stage == lengthX3)//(cnt_stage == length * 3)
+        cnt_stage <= 0;
+    else if (cnt_stage < length & valid_input_flag)
+        cnt_stage<=cnt_stage+1;
+    else if (cnt_stage >= length)
+        cnt_stage<=cnt_stage+1;
+    else
+        cnt_stage <= cnt_stage;
+end
+
+always @(posedge clk ) begin
+    length <= length_input;
+    scale_in <= scale_in_input;
+    scale_out <= scale_out_input;
+end
+
+always @(posedge clk ) begin
+    lengthX3<=length * 3;
+end
+
+always @(posedge clk ) begin
+    lengthX2<=length * 2;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        top_valid_in_delay1<=0;
+    else
+        top_valid_in_delay1<=top_valid_in;
+end
+
+always @(posedge clk) begin
+    if(buffer_wen)
+        in_data_buffer[in_addr] <= top_data_in;
+end
+
+// always @(*)begin
+//     if(cnt_stage<=length)
+//         Softmax_valid_in = top_valid_in_delay1;
+//     else if(cnt_stage >length | cnt_stage<=lengthX3)//cnt_stage <=  length*3)
+//         Softmax_valid_in = 1;
+//     else 
+//         Softmax_valid_in = 0;
+// end
+
+
+
+
+always @(*)begin
+    case({ length1_flag, length3_flag}) 
+        2'b11: Softmax_valid_in = top_valid_in_delay1 & top_ready_in_delay1;
+        2'b01: Softmax_valid_in = 1;
+        default: Softmax_valid_in=0;
+    endcase
+end
+
+// always @(*)begin
+//     if(cnt_stage>0&cnt_stage<=length)
+//         out_addr = cnt_stage -1;
+//     else if (cnt_stage>length & cnt_stage<=lengthX2)//2*length)
+//         out_addr = cnt_stage - 1 - length;
+//     else if (cnt_stage>2*length & cnt_stage <=lengthX3)//<= 3*length)
+//         out_addr = cnt_stage - 1 - lengthX2;//2*length;
+//     else
+//         out_addr = 0;
+// end
+
+
+always @(*) begin
+    case({(cnt_stage>0),length1_flag,length2_flag,length3_flag})
+        4'b1111: out_addr = cnt_stage -1;
+        4'b1011: out_addr = cnt_stage - 1 - length;
+        4'b1001: out_addr = cnt_stage - 1 - lengthX2;
+        default:out_addr = 0;
+    endcase
+end
+
+
+Softmax u_Softmax(
+    .clk(clk),
+    .rst_n(rst_n),
+    .length_input(length_input),
+    .lengthX2(lengthX2),
+    .lengthX3(lengthX3),
+    .scale_in(scale_in),//scale_in and scale_out must be kept during the valid_in, min =-1, max =10
+    .scale_out(scale_out),//min = 7,max  = 14
+    .data_in(Softmax_data_in_delay1),
+    .valid_in(Softmax_valid_in_delay1),
+
+    .data_out(Softmax_data_out),
+    .valid_out(Softmax_valid_out),
+    .out_last(Softmax_out_last)
+);
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Softmax_top.v

@@ -0,0 +1,104 @@
+
+`timescale 1 ns / 1 ps
+
+	module Softmax_top #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		localparam integer C_S00_AXI_DATA_WIDTH	= 32,
+		localparam integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+		input 										axis_aclk,
+    	input 										aresetn,
+	
+    	input [7:0] 	                            s_axis_tdata,
+    	input       								s_axis_tvalid,
+    	output      								s_axis_tready,
+    	input       								s_axis_tlast,
+	
+    	output [7:0] 	                            m_axis_tdata,
+    	output       								m_axis_tvalid,
+    	input        								m_axis_tready,
+    	output      			 					m_axis_tlast,
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire  s00_axi_aclk,
+		input wire  s00_axi_aresetn,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	Softmax_top_axi # ( 
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+	) u_Softmax_top_axi (
+        .axis_aclk(axis_aclk),
+        .aresetn(aresetn),
+
+        .s_axis_tdata(s_axis_tdata),
+        .s_axis_tvalid(s_axis_tvalid),
+        .s_axis_tready(s_axis_tready),
+        .s_axis_tlast(s_axis_tlast),
+
+
+        .m_axis_tdata(m_axis_tdata),
+        .m_axis_tvalid(m_axis_tvalid),
+        .m_axis_tready(m_axis_tready),
+        .m_axis_tlast(m_axis_tlast),
+
+
+		.S_AXI_ACLK(s00_axi_aclk),
+		.S_AXI_ARESETN(s00_axi_aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready)
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/Softmax_top_axi.v

@@ -0,0 +1,432 @@
+
+`timescale 1 ns / 1 ps
+
+	module Softmax_top_axi #
+	(
+		// Users to add parameters here
+
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+		// Width of S_AXI data bus
+		parameter integer C_S_AXI_DATA_WIDTH	= 32,
+		// Width of S_AXI address bus
+		parameter integer C_S_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+		input 										axis_aclk,
+    	input 										aresetn,
+	
+    	input [7:0] 	                            s_axis_tdata,
+    	input       								s_axis_tvalid,
+    	output      								s_axis_tready,
+    	input       								s_axis_tlast,
+	
+    	output [7:0] 	                            m_axis_tdata,
+    	output       								m_axis_tvalid,
+    	input        								m_axis_tready,
+    	output      			 					m_axis_tlast,
+
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+		// Global Clock Signal
+		input wire  S_AXI_ACLK,
+		// Global Reset Signal. This Signal is Active LOW
+		input wire  S_AXI_ARESETN,
+		// Write address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+		// Write channel Protection type. This signal indicates the
+    		// privilege and security level of the transaction, and whether
+    		// the transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_AWPROT,
+		// Write address valid. This signal indicates that the master signaling
+    		// valid write address and control information.
+		input wire  S_AXI_AWVALID,
+		// Write address ready. This signal indicates that the slave is ready
+    		// to accept an address and associated control signals.
+		output wire  S_AXI_AWREADY,
+		// Write data (issued by master, acceped by Slave) 
+		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+		// Write strobes. This signal indicates which byte lanes hold
+    		// valid data. There is one write strobe bit for each eight
+    		// bits of the write data bus.    
+		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+		// Write valid. This signal indicates that valid write
+    		// data and strobes are available.
+		input wire  S_AXI_WVALID,
+		// Write ready. This signal indicates that the slave
+    		// can accept the write data.
+		output wire  S_AXI_WREADY,
+		// Write response. This signal indicates the status
+    		// of the write transaction.
+		output wire [1 : 0] S_AXI_BRESP,
+		// Write response valid. This signal indicates that the channel
+    		// is signaling a valid write response.
+		output wire  S_AXI_BVALID,
+		// Response ready. This signal indicates that the master
+    		// can accept a write response.
+		input wire  S_AXI_BREADY,
+		// Read address (issued by master, acceped by Slave)
+		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+		// Protection type. This signal indicates the privilege
+    		// and security level of the transaction, and whether the
+    		// transaction is a data access or an instruction access.
+		input wire [2 : 0] S_AXI_ARPROT,
+		// Read address valid. This signal indicates that the channel
+    		// is signaling valid read address and control information.
+		input wire  S_AXI_ARVALID,
+		// Read address ready. This signal indicates that the slave is
+    		// ready to accept an address and associated control signals.
+		output wire  S_AXI_ARREADY,
+		// Read data (issued by slave)
+		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+		// Read response. This signal indicates the status of the
+    		// read transfer.
+		output wire [1 : 0] S_AXI_RRESP,
+		// Read valid. This signal indicates that the channel is
+    		// signaling the required read data.
+		output wire  S_AXI_RVALID,
+		// Read ready. This signal indicates that the master can
+    		// accept the read data and response information.
+		input wire  S_AXI_RREADY
+	);
+
+	// AXI4LITE signals
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+	reg  	axi_awready;
+	reg  	axi_wready;
+	reg [1 : 0] 	axi_bresp;
+	reg  	axi_bvalid;
+	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+	reg  	axi_arready;
+	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+	reg [1 : 0] 	axi_rresp;
+	reg  	axi_rvalid;
+
+	// Example-specific design signals
+	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	// ADDR_LSB is used for addressing 32/64 bit registers/memories
+	// ADDR_LSB = 2 for 32 bits (n downto 2)
+	// ADDR_LSB = 3 for 64 bits (n downto 3)
+	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+	localparam integer OPT_MEM_ADDR_BITS = 1;
+	//----------------------------------------------
+	//-- Signals for user logic register space example
+	//------------------------------------------------
+	//-- Number of Slave Registers 4
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+	wire	 slv_reg_rden;
+	wire	 slv_reg_wren;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+	integer	 byte_index;
+	reg	 aw_en;
+
+	// I/O Connections assignments
+
+	assign S_AXI_AWREADY	= axi_awready;
+	assign S_AXI_WREADY	= axi_wready;
+	assign S_AXI_BRESP	= axi_bresp;
+	assign S_AXI_BVALID	= axi_bvalid;
+	assign S_AXI_ARREADY	= axi_arready;
+	assign S_AXI_RDATA	= axi_rdata;
+	assign S_AXI_RRESP	= axi_rresp;
+	assign S_AXI_RVALID	= axi_rvalid;
+	// Implement axi_awready generation
+	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	// de-asserted when reset is low.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awready <= 1'b0;
+	      aw_en <= 1'b1;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // slave is ready to accept write address when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_awready <= 1'b1;
+	          aw_en <= 1'b0;
+	        end
+	        else if (S_AXI_BREADY && axi_bvalid)
+	            begin
+	              aw_en <= 1'b1;
+	              axi_awready <= 1'b0;
+	            end
+	      else           
+	        begin
+	          axi_awready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_awaddr latching
+	// This process is used to latch the address when both 
+	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_awaddr <= 0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+	        begin
+	          // Write Address latching 
+	          axi_awaddr <= S_AXI_AWADDR;
+	        end
+	    end 
+	end       
+
+	// Implement axi_wready generation
+	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	// de-asserted when reset is low. 
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_wready <= 1'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+	        begin
+	          // slave is ready to accept write data when 
+	          // there is a valid write address and write data
+	          // on the write address and data bus. This design 
+	          // expects no outstanding transactions. 
+	          axi_wready <= 1'b1;
+	        end
+	      else
+	        begin
+	          axi_wready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement memory mapped register select and write logic generation
+	// The write data is accepted and written to memory mapped registers when
+	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	// select byte enables of slave registers while writing.
+	// These registers are cleared when reset (active low) is applied.
+	// Slave register write enable is asserted when valid address and data are available
+	// and the slave is ready to accept the write address and write data.
+	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      slv_reg0 <= 0;
+	      slv_reg1 <= 0;
+	      slv_reg2 <= 0;
+	      slv_reg3 <= 0;
+	    end 
+	  else begin
+	    if (slv_reg_wren)
+	      begin
+	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	          2'h0:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 0
+	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h1:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 1
+	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h2:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 2
+	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          2'h3:
+	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+	                // Respective byte enables are asserted as per write strobes 
+	                // Slave register 3
+	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+	              end  
+	          default : begin
+	                      slv_reg0 <= slv_reg0;
+	                      slv_reg1 <= slv_reg1;
+	                      slv_reg2 <= slv_reg2;
+	                      slv_reg3 <= slv_reg3;
+	                    end
+	        endcase
+	      end
+	  end
+	end    
+
+	// Implement write response logic generation
+	// The write response and response valid signals are asserted by the slave 
+	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	// This marks the acceptance of address and indicates the status of 
+	// write transaction.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_bvalid  <= 0;
+	      axi_bresp   <= 2'b0;
+	    end 
+	  else
+	    begin    
+	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+	        begin
+	          // indicates a valid write response is available
+	          axi_bvalid <= 1'b1;
+	          axi_bresp  <= 2'b0; // 'OKAY' response 
+	        end                   // work error responses in future
+	      else
+	        begin
+	          if (S_AXI_BREADY && axi_bvalid) 
+	            //check if bready is asserted while bvalid is high) 
+	            //(there is a possibility that bready is always asserted high)   
+	            begin
+	              axi_bvalid <= 1'b0; 
+	            end  
+	        end
+	    end
+	end   
+
+	// Implement axi_arready generation
+	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	// S_AXI_ARVALID is asserted. axi_awready is 
+	// de-asserted when reset (active low) is asserted. 
+	// The read address is also latched when S_AXI_ARVALID is 
+	// asserted. axi_araddr is reset to zero on reset assertion.
+
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_arready <= 1'b0;
+	      axi_araddr  <= 32'b0;
+	    end 
+	  else
+	    begin    
+	      if (~axi_arready && S_AXI_ARVALID)
+	        begin
+	          // indicates that the slave has acceped the valid read address
+	          axi_arready <= 1'b1;
+	          // Read address latching
+	          axi_araddr  <= S_AXI_ARADDR;
+	        end
+	      else
+	        begin
+	          axi_arready <= 1'b0;
+	        end
+	    end 
+	end       
+
+	// Implement axi_arvalid generation
+	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	// data are available on the axi_rdata bus at this instance. The 
+	// assertion of axi_rvalid marks the validity of read data on the 
+	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	// cleared to zero on reset (active low).  
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rvalid <= 0;
+	      axi_rresp  <= 0;
+	    end 
+	  else
+	    begin    
+	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+	        begin
+	          // Valid read data is available at the read data bus
+	          axi_rvalid <= 1'b1;
+	          axi_rresp  <= 2'b0; // 'OKAY' response
+	        end   
+	      else if (axi_rvalid && S_AXI_RREADY)
+	        begin
+	          // Read data is accepted by the master
+	          axi_rvalid <= 1'b0;
+	        end                
+	    end
+	end    
+
+	// Implement memory mapped register select and read logic generation
+	// Slave register read enable is asserted when valid address is available
+	// and the slave is ready to accept the read address.
+	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+	always @(*)
+	begin
+	      // Address decoding for reading registers
+	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+	        2'h0   : reg_data_out <= slv_reg0;
+	        2'h1   : reg_data_out <= slv_reg1;
+	        2'h2   : reg_data_out <= slv_reg2;
+	        2'h3   : reg_data_out <= slv_reg3;
+	        default : reg_data_out <= 0;
+	      endcase
+	end
+
+	// Output register or memory read data
+	always @( posedge S_AXI_ACLK )
+	begin
+	  if ( S_AXI_ARESETN == 1'b0 )
+	    begin
+	      axi_rdata  <= 0;
+	    end 
+	  else
+	    begin    
+	      // When there is a valid read address (S_AXI_ARVALID) with 
+	      // acceptance of read address by the slave (axi_arready), 
+	      // output the read dada 
+	      if (slv_reg_rden)
+	        begin
+	          axi_rdata <= reg_data_out;     // register read data
+	        end   
+	    end
+	end    
+
+	// Add user logic here
+    Softmax_control u_Softmax_control(
+        .clk(axis_aclk),
+        .rst_n(aresetn),
+
+        .top_data_in(s_axis_tdata),
+        .top_valid_in(s_axis_tvalid),
+        .top_ready_in(s_axis_tready),
+        .top_last_in(s_axis_tlast),
+
+        .top_data_out(m_axis_tdata),
+        .top_valid_out(m_axis_tvalid),
+        .top_last_out(m_axis_tlast),
+        
+        .length_input(slv_reg0[9:0]), //must be smaller or eruqal to 1023
+        .scale_in_input(slv_reg1[4:0]), // -1-10
+        .scale_out_input(slv_reg2[3:0]) // 7-12
+    );
+	// User logic ends
+
+	endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/gelu.v

@@ -0,0 +1,111 @@
+`timescale 1ns / 1ps
+//latency=4+4
+module gelu(
+	input                           clk,
+    input [2:0]                     in_scale,
+    input signed [7:0]              x, 
+    output reg signed [7:0]         y_reg1
+);
+reg signed [7:0] x_reg1;
+reg signed [7:0] x_reg2;
+reg signed [7:0] x_reg3;
+reg signed [7:0] x_reg4;
+reg signed [7:0] x_reg5;
+reg signed [7:0] x_reg6;
+reg signed [7:0] x_reg7;
+
+reg [2:0] in_scale_reg1;
+reg [2:0] in_scale_reg2;
+reg [2:0] in_scale_reg3;
+reg [2:0] in_scale_reg4;
+reg [2:0] in_scale_reg5;
+reg [2:0] in_scale_reg6;
+reg [2:0] in_scale_reg7;
+always@(posedge clk)begin
+	in_scale_reg1<=in_scale;
+	in_scale_reg2<=in_scale_reg1;
+	in_scale_reg3<=in_scale_reg2;
+	in_scale_reg4<=in_scale_reg3;
+	in_scale_reg5<=in_scale_reg4;
+	in_scale_reg6<=in_scale_reg5;
+	in_scale_reg7<=in_scale_reg6;
+end
+always@(posedge clk)begin
+	x_reg1<=x;
+	x_reg2<=x_reg1;
+	x_reg3<=x_reg2;
+	x_reg4<=x_reg3;
+	x_reg5<=x_reg4;
+	x_reg6<=x_reg5;
+	x_reg7<=x_reg6;
+end
+reg signed [7:0]  y;
+reg signed [15:0] x_in_8Q7;
+reg signed [15:0] x_in_8Q7_reg1;
+reg signed [15:0] x_in_8Q7_reg2;
+reg signed [15:0] x_in_8Q7_reg3;
+reg signed [15:0] x_in_8Q7_reg4;
+reg signed [15:0] x_in_8Q7_reg5;
+reg signed [15:0] x_in_8Q7_reg6;
+reg signed [15:0] x_in_8Q7_reg7;
+always @(*) begin
+    if (in_scale < 7  ) begin
+        x_in_8Q7 = $signed(x) <<< (3'd7- in_scale);//����
+    end
+    else begin // in_scale == 7
+        x_in_8Q7 = x;
+    end
+end
+always@(posedge clk)begin
+	x_in_8Q7_reg1<=x_in_8Q7;
+	x_in_8Q7_reg2<=x_in_8Q7_reg1;
+	x_in_8Q7_reg3<=x_in_8Q7_reg2;
+	x_in_8Q7_reg4<=x_in_8Q7_reg3;
+	x_in_8Q7_reg5<=x_in_8Q7_reg4;
+	x_in_8Q7_reg6<=x_in_8Q7_reg5;
+	x_in_8Q7_reg7<=x_in_8Q7_reg6;
+end
+wire signed [9:0] c_2_5_2Q7 =  10'b0_10_1000_000;
+wire signed [9:0] _c_2_5_2Q7 = 10'b1_01_1000_000;
+wire signed [18:0] out_3Q15;
+reg  signed [18:0] out_3Q15_reg1;
+wire signed [10:0] y_3Q7;
+
+
+wire signed [11:0] x_in_L_2Q9;
+reg  signed [11:0] x_in_L_2Q9_reg1;
+assign x_in_L_2Q9 = $signed(x_in_8Q7_reg1[9:0]) * 3'sb011; 
+//                      <2.5           3/4
+always@(posedge clk)begin
+	x_in_L_2Q9_reg1<=x_in_L_2Q9;
+end
+wire signed [8:0] L_1Q7;
+lin u_lin(//latency = 4
+	.clk(clk),
+    .x_in_L_2Q9(x_in_L_2Q9_reg1),
+    .L_1Q7(L_1Q7) 
+);
+wire signed [9:0] L_2Q7_1 = L_1Q7 + 10'sb001_000_0000;
+wire signed [9:0] half_L_1Q8 = L_2Q7_1;
+assign out_3Q15 = half_L_1Q8 *  $signed(x_in_8Q7_reg6[9:0]);
+always@(posedge clk)begin
+	out_3Q15_reg1<=out_3Q15;
+end
+assign y_3Q7= out_3Q15_reg1[18:8]; 
+
+always @(*) begin
+    if(x_reg7[7]==1'b1 && x_in_8Q7_reg7<=_c_2_5_2Q7)begin
+        y = 0;
+    end
+    else if(x_reg7[7]==1'b0 && x_in_8Q7_reg7 >= c_2_5_2Q7)begin
+        y = x_reg7;
+    end
+    else begin
+//        y=y_3Q7;
+        y = (y_3Q7>>>(3'd7-in_scale_reg7));
+    end
+end
+always@(posedge clk)begin
+	y_reg1 <= y;
+end
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/In Progress/src/lin.v

@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps   //latency = 4
+module lin(
+	input  wire				  clk, 
+    input  wire signed [11:0] x_in_L_2Q9,
+    output reg  signed [8:0]  L_1Q7 
+);
+
+wire signed [9:0] x_in_L_2Q7 = x_in_L_2Q9[11:2];
+wire sign = x_in_L_2Q9[11];
+reg  sign_reg1;
+reg  sign_reg2;
+reg  sign_reg3;
+always@(posedge clk)begin
+	sign_reg1<=sign;
+	sign_reg2<=sign_reg1;
+	sign_reg3<=sign_reg2;
+end
+wire signed [9:0] x_in_L_2Q7_abs = (sign==1'b1) ? (~x_in_L_2Q7+1) : x_in_L_2Q7;
+wire signed [3:0] b_1Q2 = 4'sb0111; //b=7/4
+wire signed [6:0] a_0Q7 = -7'sd37; 
+
+wire signed [9:0] x_in_L_2Q7_abs_b = x_in_L_2Q7_abs - {b_1Q2,5'b00000};
+reg  signed [9:0] x_in_L_2Q7_abs_b_reg1; 
+always@(posedge clk)begin
+	x_in_L_2Q7_abs_b_reg1<=x_in_L_2Q7_abs_b;
+end
+
+wire signed [18:0] temp_4Q14 = x_in_L_2Q7_abs_b_reg1*x_in_L_2Q7_abs_b_reg1;
+reg  signed [18:0] temp_4Q14_reg1;
+always@(posedge clk)begin
+	temp_4Q14_reg1<=temp_4Q14;
+end	
+wire signed [25:0] l_4Q21 = a_0Q7*temp_4Q14_reg1+ 23'sb0_1_0_0000_0000_0000_0000_0000;
+reg  signed [25:0] l_4Q21_reg1;
+always@(posedge clk)begin
+	l_4Q21_reg1<=l_4Q21;
+end
+//wire signed [25:0] l_4Q21 = a_0Q7 * x_in_L_2Q7_abs_b * x_in_L_2Q7_abs_b + 23'sb0_1_0_0000_0000_0000_0000_0000;
+reg signed [25:0] sign_l_4Q21;
+always @(*) begin
+    if (sign_reg3==1'b1)begin
+        sign_l_4Q21 = ~l_4Q21_reg1+1;
+    end
+    else begin
+        sign_l_4Q21 = l_4Q21_reg1;
+    end
+end
+always@(posedge clk)begin
+	L_1Q7<=sign_l_4Q21[22:14];
+end
+//assign L_1Q7 = sign_l_4Q21[22:14];
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/README.md

@@ -0,0 +1,10 @@
+# Transformer Accelerator Based on FPGA
+You can run it on pynq z1 (or any other Zynq device, since the systolic array is parameterized). The repository contains the relevant Verilog code, Vivado configuration and C/Python code for sdk/PYNQ testing. The size of the systolic array can be changed, now it is 16X16.
+In the future, I might add some nonlinear hardware acceleration operators (for accelerating ViT, it's a kind of neural network based on Transformer), such as those that compute Softmax, Gelu and LayerNorm functions. I am still working on to improve the accuracy and performance of this part.
+
+How to reproduce this project: 
+1. In vivado2019.1, create a new project (note that the boardfile is pynq z1, you can download the corresponding boardfile here: https://pynq.readthedocs.io/en/v3.0.0/overlay_design_methodology/board_settings.html ).
+2. Add all the code to the project
+3. Run prj.tcl
+4. Create a wrapper for the block design and set it as the top module.
+5. Run the generated synthesis and implementation strategies and generate the bitstream.

Buck008_Transformer-Accelerator-Based-on-FPGA/prj.tcl

@@ -0,0 +1,1515 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl { 
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2019.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+
+# The design that will be created by this Tcl script contains the following 
+# module references:
+# MM_ultra_top
+
+# Please add the sources of those modules before sourcing this Tcl script.
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg400-1
+   set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_dma:7.1\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:axis_dwidth_converter:1.1\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:proc_sys_reset:5.0\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+##################################################################
+# CHECK Modules
+##################################################################
+set bCheckModules 1
+if { $bCheckModules == 1 } {
+   set list_check_mods "\ 
+MM_ultra_top\
+"
+
+   set list_mods_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+
+  # Create ports
+
+  # Create instance: MM_ultra_top_0, and set properties
+  set block_name MM_ultra_top
+  set block_cell_name MM_ultra_top_0
+  if { [catch {set MM_ultra_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $MM_ultra_top_0 eq "" } {
+     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.Weight_block_num {2500} \
+   CONFIG.array_size {24} \
+   CONFIG.in_feature_Block_num {2500} \
+   CONFIG.out_feature_block_num {2500} \
+   CONFIG.weight_width_block_num_width {5} \
+ ] $MM_ultra_top_0
+
+  # Create instance: axi_dma_0, and set properties
+  set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
+  set_property -dict [ list \
+   CONFIG.c_include_mm2s {1} \
+   CONFIG.c_include_mm2s_dre {1} \
+   CONFIG.c_include_s2mm {0} \
+   CONFIG.c_include_s2mm_dre {0} \
+   CONFIG.c_include_sg {0} \
+   CONFIG.c_m_axi_mm2s_data_width {64} \
+   CONFIG.c_m_axis_mm2s_tdata_width {64} \
+   CONFIG.c_mm2s_burst_size {256} \
+   CONFIG.c_sg_include_stscntrl_strm {0} \
+   CONFIG.c_sg_length_width {16} \
+ ] $axi_dma_0
+
+  # Create instance: axi_dma_1, and set properties
+  set axi_dma_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_1 ]
+  set_property -dict [ list \
+   CONFIG.c_include_mm2s {1} \
+   CONFIG.c_include_mm2s_dre {1} \
+   CONFIG.c_include_s2mm {0} \
+   CONFIG.c_include_s2mm_dre {0} \
+   CONFIG.c_include_sg {0} \
+   CONFIG.c_m_axi_mm2s_data_width {64} \
+   CONFIG.c_m_axis_mm2s_tdata_width {64} \
+   CONFIG.c_mm2s_burst_size {256} \
+   CONFIG.c_sg_include_stscntrl_strm {0} \
+   CONFIG.c_sg_length_width {16} \
+ ] $axi_dma_1
+
+  # Create instance: axi_dma_2, and set properties
+  set axi_dma_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_2 ]
+  set_property -dict [ list \
+   CONFIG.c_include_mm2s {0} \
+   CONFIG.c_include_mm2s_dre {0} \
+   CONFIG.c_include_s2mm {1} \
+   CONFIG.c_include_s2mm_dre {1} \
+   CONFIG.c_include_sg {0} \
+   CONFIG.c_m_axi_mm2s_data_width {64} \
+   CONFIG.c_m_axis_mm2s_tdata_width {32} \
+   CONFIG.c_mm2s_burst_size {16} \
+   CONFIG.c_s2mm_burst_size {256} \
+   CONFIG.c_sg_include_stscntrl_strm {0} \
+   CONFIG.c_sg_length_width {16} \
+ ] $axi_dma_2
+
+  # Create instance: axi_smc, and set properties
+  set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
+  set_property -dict [ list \
+   CONFIG.NUM_SI {1} \
+ ] $axi_smc
+
+  # Create instance: axi_smc_1, and set properties
+  set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ]
+  set_property -dict [ list \
+   CONFIG.NUM_SI {1} \
+ ] $axi_smc_1
+
+  # Create instance: axi_smc_2, and set properties
+  set axi_smc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_2 ]
+  set_property -dict [ list \
+   CONFIG.NUM_SI {1} \
+ ] $axi_smc_2
+
+  # Create instance: axis_dwidth_converter_0, and set properties
+  set axis_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_0 ]
+  set_property -dict [ list \
+   CONFIG.M_TDATA_NUM_BYTES {24} \
+ ] $axis_dwidth_converter_0
+
+  # Create instance: axis_dwidth_converter_1, and set properties
+  set axis_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_1 ]
+  set_property -dict [ list \
+   CONFIG.M_TDATA_NUM_BYTES {24} \
+ ] $axis_dwidth_converter_1
+
+  # Create instance: axis_dwidth_converter_2, and set properties
+  set axis_dwidth_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_2 ]
+  set_property -dict [ list \
+   CONFIG.M_TDATA_NUM_BYTES {8} \
+ ] $axis_dwidth_converter_2
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
+   CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
+   CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
+   CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
+   CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+   CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+   CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_CLK0_FREQ {100000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CORE0_FIQ_INTR {0} \
+   CONFIG.PCW_CORE0_IRQ_INTR {0} \
+   CONFIG.PCW_CORE1_FIQ_INTR {0} \
+   CONFIG.PCW_CORE1_IRQ_INTR {0} \
+   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
+   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
+   CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+   CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+   CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DM_WIDTH {4} \
+   CONFIG.PCW_DQS_WIDTH {4} \
+   CONFIG.PCW_DQ_WIDTH {32} \
+   CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+   CONFIG.PCW_ENET0_ENET0_IO {<Select>} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {<Select>} \
+   CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET0_RESET_IO {MIO 9} \
+   CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
+   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
+   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
+   CONFIG.PCW_EN_4K_TIMER {0} \
+   CONFIG.PCW_EN_CAN0 {0} \
+   CONFIG.PCW_EN_CAN1 {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_CLK1_PORT {0} \
+   CONFIG.PCW_EN_CLK2_PORT {0} \
+   CONFIG.PCW_EN_CLK3_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+   CONFIG.PCW_EN_DDR {1} \
+   CONFIG.PCW_EN_EMIO_CAN0 {0} \
+   CONFIG.PCW_EN_EMIO_CAN1 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_ENET1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {0} \
+   CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {0} \
+   CONFIG.PCW_EN_EMIO_SPI1 {0} \
+   CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+   CONFIG.PCW_EN_EMIO_TRACE {0} \
+   CONFIG.PCW_EN_EMIO_TTC0 {0} \
+   CONFIG.PCW_EN_EMIO_TTC1 {0} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_WDT {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {0} \
+   CONFIG.PCW_EN_ENET1 {0} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {0} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_PTP_ENET0 {0} \
+   CONFIG.PCW_EN_PTP_ENET1 {0} \
+   CONFIG.PCW_EN_QSPI {0} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SDIO1 {0} \
+   CONFIG.PCW_EN_SMC {0} \
+   CONFIG.PCW_EN_SPI0 {0} \
+   CONFIG.PCW_EN_SPI1 {0} \
+   CONFIG.PCW_EN_TRACE {0} \
+   CONFIG.PCW_EN_TTC0 {0} \
+   CONFIG.PCW_EN_TTC1 {0} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {0} \
+   CONFIG.PCW_EN_USB0 {1} \
+   CONFIG.PCW_EN_USB1 {0} \
+   CONFIG.PCW_EN_WDT {0} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+   CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+   CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_I2C_RESET_ENABLE {1} \
+   CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+   CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+   CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {32} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {inout} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {inout} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {slow} \
+   CONFIG.PCW_MIO_17_DIRECTION {inout} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {slow} \
+   CONFIG.PCW_MIO_18_DIRECTION {inout} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {slow} \
+   CONFIG.PCW_MIO_19_DIRECTION {inout} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {slow} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {inout} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {slow} \
+   CONFIG.PCW_MIO_21_DIRECTION {inout} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {slow} \
+   CONFIG.PCW_MIO_22_DIRECTION {inout} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {slow} \
+   CONFIG.PCW_MIO_23_DIRECTION {inout} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {slow} \
+   CONFIG.PCW_MIO_24_DIRECTION {inout} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {slow} \
+   CONFIG.PCW_MIO_25_DIRECTION {inout} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {slow} \
+   CONFIG.PCW_MIO_26_DIRECTION {inout} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {slow} \
+   CONFIG.PCW_MIO_27_DIRECTION {inout} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {slow} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {in} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {out} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {in} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {in} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {out} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {in} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {inout} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {out} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_PRIMITIVE {54} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#gpio[16]#gpio[17]#gpio[18]#gpio[19]#gpio[20]#gpio[21]#gpio[22]#gpio[23]#gpio[24]#gpio[25]#gpio[26]#gpio[27]#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53]} \
+   CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+   CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+   CONFIG.PCW_P2F_CAN0_INTR {0} \
+   CONFIG.PCW_P2F_CAN1_INTR {0} \
+   CONFIG.PCW_P2F_CTI_INTR {0} \
+   CONFIG.PCW_P2F_DMAC0_INTR {0} \
+   CONFIG.PCW_P2F_DMAC1_INTR {0} \
+   CONFIG.PCW_P2F_DMAC2_INTR {0} \
+   CONFIG.PCW_P2F_DMAC3_INTR {0} \
+   CONFIG.PCW_P2F_DMAC4_INTR {0} \
+   CONFIG.PCW_P2F_DMAC5_INTR {0} \
+   CONFIG.PCW_P2F_DMAC6_INTR {0} \
+   CONFIG.PCW_P2F_DMAC7_INTR {0} \
+   CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
+   CONFIG.PCW_P2F_ENET0_INTR {0} \
+   CONFIG.PCW_P2F_ENET1_INTR {0} \
+   CONFIG.PCW_P2F_GPIO_INTR {0} \
+   CONFIG.PCW_P2F_I2C0_INTR {0} \
+   CONFIG.PCW_P2F_I2C1_INTR {0} \
+   CONFIG.PCW_P2F_QSPI_INTR {0} \
+   CONFIG.PCW_P2F_SDIO0_INTR {0} \
+   CONFIG.PCW_P2F_SDIO1_INTR {0} \
+   CONFIG.PCW_P2F_SMC_INTR {0} \
+   CONFIG.PCW_P2F_SPI0_INTR {0} \
+   CONFIG.PCW_P2F_SPI1_INTR {0} \
+   CONFIG.PCW_P2F_UART0_INTR {0} \
+   CONFIG.PCW_P2F_UART1_INTR {0} \
+   CONFIG.PCW_P2F_USB0_INTR {0} \
+   CONFIG.PCW_P2F_USB1_INTR {0} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_PACKAGE_NAME {clg400} \
+   CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \
+   CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_IO {<Select>} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {<Select>} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+   CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {<Select>} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+   CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+   CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+   CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+   CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {32} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {<Select>} \
+   CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+   CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
+   CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
+   CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
+   CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
+   CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+   CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
+   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+   CONFIG.PCW_UART0_BAUD_RATE {115200} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
+   CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+   CONFIG.PCW_UART1_BAUD_RATE {115200} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {16} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
+   CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+   CONFIG.PCW_UIPARAM_DDR_AL {0} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BL {8} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
+   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+   CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+   CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+   CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 46} \
+   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+   CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
+   CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
+   CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+   CONFIG.PCW_USE_AXI_NONSECURE {0} \
+   CONFIG.PCW_USE_CORESIGHT {0} \
+   CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+   CONFIG.PCW_USE_CR_FABRIC {1} \
+   CONFIG.PCW_USE_DDR_BYPASS {0} \
+   CONFIG.PCW_USE_DEBUG {0} \
+   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
+   CONFIG.PCW_USE_DMA0 {0} \
+   CONFIG.PCW_USE_DMA1 {0} \
+   CONFIG.PCW_USE_DMA2 {0} \
+   CONFIG.PCW_USE_DMA3 {0} \
+   CONFIG.PCW_USE_EXPANDED_IOP {0} \
+   CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_HIGH_OCM {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_S_AXI_ACP {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {1} \
+   CONFIG.PCW_USE_S_AXI_HP1 {1} \
+   CONFIG.PCW_USE_S_AXI_HP2 {1} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+   CONFIG.PCW_USE_TRACE {0} \
+   CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
+   CONFIG.PCW_VALUE_SILVERSION {3} \
+   CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
+ ] $processing_system7_0
+
+  # Create instance: ps7_0_axi_periph, and set properties
+  set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {4} \
+ ] $ps7_0_axi_periph
+
+  # Create instance: rst_ps7_0_100M, and set properties
+  set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net MM_ultra_top_0_m0_axis [get_bd_intf_pins MM_ultra_top_0/m0_axis] [get_bd_intf_pins axis_dwidth_converter_2/S_AXIS]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_dwidth_converter_0/S_AXIS]
+  connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI]
+  connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S [get_bd_intf_pins axi_dma_1/M_AXIS_MM2S] [get_bd_intf_pins axis_dwidth_converter_1/S_AXIS]
+  connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S [get_bd_intf_pins axi_dma_1/M_AXI_MM2S] [get_bd_intf_pins axi_smc_1/S00_AXI]
+  connect_bd_intf_net -intf_net axi_dma_2_M_AXI_S2MM [get_bd_intf_pins axi_dma_2/M_AXI_S2MM] [get_bd_intf_pins axi_smc_2/S00_AXI]
+  connect_bd_intf_net -intf_net axi_smc_1_M00_AXI [get_bd_intf_pins axi_smc_1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
+  connect_bd_intf_net -intf_net axi_smc_2_M00_AXI [get_bd_intf_pins axi_smc_2/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
+  connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
+  connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins MM_ultra_top_0/s0_axis] [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS]
+  connect_bd_intf_net -intf_net axis_dwidth_converter_1_M_AXIS [get_bd_intf_pins MM_ultra_top_0/s1_axis] [get_bd_intf_pins axis_dwidth_converter_1/M_AXIS]
+  connect_bd_intf_net -intf_net axis_dwidth_converter_2_M_AXIS [get_bd_intf_pins axi_dma_2/S_AXIS_S2MM] [get_bd_intf_pins axis_dwidth_converter_2/M_AXIS]
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins MM_ultra_top_0/s00_axi] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_dma_1/S_AXI_LITE] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_dma_2/S_AXI_LITE] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
+
+  # Create port connections
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins MM_ultra_top_0/aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_dma_1/m_axi_mm2s_aclk] [get_bd_pins axi_dma_1/s_axi_lite_aclk] [get_bd_pins axi_dma_2/m_axi_s2mm_aclk] [get_bd_pins axi_dma_2/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axi_smc_1/aclk] [get_bd_pins axi_smc_2/aclk] [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins axis_dwidth_converter_1/aclk] [get_bd_pins axis_dwidth_converter_2/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
+  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins MM_ultra_top_0/aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_dma_1/axi_resetn] [get_bd_pins axi_dma_2/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_smc_1/aresetn] [get_bd_pins axi_smc_2/aresetn] [get_bd_pins axis_dwidth_converter_0/aresetn] [get_bd_pins axis_dwidth_converter_1/aresetn] [get_bd_pins axis_dwidth_converter_2/aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM
+  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_1/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
+  create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_2/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
+  create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs MM_ultra_top_0/s00_axi/reg0] SEG_MM_ultra_top_0_reg0
+  create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
+  create_bd_addr_seg -range 0x00010000 -offset 0x40410000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_1/S_AXI_LITE/Reg] SEG_axi_dma_1_Reg
+  create_bd_addr_seg -range 0x00010000 -offset 0x40420000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_2/S_AXI_LITE/Reg] SEG_axi_dma_2_Reg
+
+# Perform GUI Layout
+  regenerate_bd_layout -layout_string {
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0.19  2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 non-TLS-threadsafe
+#  -string -flagsOSRD
+preplace port DDR -pg 1 -lvl 11 -x 3350 -y 180 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -lvl 11 -x 3350 -y 200 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 9 -x 2860 -y 230 -defaultsOSRD
+preplace inst axi_dma_0 -pg 1 -lvl 3 -x 920 -y 110 -defaultsOSRD
+preplace inst axi_dma_1 -pg 1 -lvl 3 -x 920 -y 300 -defaultsOSRD
+preplace inst axi_dma_2 -pg 1 -lvl 7 -x 2120 -y 360 -defaultsOSRD
+preplace inst axis_dwidth_converter_0 -pg 1 -lvl 4 -x 1270 -y 100 -defaultsOSRD
+preplace inst axis_dwidth_converter_1 -pg 1 -lvl 4 -x 1270 -y 280 -defaultsOSRD
+preplace inst axis_dwidth_converter_2 -pg 1 -lvl 6 -x 1830 -y 300 -defaultsOSRD
+preplace inst axi_smc -pg 1 -lvl 8 -x 2470 -y 200 -defaultsOSRD
+preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 200 -y 120 -defaultsOSRD
+preplace inst axi_smc_1 -pg 1 -lvl 8 -x 2470 -y 500 -defaultsOSRD
+preplace inst axi_smc_2 -pg 1 -lvl 8 -x 2470 -y 360 -defaultsOSRD
+preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 540 -y 230 -defaultsOSRD
+preplace inst MM_ultra_top_0 -pg 1 -lvl 5 -x 1550 -y 280 -defaultsOSRD
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 10 30 20 370 50 710 210 1130 190 1400 380 1680 380 1950 460 2300 280 2610 80 3090
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 10 20 10 NJ 10 NJ 10 1100J 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 3110
+preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 7 380 40 730 20 1090 360 1410 390 1690 390 1940 470 2310
+preplace netloc axi_dma_1_M_AXI_MM2S 1 3 5 1110 180 NJ 180 NJ 180 NJ 180 2290J
+preplace netloc axi_smc_1_M00_AXI 1 8 1 2620 220n
+preplace netloc axi_dma_0_M_AXI_MM2S 1 3 5 1110 10 NJ 10 NJ 10 NJ 10 2310J
+preplace netloc axi_dma_1_M_AXIS_MM2S 1 3 1 1140 260n
+preplace netloc axi_dma_0_M_AXIS_MM2S 1 3 1 1120 80n
+preplace netloc processing_system7_0_DDR 1 9 2 NJ 180 N
+preplace netloc axis_dwidth_converter_1_M_AXIS 1 4 1 1380 260n
+preplace netloc ps7_0_axi_periph_M02_AXI 1 2 1 700 240n
+preplace netloc axi_smc_M00_AXI 1 8 1 N 200
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 9 390 -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 3100
+preplace netloc MM_ultra_top_0_m0_axis 1 5 1 N 280
+preplace netloc axis_dwidth_converter_0_M_AXIS 1 4 1 1410 100n
+preplace netloc axi_smc_2_M00_AXI 1 8 1 2630 240n
+preplace netloc ps7_0_axi_periph_M03_AXI 1 2 5 690 0 NJ 0 NJ 0 NJ 0 1950J
+preplace netloc axis_dwidth_converter_2_M_AXIS 1 6 1 1940 300n
+preplace netloc ps7_0_axi_periph_M00_AXI 1 2 3 N 200 NJ 200 1390J
+preplace netloc ps7_0_axi_periph_M01_AXI 1 2 1 720 80n
+preplace netloc axi_dma_2_M_AXI_S2MM 1 7 1 N 340
+preplace netloc processing_system7_0_FIXED_IO 1 9 2 NJ 200 N
+levelinfo -pg 1 0 200 540 920 1270 1550 1830 2120 2470 2860 3230 3350
+pagesize -pg 1 -db -bbox -sgen 0 -40 3470 610
+"
+}
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+  close_bd_design $design_name 
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+set_property GENERATE_SYNTH_CHECKPOINT "0" [get_files design_1.bd ] 
+set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] 
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2019} -strategy "Flow_AreaMultThresholdDSP" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Flow_AreaMultThresholdDSP" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2019" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "strategy" -value "Flow_AreaMultThresholdDSP" -objects $obj
+set_property -name "steps.synth_design.args.directive" -value "AreaMultThresholdDSP" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2019} -strategy "Performance_ExplorePostRoutePhysOpt" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Performance_ExplorePostRoutePhysOpt" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2019" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "strategy" -value "Performance_ExplorePostRoutePhysOpt" -objects $obj
+set_property -name "steps.opt_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.place_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.route_design.args.more options" -value "-tns_cleanup" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+# puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
+

Buck008_Transformer-Accelerator-Based-on-FPGA/pynq/MM.py

@@ -0,0 +1,155 @@
+import numpy as np
+from pynq import allocate
+from pynq import MMIO
+
+A_SIZE = 25
+in_F_max_size = 4000 * A_SIZE
+in_W_max_size = 4000 * A_SIZE
+out_F_max_size = 4000 * A_SIZE
+in_F_width_max = 64 * A_SIZE
+in_W_width_max  = 64 * A_SIZE
+shift_max = 32
+
+def mat_create(shape, data_type = np.int8):
+    height = shape[0]
+    width = shape[1]
+    if height % A_SIZE != 0:
+        An_h = height + A_SIZE - height % A_SIZE
+    else:
+        An_h = height
+        
+    if width % A_SIZE != 0:
+        An_w = width+ A_SIZE - width % A_SIZE
+    else:
+        An_w = width
+    A = allocate(shape=(An_h,An_w), dtype=data_type)
+    return [A[0:height,0:width], A]
+
+def mat_setValue(A,B:np.ndarray): #use numpy array to set value
+    A[0][:] = B 
+    
+def mat_getNdarray(A):
+    B = np.zeros((A[0].shape[0],A[0].shape[1])) 
+    B = A[0].copy()
+    return B
+
+def mat_delete(A):
+    A[1].freebuffer()
+    
+def mat_print(A):
+    print(A[0])
+
+def mat_mul_soft(A,B,C,shift):
+    C0 = A[0].astype(np.int32) @ B[0].astype(np.int32)
+    C0 = np.right_shift(C0,shift)
+    C0 = np.clip(C0,-128,127)
+    C[0][:] = C0 
+
+def ini_MM():
+    global MM_ultra 
+    global in_f_dma 
+    global in_w_dma
+    global out_f_dma
+
+    MM_ultra_addr= 0xA0030000
+    MM_ultra_addr_range = 0xFFF
+    MM_ultra = MMIO(MM_ultra_addr, MM_ultra_addr_range)
+    
+    global XAXIDMA_IDLE_MASK
+    XAXIDMA_IDLE_MASK = 0x00000002
+    
+    IN_FEATURE_DMA_ADDR = 0xA0000000
+    in_f_range = 0x10000
+    in_f_dma = MMIO(IN_FEATURE_DMA_ADDR, in_f_range)
+
+    IN_WEIGHT_DMA_ADDR = 0xA0010000
+    in_w_range = 0x10000
+    in_w_dma = MMIO(IN_WEIGHT_DMA_ADDR, in_w_range)
+
+    OUT_FEATURE_DMA_ADDR = 0xA0020000
+    out_f_range = 0x10000
+    out_f_dma = MMIO(OUT_FEATURE_DMA_ADDR, out_f_range)
+    
+
+def in_feature_transfer(array, start_offset = 0, len = 0):
+    start_addr = array.physical_address + start_offset
+    if len == 0:
+        len = array.nbytes
+    array.flush()
+    in_f_dma.write(0x0,0x4) #reset
+    in_f_dma.write(0x18,start_addr)
+    in_f_dma.write(0x0,0x1) #open channel 
+    in_f_dma.write(0x28,len)
+    
+def in_weight_transfer(array, start_offset = 0, len = 0):
+    start_addr = array.physical_address + start_offset
+    if len == 0:
+        len = array.nbytes
+    array.flush()
+    in_w_dma.write(0x0,0x4) #reset
+    in_w_dma.write(0x18,start_addr)
+    in_w_dma.write(0x0,0x1) #open channel 
+    in_w_dma.write(0x28,len)
+
+def out_feature_transfer(array, start_offset = 0, len = 0):
+    start_addr = array.physical_address + start_offset
+    if len == 0:
+        len = array.nbytes
+    out_f_dma.write(0x30,0x4) #reset
+    out_f_dma.write(0x48,start_addr)
+    out_f_dma.write(0x30,0x1) #open channel 
+    out_f_dma.write(0x58,len)
+    array.invalidate()
+    
+def out_feature_wait():
+    while False if out_f_dma.read(0x34) & XAXIDMA_IDLE_MASK else True:
+        pass
+def in_feature_wait():
+    while False if in_f_dma.read(0x4) & XAXIDMA_IDLE_MASK else True:
+        pass
+def in_weight_wait():
+    while False if in_w_dma.read(0x4) & XAXIDMA_IDLE_MASK else True:
+        pass
+    
+def mat_mul(A, B, C,shift=0):
+    A = A[1]
+    B = B[1]
+    C = C[1]
+    A_h = A.shape[0]
+    A_w = A.shape[1]
+    B_h = B.shape[0]
+    B_w = B.shape[1]
+    if A_h == 1:
+        print("\033[31mThe height of matrix A can not be 1\033[0m")
+        return 
+    if A_w > in_F_width_max:
+        print("\033[31mThe width of matrix A is too large\033[0m")
+        return 
+    if A_w != B_h:
+        print("\033[31mThe width of matrix A is not equal to the height of matrix B\033[0m")
+        return
+    if A_w % A_SIZE != 0 :
+        print("\033[31mThe width of matrix A is not the integer multiple of A_SIZE\033[0m")
+        return
+    if B_w % A_SIZE != 0 :
+        print("\033[31mThe width of matrix B is not the integer multiple of A_SIZE\033[0m")
+        return
+    if A.nbytes > in_F_max_size:
+        print("\033[31mThe size of matrix A is too large\033[0m")
+        return
+    if B.nbytes > in_W_max_size:
+        print("\033[31mThe size of matrix B is too large\033[0m")
+        return
+    if C.nbytes > in_W_max_size:
+        print("\033[31mThe size of matrix C is too large\033[0m")
+        return
+    F_width_block_num = int(A_w / A_SIZE)
+    W_width_block_num = int(B_w /A_SIZE)
+    MM_ultra.write(0x0,shift)
+    MM_ultra.write(0x4,A_h)
+    MM_ultra.write(0x8,F_width_block_num)
+    MM_ultra.write(0xc,W_width_block_num)
+    out_feature_transfer(C)
+    in_feature_transfer(A)
+    in_weight_transfer(B)
+    out_feature_wait()

Buck008_Transformer-Accelerator-Based-on-FPGA/sdk/README.txt

@@ -0,0 +1 @@
+Empty application. Add your own sources.

Buck008_Transformer-Accelerator-Based-on-FPGA/sdk/defines.h

@@ -0,0 +1,33 @@
+#ifndef SRC_DEFINES_H_
+#define SRC_DEFINES_H_
+#include "xparameters.h"
+#define CACHE_LINE_SIZE 32
+
+#define MM_ADDR 			XPAR_MM_ULTRA_TOP_0_BASEADDR
+#define SHIFT_ADDR 			MM_ADDR
+#define FL_ADDR 			(MM_ADDR + 0x04)
+#define FWBN_ADDR 		    (MM_ADDR +0x08)
+#define WWBN_ADDR	        (MM_ADDR +0x0c)
+
+#define WEIGHT_DMA_ADDR 	XPAR_AXI_DMA_1_BASEADDR
+#define WEIGHT_MM2S_DMACR  	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
+#define WEIGHT_MM2S_DMASR  	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
+#define WEIGHT_MM2S_SA	    (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
+#define WEIGHT_MM2S_LENGTH 	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
+
+#define FEATURE_DMA_ADDR 	XPAR_AXI_DMA_0_BASEADDR
+#define FEATURE_MM2S_DMACR  (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
+#define FEATURE_MM2S_DMASR  (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
+#define FEATURE_MM2S_SA	    (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
+#define FEATURE_MM2S_LENGTH (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
+
+#define RESULT_DMA_ADDR		XPAR_AXI_DMA_2_BASEADDR
+#define RESULT_S2MM_DMACR  (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET) //S2MM DMA Control register
+#define RESULT_S2MM_DMASR  (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET) //S2MM DMA Status register
+#define RESULT_S2MM_DA	    (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //S2MM Destination Address
+#define RESULT_S2MM_LENGTH (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //S2MM Transfer Length (Bytes)
+
+#define A_SIZE 24
+
+
+#endif /* SRC_DEFINES_H_ */

Buck008_Transformer-Accelerator-Based-on-FPGA/sdk/main.c

@@ -0,0 +1,155 @@
+#include "xparameters.h"
+#include "xil_io.h"
+#include "stdio.h"
+#include "xtime_l.h"
+#include <stdlib.h>
+#include "xil_cache.h"
+#include "xil_types.h"
+#include "xaxidma_hw.h"
+#include "sleep.h"
+#include "matrix.h"
+#include "defines.h"
+
+#define CAL_SOFT 1
+XTime t1,t2,t3,t4,t5,t6;
+
+int main()
+{
+int times = 10;
+int a;
+for(a=0;a<times;a++){
+	printf("/*************************************************************/\n");
+	printf("Hello,%d\n",a);
+	u32 shift = 10;
+	u32 IN_ROWS_NUM = 160;
+	u32 IN_COLS_NUM = 160;
+	u32 OUT_COLS_NUM = 160;
+
+	u32 F_width_block_num = IN_COLS_NUM / A_SIZE;
+	u32 W_width_block_num = OUT_COLS_NUM /A_SIZE;
+//	Xil_DCacheDisable();
+	int feature_in_size = IN_ROWS_NUM * IN_COLS_NUM;
+	int feature_out_size = IN_ROWS_NUM * OUT_COLS_NUM;
+	int weight_size = IN_COLS_NUM * OUT_COLS_NUM;
+
+#if CAL_SOFT
+    matrix A = mat_create(IN_ROWS_NUM,IN_COLS_NUM);
+    matrix B = mat_create(IN_COLS_NUM,OUT_COLS_NUM);
+    matrix C = mat_create(IN_ROWS_NUM,OUT_COLS_NUM);
+#endif
+    s8 *weight_buffer ;
+    s8 *feature_in_buffer;
+    s8 *feature_out_buffer;
+
+	XTime_GetTime(&t1);
+    feature_in_buffer = (s8*) malloc(feature_in_size);
+    weight_buffer =  (s8*) malloc(weight_size);
+    feature_out_buffer = (s8*) malloc(feature_out_size);
+
+	XTime_GetTime(&t2);
+    int i;
+    int j;
+	for(i=0;i<IN_ROWS_NUM;i++){
+		for(j=0;j<IN_COLS_NUM;j++){
+			int value = rand()%256-128;//rand()%16-7;
+//			int value = (i * A_SIZE +j + 128)%256 - 128;
+//			int value = 1;
+			*(feature_in_buffer + i * IN_COLS_NUM + j)=value;
+#if CAL_SOFT
+			mat_setValue(A,i,j,value);
+#endif
+		}
+	}
+	for(i=0;i<IN_COLS_NUM;i++){
+		for(j=0;j<OUT_COLS_NUM;j++){
+			int value = rand()%256-128;//rand()%16-7;
+//			int value = (i * A_SIZE +j + 128)%256 - 128;
+//			int value = 2;
+			*(weight_buffer + i * OUT_COLS_NUM + j)=value;
+#if CAL_SOFT
+			mat_setValue(B,i,j,value);
+#endif
+		}
+	}
+
+	Xil_DCacheFlushRange(weight_buffer,weight_size);
+	Xil_DCacheFlushRange(feature_in_buffer,feature_in_size);
+	Xil_DCacheFlushRange(feature_out_buffer,feature_out_size);//make sure that the invalidate data will not cause data loss
+	Xil_DCacheInvalidateRange(feature_out_buffer,feature_out_size);
+	XTime_GetTime(&t3);
+	Xil_Out32(SHIFT_ADDR,shift);
+	Xil_Out32(FL_ADDR,IN_ROWS_NUM);
+	Xil_Out32(FWBN_ADDR,F_width_block_num);
+	Xil_Out32(WWBN_ADDR,W_width_block_num);
+
+
+	//first open receive channel
+	Xil_Out32(RESULT_S2MM_DMACR, 0x4);//reset
+	Xil_Out32(RESULT_S2MM_DA, (u32)feature_out_buffer); //set addr
+	Xil_Out32(RESULT_S2MM_DMACR, 0x1);  //open channel
+	Xil_Out32(RESULT_S2MM_LENGTH,feature_out_size); //set length
+
+	Xil_Out32(WEIGHT_MM2S_DMACR, 0x4);
+	Xil_Out32(WEIGHT_MM2S_SA, (u32)weight_buffer);
+	Xil_Out32(WEIGHT_MM2S_DMACR, 0x1);
+	Xil_Out32(WEIGHT_MM2S_LENGTH,weight_size);
+
+	Xil_Out32(FEATURE_MM2S_DMACR, 0x4);
+	Xil_Out32(FEATURE_MM2S_SA, (u32)feature_in_buffer);
+	Xil_Out32(FEATURE_MM2S_DMACR, 0x1);
+	Xil_Out32(FEATURE_MM2S_LENGTH,feature_in_size);
+
+
+	while((Xil_In32(RESULT_S2MM_DMASR) & XAXIDMA_IDLE_MASK) ? FALSE : TRUE){
+		printf("*\n");
+	};
+//	sleep(1);
+	XTime_GetTime(&t4);
+
+	XTime_GetTime(&t5);
+#if CAL_SOFT
+	mat_mul(A,B,C,shift);
+#endif
+	XTime_GetTime(&t6);
+
+
+	float T_allocBuffer = (float)(t2-t1)*(1000000 / COUNTS_PER_SECOND);
+	float T_hard = (float)(t4-t3)*1000000 / COUNTS_PER_SECOND;
+#if CAL_SOFT
+	float T_soft = (float)(t6-t5)*1000000 / COUNTS_PER_SECOND;
+#endif
+
+#if CAL_SOFT
+	unsigned long error_num = 0;
+	for(i=0;i<IN_ROWS_NUM;i++){
+		for(j=0;j<OUT_COLS_NUM;j++){
+			int temp = (int)*(feature_out_buffer + i * OUT_COLS_NUM + j)- mat_getValue(C,i,j);
+			if(temp!=0){
+				error_num++;
+				if(error_num < 1000){
+					printf("row %d, col %d: %7d,%7d\n",i,j,temp,mat_getValue(C,i,j));
+				}
+			}
+
+		}
+	}
+#endif
+	printf("Time spent on memory allocation:%.2fus\n",T_allocBuffer);
+
+	printf("Time spent on hardware calculation:%.2fus\n",T_hard);
+#if CAL_SOFT
+	printf("Time spent on software calculation��%.2fus\n",T_soft);
+#endif
+	free(weight_buffer);
+	free(feature_in_buffer);
+	free(feature_out_buffer);
+#if CAL_SOFT
+	mat_free(A);
+	mat_free(B);
+	mat_free(C);
+#endif
+	printf("END\n");
+	printf("/*************************************************************/\n\n\n\n\n\n\n");
+}
+	return 0;
+}

Buck008_Transformer-Accelerator-Based-on-FPGA/sdk/matrix.c

@@ -0,0 +1,100 @@
+#include"matrix.h"
+
+
+matrix mat_create(int num_of_rows, int num_of_cols){
+    matrix A;
+    A.num_of_rows = num_of_rows;
+    A.num_of_cols = num_of_cols;
+    DATA_TYPE * ddrAddr = (DATA_TYPE*) malloc( num_of_rows * num_of_cols * sizeof(DATA_TYPE));
+    A.ddrAddr = ddrAddr;
+    return A;
+}
+
+void mat_setValue(matrix A, int row, int col, DATA_TYPE value){
+    if((row > A.num_of_rows-1) || (col > A.num_of_cols -1)){
+        printf("mat_setValue: index out of bound, row = %d, col = %d\n",row,col);
+        return;
+    }
+    if(row <0  || col < 0){
+        printf("mat_setValue: negative index\n");
+        return;
+    }
+    *(A.ddrAddr + row * A.num_of_cols + col) = value;
+}
+
+DATA_TYPE mat_getValue(matrix A, int row, int col){
+    if((row > A.num_of_rows-1) || (col > A.num_of_cols -1)){
+        printf("mat_getValue: index out of bound, row = %d, col = %d\n",row,col);
+        return 0;
+    }
+        if(row <0  || col < 0){
+        printf("mat_getValue: negative index\n");
+        return 0;
+    }
+    return *(A.ddrAddr + row * A.num_of_cols + col);
+}
+
+void mat_set(matrix_Ptr A_p, void * addr, int num_of_rows, int num_of_cols){ 
+    int size = num_of_cols * num_of_rows * sizeof(DATA_TYPE);
+    free(A_p->ddrAddr);
+    A_p->ddrAddr = (DATA_TYPE *) malloc(size);
+    memcpy(A_p->ddrAddr,addr,size);
+    A_p->num_of_cols = num_of_cols;
+    A_p->num_of_rows = num_of_rows;
+    return;
+}
+
+void mat_mul(matrix A, matrix B, matrix C, int R_shift){ //A * B = C
+    if(A.num_of_cols != B.num_of_rows){
+        printf("size mismatch\n");
+        return;
+    }
+    if(A.num_of_rows != C.num_of_rows || B.num_of_cols != C.num_of_cols){
+        printf("size mismatch\n");
+        return;
+    }
+    int temp;
+    int i;
+    int j;
+    int k;
+
+    for (i=0;i<C.num_of_rows;i++){
+//    	printf("\n");
+        for(j=0;j<C.num_of_cols;j++){
+            temp=0;
+            for(k=0;k<A.num_of_cols;k++){
+                temp = temp + mat_getValue(A,i,k)*mat_getValue(B,k,j);
+            }
+//            printf("temp: %d\n",temp);
+            if(R_shift > 0){
+            	temp = (temp+(1<<(R_shift-1))) >> R_shift; 
+            }
+
+            if (temp > MAX_LIMIT){
+                temp = MAX_LIMIT;
+            }
+            if (temp < MIN_LIMIT){
+                temp = MIN_LIMIT;
+            }
+//            printf("%d",temp);
+            mat_setValue(C,i,j,temp);
+        }
+    }
+};
+
+void mat_print(matrix A){
+	int i,j;
+	for(i=0;i<A.num_of_rows;i++){
+		printf("row %d: ",i);
+		for(j=0;j<A.num_of_cols;j++){
+			printf("%7d",(int)mat_getValue(A,i,j));
+		}
+		printf("\n");
+	}
+	printf("\n");
+}
+
+void mat_free(matrix A){
+    free(A.ddrAddr);
+}
+

Buck008_Transformer-Accelerator-Based-on-FPGA/sdk/matrix.h

@@ -0,0 +1,28 @@
+#ifndef SRC_MATRIX_H_
+#define SRC_MATRIX_H_
+#include "xil_types.h"
+#include <stdio.h>
+#include<stdlib.h>
+#include <limits.h>
+#include "xil_printf.h"
+#include <string.h>
+
+#define DATA_TYPE s8
+#define MAX_LIMIT 127
+#define MIN_LIMIT -128
+
+typedef struct{
+    int num_of_rows;
+    int num_of_cols;
+    DATA_TYPE *ddrAddr;
+} matrix, *matrix_Ptr;
+
+matrix mat_create(int num_of_rows, int num_of_cols);
+void mat_setValue(matrix A, int row, int col, DATA_TYPE value);
+DATA_TYPE mat_getValue(matrix A, int row, int col);
+void mat_set(matrix_Ptr A, void * addr, int num_of_rows, int num_of_cols);
+void mat_mul(matrix A, matrix B, matrix C, int R_shift);
+void mat_free(matrix A);
+void mat_print(matrix A);
+
+#endif /* SRC_MATRIX_H_ */

Buck008_Transformer-Accelerator-Based-on-FPGA/sim/MM_Ultra_tb.sv

@@ -0,0 +1,378 @@
+`timescale 1ns / 1ns
+
+`define A_size 16
+`define DATA_WIDTH 8
+`define SHIFT_WIDTH 10 
+`define IN_Feature_Block_num 2400
+`define Weight_Block_num 2400
+`define OUT_Feature_Block_num 2400
+`define OUT_MEM_WIDTH 21
+`define F_length_width 10
+`define F_width_block_num_width 5
+`define W_width_block_num_width 5
+
+`define IN_ROWS_NUM 200 //MM_buffer also has limit
+`define IN_COLS_NUM 96 //Must be integer multiple of A_size
+`define OUT_COLS_NUM 160 //Must be integer multiple of A_size
+
+
+module MM_Ultra_tb;
+
+parameter integer P_shift = 9;
+parameter integer P_F_length = `IN_ROWS_NUM;
+parameter integer P_F_width_block_num = `IN_COLS_NUM / `A_size;
+parameter integer P_W_width_block_num = `OUT_COLS_NUM / `A_size;
+
+
+
+task MM_soft(input integer x[`IN_ROWS_NUM-1:0][`IN_COLS_NUM-1:0], 
+               input integer y[`IN_COLS_NUM-1:0][`OUT_COLS_NUM-1:0],
+               input integer scale,
+               output integer z[`IN_ROWS_NUM-1:0][`OUT_COLS_NUM-1:0]);
+begin
+    automatic integer temp;
+    automatic integer i;
+    automatic integer j;
+    automatic integer k;
+
+    for (i=0;i<`IN_ROWS_NUM;i++)begin
+        for (j=0;j<`OUT_COLS_NUM;j++)begin
+            temp = 0;
+            for (k=0;k<`IN_COLS_NUM;k++) begin
+                temp = temp + x[i][k] * y[k][j];    
+            end
+
+//            $display("%d",temp);
+            if(scale > 0 )begin
+                temp = (temp+(1<<(scale-1))) >>> scale; //round
+            end
+            if (temp > 127)
+                temp = 127;
+            if (temp < -128)
+                temp = -128;
+//                        $display("%d",temp);
+            z[i][j] = temp;
+        end
+    end
+end
+endtask
+
+
+reg                                                   clk;
+reg                                                   rst_n;
+
+reg [`SHIFT_WIDTH-1:0]                                shift;
+reg [`F_length_width-1:0]                             F_length; //1 ~ block_num *A_size
+reg [`F_width_block_num_width-1:0]                    F_width_block_num; //1 ~ block_num
+reg [`W_width_block_num_width-1:0]                    W_width_block_num; //1 ~ block_num
+
+
+reg                                                   in_F_valid;
+wire                                                  in_F_last;
+wire                                                  in_F_ready;
+wire [`A_size * `DATA_WIDTH - 1:0]                    in_F_data;
+
+reg                                                   out_data_ready;
+reg                                                   in_W_valid;
+wire                                                  in_W_last;
+wire                                                  in_W_ready;
+wire  [`A_size * `DATA_WIDTH - 1:0]                   in_W_data;
+
+wire                                                  out_data_valid;
+wire                                                  out_data_last;
+wire [`A_size * `DATA_WIDTH -1:0]                     out_data;
+
+genvar i,j;
+
+
+MM_ultra
+#(
+    .A_size(`A_size),                                                   //Determines the side length of SA, that is, the size
+    .data_width(`DATA_WIDTH),                                           //Determines the quantized data bit width
+    .shift_width(`SHIFT_WIDTH),                                         //Determines the bit width of the shifter shift variable
+    .Weight_Block_num(`Weight_Block_num),                               //Determines the number of weight_buffer_blocks in the IN_BUFFER.
+    .IN_Feature_Block_num(`IN_Feature_Block_num),                       //Determines the number of feature_buffer_blocks in the IN_BUFFER.
+    .OUT_Feature_Block_num(`OUT_Feature_Block_num),                     //Determines the number of feature_buffer_blocks in the OUT_BUFFER.
+    .OUT_MEM_WIDTH(`OUT_MEM_WIDTH),                                     //Determines the data bit width of the OUT_BUFFER
+    .F_length_width(`F_length_width),                                   //Determines the bit width of the F_length register and the bram size in the MM_buffer
+    .F_width_block_num_width(`F_width_block_num_width),                 
+    .W_width_block_num_width(`W_width_block_num_width)                  
+                                                                        //F length and W width block num will be multiplied. Notice the timing
+)u_MM_ultra(
+    .clk(clk),
+    .rst_n(rst_n),
+
+
+    .shift_in(shift),
+    .F_length_in(F_length), //1 ~ block_num *A_size
+    .F_width_block_num_in(F_width_block_num), //1 ~ block_num
+    .W_width_block_num_in(W_width_block_num), //1 ~ block_num
+
+
+    .in_F_valid(in_F_valid),
+    .in_F_last(in_F_last),
+    .in_F_ready(in_F_ready),
+    .in_F_data(in_F_data),
+
+    .in_W_valid(in_W_valid),
+    .in_W_last(in_W_last),
+    .in_W_ready(in_W_ready),
+    .in_W_data(in_W_data),
+
+    .out_data_valid(out_data_valid),
+    .out_data_last(out_data_last),
+    .out_data_ready(out_data_ready),
+    .out_data(out_data)
+);
+
+integer x[`IN_ROWS_NUM-1:0][`IN_COLS_NUM-1:0];
+integer y[`IN_COLS_NUM-1:0][`OUT_COLS_NUM-1:0];
+
+integer x_flatten[`IN_ROWS_NUM * `IN_COLS_NUM - 1:0];
+integer y_flatten[`IN_COLS_NUM * `OUT_COLS_NUM - 1:0];
+
+initial begin
+    integer i;
+    integer j;
+    $display("x:");
+    $write("[");
+    for(i=0;i<`IN_ROWS_NUM;i++)begin
+        $write("[");
+        for(j=0;j<`IN_COLS_NUM;j++)begin
+//            automatic integer temp = (i * `IN_COLS_NUM + j)%256 - 128;
+            automatic integer temp = $random%128;
+//            automatic integer temp = 1;
+            if (temp > 127)
+                temp = 127;
+            if(temp < -128)
+                temp = -128;
+            x[i][j] = temp;
+            x_flatten[i*`IN_COLS_NUM + j] = temp;
+             $write("%5d,",x[i][j]);
+        end
+             $display("],");
+    end    
+    $write("]");
+    $display();
+    $display("y:");
+    $write("[");
+    for(i=0;i<`IN_COLS_NUM;i++)begin
+        $write("[");
+        for(j=0;j<`OUT_COLS_NUM;j++)begin
+//            automatic integer temp = j; 
+            automatic integer temp = $random%128;            
+//            automatic integer temp = 1;
+            if (temp > 127)
+                temp = 127;
+            if(temp < -128)
+                temp = -128;
+            y[i][j] = temp;
+            y_flatten[i*`OUT_COLS_NUM + j] = temp;
+            $write("%5d,",y[i][j]);
+        end
+        $display("],");
+    end
+    $display("]");
+end
+integer z_soft[`IN_ROWS_NUM-1:0][`OUT_COLS_NUM-1:0];
+
+
+
+wire [`A_size * `DATA_WIDTH - 1:0] x_in_array [`IN_ROWS_NUM * P_F_width_block_num - 1:0];
+wire [`A_size * `DATA_WIDTH - 1:0] y_in_array [`IN_COLS_NUM * P_W_width_block_num - 1:0];
+
+
+generate
+    for(i=0;i<`IN_ROWS_NUM * P_F_width_block_num;i++)begin
+        for(j=0;j<`A_size;j++)begin
+            assign x_in_array[i][j*`DATA_WIDTH +: `DATA_WIDTH] = x_flatten[i*`A_size + j];
+        end
+    end
+
+    for(i=0;i<`IN_COLS_NUM * P_W_width_block_num;i++)begin
+        for(j=0;j<`A_size;j++)begin
+            assign y_in_array[i][j*`DATA_WIDTH +: `DATA_WIDTH] = y_flatten[i*`A_size + j];
+        end
+    end
+endgenerate
+
+reg start_trans;
+initial start_trans = 0;
+
+reg [31:0] in_F_addr;
+initial in_F_addr = 0;
+
+always @(posedge clk ) begin
+    if(in_F_last)
+        in_F_addr <=0;
+    if(in_F_valid)
+        in_F_addr <= in_F_addr + 1;
+end
+
+assign in_F_data = x_in_array[in_F_addr];
+wire [`DATA_WIDTH - 1:0] F_in_data_display  [`A_size - 1:0];
+generate
+    for(i=0;i<`A_size;i++)begin
+        assign F_in_data_display[i] = in_F_data[i*`DATA_WIDTH +: `DATA_WIDTH];
+    end
+endgenerate
+assign in_F_last =(in_F_addr == `IN_ROWS_NUM * P_F_width_block_num - 1)? 1:0;
+
+always @(posedge clk) begin
+    if(~rst_n)
+        in_F_valid <= 0;
+    else if (start_trans)
+        in_F_valid <= 1;
+    else if (in_F_last)
+        in_F_valid <= 0;
+end
+
+reg [31:0] in_W_addr;
+initial in_W_addr = 0;
+
+always @(posedge clk ) begin
+    if(in_W_last)
+        in_W_addr <=0;
+    if(in_W_valid)
+        in_W_addr <= in_W_addr + 1;
+end
+
+assign in_W_data = y_in_array[in_W_addr];
+wire [`DATA_WIDTH - 1:0] W_in_data_display [`A_size - 1:0];
+generate
+    for(i=0;i<`A_size;i++)begin
+        assign W_in_data_display[i] = in_W_data[i*`DATA_WIDTH +: `DATA_WIDTH];
+    end
+endgenerate
+assign in_W_last =(in_W_addr == `IN_COLS_NUM * P_W_width_block_num - 1)? 1:0;
+
+always @(posedge clk) begin
+    if(~rst_n)
+        in_W_valid <= 0;
+    else if (start_trans)
+        in_W_valid <= 1;
+    else if (in_W_last)
+        in_W_valid <= 0;
+end
+
+wire [`DATA_WIDTH - 1:0] out_data_display   [`A_size - 1:0];
+generate
+    for(i=0;i<`A_size;i++)begin
+        assign out_data_display[i] = out_data[i*`DATA_WIDTH +: `DATA_WIDTH];
+    end
+endgenerate
+
+reg [`A_size * `DATA_WIDTH - 1:0] z_hard [`IN_ROWS_NUM * P_W_width_block_num-1:0];
+reg [31:0] z_hard_addr;
+integer z_hard_array [`IN_ROWS_NUM-1:0][`OUT_COLS_NUM-1:0];
+wire [`DATA_WIDTH - 1:0] z_hard_flatten [`IN_ROWS_NUM * `OUT_COLS_NUM-1:0];
+initial z_hard_addr = 0;
+
+always @(posedge clk ) begin
+    if (out_data_last)
+        z_hard_addr <= 0;
+    else if(out_data_valid&out_data_ready)
+        z_hard_addr <= z_hard_addr + 1;
+end
+
+always @(posedge clk) begin
+    if(out_data_valid &out_data_ready)
+        z_hard[z_hard_addr] <= out_data;
+end
+
+generate
+    for(i = 0;i<`IN_ROWS_NUM * P_W_width_block_num;i++)begin
+        for(j=0;j<`A_size;j++)begin
+            assign z_hard_flatten[i*`A_size+j] = z_hard[i][j*`DATA_WIDTH +: `DATA_WIDTH]; 
+        end
+    end
+
+    for(i=0;i<`IN_ROWS_NUM;i++)begin
+        for(j=0;j<`OUT_COLS_NUM;j++)begin
+            always @(*) begin
+                z_hard_array[i][j] = $signed(z_hard_flatten[i*`OUT_COLS_NUM + j]);
+            end
+        end
+    end
+endgenerate
+
+
+
+initial clk = 0;
+always  begin
+    #5 clk = ~clk;
+end
+
+reg out_data_ready_gen;
+
+initial out_data_ready_gen = 0;
+always begin
+    #10 out_data_ready_gen = //~out_data_ready_gen;
+                            {$random}%2;
+end
+
+always @(posedge clk ) begin
+    out_data_ready <= out_data_ready_gen;
+end
+
+initial begin
+    shift = 0;
+    F_length = 0;
+    F_width_block_num = 0;
+    W_width_block_num =0;
+end
+
+
+initial begin
+    rst_n = 0;
+    #50 rst_n = 1;
+    #50
+    #1000
+    shift = P_shift;
+    F_length = P_F_length;
+    F_width_block_num = P_F_width_block_num;
+    W_width_block_num = P_W_width_block_num;
+    MM_soft(x,y,shift,z_soft);
+    #1000 start_trans = 1;
+    #10 start_trans = 0;
+end
+integer error = 0;
+integer zero_error = 0;
+
+integer m,n;
+always  begin
+    #10
+    if(out_data_last) begin
+        error = 0;
+        #(200*`IN_ROWS_NUM)
+        $display("z_hard:");
+        for(m=0;m<`IN_ROWS_NUM;m++)begin
+            for(n=0;n<`OUT_COLS_NUM;n++)begin
+                if($signed(z_hard_array[m][n])!= z_soft[m][n])begin
+                    $write("error:hard = %0d, soft = %0d.      ",$signed(z_hard_array[m][n]),z_soft[m][n]);
+                    error++;
+                end
+                else
+                    $write("%7d,",$signed(z_hard_array[m][n]));
+            end
+            $display();
+        end
+        #10;
+        if(error != 0)
+            $display("Error!, error = %d.",error);
+        else
+        $display("No Error.");
+
+        for(m=0;m<`OUT_Feature_Block_num;m++)begin
+            if(u_MM_ultra.u_MM_out_buffer.F_array[m]!=0)
+                zero_error= zero_error+1;
+        end
+        if(zero_error != 0)
+            $display("Error!, zero_error = %d.",zero_error);
+        else
+        $display("No zero_error.");
+        $finish();
+    end
+end
+    
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/sim/MM_Ultra_tb_behav.wcfg

@@ -0,0 +1,1331 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="MM_Ultra_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="MM_Ultra_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="183045494684fs"></ZoomStartTime>
+      <ZoomEndTime time="190760901064fs"></ZoomEndTime>
+      <Cursor1Time time="181222017000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="306"></NameColumnWidth>
+      <ValueColumnWidth column_width="72"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="6" />
+   <wvobject fp_name="group67" type="group">
+      <obj_property name="label">tb</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/start_trans" type="logic">
+         <obj_property name="ElementShortName">start_trans</obj_property>
+         <obj_property name="ObjectShortName">start_trans</obj_property>
+      </wvobject>
+      <wvobject fp_name="group68" type="group">
+         <obj_property name="label">registers</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/shift" type="array">
+            <obj_property name="ElementShortName">shift[9:0]</obj_property>
+            <obj_property name="ObjectShortName">shift[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/F_length" type="array">
+            <obj_property name="ElementShortName">F_length[9:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/F_width_block_num" type="array">
+            <obj_property name="ElementShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/W_width_block_num" type="array">
+            <obj_property name="ElementShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group69" type="group">
+         <obj_property name="label">IN_F</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/in_F_valid" type="logic">
+            <obj_property name="ElementShortName">in_F_valid</obj_property>
+            <obj_property name="ObjectShortName">in_F_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_F_last" type="logic">
+            <obj_property name="ElementShortName">in_F_last</obj_property>
+            <obj_property name="ObjectShortName">in_F_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_F_ready" type="logic">
+            <obj_property name="ElementShortName">in_F_ready</obj_property>
+            <obj_property name="ObjectShortName">in_F_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_F_data" type="array">
+            <obj_property name="ElementShortName">in_F_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_F_addr" type="array">
+            <obj_property name="ElementShortName">in_F_addr[31:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_addr[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/F_in_data_display" type="array">
+            <obj_property name="ElementShortName">F_in_data_display[15:0][7:0]</obj_property>
+            <obj_property name="ObjectShortName">F_in_data_display[15:0][7:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group70" type="group">
+         <obj_property name="label">IN_W</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/in_W_valid" type="logic">
+            <obj_property name="ElementShortName">in_W_valid</obj_property>
+            <obj_property name="ObjectShortName">in_W_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_W_last" type="logic">
+            <obj_property name="ElementShortName">in_W_last</obj_property>
+            <obj_property name="ObjectShortName">in_W_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_W_ready" type="logic">
+            <obj_property name="ElementShortName">in_W_ready</obj_property>
+            <obj_property name="ObjectShortName">in_W_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_W_data" type="array">
+            <obj_property name="ElementShortName">in_W_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/in_W_addr" type="array">
+            <obj_property name="ElementShortName">in_W_addr[31:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_addr[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/W_in_data_display" type="array">
+            <obj_property name="ElementShortName">W_in_data_display[15:0][7:0]</obj_property>
+            <obj_property name="ObjectShortName">W_in_data_display[15:0][7:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group71" type="group">
+         <obj_property name="label">OUT_D</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_valid" type="logic">
+            <obj_property name="ElementShortName">out_data_valid</obj_property>
+            <obj_property name="ObjectShortName">out_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_ready" type="logic">
+            <obj_property name="ElementShortName">out_data_ready</obj_property>
+            <obj_property name="ObjectShortName">out_data_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_last" type="logic">
+            <obj_property name="ElementShortName">out_data_last</obj_property>
+            <obj_property name="ObjectShortName">out_data_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data" type="array">
+            <obj_property name="ElementShortName">out_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/z_hard_addr" type="array">
+            <obj_property name="ElementShortName">z_hard_addr[31:0]</obj_property>
+            <obj_property name="ObjectShortName">z_hard_addr[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_display" type="array">
+            <obj_property name="ElementShortName">out_data_display[15:0][7:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data_display[15:0][7:0]</obj_property>
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group72" type="group">
+         <obj_property name="label">parameters</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/P_shift" type="array">
+            <obj_property name="ElementShortName">P_shift[31:0]</obj_property>
+            <obj_property name="ObjectShortName">P_shift[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/P_F_length" type="array">
+            <obj_property name="ElementShortName">P_F_length[31:0]</obj_property>
+            <obj_property name="ObjectShortName">P_F_length[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/P_F_width_block_num" type="array">
+            <obj_property name="ElementShortName">P_F_width_block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">P_F_width_block_num[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/P_W_width_block_num" type="array">
+            <obj_property name="ElementShortName">P_W_width_block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">P_W_width_block_num[31:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group116" type="group">
+      <obj_property name="label">MM_Ultra</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="group108" type="group">
+         <obj_property name="label">registers</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/shift" type="array">
+            <obj_property name="ElementShortName">shift[9:0]</obj_property>
+            <obj_property name="ObjectShortName">shift[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/F_length" type="array">
+            <obj_property name="ElementShortName">F_length[9:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/F_width_block_num" type="array">
+            <obj_property name="ElementShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/W_width_block_num" type="array">
+            <obj_property name="ElementShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group109" type="group">
+         <obj_property name="label">IN_F</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_F_valid" type="logic">
+            <obj_property name="ElementShortName">in_F_valid</obj_property>
+            <obj_property name="ObjectShortName">in_F_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_F_last" type="logic">
+            <obj_property name="ElementShortName">in_F_last</obj_property>
+            <obj_property name="ObjectShortName">in_F_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_F_ready" type="logic">
+            <obj_property name="ElementShortName">in_F_ready</obj_property>
+            <obj_property name="ObjectShortName">in_F_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_F_data" type="array">
+            <obj_property name="ElementShortName">in_F_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_data[127:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group110" type="group">
+         <obj_property name="label">IN_W</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_W_valid" type="logic">
+            <obj_property name="ElementShortName">in_W_valid</obj_property>
+            <obj_property name="ObjectShortName">in_W_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_W_last" type="logic">
+            <obj_property name="ElementShortName">in_W_last</obj_property>
+            <obj_property name="ObjectShortName">in_W_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_W_ready" type="logic">
+            <obj_property name="ElementShortName">in_W_ready</obj_property>
+            <obj_property name="ObjectShortName">in_W_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_W_data" type="array">
+            <obj_property name="ElementShortName">in_W_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_data[127:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group111" type="group">
+         <obj_property name="label">OUT_D</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/out_data_valid" type="logic">
+            <obj_property name="ElementShortName">out_data_valid</obj_property>
+            <obj_property name="ObjectShortName">out_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_ready" type="logic">
+            <obj_property name="ElementShortName">out_data_ready</obj_property>
+            <obj_property name="ObjectShortName">out_data_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/out_data_last" type="logic">
+            <obj_property name="ElementShortName">out_data_last</obj_property>
+            <obj_property name="ObjectShortName">out_data_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/out_data" type="array">
+            <obj_property name="ElementShortName">out_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/out_data_display" type="array">
+            <obj_property name="ElementShortName">out_data_display[15:0][7:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data_display[15:0][7:0]</obj_property>
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group112" type="group">
+         <obj_property name="label">MM_buffer_out</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/MM_buffer_out_data" type="array">
+            <obj_property name="ElementShortName">MM_buffer_out_data[319:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_data[319:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/MM_buffer_out_valid" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_out_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/MM_buffer_out_last" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_out_last</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_last</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group113" type="group">
+         <obj_property name="label">IN_MM_buffer_F</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_F_valid" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_valid</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_valid</obj_property>
+            <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_F_last" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_last</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_last</obj_property>
+            <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_F_ready" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_ready</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_ready</obj_property>
+            <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_F_data" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_F_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_data[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#E0FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group114" type="group">
+         <obj_property name="label">IN_MM_buffer_W</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_W_valid" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_valid</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_valid</obj_property>
+            <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_W_last" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_last</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_last</obj_property>
+            <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_W_ready" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_ready</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_ready</obj_property>
+            <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/in_MM_buffer_W_data" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_W_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_data[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group115" type="group">
+         <obj_property name="label">parameters</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/A_size" type="array">
+            <obj_property name="ElementShortName">A_size[31:0]</obj_property>
+            <obj_property name="ObjectShortName">A_size[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/data_width" type="array">
+            <obj_property name="ElementShortName">data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">data_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/shift_width" type="array">
+            <obj_property name="ElementShortName">shift_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">shift_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/log2_array_m" type="array">
+            <obj_property name="ElementShortName">log2_array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">log2_array_m[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/Weight_Block_num" type="array">
+            <obj_property name="ElementShortName">Weight_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">Weight_Block_num[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/IN_Feature_Block_num" type="array">
+            <obj_property name="ElementShortName">IN_Feature_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">IN_Feature_Block_num[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/OUT_Feature_Block_num" type="array">
+            <obj_property name="ElementShortName">OUT_Feature_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">OUT_Feature_Block_num[31:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group1982" type="group">
+      <obj_property name="label">MM_in_buffer</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/MM_buffer_out_last" type="logic">
+         <obj_property name="ElementShortName">MM_buffer_out_last</obj_property>
+         <obj_property name="ObjectShortName">MM_buffer_out_last</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/start" type="logic">
+         <obj_property name="ElementShortName">start</obj_property>
+         <obj_property name="ObjectShortName">start</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/state" type="array">
+         <obj_property name="ElementShortName">state[1:0]</obj_property>
+         <obj_property name="ObjectShortName">state[1:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/W_block_size" type="array">
+         <obj_property name="ElementShortName">W_block_size[11:0]</obj_property>
+         <obj_property name="ObjectShortName">W_block_size[11:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_block_size" type="array">
+         <obj_property name="ElementShortName">F_block_size[11:0]</obj_property>
+         <obj_property name="ObjectShortName">F_block_size[11:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="group1983" type="group">
+         <obj_property name="label">registers</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/W_width_block_num" type="array">
+            <obj_property name="ElementShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_width_block_num" type="array">
+            <obj_property name="ElementShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_length" type="array">
+            <obj_property name="ElementShortName">F_length[9:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1984" type="group">
+         <obj_property name="label">IN_F</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_valid" type="logic">
+            <obj_property name="ElementShortName">in_F_valid</obj_property>
+            <obj_property name="ObjectShortName">in_F_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_last" type="logic">
+            <obj_property name="ElementShortName">in_F_last</obj_property>
+            <obj_property name="ObjectShortName">in_F_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_ready" type="logic">
+            <obj_property name="ElementShortName">in_F_ready</obj_property>
+            <obj_property name="ObjectShortName">in_F_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_data" type="array">
+            <obj_property name="ElementShortName">in_F_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_cnt" type="array">
+            <obj_property name="ElementShortName">in_F_cnt[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_cnt[11:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_F_addr" type="array">
+            <obj_property name="ElementShortName">in_F_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_addr[11:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1985" type="group">
+         <obj_property name="label">IN_W</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_valid" type="logic">
+            <obj_property name="ElementShortName">in_W_valid</obj_property>
+            <obj_property name="ObjectShortName">in_W_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_last" type="logic">
+            <obj_property name="ElementShortName">in_W_last</obj_property>
+            <obj_property name="ObjectShortName">in_W_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_ready" type="logic">
+            <obj_property name="ElementShortName">in_W_ready</obj_property>
+            <obj_property name="ObjectShortName">in_W_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_data" type="array">
+            <obj_property name="ElementShortName">in_W_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_cnt" type="array">
+            <obj_property name="ElementShortName">in_W_cnt[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_cnt[11:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_W_addr" type="array">
+            <obj_property name="ElementShortName">in_W_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_W_addr[11:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1986" type="group">
+         <obj_property name="label">IN_MM_buffer_F</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_F_valid" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_valid</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_F_last" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_last</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_F_ready" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_F_ready</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_F_data" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_F_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_F_cnt" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_F_cnt[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_F_cnt[11:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/out_F_row_addr" type="array">
+            <obj_property name="ElementShortName">out_F_row_addr[9:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_row_addr[9:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/out_F_col_addr" type="array">
+            <obj_property name="ElementShortName">out_F_col_addr[4:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_col_addr[4:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/out_F_addr" type="array">
+            <obj_property name="ElementShortName">out_F_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_addr[11:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1987" type="group">
+         <obj_property name="label">IN_MM_buffer_W</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_W_valid" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_valid</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_W_last" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_last</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_W_ready" type="logic">
+            <obj_property name="ElementShortName">in_MM_buffer_W_ready</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_W_data" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_W_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/in_MM_buffer_W_cnt" type="array">
+            <obj_property name="ElementShortName">in_MM_buffer_W_cnt[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_MM_buffer_W_cnt[11:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/out_W_addr" type="array">
+            <obj_property name="ElementShortName">out_W_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">out_W_addr[11:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/temp_m" type="array">
+         <obj_property name="ElementShortName">temp_m[8:0]</obj_property>
+         <obj_property name="ObjectShortName">temp_m[8:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="group1988" type="group">
+         <obj_property name="label">parameters</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/A_size" type="array">
+            <obj_property name="ElementShortName">A_size[31:0]</obj_property>
+            <obj_property name="ObjectShortName">A_size[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/data_width" type="array">
+            <obj_property name="ElementShortName">data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">data_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/Weight_Block_num" type="array">
+            <obj_property name="ElementShortName">Weight_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">Weight_Block_num[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/IN_Feature_Block_num" type="array">
+            <obj_property name="ElementShortName">IN_Feature_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">IN_Feature_Block_num[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_length_width" type="array">
+            <obj_property name="ElementShortName">F_length_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_width_block_num_width" type="array">
+            <obj_property name="ElementShortName">F_width_block_num_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/W_width_block_num_width" type="array">
+            <obj_property name="ElementShortName">W_width_block_num_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/F_size_width" type="array">
+            <obj_property name="ElementShortName">F_size_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_size_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/W_size_width" type="array">
+            <obj_property name="ElementShortName">W_size_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">W_size_width[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_in_buffer/log_A_size" type="array">
+            <obj_property name="ElementShortName">log_A_size[31:0]</obj_property>
+            <obj_property name="ObjectShortName">log_A_size[31:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group230" type="group">
+      <obj_property name="label">MM_buffer</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="group220" type="group">
+         <obj_property name="label">registers</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/FL" type="array">
+            <obj_property name="ElementShortName">FL[9:0]</obj_property>
+            <obj_property name="ObjectShortName">FL[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/num_blobk_W" type="array">
+            <obj_property name="ElementShortName">num_blobk_W[4:0]</obj_property>
+            <obj_property name="ObjectShortName">num_blobk_W[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/total_WL_reg" type="array">
+            <obj_property name="ElementShortName">total_WL_reg[8:0]</obj_property>
+            <obj_property name="ObjectShortName">total_WL_reg[8:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/FL_reg" type="array">
+            <obj_property name="ElementShortName">FL_reg[9:0]</obj_property>
+            <obj_property name="ObjectShortName">FL_reg[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group224" type="group">
+         <obj_property name="label">Control</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/state" type="array">
+            <obj_property name="ElementShortName">state[1:0]</obj_property>
+            <obj_property name="ObjectShortName">state[1:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/start" type="logic">
+            <obj_property name="ElementShortName">start</obj_property>
+            <obj_property name="ObjectShortName">start</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/start_ahead1" type="logic">
+            <obj_property name="ElementShortName">start_ahead1</obj_property>
+            <obj_property name="ObjectShortName">start_ahead1</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/set_w_delay1" type="logic">
+            <obj_property name="ElementShortName">set_w_delay1</obj_property>
+            <obj_property name="ObjectShortName">set_w_delay1</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/w_end" type="logic">
+            <obj_property name="ElementShortName">w_end</obj_property>
+            <obj_property name="ObjectShortName">w_end</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/weight_flag_up" type="logic">
+            <obj_property name="ElementShortName">weight_flag_up</obj_property>
+            <obj_property name="ObjectShortName">weight_flag_up</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/both_full" type="logic">
+            <obj_property name="ElementShortName">both_full</obj_property>
+            <obj_property name="ObjectShortName">both_full</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/both_full_delay1" type="logic">
+            <obj_property name="ElementShortName">both_full_delay1</obj_property>
+            <obj_property name="ObjectShortName">both_full_delay1</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/set_w" type="logic">
+            <obj_property name="ElementShortName">set_w</obj_property>
+            <obj_property name="ObjectShortName">set_w</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/total_last" type="logic">
+            <obj_property name="ElementShortName">total_last</obj_property>
+            <obj_property name="ObjectShortName">total_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/wdata_flag_up" type="logic">
+            <obj_property name="ElementShortName">wdata_flag_up</obj_property>
+            <obj_property name="ObjectShortName">wdata_flag_up</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group221" type="group">
+         <obj_property name="label">MM_buffer_in_weight</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inWeight_data" type="array">
+            <obj_property name="ElementShortName">MM_buffer_inWeight_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inWeight_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inWeight_valid" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inWeight_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inWeight_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inWeight_ready" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inWeight_ready</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inWeight_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inWeight_last" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inWeight_last</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inWeight_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/weight_buffer_cnt" type="array">
+            <obj_property name="ElementShortName">weight_buffer_cnt[8:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_buffer_cnt[8:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/weight_buffer_in_addr" type="array">
+            <obj_property name="ElementShortName">weight_buffer_in_addr[8:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_buffer_in_addr[8:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group222" type="group">
+         <obj_property name="label">MM_buffer_in_feature</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inFeature_data" type="array">
+            <obj_property name="ElementShortName">MM_buffer_inFeature_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inFeature_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inFeature_valid" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inFeature_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inFeature_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inFeature_ready" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inFeature_ready</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inFeature_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_inFeature_last" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_inFeature_last</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_inFeature_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/feature_buffer_cnt" type="array">
+            <obj_property name="ElementShortName">feature_buffer_cnt[9:0]</obj_property>
+            <obj_property name="ObjectShortName">feature_buffer_cnt[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/feature_buffer_in_addr" type="array">
+            <obj_property name="ElementShortName">feature_buffer_in_addr[9:0]</obj_property>
+            <obj_property name="ObjectShortName">feature_buffer_in_addr[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group223" type="group">
+         <obj_property name="label">MM_buffer_out</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_out_data" type="array">
+            <obj_property name="ElementShortName">MM_buffer_out_data[319:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_data[319:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_out_valid" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_out_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_buffer_out_last" type="logic">
+            <obj_property name="ElementShortName">MM_buffer_out_last</obj_property>
+            <obj_property name="ObjectShortName">MM_buffer_out_last</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group225" type="group">
+         <obj_property name="label">MM_in</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_in_data" type="array">
+            <obj_property name="ElementShortName">MM_in_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_in_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_in_data_valid" type="logic">
+            <obj_property name="ElementShortName">MM_in_data_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_in_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/MM_in_last" type="logic">
+            <obj_property name="ElementShortName">MM_in_last</obj_property>
+            <obj_property name="ObjectShortName">MM_in_last</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group228" type="group">
+         <obj_property name="label">out_MM</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/output_feature_data" type="array">
+            <obj_property name="ElementShortName">output_feature_data[319:0]</obj_property>
+            <obj_property name="ObjectShortName">output_feature_data[319:0]</obj_property>
+            <obj_property name="CustomSignalColor">#FFD700</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/output_feature_valid" type="logic">
+            <obj_property name="ElementShortName">output_feature_valid</obj_property>
+            <obj_property name="ObjectShortName">output_feature_valid</obj_property>
+            <obj_property name="CustomSignalColor">#FFD700</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/output_feature_last" type="logic">
+            <obj_property name="ElementShortName">output_feature_last</obj_property>
+            <obj_property name="ObjectShortName">output_feature_last</obj_property>
+            <obj_property name="CustomSignalColor">#FFD700</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group226" type="group">
+         <obj_property name="label">MM_in_weight</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_valid" type="logic">
+            <obj_property name="ElementShortName">input_weight_valid</obj_property>
+            <obj_property name="ObjectShortName">input_weight_valid</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_last" type="logic">
+            <obj_property name="ElementShortName">input_weight_last</obj_property>
+            <obj_property name="ObjectShortName">input_weight_last</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_data" type="array">
+            <obj_property name="ElementShortName">input_weight_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">input_weight_data[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_addr" type="array">
+            <obj_property name="ElementShortName">input_weight_addr[8:0]</obj_property>
+            <obj_property name="ObjectShortName">input_weight_addr[8:0]</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_col" type="array">
+            <obj_property name="ElementShortName">input_weight_col[4:0]</obj_property>
+            <obj_property name="ObjectShortName">input_weight_col[4:0]</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_weight_row" type="array">
+            <obj_property name="ElementShortName">input_weight_row[3:0]</obj_property>
+            <obj_property name="ObjectShortName">input_weight_row[3:0]</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/weight_cnt" type="array">
+            <obj_property name="ElementShortName">weight_cnt[8:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_cnt[8:0]</obj_property>
+            <obj_property name="CustomSignalColor">#F0E68C</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group227" type="group">
+         <obj_property name="label">MM_in_feature</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_feature_valid" type="logic">
+            <obj_property name="ElementShortName">input_feature_valid</obj_property>
+            <obj_property name="ObjectShortName">input_feature_valid</obj_property>
+            <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_feature_last" type="logic">
+            <obj_property name="ElementShortName">input_feature_last</obj_property>
+            <obj_property name="ObjectShortName">input_feature_last</obj_property>
+            <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_feature_data" type="array">
+            <obj_property name="ElementShortName">input_feature_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">input_feature_data[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/input_feature_addr" type="array">
+            <obj_property name="ElementShortName">input_feature_addr[9:0]</obj_property>
+            <obj_property name="ObjectShortName">input_feature_addr[9:0]</obj_property>
+            <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/feature_cnt" type="array">
+            <obj_property name="ElementShortName">feature_cnt[9:0]</obj_property>
+            <obj_property name="ObjectShortName">feature_cnt[9:0]</obj_property>
+            <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group229" type="group">
+         <obj_property name="label">parameters</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/array_m" type="array">
+            <obj_property name="ElementShortName">array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">array_m[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/array_n" type="array">
+            <obj_property name="ElementShortName">array_n[31:0]</obj_property>
+            <obj_property name="ObjectShortName">array_n[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/data_width" type="array">
+            <obj_property name="ElementShortName">data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">data_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/log2_array_m" type="array">
+            <obj_property name="ElementShortName">log2_array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">log2_array_m[31:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group814" type="group">
+      <obj_property name="label">MM</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/set_w_port" type="logic">
+         <obj_property name="ElementShortName">set_w_port</obj_property>
+         <obj_property name="ObjectShortName">set_w_port</obj_property>
+      </wvobject>
+      <wvobject fp_name="group813" type="group">
+         <obj_property name="label">Control</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/wdata_flag_up" type="logic">
+            <obj_property name="ElementShortName">wdata_flag_up</obj_property>
+            <obj_property name="ObjectShortName">wdata_flag_up</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/wdata_flag" type="logic">
+            <obj_property name="ElementShortName">wdata_flag</obj_property>
+            <obj_property name="ObjectShortName">wdata_flag</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/set_w" type="logic">
+            <obj_property name="ElementShortName">set_w</obj_property>
+            <obj_property name="ObjectShortName">set_w</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group305" type="group">
+         <obj_property name="label">MM_in</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_in_data" type="array">
+            <obj_property name="ElementShortName">MM_in_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_in_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_in_data_valid" type="logic">
+            <obj_property name="ElementShortName">MM_in_data_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_in_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_in_last" type="logic">
+            <obj_property name="ElementShortName">MM_in_last</obj_property>
+            <obj_property name="ObjectShortName">MM_in_last</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group306" type="group">
+         <obj_property name="label">MM_out</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_out_data" type="array">
+            <obj_property name="ElementShortName">MM_out_data[319:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_out_data[319:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_out_data_valid" type="logic">
+            <obj_property name="ElementShortName">MM_out_data_valid</obj_property>
+            <obj_property name="ObjectShortName">MM_out_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_out_last" type="logic">
+            <obj_property name="ElementShortName">MM_out_last</obj_property>
+            <obj_property name="ObjectShortName">MM_out_last</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group308" type="group">
+         <obj_property name="label">SA</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/w_packed" type="array">
+            <obj_property name="ElementShortName">w_packed[2047:0]</obj_property>
+            <obj_property name="ObjectShortName">w_packed[2047:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/weight_in" type="array">
+            <obj_property name="ElementShortName">weight_in[127:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_in[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/feature_in" type="array">
+            <obj_property name="ElementShortName">feature_in[127:0]</obj_property>
+            <obj_property name="ObjectShortName">feature_in[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/x_packed" type="array">
+            <obj_property name="ElementShortName">x_packed[127:0]</obj_property>
+            <obj_property name="ObjectShortName">x_packed[127:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/data_out" type="array">
+            <obj_property name="ElementShortName">data_out[319:0]</obj_property>
+            <obj_property name="ObjectShortName">data_out[319:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/PE_out_packed" type="array">
+            <obj_property name="ElementShortName">PE_out_packed[319:0]</obj_property>
+            <obj_property name="ObjectShortName">PE_out_packed[319:0]</obj_property>
+            <obj_property name="CustomSignalColor">#800080</obj_property>
+            <obj_property name="UseCustomSignalColor">true</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group307" type="group">
+         <obj_property name="label">PARAMETERS</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/array_m" type="array">
+            <obj_property name="ElementShortName">array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">array_m[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/array_n" type="array">
+            <obj_property name="ElementShortName">array_n[31:0]</obj_property>
+            <obj_property name="ObjectShortName">array_n[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/data_width" type="array">
+            <obj_property name="ElementShortName">data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">data_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/log2_array_m" type="array">
+            <obj_property name="ElementShortName">log2_array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">log2_array_m[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/axis_data_width" type="array">
+            <obj_property name="ElementShortName">axis_data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">axis_data_width[31:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group557" type="group">
+         <obj_property name="label">Buffer</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/data_out_reg1" type="array">
+            <obj_property name="ElementShortName">data_out_reg1[319:0]</obj_property>
+            <obj_property name="ObjectShortName">data_out_reg1[319:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/feature_in_reg1" type="array">
+            <obj_property name="ElementShortName">feature_in_reg1[127:0]</obj_property>
+            <obj_property name="ObjectShortName">feature_in_reg1[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/weight_buffer" type="array">
+            <obj_property name="ElementShortName">weight_buffer[15:0][127:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_buffer[15:0][127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/weight_buffer_cnt" type="array">
+            <obj_property name="ElementShortName">weight_buffer_cnt[5:0]</obj_property>
+            <obj_property name="ObjectShortName">weight_buffer_cnt[5:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_out_data_valid_reg_array" type="array">
+            <obj_property name="ElementShortName">MM_out_data_valid_reg_array[32:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_out_data_valid_reg_array[32:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_buffer/u_MM/MM_out_last_reg_array" type="array">
+            <obj_property name="ElementShortName">MM_out_last_reg_array[32:0]</obj_property>
+            <obj_property name="ObjectShortName">MM_out_last_reg_array[32:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group1914" type="group">
+      <obj_property name="label">MM_out_buffer_buffer</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/clk" type="logic">
+         <obj_property name="ElementShortName">clk</obj_property>
+         <obj_property name="ObjectShortName">clk</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/rst_n" type="logic">
+         <obj_property name="ElementShortName">rst_n</obj_property>
+         <obj_property name="ObjectShortName">rst_n</obj_property>
+      </wvobject>
+      <wvobject fp_name="group1915" type="group">
+         <obj_property name="label">registers</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/shift" type="array">
+            <obj_property name="ElementShortName">shift[9:0]</obj_property>
+            <obj_property name="ObjectShortName">shift[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_length" type="array">
+            <obj_property name="ElementShortName">F_length[9:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length[9:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_width_block_num" type="array">
+            <obj_property name="ElementShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/W_width_block_num" type="array">
+            <obj_property name="ElementShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1932" type="group">
+         <obj_property name="label">control</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/start_trans" type="logic">
+            <obj_property name="ElementShortName">start_trans</obj_property>
+            <obj_property name="ObjectShortName">start_trans</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/last_cnt" type="array">
+            <obj_property name="ElementShortName">last_cnt[4:0]</obj_property>
+            <obj_property name="ObjectShortName">last_cnt[4:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_F_block_size" type="array">
+            <obj_property name="ElementShortName">out_F_block_size[11:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_block_size[11:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1916" type="group">
+         <obj_property name="label">IN_D</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/in_data_valid" type="logic">
+            <obj_property name="ElementShortName">in_data_valid</obj_property>
+            <obj_property name="ObjectShortName">in_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/in_data_last" type="logic">
+            <obj_property name="ElementShortName">in_data_last</obj_property>
+            <obj_property name="ObjectShortName">in_data_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/in_data" type="array">
+            <obj_property name="ElementShortName">in_data[319:0]</obj_property>
+            <obj_property name="ObjectShortName">in_data[319:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1917" type="group">
+         <obj_property name="label">OUT_D</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_valid" type="logic">
+            <obj_property name="ElementShortName">out_data_valid</obj_property>
+            <obj_property name="ObjectShortName">out_data_valid</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_cnt" type="array">
+            <obj_property name="ElementShortName">out_data_cnt[11:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data_cnt[11:0]</obj_property>
+            <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_last" type="logic">
+            <obj_property name="ElementShortName">out_data_last</obj_property>
+            <obj_property name="ObjectShortName">out_data_last</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_ready" type="logic">
+            <obj_property name="ElementShortName">out_data_ready</obj_property>
+            <obj_property name="ObjectShortName">out_data_ready</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data" type="array">
+            <obj_property name="ElementShortName">out_data[127:0]</obj_property>
+            <obj_property name="ObjectShortName">out_data[127:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="group1933" type="group">
+            <obj_property name="label">out_data_addr</obj_property>
+            <obj_property name="DisplayName">label</obj_property>
+            <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_col_addr" type="array">
+               <obj_property name="ElementShortName">out_data_col_addr[4:0]</obj_property>
+               <obj_property name="ObjectShortName">out_data_col_addr[4:0]</obj_property>
+            </wvobject>
+            <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_row_addr" type="array">
+               <obj_property name="ElementShortName">out_data_row_addr[9:0]</obj_property>
+               <obj_property name="ObjectShortName">out_data_row_addr[9:0]</obj_property>
+            </wvobject>
+            <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_data_addr" type="array">
+               <obj_property name="ElementShortName">out_data_addr[11:0]</obj_property>
+               <obj_property name="ObjectShortName">out_data_addr[11:0]</obj_property>
+            </wvobject>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1934" type="group">
+         <obj_property name="label">read port</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_F_array_addr" type="array">
+            <obj_property name="ElementShortName">out_F_array_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_array_addr[11:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_F_array_data" type="array">
+            <obj_property name="ElementShortName">out_F_array_data[335:0]</obj_property>
+            <obj_property name="ObjectShortName">out_F_array_data[335:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group3593" type="group">
+         <obj_property name="label">write port</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="isExpanded"></obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/in_F_array_addr" type="array">
+            <obj_property name="ElementShortName">in_F_array_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_array_addr[11:0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/in_F_array_data" type="array">
+            <obj_property name="ElementShortName">in_F_array_data[335:0]</obj_property>
+            <obj_property name="ObjectShortName">in_F_array_data[335:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="group1931" type="group">
+         <obj_property name="label">Adder</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/A" type="array">
+            <obj_property name="ElementShortName">A[319:0]</obj_property>
+            <obj_property name="ObjectShortName">A[319:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/A_in_adder" type="array">
+            <obj_property name="ElementShortName">A_in_adder[335:0]</obj_property>
+            <obj_property name="ObjectShortName">A_in_adder[335:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/B" type="array">
+            <obj_property name="ElementShortName">B[335:0]</obj_property>
+            <obj_property name="ObjectShortName">B[335:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/C" type="array">
+            <obj_property name="ElementShortName">C[335:0]</obj_property>
+            <obj_property name="ObjectShortName">C[335:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/B_addr" type="array">
+            <obj_property name="ElementShortName">B_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">B_addr[11:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/C_addr" type="array">
+            <obj_property name="ElementShortName">C_addr[11:0]</obj_property>
+            <obj_property name="ObjectShortName">C_addr[11:0]</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_valid" type="logic">
+         <obj_property name="ElementShortName">F_array_out_valid</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_valid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_cnt" type="array">
+         <obj_property name="ElementShortName">F_array_out_cnt[11:0]</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_cnt[11:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_valid_delay1" type="logic">
+         <obj_property name="ElementShortName">F_array_out_valid_delay1</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_valid_delay1</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_cnt_delay1" type="array">
+         <obj_property name="ElementShortName">F_array_out_cnt_delay1[11:0]</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_cnt_delay1[11:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_valid_delay2" type="logic">
+         <obj_property name="ElementShortName">F_array_out_valid_delay2</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_valid_delay2</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_array_out_last_delay2" type="logic">
+         <obj_property name="ElementShortName">F_array_out_last_delay2</obj_property>
+         <obj_property name="ObjectShortName">F_array_out_last_delay2</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_F_data" type="array">
+         <obj_property name="ElementShortName">out_F_data[335:0]</obj_property>
+         <obj_property name="ObjectShortName">out_F_data[335:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/out_F_data_delay1" type="array">
+         <obj_property name="ElementShortName">out_F_data_delay1[335:0]</obj_property>
+         <obj_property name="ObjectShortName">out_F_data_delay1[335:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/shifted_data" type="array">
+         <obj_property name="ElementShortName">shifted_data[127:0]</obj_property>
+         <obj_property name="ObjectShortName">shifted_data[127:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/clear_addr" type="array">
+         <obj_property name="ElementShortName">clear_addr[11:0]</obj_property>
+         <obj_property name="ObjectShortName">clear_addr[11:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="group1918" type="group">
+         <obj_property name="label">parameters</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/data_width" type="array">
+            <obj_property name="ElementShortName">data_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">data_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/OUT_Feature_Block_num" type="array">
+            <obj_property name="ElementShortName">OUT_Feature_Block_num[31:0]</obj_property>
+            <obj_property name="ObjectShortName">OUT_Feature_Block_num[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/OUT_MEM_WIDTH" type="array">
+            <obj_property name="ElementShortName">OUT_MEM_WIDTH[31:0]</obj_property>
+            <obj_property name="ObjectShortName">OUT_MEM_WIDTH[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/A_size" type="array">
+            <obj_property name="ElementShortName">A_size[31:0]</obj_property>
+            <obj_property name="ObjectShortName">A_size[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/shift_width" type="array">
+            <obj_property name="ElementShortName">shift_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">shift_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/log2_array_m" type="array">
+            <obj_property name="ElementShortName">log2_array_m[31:0]</obj_property>
+            <obj_property name="ObjectShortName">log2_array_m[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_length_width" type="array">
+            <obj_property name="ElementShortName">F_length_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_length_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_width_block_num_width" type="array">
+            <obj_property name="ElementShortName">F_width_block_num_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_width_block_num_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/W_width_block_num_width" type="array">
+            <obj_property name="ElementShortName">W_width_block_num_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">W_width_block_num_width[31:0]</obj_property>
+         </wvobject>
+         <wvobject fp_name="/MM_Ultra_tb/u_MM_ultra/u_MM_out_buffer/F_size_width" type="array">
+            <obj_property name="ElementShortName">F_size_width[31:0]</obj_property>
+            <obj_property name="ObjectShortName">F_size_width[31:0]</obj_property>
+         </wvobject>
+      </wvobject>
+   </wvobject>
+</wave_config>

Buck008_Transformer-Accelerator-Based-on-FPGA/src/AdderS.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+
+module AdderS
+#(
+    parameter integer A_size = 4,
+    parameter integer data_width = 8
+)(
+    input  [A_size * data_width - 1 : 0] A,
+    input  [A_size * data_width - 1 : 0] B,
+    output reg [A_size * data_width - 1 : 0] C
+);
+wire [(data_width + 1)-1:0] temp [A_size-1:0]; //Double sign bit to determine positive overflow or negative overflow
+wire [data_width - 1:0] C_array_display [A_size-1:0];
+genvar i;
+
+generate
+    for(i=0;i<A_size;i=i+1)begin
+        assign C_array_display[i] = C[i*data_width +: data_width];
+    end
+endgenerate
+
+generate
+    for(i=0;i<A_size;i=i+1)begin
+        assign temp[i] = {A[(i+1)*data_width-1],A[i *data_width +: data_width]} 
+                       + {B[(i+1)*data_width-1],B[i *data_width +: data_width]};
+    end
+endgenerate
+generate
+    for(i=0;i<A_size;i=i+1)begin
+        always @(*) begin
+            case (temp[i][data_width:data_width-1])
+                2'b01: C[i * data_width +: data_width] = {1'b0,{(data_width-1){1'b1}}};   
+                2'b10: C[i * data_width +: data_width] = {1'b1,{(data_width-1){1'b0}}};   
+                default: C[i * data_width +: data_width] = temp[i][data_width-1:0];
+            endcase
+         
+        end
+    end
+endgenerate
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM.v

@@ -0,0 +1,219 @@
+`timescale 1ns / 1ps
+
+module MM
+#(
+    parameter array_m = 6, 
+    parameter array_n = 6, 
+    parameter data_width = 8, 
+    // parameter shift_width = 20,
+    parameter log2_array_m = 4,
+    localparam integer axis_data_width = array_m * data_width 
+)
+(
+    clk,
+    rst_n,
+
+    set_w_port,
+
+    // shift,
+    wdata_flag_up, 
+
+    MM_in_data,
+    MM_in_data_valid,
+    MM_in_last,
+
+    MM_out_data,
+    MM_out_data_valid,
+    MM_out_last
+);
+
+input wire                                                      clk;
+input wire                                                      rst_n;
+
+output wire                                                      set_w_port;
+
+// input wire [shift_width-1:0]                                    shift;
+input wire                                                      wdata_flag_up; 
+
+input wire [axis_data_width-1:0]                                MM_in_data;
+input wire                                                      MM_in_data_valid;
+input wire                                                      MM_in_last;
+
+output wire [array_n*(log2_array_m+data_width*2)-1:0]           MM_out_data;
+output wire                                                     MM_out_data_valid;
+output wire                                                     MM_out_last;
+
+
+
+reg [array_n*(log2_array_m+data_width*2)-1:0]    data_out_reg1;
+reg [axis_data_width-1:0] feature_in_reg1;
+reg [axis_data_width-1:0] weight_buffer [array_m-1:0];
+reg MM_out_data_valid_reg_array [2*array_m:0];
+reg MM_out_last_reg_array [2*array_m:0];
+reg [5:0] weight_buffer_cnt;
+//reg weight_ready;
+reg wdata_flag;
+
+wire set_w;
+wire [array_n*(log2_array_m+data_width*2)-1:0]  data_out;
+wire [array_m*array_n*data_width-1:0] w_packed;
+wire [array_n*(log2_array_m+data_width*2)-1:0] PE_out_packed;
+wire [axis_data_width-1:0] feature_in;
+wire [axis_data_width-1:0] weight_in;
+wire [data_width*array_m-1:0] x_packed;
+
+
+genvar i;
+generate
+    for(i=0;i<array_m;i=i+1)begin:array_to_packed
+        assign w_packed[(data_width*array_n)*i +: (data_width*array_n)] = weight_buffer[array_m-1-i];//ע���±������Ƿ���
+    end
+endgenerate
+
+assign set_w_port = set_w;
+assign MM_out_data = data_out_reg1;
+assign weight_in = (wdata_flag & MM_in_data_valid) ? MM_in_data : 0;
+assign feature_in = ((~wdata_flag) & MM_in_data_valid)? MM_in_data : 0;
+assign set_w = (weight_buffer_cnt==array_m) ? 1:0;
+assign x_packed = feature_in_reg1;
+assign MM_out_data_valid = MM_out_data_valid_reg_array[2*array_m];
+assign MM_out_last = MM_out_last_reg_array[2*array_m];
+
+
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        weight_buffer_cnt <= 0;
+    else if(weight_buffer_cnt == array_m)
+        weight_buffer_cnt<=0;
+    else if (wdata_flag & MM_in_data_valid)
+        weight_buffer_cnt<=weight_buffer_cnt+1;
+    else 
+        weight_buffer_cnt<=weight_buffer_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        wdata_flag<=0;
+    else 
+        case ({wdata_flag_up,MM_in_last})
+            2'b10 :  wdata_flag <= 1;
+            2'b01 :  wdata_flag <= 0;
+            default :  wdata_flag <= wdata_flag;
+        endcase
+end
+
+always @(posedge clk)begin
+    data_out_reg1 <= data_out;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        feature_in_reg1 <= 0;
+    else
+        feature_in_reg1 <= feature_in;
+end
+
+//always @(posedge clk or negedge rst_n) begin
+//    if(~rst_n)
+//        weight_ready <= 0;
+//    else if (wdata_flag & MM_in_data_valid)
+//        weight_ready <= 0;
+//    else if (weight_buffer_cnt == array_m - 1)
+//        weight_ready <= 1;
+//    else
+//        weight_ready <= weight_ready;
+//end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        weight_buffer[0]<=0;
+    else if(wdata_flag & MM_in_data_valid)
+        weight_buffer[0]<=weight_in;
+    else
+        weight_buffer[0]<=weight_buffer[0];
+end
+
+integer j;
+always @(posedge clk or negedge rst_n) begin
+    for(j=1;j<array_m;j=j+1)begin
+        if(~rst_n)
+            weight_buffer[j]<=0;
+        else if (wdata_flag & MM_in_data_valid)
+            weight_buffer[j]<=weight_buffer[j-1];
+        else
+            weight_buffer[j]<=weight_buffer[j];
+    end
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        MM_out_data_valid_reg_array[0]<=0;
+    else
+        MM_out_data_valid_reg_array[0]<=MM_in_data_valid & (~wdata_flag);
+end
+generate
+    for(i=1;i<=array_m*2;i=i+1)begin
+        always @(posedge clk or negedge rst_n) begin
+            if(~rst_n)
+                MM_out_data_valid_reg_array[i]<=0;
+            else
+                MM_out_data_valid_reg_array[i]<=MM_out_data_valid_reg_array[i-1];
+        end
+    end
+endgenerate
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        MM_out_last_reg_array[0]<=0;
+    else
+        MM_out_last_reg_array[0]<=MM_in_last & (~wdata_flag);
+end
+
+generate
+    for(i=1;i<=array_m*2;i=i+1) begin
+        always @(posedge clk or negedge rst_n) begin
+            if(~rst_n)
+                MM_out_last_reg_array[i]<=0;
+            else
+                MM_out_last_reg_array[i]<=MM_out_last_reg_array[i-1];
+        end
+    end
+endgenerate
+
+PE_array#
+(
+    .data_width(data_width),
+    .array_m(array_m),
+    .array_n(array_n),
+    .log2_array_m(log2_array_m)
+)
+u_PE_array
+(
+    .clk(clk),
+    .rst_n(rst_n),
+    .set_w(set_w),
+    .x_packed(x_packed),
+    .w_packed(w_packed),
+    .PE_out_packed(PE_out_packed)
+);
+
+// generate
+//     for(i=0;i<array_n;i=i+1)begin:right_shifter_u
+//         right_shifter 
+//         #(
+//             .data_width(data_width),
+//             .array_m(array_m),
+//             .array_n(array_n),
+//             .log2_array_m(log2_array_m),
+//             .shift_width(shift_width)
+//         )u_right_shifter(
+//             .shift(shift),
+//             .data_in(PE_out_packed[i*(log2_array_m+data_width*2)+:(log2_array_m+data_width*2)]),
+//             .data_out(data_out[i*data_width+:data_width])
+//         );
+//     end
+// endgenerate
+
+assign data_out = PE_out_packed;
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_buffer.v

@@ -0,0 +1,359 @@
+`timescale 1ns / 1ps
+`define IDLE 2'b00
+`define SET_WEIGHT 2'b01
+`define SET_FEATURE 2'b11
+
+module MM_buffer#
+(
+    parameter integer                                  array_m = 3,
+    parameter integer                                  array_n = 3,
+    parameter integer                                  data_width = 8,
+    parameter integer                                  log2_array_m = 4,
+    parameter integer                                  F_length_width = 10,
+    parameter integer                                  W_width_block_num_width = 5 
+)(
+    input                                                   clk,
+    input                                                   rst_n,
+
+
+    input [F_length_width-1:0]                              FL, 
+    input [W_width_block_num_width-1:0]                     num_blobk_W, 
+
+
+    input [array_m * data_width - 1:0]                      MM_buffer_inWeight_data,
+    input                                                   MM_buffer_inWeight_valid,
+    output                                                  MM_buffer_inWeight_ready,
+    input                                                   MM_buffer_inWeight_last,
+
+    input [array_m * data_width - 1:0]                      MM_buffer_inFeature_data,
+    input                                                   MM_buffer_inFeature_valid,
+    output                                                  MM_buffer_inFeature_ready,
+    input                                                   MM_buffer_inFeature_last,
+
+    output [array_n*(log2_array_m+data_width*2)-1:0]        MM_buffer_out_data,
+    output                                                  MM_buffer_out_valid,
+    output                                                  MM_buffer_out_last
+);
+localparam integer feature_buffer_depth = $pow(2, F_length_width);
+localparam integer W_block_num_width = W_width_block_num_width + log2_array_m;
+localparam integer weight_buffer_depth = $pow(2, W_width_block_num_width) * array_m;
+
+
+reg [1:0]                                                   state;
+
+
+reg                                                         start;
+wire                                                        start_ahead1;
+reg                                                         set_w_delay1;
+reg                                                         w_end;
+reg                                                         weight_flag_up;
+
+reg [W_block_num_width-1:0]                                 total_WL_reg;
+reg [F_length_width-1:0]                                    FL_reg;
+
+reg [W_block_num_width-1:0]                                 weight_buffer_cnt;
+reg [W_block_num_width-1:0]                                 weight_buffer_in_addr;
+reg [array_m * data_width - 1:0]                            weight_buffer [weight_buffer_depth-1:0];
+
+reg [F_length_width-1:0]                                    feature_buffer_cnt;
+reg [F_length_width-1:0]                                    feature_buffer_in_addr;
+reg [array_m * data_width - 1:0]                            feature_buffer [feature_buffer_depth-1:0];
+
+wire                                                        both_full;
+reg                                                         both_full_delay1;
+
+reg [array_m * data_width - 1:0]                            MM_in_data;
+reg                                                         MM_in_data_valid;
+reg                                                         MM_in_last;
+
+reg                                                         input_weight_valid;
+wire                                                        input_weight_last;
+reg [array_m * data_width - 1:0]                            input_weight_data;
+wire [W_block_num_width-1:0]                                input_weight_addr;
+reg [W_width_block_num_width-1:0]                           input_weight_col;
+reg [log2_array_m-1:0]                                      input_weight_row;
+reg [W_block_num_width-1:0]                                 weight_cnt;                                
+
+reg                                                         input_feature_valid;
+wire                                                        input_feature_last;
+reg [array_m * data_width - 1:0]                            input_feature_data;
+reg [F_length_width-1:0]                                    input_feature_addr;
+reg [F_length_width-1:0]                                    feature_cnt;
+
+wire                                                        set_w;
+wire                                                        total_last;
+wire                                                        wdata_flag_up;
+
+wire [array_n*(log2_array_m+data_width*2)-1:0]              output_feature_data;
+wire                                                        output_feature_valid;
+wire                                                        output_feature_last;
+
+
+assign both_full = (weight_buffer_cnt == total_WL_reg) & (feature_buffer_cnt == FL_reg);
+assign MM_buffer_out_valid = output_feature_valid;
+assign MM_buffer_out_data = output_feature_data;
+assign MM_buffer_out_last = total_last;
+assign total_last = output_feature_last & w_end;
+assign MM_buffer_inWeight_ready = (weight_buffer_cnt<=total_WL_reg-1);
+assign MM_buffer_inFeature_ready = (feature_buffer_cnt<=FL_reg-1);
+// assign wdata_flag_up = start | weight_flag_up;
+assign wdata_flag_up = start | weight_flag_up & (state != 0);
+assign input_weight_last = weight_cnt == array_m - 1;
+assign input_feature_last = feature_cnt == FL_reg - 1;
+assign input_weight_addr = input_weight_row * num_blobk_W + input_weight_col;
+assign start_ahead1 = both_full & (~both_full_delay1);
+
+
+always @(*) begin
+    case (state)
+        `IDLE : begin
+            MM_in_data_valid = 0;
+            MM_in_last = 0;
+            MM_in_data = 0;
+        end 
+        `SET_WEIGHT : begin
+            MM_in_data_valid = input_weight_valid;
+            MM_in_last = input_weight_last;
+            MM_in_data = input_weight_data;
+        end
+        `SET_FEATURE: begin
+            MM_in_data_valid = input_feature_valid;
+            MM_in_last = input_feature_last;
+            MM_in_data = input_feature_data;
+        end
+        default: begin
+            MM_in_data_valid = 0;
+            MM_in_last = 0;
+            MM_in_data = 0;
+        end
+    endcase
+end
+
+initial both_full_delay1 =0;
+always @(posedge clk ) begin
+    both_full_delay1 <= both_full;
+end
+
+initial start = 0;
+always @(posedge clk ) begin
+    start <= start_ahead1;
+end
+initial set_w_delay1= 0;
+always @(posedge clk ) begin
+    set_w_delay1 <= set_w;
+end
+initial total_WL_reg= 0;
+always @(posedge clk ) begin
+    total_WL_reg <= num_blobk_W * array_m;
+end
+initial FL_reg= 0;
+always @(posedge clk ) begin
+    FL_reg <= FL;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        weight_buffer_cnt <= 0;
+    else if ( MM_buffer_inWeight_valid & MM_buffer_inWeight_ready)
+        weight_buffer_cnt <= weight_buffer_cnt + 1;
+    else if (total_last)
+        weight_buffer_cnt <= 0;
+    else
+        weight_buffer_cnt <= weight_buffer_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        feature_buffer_cnt <= 0;
+    else if ( MM_buffer_inFeature_valid & MM_buffer_inFeature_ready)
+        feature_buffer_cnt <= feature_buffer_cnt + 1;
+    else if (total_last)
+        feature_buffer_cnt <= 0;
+    else
+        feature_buffer_cnt <= feature_buffer_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        w_end <= 1;
+    else if(start)
+        w_end <= 0;
+    else if (input_weight_addr == total_WL_reg -1)
+        w_end <= 1;
+    else 
+        w_end <= w_end;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        weight_buffer_in_addr <= 0;
+    else if ( MM_buffer_inWeight_last)
+        weight_buffer_in_addr <= 0;
+    else if ( MM_buffer_inWeight_valid & MM_buffer_inWeight_ready)
+        weight_buffer_in_addr <= weight_buffer_in_addr + 1;
+    else 
+        weight_buffer_in_addr <= weight_buffer_in_addr;
+end
+
+always @(posedge clk ) begin
+    if( MM_buffer_inWeight_valid & MM_buffer_inWeight_ready)
+        weight_buffer[weight_buffer_in_addr] <= MM_buffer_inWeight_data;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        feature_buffer_in_addr <= 0;
+    else if ( MM_buffer_inFeature_last)
+        feature_buffer_in_addr <= 0;
+    else if ( MM_buffer_inFeature_valid & MM_buffer_inFeature_ready)
+        feature_buffer_in_addr <= feature_buffer_in_addr + 1;
+    else 
+        feature_buffer_in_addr <= feature_buffer_in_addr;
+end
+
+always @(posedge clk ) begin
+    if( MM_buffer_inFeature_valid & MM_buffer_inFeature_ready)
+        feature_buffer[feature_buffer_in_addr] <= MM_buffer_inFeature_data;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        state <= `IDLE;
+    else if (state == `IDLE) begin //only start can wake up state
+        if (start)
+            state <= `SET_WEIGHT;
+        else
+            state <= state;
+    end
+    else begin
+        case ({weight_flag_up, set_w_delay1,total_last})
+            3'b100: state <= `SET_WEIGHT;
+            3'b010: state <= `SET_FEATURE;
+            3'b001: state <= `IDLE;
+            default: state <= state;
+        endcase
+    end
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if (~rst_n)
+        weight_flag_up <= 0;
+    else if(weight_flag_up)
+        weight_flag_up <= 0;
+    else if (output_feature_last)
+        weight_flag_up <= 1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        input_weight_valid <= 0;
+    else if(wdata_flag_up)
+        input_weight_valid <= 1;
+    else if(input_weight_last)
+        input_weight_valid <= 0;
+    else
+        input_weight_valid <= input_weight_valid;
+end
+
+always @(posedge clk ) begin
+    input_weight_data <= weight_buffer[input_weight_addr];
+end
+
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        weight_cnt <= 0;
+    else if (weight_cnt == array_m)
+        weight_cnt <= 0;
+    else if (state == `SET_WEIGHT & input_weight_valid)
+        weight_cnt <= weight_cnt + 1;
+    else
+        weight_cnt <= weight_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        input_feature_valid <= 0;
+    else if (set_w_delay1)
+        input_feature_valid <= 1;
+    else if (input_feature_last)
+        input_feature_valid <= 0;
+    else 
+        input_feature_valid <= input_feature_valid;
+end
+
+always @(posedge clk ) begin
+    input_feature_data <= feature_buffer[input_feature_addr];
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        input_feature_addr <= 0;
+    else if (input_feature_addr == FL_reg - 1)
+        input_feature_addr <= 0;
+    else if (set_w_delay1)
+        input_feature_addr <= 1;
+    else if (state == `SET_FEATURE & input_feature_valid & input_feature_addr!=0)//make sure that only set_w_dealy1 can pull up the addr when it equal to zero 
+        input_feature_addr <= input_feature_addr + 1;
+    else
+        input_feature_addr <= input_feature_addr;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        feature_cnt <= 0;
+    else if(feature_cnt == FL_reg)
+        feature_cnt <= 0;
+    else if(state == `SET_FEATURE & input_feature_valid)
+        feature_cnt <= feature_cnt + 1;
+    else 
+        feature_cnt <= feature_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        input_weight_col <= 0;
+    else if(input_weight_col == num_blobk_W)
+        input_weight_col <= 0;
+    else if(input_weight_last)
+        input_weight_col <= input_weight_col + 1;
+    else
+        input_weight_col <= input_weight_col;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        input_weight_row <= 0;
+    else if (input_weight_row == array_m - 1)
+        input_weight_row <= 0;
+    else if (wdata_flag_up)
+        input_weight_row <= 1;
+    else if (input_weight_row != 0)
+        input_weight_row <= input_weight_row + 1;
+end
+
+MM
+#(
+    .array_m(array_m), //Array 行数
+    .array_n(array_n), //Array 列数
+    .data_width(data_width), //数据宽度
+    .log2_array_m(log2_array_m)
+) u_MM
+(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .set_w_port(set_w),
+
+    .wdata_flag_up(wdata_flag_up), 
+
+    .MM_in_data(MM_in_data),
+    .MM_in_data_valid(MM_in_data_valid),
+    .MM_in_last(MM_in_last),
+
+    .MM_out_data(output_feature_data),
+    .MM_out_data_valid(output_feature_valid),
+    .MM_out_last(output_feature_last)
+);
+    
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_in_buffer.v

@@ -0,0 +1,268 @@
+`timescale 1ns / 1ps
+`define IDLE 2'b00
+`define IN_DATA 2'b01
+`define CAL 2'b11
+// reg [A_size * data_width - 1:0] in_F_array [Feature_Width_Block_num * Feature_Length : 0];
+// reg [A_size * data_width - 1:0] in_W_array [A_size * Weight_Width_Block_num * Feature_Width_Block_num : 0];
+module MM_in_buffer
+#(
+    parameter integer                               A_size = 24,
+    parameter integer                               data_width = 8,
+    parameter integer                               Weight_Block_num = 2400, 
+    parameter integer                               IN_Feature_Block_num = 2400,
+    parameter integer                               F_length_width = 10,
+    parameter integer                               F_width_block_num_width = 5,
+    parameter integer                               W_width_block_num_width = 5
+)(
+    input                                           clk,
+    input                                           rst_n,
+    
+    input [W_width_block_num_width-1:0]             W_width_block_num, //1 ~ block_num
+
+
+    input [F_width_block_num_width-1:0]             F_width_block_num, //1 ~ block_num
+    input [F_length_width-1:0]                      F_length, //1 ~ block_num *A_size
+
+    input                                           MM_buffer_out_last,
+
+    input                                           in_F_valid,
+    input                                           in_F_last,
+    output                                          in_F_ready,
+    input [A_size * data_width - 1:0]               in_F_data,
+
+    input                                           in_W_valid,
+    input                                           in_W_last,
+    output                                          in_W_ready,
+    input [A_size * data_width - 1:0]               in_W_data,
+
+    output reg                                      in_MM_buffer_F_valid,
+    output                                          in_MM_buffer_F_last,
+    input                                           in_MM_buffer_F_ready,
+    output reg [A_size * data_width - 1:0]          in_MM_buffer_F_data,
+
+    output reg                                      in_MM_buffer_W_valid,
+    output                                          in_MM_buffer_W_last,
+    input                                           in_MM_buffer_W_ready,
+    output reg [A_size * data_width - 1:0]          in_MM_buffer_W_data
+
+);
+function integer clogb2 (input integer bit_depth);              
+begin:log
+    automatic integer temp;
+    temp = 0;                                                        
+    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)begin
+        if(bit_depth[0] & bit_depth!=1)
+            temp = 1;                   
+        bit_depth = bit_depth >> 1;
+    end
+    clogb2 = clogb2 + temp - 1;                                   
+end                                                   
+endfunction
+
+localparam integer F_size_width = clogb2(IN_Feature_Block_num);
+localparam integer W_size_width = clogb2(Weight_Block_num);
+localparam integer log_A_size = clogb2(A_size);
+wire start;
+
+reg [A_size * data_width - 1:0] in_F_array [IN_Feature_Block_num - 1 : 0];
+reg [A_size * data_width - 1:0] in_W_array [Weight_Block_num - 1 : 0];
+ 
+reg [1:0]                                    state;
+reg [W_size_width-1:0]                       W_block_size;
+reg [F_size_width-1:0]                       F_block_size; 
+
+reg [F_size_width-1:0]                       in_F_cnt;
+reg [F_size_width-1:0]                       in_F_addr;
+
+reg [W_size_width-1:0]                       in_W_cnt;
+reg [W_size_width-1:0]                       in_W_addr;
+
+reg [F_size_width-1:0]                       in_MM_buffer_F_cnt;
+reg [F_length_width-1:0]                     out_F_row_addr;
+reg [F_width_block_num_width-1:0]            out_F_col_addr;
+wire [F_size_width-1:0]                      out_F_addr;
+
+reg [W_size_width-1:0]                       in_MM_buffer_W_cnt;
+reg [W_size_width-1:0]                       out_W_addr;
+
+
+assign in_F_ready = (in_F_cnt < F_block_size) & (state != `CAL);
+assign in_W_ready = (in_W_cnt < W_block_size) & (state != `CAL);
+assign out_F_addr = out_F_row_addr * F_width_block_num + out_F_col_addr;
+assign start = ((in_F_cnt == F_block_size & in_W_cnt == W_block_size) 
+                | MM_buffer_out_last)
+                & (out_F_col_addr!=F_width_block_num);
+assign in_MM_buffer_F_last = in_MM_buffer_F_cnt == F_length - 1;
+assign in_MM_buffer_W_last = in_MM_buffer_W_cnt == W_width_block_num * A_size - 1; 
+
+initial F_block_size=0;
+always @(posedge clk ) begin
+    F_block_size <= F_length * F_width_block_num;
+end
+
+reg [log_A_size + F_width_block_num_width-1:0] temp_m;
+initial temp_m = 0;
+initial W_block_size=0;
+always @(posedge clk ) begin
+    temp_m <= F_width_block_num *A_size;
+    W_block_size <= W_width_block_num * temp_m;
+end
+
+always @(posedge clk ) begin
+    if(in_F_valid & in_F_ready)
+        in_F_array[in_F_addr] <= in_F_data;
+end
+
+always @(posedge clk ) begin
+    if(in_W_valid & in_W_ready)
+        in_W_array[in_W_addr] <= in_W_data;
+end
+
+always @(posedge clk) begin
+    in_MM_buffer_F_data <= in_F_array[out_F_addr];
+end
+
+
+always @(posedge clk) begin
+    in_MM_buffer_W_data <= in_W_array[out_W_addr];
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        state <= `IDLE;
+    else if (state == `IDLE & (in_F_valid | in_W_valid))
+        state <= `IN_DATA;
+    else if (state == `IN_DATA & start)
+        state <= `CAL;
+    else if (state == `CAL & MM_buffer_out_last 
+            & ( out_F_col_addr == F_width_block_num))
+        state <= `IDLE;
+    else
+        state <= state;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_F_cnt<=0;
+    else if (start)
+        in_F_cnt <= 0;
+    else if (in_F_valid & in_F_ready)
+        in_F_cnt <= in_F_cnt + 1;
+    else
+        in_F_cnt <= in_F_cnt;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_F_addr<=0;
+    else if (in_F_last)
+        in_F_addr <= 0;
+    else if (in_F_valid & in_F_ready)
+        in_F_addr <= in_F_addr + 1;
+    else
+        in_F_addr <= in_F_addr;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_W_cnt<=0;
+    else if (start)
+        in_W_cnt <= 0;
+    else if (in_W_valid & in_W_ready)
+        in_W_cnt <= in_W_cnt + 1;
+    else
+        in_W_cnt <= in_W_cnt;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_W_addr<=0;
+    else if (in_W_last)
+        in_W_addr <= 0;
+    else if (in_W_valid & in_W_ready)
+        in_W_addr <= in_W_addr + 1;
+    else
+        in_W_addr <= in_W_addr;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_MM_buffer_F_valid <= 0;
+    else if(start)
+        in_MM_buffer_F_valid <= 1;
+    else if (in_MM_buffer_F_last)
+        in_MM_buffer_F_valid <= 0;
+    else 
+        in_MM_buffer_F_valid<=in_MM_buffer_F_valid;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_MM_buffer_F_cnt<=0;
+    else if (in_MM_buffer_F_cnt == F_length)
+        in_MM_buffer_F_cnt<=0;
+    else if (in_MM_buffer_F_valid & in_MM_buffer_F_ready)
+        in_MM_buffer_F_cnt<=in_MM_buffer_F_cnt+1;
+    else
+        in_MM_buffer_F_cnt <= in_MM_buffer_F_cnt;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        out_F_row_addr <= 0;
+    else if (start)
+        out_F_row_addr <= 1;
+    else if (out_F_row_addr == F_length - 1)
+        out_F_row_addr <= 0;
+    else if (out_F_row_addr != 0 & in_MM_buffer_F_valid & in_MM_buffer_F_ready)
+        out_F_row_addr <= out_F_row_addr + 1;
+    else
+        out_F_row_addr <= out_F_row_addr;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+       out_F_col_addr <= 0;
+    else if (MM_buffer_out_last & out_F_col_addr == F_width_block_num)
+        out_F_col_addr <= 0; 
+    else if(in_MM_buffer_F_last)
+        out_F_col_addr <= out_F_col_addr + 1;
+    else
+        out_F_col_addr <= out_F_col_addr;
+end
+
+always @(posedge clk  or negedge rst_n) begin
+    if(~rst_n)
+        in_MM_buffer_W_valid <= 0;
+    else if(start)
+        in_MM_buffer_W_valid <= 1;
+    else if (in_MM_buffer_W_last)
+        in_MM_buffer_W_valid <= 0;
+    else 
+        in_MM_buffer_W_valid<=in_MM_buffer_W_valid;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        in_MM_buffer_W_cnt <= 0;
+    else if (in_MM_buffer_W_cnt == W_width_block_num * A_size)
+        in_MM_buffer_W_cnt <= 0;
+    else if (in_MM_buffer_W_valid & in_MM_buffer_W_ready)
+        in_MM_buffer_W_cnt<=in_MM_buffer_W_cnt+1;
+    else
+        in_MM_buffer_W_cnt<=in_MM_buffer_W_cnt;
+end
+
+always @(posedge clk or negedge rst_n ) begin
+    if(~rst_n)
+        out_W_addr <= 0;
+    else if (out_W_addr== W_block_size -1)
+        out_W_addr <= 0;
+    else if ((start 
+            | (in_MM_buffer_W_valid & in_MM_buffer_W_ready))
+            & (~in_MM_buffer_W_last))
+        out_W_addr<=out_W_addr+1;
+    else
+        out_W_addr<=out_W_addr;
+end
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_out_buffer.v

@@ -0,0 +1,331 @@
+`timescale 1ns / 1ps
+
+module MM_out_buffer
+#(              
+    parameter integer                                        data_width = 8,
+    parameter integer                                        OUT_Feature_Block_num = 2400,
+    parameter integer                                        OUT_MEM_WIDTH = 32,
+    parameter integer                                        A_size =  2,
+    parameter integer                                        shift_width = 20,
+    parameter integer                                        log2_array_m = 4,
+    parameter integer                                        F_length_width = 10,
+    parameter integer                                        F_width_block_num_width = 5,
+    parameter integer                                        W_width_block_num_width = 5
+)(
+    input                                                    clk,
+    input                                                    rst_n,
+        
+    input [shift_width - 1:0]                                shift,
+    input [F_length_width-1:0]                               F_length, //1 ~ block_num *A_size
+    input [F_width_block_num_width-1:0]                      F_width_block_num, //1 ~ block_num
+    input [W_width_block_num_width-1:0]                      W_width_block_num, //1 ~ block_num
+            
+    input                                                    in_data_valid,
+    input                                                    in_data_last,
+    input [A_size*(log2_array_m+data_width*2)-1:0]           in_data,
+
+    output reg                                               out_data_valid,
+    output                                                   out_data_last,
+    input                                                    out_data_ready,
+    output reg [A_size * data_width -1:0]                    out_data
+);
+
+function integer clogb2 (input integer bit_depth);              
+begin:log
+    automatic integer temp;
+    temp = 0;                                                        
+    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)begin
+        if(bit_depth[0] & bit_depth!=1)
+            temp = 1;                   
+        bit_depth = bit_depth >> 1;
+    end
+    clogb2 = clogb2 + temp - 1;                                   
+end                                                   
+endfunction
+localparam integer F_size_width = clogb2(OUT_Feature_Block_num);
+
+(*ram_style="block"*) reg  [A_size*OUT_MEM_WIDTH-1:0]                  F_array [OUT_Feature_Block_num-1 : 0];
+
+reg  [F_size_width-1:0]                                                  out_F_block_size;
+reg  [F_size_width-1:0]                                                  B_addr;
+reg  [F_size_width-1:0]                                                  C_addr;
+wire [A_size*(log2_array_m+data_width*2)-1:0]                            A;
+wire [A_size*OUT_MEM_WIDTH-1:0]                                          A_in_adder; //bit width extension
+wire [A_size*OUT_MEM_WIDTH-1:0]                                          B;
+wire [A_size*OUT_MEM_WIDTH-1:0]                                          C;
+reg  [F_width_block_num_width-1:0]                                       last_cnt;
+
+reg                                                                      start_trans;                   
+
+reg                                                                      F_array_out_valid;
+reg                                                                      F_array_out_valid_delay1;
+reg                                                                      F_array_out_valid_delay2;
+wire                                                                     F_array_out_last_delay2;
+reg  [F_size_width-1:0]                                                  F_array_out_cnt;
+reg  [F_size_width-1:0]                                                  F_array_out_cnt_delay1;
+
+
+wire [A_size*OUT_MEM_WIDTH-1:0]                                          out_F_data;
+reg  [A_size*OUT_MEM_WIDTH-1:0]                                          out_F_data_delay1;
+wire [A_size * data_width -1:0]                                          shifted_data;
+reg  [F_size_width-1:0]                                                  out_data_cnt;
+
+reg  [F_size_width-1:0]                                                  in_F_array_addr;
+reg  [A_size*OUT_MEM_WIDTH-1:0]                                          in_F_array_data;
+
+reg  [W_width_block_num_width-1:0]                                       out_data_col_addr;
+reg  [F_length_width-1:0]                                                out_data_row_addr;
+wire [F_size_width-1:0]                                                  out_data_addr;
+reg  [F_size_width-1:0]                                                  clear_addr;
+
+wire [F_size_width-1:0]                                                  out_F_array_addr;
+reg  [A_size*OUT_MEM_WIDTH-1:0]                                          out_F_array_data;
+
+
+assign A = in_data;
+// assign start_trans = last_cnt == F_width_block_num;
+assign F_array_out_last_delay2 = F_array_out_cnt_delay1 == out_F_block_size;
+assign out_data_addr = out_data_col_addr * F_length + out_data_row_addr;
+assign out_data_last = (out_data_cnt == out_F_block_size-1) & out_data_ready;
+
+genvar i;
+generate
+    for(i=0; i<OUT_Feature_Block_num; i=i+1 )begin
+        initial begin F_array[i]<=0;end
+    end
+endgenerate
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        start_trans <= 0;
+    else if (F_array_out_valid)
+        start_trans <= 0;
+    else if (last_cnt == F_width_block_num)
+        start_trans <= 1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        F_array_out_valid <= 0;
+    else if(start_trans & out_data_ready)
+        F_array_out_valid <= 1;
+    else if(F_array_out_cnt == out_F_block_size - 1 & (F_array_out_valid&out_data_ready))
+        F_array_out_valid <= 0;
+    else 
+        F_array_out_valid <= F_array_out_valid;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        F_array_out_valid_delay1 <= 0;
+    else if (F_array_out_cnt_delay1 ==out_F_block_size-1 &(F_array_out_valid_delay1&out_data_ready))
+        F_array_out_valid_delay1<=0;
+    else if (F_array_out_valid & out_data_ready)
+        F_array_out_valid_delay1 <= 1;
+    else
+        F_array_out_valid_delay1<=F_array_out_valid_delay1;
+end
+
+initial F_array_out_valid_delay2 =0;
+always @(posedge clk ) begin
+    if(out_data_ready)
+        F_array_out_valid_delay2<=F_array_out_valid_delay1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        F_array_out_cnt <= 0;
+    else if (F_array_out_cnt == out_F_block_size)
+        F_array_out_cnt <= 0;
+    else if (F_array_out_valid & out_data_ready)
+        F_array_out_cnt <= F_array_out_cnt + 1;
+    else
+        F_array_out_cnt <= F_array_out_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        out_data_cnt <= 0;
+    else if (out_data_cnt == out_F_block_size)
+        out_data_cnt <= 0;
+    else if (out_data_valid & out_data_ready)
+        out_data_cnt <= out_data_cnt + 1;
+    else
+        out_data_cnt <= out_data_cnt;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        F_array_out_cnt_delay1 <= 0;
+    else if (F_array_out_cnt_delay1 == out_F_block_size)
+        F_array_out_cnt_delay1 <= 0;
+    else if (F_array_out_valid_delay1 & out_data_ready)
+        F_array_out_cnt_delay1 <= F_array_out_cnt_delay1 + 1;
+    else
+        F_array_out_cnt_delay1 <= F_array_out_cnt_delay1;
+end
+
+always @(posedge clk ) begin
+    if(F_array_out_valid_delay1 & out_data_ready)
+        out_F_data_delay1 <= out_F_data;
+    else 
+        out_F_data_delay1 <= out_F_data_delay1;
+end
+
+
+always @(posedge clk ) begin
+    if(F_array_out_valid_delay2 & out_data_ready)
+        out_data <= shifted_data;
+    else
+        out_data <= out_data;
+end
+
+initial out_data_valid = 0;
+always @(posedge clk ) begin
+    if(out_data_ready)
+        out_data_valid <= F_array_out_valid_delay2;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        out_data_col_addr <= 0;
+    else if (F_array_out_last_delay2)
+        out_data_col_addr <= 0;
+    else if (out_data_col_addr == W_width_block_num-1 & out_data_row_addr == F_length - 1 )
+        out_data_col_addr <= out_data_col_addr;
+    else if (out_data_col_addr == W_width_block_num-1 & (F_array_out_valid & out_data_ready))
+        out_data_col_addr <= 0;
+    else if (F_array_out_valid & out_data_ready)
+        out_data_col_addr <= out_data_col_addr+1;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        out_data_row_addr <= 0;
+    else if (F_array_out_last_delay2)
+        out_data_row_addr <= 0;
+    else if (out_data_row_addr == F_length - 1)
+        out_data_row_addr<=out_data_row_addr;
+    else if ((F_array_out_valid & out_data_ready)&
+             ((out_data_col_addr == W_width_block_num-1 ) | ( W_width_block_num == 1 ))
+             )
+        out_data_row_addr <= out_data_row_addr + 1;
+    else
+        out_data_row_addr <= out_data_row_addr;
+end
+
+always @(*) begin
+    if(in_data_valid)
+        B_addr = C_addr + 1;
+    else 
+        B_addr = C_addr;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        clear_addr <= 0;
+    // else if (out_data_last)
+    //     clear_addr <= 0;
+    else if (F_array_out_last_delay2)
+        clear_addr <= out_F_block_size - 1;
+    // else if (out_data_addr == out_F_block_size - 1)
+    else if(out_data_col_addr == W_width_block_num-1 & out_data_row_addr == F_length - 1)
+        clear_addr <= clear_addr;
+    else if (F_array_out_valid & out_data_ready)
+        clear_addr <= out_data_addr;
+end
+
+always @(*) begin
+    case (in_data_valid)
+        1'b1: in_F_array_addr = C_addr;
+        1'b0: in_F_array_addr = clear_addr; 
+        default: in_F_array_addr = 0;
+    endcase
+end
+
+always @(posedge clk ) begin  //write port
+    if(in_data_valid)
+        F_array[in_F_array_addr] <= in_F_array_data;
+    else if (F_array_out_valid_delay1 | out_data_valid & out_data_ready)
+        F_array[in_F_array_addr] <=in_F_array_data;
+end
+
+always @(*) begin
+    if(in_data_valid)
+        in_F_array_data = C;
+    else
+        in_F_array_data = 0;
+end
+
+assign out_F_array_addr = (F_array_out_valid_delay2 | F_array_out_valid)? out_data_addr : B_addr;
+
+always @(posedge clk) begin //read port
+    if (F_array_out_valid & ~out_data_ready)
+        out_F_array_data <= out_F_array_data;
+    else
+        out_F_array_data<=F_array[out_F_array_addr];
+end
+                            
+assign B = out_F_array_data;
+assign out_F_data = out_F_array_data;
+
+initial out_F_block_size =0;
+always @(posedge clk ) begin
+    out_F_block_size <= F_length * W_width_block_num;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        C_addr <= 0;
+    else if (in_data_last)
+        C_addr <= 0;
+    else if(in_data_valid)
+        C_addr <= C_addr + 1;
+    else
+        C_addr <= C_addr;
+end
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)
+        last_cnt <= 0;
+    else if (last_cnt == F_width_block_num)
+        last_cnt <= 0;
+    else if (in_data_last)
+        last_cnt <= last_cnt + 1;
+    else 
+        last_cnt <= last_cnt;
+end
+
+
+AdderS 
+#(
+    .data_width(OUT_MEM_WIDTH),
+    .A_size(A_size)
+)U_Adders 
+(
+    .A(A_in_adder),
+    .B(B),
+    .C(C)
+);
+
+generate
+    for(i=0;i<A_size;i=i+1)begin
+        assign A_in_adder[i*OUT_MEM_WIDTH +: OUT_MEM_WIDTH] = $signed(A[i*(log2_array_m+data_width*2) +: (log2_array_m+data_width*2)]);
+    end
+endgenerate
+
+generate
+    for(i=0;i<A_size;i=i+1)begin:right_shifter_u
+        right_shifter 
+        #(
+            .before_data_width(OUT_MEM_WIDTH),
+            .after_data_width(data_width),
+            .shift_width(shift_width)
+        )u_right_shifter(
+            .shift(shift),
+            .data_in(out_F_data_delay1[i*OUT_MEM_WIDTH +: OUT_MEM_WIDTH]),
+            .data_out(shifted_data[i*data_width+:data_width])
+        );
+    end
+endgenerate
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_ultra.v

@@ -0,0 +1,221 @@
+`timescale 1ns / 1ps
+
+
+module MM_ultra
+#(
+    parameter integer                                       A_size = 16,
+    parameter integer                                       data_width = 8,
+    parameter integer                                       shift_width = 10,
+    parameter integer                                       Weight_Block_num = 2400, 
+    parameter integer                                       IN_Feature_Block_num = 2400, 
+    parameter integer                                       OUT_Feature_Block_num = 2400,
+    parameter integer                                       OUT_MEM_WIDTH = 32,
+    parameter integer                                       F_length_width = 9,
+    parameter integer                                       F_width_block_num_width = 5,
+    parameter integer                                       W_width_block_num_width = 5
+)(
+    input                                                   clk,
+    input                                                   rst_n,
+
+
+    input [shift_width-1:0]                                 shift_in,
+    input [F_length_width-1:0]                              F_length_in, 
+    input [F_width_block_num_width-1:0]                     F_width_block_num_in,
+    input [W_width_block_num_width-1:0]                     W_width_block_num_in, 
+
+
+    input                                                   in_F_valid,
+    input                                                   in_F_last,
+    output                                                  in_F_ready,
+    input [A_size * data_width - 1:0]                       in_F_data,
+
+    input                                                   in_W_valid,
+    input                                                   in_W_last,
+    output                                                  in_W_ready,
+    input [A_size * data_width - 1:0]                       in_W_data,
+
+    output                                                  out_data_valid,
+    input                                                   out_data_ready,
+    output                                                  out_data_last,
+    output [A_size * data_width -1:0]                       out_data
+
+);
+function integer clogb2 (input integer bit_depth);              
+begin:log
+    automatic integer temp;
+    temp = 0;                                                        
+    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)begin
+        if(bit_depth[0] & bit_depth!=1)
+            temp = 1;                   
+        bit_depth = bit_depth >> 1;
+    end
+    clogb2 = clogb2 + temp - 1;                                   
+end                                                   
+endfunction
+localparam integer log2_array_m = clogb2(A_size);
+
+reg [shift_width-1:0]                                 shift;
+reg [F_length_width-1:0]                              F_length; 
+reg [F_width_block_num_width-1:0]                     F_width_block_num;
+reg [W_width_block_num_width-1:0]                     W_width_block_num; 
+reg [shift_width-1:0]                                 shift_in_delay1;
+reg [F_length_width-1:0]                              F_length_in_delay1; 
+reg [F_width_block_num_width-1:0]                     F_width_block_num_in_delay1;
+reg [W_width_block_num_width-1:0]                     W_width_block_num_in_delay1; 
+
+initial begin
+    shift = {(shift_width){1'b1}};
+    F_length = {(F_length_width){1'b1}};
+    F_width_block_num = {(F_width_block_num_width){1'b1}};
+    W_width_block_num = {(W_width_block_num_width){1'b1}};
+end
+
+always @(posedge clk ) begin
+    if(shift_in_delay1 != shift_in)
+        shift <= shift_in;
+end
+
+always @(posedge clk ) begin
+    if(F_length_in_delay1 != F_length_in)
+        F_length <=F_length_in;
+end
+
+always @(posedge clk ) begin
+    if(F_width_block_num_in_delay1 != F_width_block_num_in)
+        F_width_block_num <= F_width_block_num_in;
+end
+
+always @(posedge clk ) begin
+    if(W_width_block_num_in_delay1 != W_width_block_num_in)
+        W_width_block_num <= W_width_block_num_in;
+end
+
+always @(posedge clk ) begin
+    shift_in_delay1 <= shift_in;
+    F_length_in_delay1 <= F_length_in;
+    F_width_block_num_in_delay1 <= F_width_block_num_in;
+    W_width_block_num_in_delay1 <= W_width_block_num_in;
+end
+
+
+wire [A_size*(log2_array_m+data_width*2)-1:0]               MM_buffer_out_data;
+wire                                                        MM_buffer_out_valid;
+wire                                                        MM_buffer_out_last;
+
+wire                                                        in_MM_buffer_F_valid;
+wire                                                        in_MM_buffer_F_last;
+wire                                                        in_MM_buffer_F_ready;
+wire [A_size * data_width - 1:0]                            in_MM_buffer_F_data;
+
+wire                                                        in_MM_buffer_W_valid;
+wire                                                        in_MM_buffer_W_last;
+wire                                                        in_MM_buffer_W_ready;
+wire [A_size * data_width - 1:0]                            in_MM_buffer_W_data;
+
+
+
+
+MM_in_buffer
+#(
+    .A_size(A_size),
+    .data_width(data_width),
+    .Weight_Block_num(Weight_Block_num), 
+    .IN_Feature_Block_num(IN_Feature_Block_num),
+    .F_length_width(F_length_width),
+    .F_width_block_num_width(F_width_block_num_width),
+    .W_width_block_num_width(W_width_block_num_width)
+)u_MM_in_buffer(
+    .clk(clk),
+    .rst_n(rst_n),
+    
+    .W_width_block_num(W_width_block_num), //1 ~ block_num
+    .F_width_block_num(F_width_block_num), //1 ~ block_num
+    .F_length(F_length),                   //1 ~ block_num *A_size
+
+    .MM_buffer_out_last(MM_buffer_out_last),
+
+    .in_F_valid(in_F_valid),
+    .in_F_last(in_F_last),
+    .in_F_ready(in_F_ready),
+    .in_F_data(in_F_data),
+
+    .in_W_valid(in_W_valid),
+    .in_W_last(in_W_last),
+    .in_W_ready(in_W_ready),
+    .in_W_data(in_W_data),
+
+    .in_MM_buffer_F_valid(in_MM_buffer_F_valid),
+    .in_MM_buffer_F_last(in_MM_buffer_F_last),
+    .in_MM_buffer_F_ready(in_MM_buffer_F_ready),
+    .in_MM_buffer_F_data(in_MM_buffer_F_data),
+
+    .in_MM_buffer_W_valid(in_MM_buffer_W_valid),
+    .in_MM_buffer_W_last(in_MM_buffer_W_last),
+    .in_MM_buffer_W_ready(in_MM_buffer_W_ready),
+    .in_MM_buffer_W_data(in_MM_buffer_W_data)
+
+);
+
+
+MM_buffer
+#(
+    .array_m(A_size),
+    .array_n(A_size),
+    .data_width(data_width),
+    .log2_array_m(log2_array_m),
+    .F_length_width(F_length_width),
+    .W_width_block_num_width(W_width_block_num_width)
+)u_MM_buffer(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    // .shift(shift),
+    .FL(F_length), //feature length
+    .num_blobk_W(W_width_block_num),
+
+    .MM_buffer_inWeight_data(in_MM_buffer_W_data),
+    .MM_buffer_inWeight_valid(in_MM_buffer_W_valid),
+    .MM_buffer_inWeight_ready(in_MM_buffer_W_ready),
+    .MM_buffer_inWeight_last(in_MM_buffer_W_last),
+
+    .MM_buffer_inFeature_data(in_MM_buffer_F_data),
+    .MM_buffer_inFeature_valid(in_MM_buffer_F_valid),
+    .MM_buffer_inFeature_ready(in_MM_buffer_F_ready),
+    .MM_buffer_inFeature_last(in_MM_buffer_F_last),
+
+    .MM_buffer_out_data(MM_buffer_out_data),
+    .MM_buffer_out_valid(MM_buffer_out_valid),
+    .MM_buffer_out_last(MM_buffer_out_last)
+);
+
+
+MM_out_buffer
+#(
+    .data_width(data_width),
+    .OUT_Feature_Block_num(OUT_Feature_Block_num),
+    .A_size(A_size),
+    .shift_width(shift_width),
+    .log2_array_m(log2_array_m),
+    .OUT_MEM_WIDTH(OUT_MEM_WIDTH),
+    .F_length_width(F_length_width),
+    .F_width_block_num_width(F_width_block_num_width),
+    .W_width_block_num_width(W_width_block_num_width)
+)u_MM_out_buffer(
+    .clk(clk),
+    .rst_n(rst_n),
+
+    .shift(shift),
+    .F_length(F_length), //1 ~ block_num *A_size
+    .F_width_block_num(F_width_block_num), //1 ~ block_num
+    .W_width_block_num(W_width_block_num), //1 ~ block_num
+    
+    .in_data_valid(MM_buffer_out_valid),
+    .in_data_last(MM_buffer_out_last),
+    .in_data(MM_buffer_out_data),
+
+    .out_data_valid(out_data_valid),
+    .out_data_ready(out_data_ready),
+    .out_data_last(out_data_last),
+    .out_data(out_data)
+);
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_ultra_axi.v

@@ -0,0 +1,468 @@
+
+`timescale 1 ns / 1 ps
+
+module MM_ultra_axi #
+(
+	// Users to add parameters here
+    parameter integer     array_size=24,                                      
+    parameter integer     data_width=8,                                       
+    parameter integer     shift_width=5,                                      
+    parameter integer     Weight_block_num=2500,                              
+    parameter integer     in_feature_Block_num=2500,                          
+    parameter integer     out_feature_block_num=2500,                         
+    parameter integer     out_mem_width=32,                                   
+    parameter integer     feature_length_width=10,                            
+    parameter integer     feature_width_block_num_width=5,                    
+    parameter integer     weight_width_block_num_width=5,                     
+                   
+	// User parameters ends
+	// Do not modify the parameters beyond this line
+
+	// Width of S_AXI data bus
+	parameter integer C_S_AXI_DATA_WIDTH	= 32,
+	// Width of S_AXI address bus
+	parameter integer C_S_AXI_ADDR_WIDTH	= 4
+)
+(
+	// Users to add ports here
+  input 										axis_aclk,
+	input 										aresetn,
+
+	input [array_size*data_width-1:0] 	  s0_axis_tdata,
+	input       								          s0_axis_tvalid,
+	output      								          s0_axis_tready,
+	input       								          s0_axis_tlast,
+	
+    input [array_size*data_width-1:0] 	s1_axis_tdata,
+	input       								          s1_axis_tvalid,
+	output      								          s1_axis_tready,
+	input       								          s1_axis_tlast,
+
+	output [array_size*data_width-1:0] 	  m0_axis_tdata,
+	output       								          m0_axis_tvalid,
+	input        								          m0_axis_tready,
+	output      			 					          m0_axis_tlast,
+	// User ports ends
+	// Do not modify the ports beyond this line
+
+	// Global Clock Signal
+	input wire  S_AXI_ACLK,
+	// Global Reset Signal. This Signal is Active LOW
+	input wire  S_AXI_ARESETN,
+	// Write address (issued by master, acceped by Slave)
+	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+	// Write channel Protection type. This signal indicates the
+		// privilege and security level of the transaction, and whether
+		// the transaction is a data access or an instruction access.
+	input wire [2 : 0] S_AXI_AWPROT,
+	// Write address valid. This signal indicates that the master signaling
+		// valid write address and control information.
+	input wire  S_AXI_AWVALID,
+	// Write address ready. This signal indicates that the slave is ready
+		// to accept an address and associated control signals.
+	output wire  S_AXI_AWREADY,
+	// Write data (issued by master, acceped by Slave) 
+	input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+	// Write strobes. This signal indicates which byte lanes hold
+		// valid data. There is one write strobe bit for each eight
+		// bits of the write data bus.    
+	input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+	// Write valid. This signal indicates that valid write
+		// data and strobes are available.
+	input wire  S_AXI_WVALID,
+	// Write ready. This signal indicates that the slave
+		// can accept the write data.
+	output wire  S_AXI_WREADY,
+	// Write response. This signal indicates the status
+		// of the write transaction.
+	output wire [1 : 0] S_AXI_BRESP,
+	// Write response valid. This signal indicates that the channel
+		// is signaling a valid write response.
+	output wire  S_AXI_BVALID,
+	// Response ready. This signal indicates that the master
+		// can accept a write response.
+	input wire  S_AXI_BREADY,
+	// Read address (issued by master, acceped by Slave)
+	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+	// Protection type. This signal indicates the privilege
+		// and security level of the transaction, and whether the
+		// transaction is a data access or an instruction access.
+	input wire [2 : 0] S_AXI_ARPROT,
+	// Read address valid. This signal indicates that the channel
+		// is signaling valid read address and control information.
+	input wire  S_AXI_ARVALID,
+	// Read address ready. This signal indicates that the slave is
+		// ready to accept an address and associated control signals.
+	output wire  S_AXI_ARREADY,
+	// Read data (issued by slave)
+	output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+	// Read response. This signal indicates the status of the
+		// read transfer.
+	output wire [1 : 0] S_AXI_RRESP,
+	// Read valid. This signal indicates that the channel is
+		// signaling the required read data.
+	output wire  S_AXI_RVALID,
+	// Read ready. This signal indicates that the master can
+		// accept the read data and response information.
+	input wire  S_AXI_RREADY
+);
+
+// AXI4LITE signals
+reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
+reg  	axi_awready;
+reg  	axi_wready;
+reg [1 : 0] 	axi_bresp;
+reg  	axi_bvalid;
+reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
+reg  	axi_arready;
+reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
+reg [1 : 0] 	axi_rresp;
+reg  	axi_rvalid;
+
+// Example-specific design signals
+// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+// ADDR_LSB is used for addressing 32/64 bit registers/memories
+// ADDR_LSB = 2 for 32 bits (n downto 2)
+// ADDR_LSB = 3 for 64 bits (n downto 3)
+localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+localparam integer OPT_MEM_ADDR_BITS = 1;
+//----------------------------------------------
+//-- Signals for user logic register space example
+//------------------------------------------------
+//-- Number of Slave Registers 4
+reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
+reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
+reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
+reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
+wire	 slv_reg_rden;
+wire	 slv_reg_wren;
+reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
+integer	 byte_index;
+reg	 aw_en;
+
+// I/O Connections assignments
+
+assign S_AXI_AWREADY	= axi_awready;
+assign S_AXI_WREADY	= axi_wready;
+assign S_AXI_BRESP	= axi_bresp;
+assign S_AXI_BVALID	= axi_bvalid;
+assign S_AXI_ARREADY	= axi_arready;
+assign S_AXI_RDATA	= axi_rdata;
+assign S_AXI_RRESP	= axi_rresp;
+assign S_AXI_RVALID	= axi_rvalid;
+// Implement axi_awready generation
+// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+// de-asserted when reset is low.
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_awready <= 1'b0;
+      aw_en <= 1'b1;
+    end 
+  else
+    begin    
+      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+        begin
+          // slave is ready to accept write address when 
+          // there is a valid write address and write data
+          // on the write address and data bus. This design 
+          // expects no outstanding transactions. 
+          axi_awready <= 1'b1;
+          aw_en <= 1'b0;
+        end
+        else if (S_AXI_BREADY && axi_bvalid)
+            begin
+              aw_en <= 1'b1;
+              axi_awready <= 1'b0;
+            end
+      else           
+        begin
+          axi_awready <= 1'b0;
+        end
+    end 
+end       
+
+// Implement axi_awaddr latching
+// This process is used to latch the address when both 
+// S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_awaddr <= 0;
+    end 
+  else
+    begin    
+      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+        begin
+          // Write Address latching 
+          axi_awaddr <= S_AXI_AWADDR;
+        end
+    end 
+end       
+
+// Implement axi_wready generation
+// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+// de-asserted when reset is low. 
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_wready <= 1'b0;
+    end 
+  else
+    begin    
+      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+        begin
+          // slave is ready to accept write data when 
+          // there is a valid write address and write data
+          // on the write address and data bus. This design 
+          // expects no outstanding transactions. 
+          axi_wready <= 1'b1;
+        end
+      else
+        begin
+          axi_wready <= 1'b0;
+        end
+    end 
+end       
+
+// Implement memory mapped register select and write logic generation
+// The write data is accepted and written to memory mapped registers when
+// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+// select byte enables of slave registers while writing.
+// These registers are cleared when reset (active low) is applied.
+// Slave register write enable is asserted when valid address and data are available
+// and the slave is ready to accept the write address and write data.
+assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      slv_reg0 <= 0;
+      slv_reg1 <= 0;
+      slv_reg2 <= 0;
+      slv_reg3 <= 0;
+    end 
+  else begin
+    if (slv_reg_wren)
+      begin
+        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+          2'h0:
+            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+                // Respective byte enables are asserted as per write strobes 
+                // Slave register 0
+                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+              end  
+          2'h1:
+            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+                // Respective byte enables are asserted as per write strobes 
+                // Slave register 1
+                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+              end  
+          2'h2:
+            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+                // Respective byte enables are asserted as per write strobes 
+                // Slave register 2
+                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+              end  
+          2'h3:
+            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+                // Respective byte enables are asserted as per write strobes 
+                // Slave register 3
+                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+              end  
+          default : begin
+                      slv_reg0 <= slv_reg0;
+                      slv_reg1 <= slv_reg1;
+                      slv_reg2 <= slv_reg2;
+                      slv_reg3 <= slv_reg3;
+                    end
+        endcase
+      end
+  end
+end    
+
+// Implement write response logic generation
+// The write response and response valid signals are asserted by the slave 
+// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+// This marks the acceptance of address and indicates the status of 
+// write transaction.
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_bvalid  <= 0;
+      axi_bresp   <= 2'b0;
+    end 
+  else
+    begin    
+      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+        begin
+          // indicates a valid write response is available
+          axi_bvalid <= 1'b1;
+          axi_bresp  <= 2'b0; // 'OKAY' response 
+        end                   // work error responses in future
+      else
+        begin
+          if (S_AXI_BREADY && axi_bvalid) 
+            //check if bready is asserted while bvalid is high) 
+            //(there is a possibility that bready is always asserted high)   
+            begin
+              axi_bvalid <= 1'b0; 
+            end  
+        end
+    end
+end   
+
+// Implement axi_arready generation
+// axi_arready is asserted for one S_AXI_ACLK clock cycle when
+// S_AXI_ARVALID is asserted. axi_awready is 
+// de-asserted when reset (active low) is asserted. 
+// The read address is also latched when S_AXI_ARVALID is 
+// asserted. axi_araddr is reset to zero on reset assertion.
+
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_arready <= 1'b0;
+      axi_araddr  <= 32'b0;
+    end 
+  else
+    begin    
+      if (~axi_arready && S_AXI_ARVALID)
+        begin
+          // indicates that the slave has acceped the valid read address
+          axi_arready <= 1'b1;
+          // Read address latching
+          axi_araddr  <= S_AXI_ARADDR;
+        end
+      else
+        begin
+          axi_arready <= 1'b0;
+        end
+    end 
+end       
+
+// Implement axi_arvalid generation
+// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+// data are available on the axi_rdata bus at this instance. The 
+// assertion of axi_rvalid marks the validity of read data on the 
+// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+// is deasserted on reset (active low). axi_rresp and axi_rdata are 
+// cleared to zero on reset (active low).  
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_rvalid <= 0;
+      axi_rresp  <= 0;
+    end 
+  else
+    begin    
+      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+        begin
+          // Valid read data is available at the read data bus
+          axi_rvalid <= 1'b1;
+          axi_rresp  <= 2'b0; // 'OKAY' response
+        end   
+      else if (axi_rvalid && S_AXI_RREADY)
+        begin
+          // Read data is accepted by the master
+          axi_rvalid <= 1'b0;
+        end                
+    end
+end    
+
+// Implement memory mapped register select and read logic generation
+// Slave register read enable is asserted when valid address is available
+// and the slave is ready to accept the read address.
+assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+always @(*)
+begin
+      // Address decoding for reading registers
+      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+        2'h0   : reg_data_out <= slv_reg0;
+        2'h1   : reg_data_out <= slv_reg1;
+        2'h2   : reg_data_out <= slv_reg2;
+        2'h3   : reg_data_out <= slv_reg3;
+        default : reg_data_out <= 0;
+      endcase
+end
+
+// Output register or memory read data
+always @( posedge S_AXI_ACLK )
+begin
+  if ( S_AXI_ARESETN == 1'b0 )
+    begin
+      axi_rdata  <= 0;
+    end 
+  else
+    begin    
+      // When there is a valid read address (S_AXI_ARVALID) with 
+      // acceptance of read address by the slave (axi_arready), 
+      // output the read dada 
+      if (slv_reg_rden)
+        begin
+          axi_rdata <= reg_data_out;     // register read data
+        end   
+    end
+end    
+
+// Add user logic here
+MM_ultra
+#(
+    .A_size(array_size),                                                   //决定了SA的边长，即大小
+    .data_width(data_width),                                           //决定了量化的数据位宽
+    .shift_width(shift_width),                                         //决定了移位器移位变量的位宽
+    .Weight_Block_num(Weight_block_num),                               //决定了IN_BUFFER里面weight_buffer_block的数量 一个block包含A_size个数据,数据位宽 data_width
+    .IN_Feature_Block_num(in_feature_Block_num),                       //决定了IN_BUFFER里面feature_buffer_block的数量 一个block包含A_size个数据,数据位宽 data_width
+    .OUT_Feature_Block_num(out_feature_block_num),                     //决定了OUT_BUFFER里面feature_buffer_block的数量 一个block包含A_size个数据,数据位宽OUT_MEM_WIDTH
+    .OUT_MEM_WIDTH(out_mem_width),                                     //决定了OUT_BUFFER的数据位宽
+    .F_length_width(feature_length_width),                                   //决定了F_length寄存器位宽以及MM_buffer里面bram大小
+    .F_width_block_num_width(feature_width_block_num_width),                 //决定了F_width_block_num寄存器位宽
+    .W_width_block_num_width(weight_width_block_num_width)                  //决定了W_width_block_num寄存器位宽以及MM_buffer里面bram大小
+                                                                        //F_length和W_width_block_num会有相乘，注意时序
+)u_MM_ultra(
+    .clk(axis_aclk),
+    .rst_n(aresetn),
+
+
+    .shift_in(slv_reg0),
+    .F_length_in(slv_reg1), //1 ~ block_num *A_size
+    .F_width_block_num_in(slv_reg2), //1 ~ block_num
+    .W_width_block_num_in(slv_reg3), //1 ~ block_num
+
+
+    .in_F_valid(s0_axis_tvalid),
+    .in_F_last(s0_axis_tlast),
+    .in_F_ready(s0_axis_tready),
+    .in_F_data(s0_axis_tdata),
+
+    .in_W_valid(s1_axis_tvalid),
+    .in_W_last(s1_axis_tlast),
+    .in_W_ready(s1_axis_tready),
+    .in_W_data(s1_axis_tdata),
+
+    .out_data_valid(m0_axis_tvalid),
+    .out_data_last(m0_axis_tlast),
+    .out_data_ready(m0_axis_tready),
+    .out_data(m0_axis_tdata)
+);
+
+// User logic ends
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/MM_ultra_top.v

@@ -0,0 +1,129 @@
+`timescale 1ns / 1ps
+
+module MM_ultra_top #
+	(
+		// Users to add parameters here
+        parameter integer     array_size=24,                                      
+        parameter integer     data_width=8,                                       
+        parameter integer     shift_width=5,                                      
+        parameter integer     Weight_block_num=2000,                              
+        parameter integer     in_feature_Block_num=2000,                          
+        parameter integer     out_feature_block_num=2000,                         
+        parameter integer     out_mem_width=21,                                   
+        parameter integer     feature_length_width=10,                            
+        parameter integer     feature_width_block_num_width=6,                    
+        parameter integer     weight_width_block_num_width=6,                     
+		// User parameters ends
+		// Do not modify the parameters beyond this line
+
+
+		// Parameters of Axi Slave Bus Interface S00_AXI
+		localparam integer C_S00_AXI_DATA_WIDTH	= 32,
+		localparam integer C_S00_AXI_ADDR_WIDTH	= 4
+	)
+	(
+		// Users to add ports here
+		input 										aclk,
+    	input 										aresetn,
+	
+    	input [array_size*data_width-1:0] 	        s0_axis_tdata,
+    	input       								s0_axis_tvalid,
+    	output      								s0_axis_tready,
+    	input       								s0_axis_tlast,
+
+    	input [array_size*data_width-1:0] 	        s1_axis_tdata,
+    	input       								s1_axis_tvalid,
+    	output      								s1_axis_tready,
+    	input       								s1_axis_tlast,
+    		
+    	output [array_size*data_width-1:0] 	        m0_axis_tdata,
+    	output       								m0_axis_tvalid,
+    	input        								m0_axis_tready,
+    	output      			 					m0_axis_tlast,
+		// User ports ends
+		// Do not modify the ports beyond this line
+
+
+		// Ports of Axi Slave Bus Interface S00_AXI
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+		input wire [2 : 0] s00_axi_awprot,
+		input wire  s00_axi_awvalid,
+		output wire  s00_axi_awready,
+		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+		input wire  s00_axi_wvalid,
+		output wire  s00_axi_wready,
+		output wire [1 : 0] s00_axi_bresp,
+		output wire  s00_axi_bvalid,
+		input wire  s00_axi_bready,
+		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+		input wire [2 : 0] s00_axi_arprot,
+		input wire  s00_axi_arvalid,
+		output wire  s00_axi_arready,
+		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+		output wire [1 : 0] s00_axi_rresp,
+		output wire  s00_axi_rvalid,
+		input wire  s00_axi_rready
+	);
+// Instantiation of Axi Bus Interface S00_AXI
+	MM_ultra_axi # ( 
+		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
+
+        .array_size(array_size),                  
+        .data_width(data_width),                   
+        .shift_width(shift_width),                  
+        .Weight_block_num(Weight_block_num),          
+        .in_feature_Block_num(in_feature_Block_num),      
+        .out_feature_block_num(out_feature_block_num),     
+        .out_mem_width(out_mem_width),               
+        .feature_length_width(feature_length_width),        
+        .feature_width_block_num_width(feature_width_block_num_width),
+        .weight_width_block_num_width(weight_width_block_num_width)
+	) U_MM_ultra_axi (
+		.S_AXI_ACLK(aclk),
+		.S_AXI_ARESETN(aresetn),
+		.S_AXI_AWADDR(s00_axi_awaddr),
+		.S_AXI_AWPROT(s00_axi_awprot),
+		.S_AXI_AWVALID(s00_axi_awvalid),
+		.S_AXI_AWREADY(s00_axi_awready),
+		.S_AXI_WDATA(s00_axi_wdata),
+		.S_AXI_WSTRB(s00_axi_wstrb),
+		.S_AXI_WVALID(s00_axi_wvalid),
+		.S_AXI_WREADY(s00_axi_wready),
+		.S_AXI_BRESP(s00_axi_bresp),
+		.S_AXI_BVALID(s00_axi_bvalid),
+		.S_AXI_BREADY(s00_axi_bready),
+		.S_AXI_ARADDR(s00_axi_araddr),
+		.S_AXI_ARPROT(s00_axi_arprot),
+		.S_AXI_ARVALID(s00_axi_arvalid),
+		.S_AXI_ARREADY(s00_axi_arready),
+		.S_AXI_RDATA(s00_axi_rdata),
+		.S_AXI_RRESP(s00_axi_rresp),
+		.S_AXI_RVALID(s00_axi_rvalid),
+		.S_AXI_RREADY(s00_axi_rready),
+
+		.axis_aclk(aclk),
+		.aresetn(aresetn),
+
+		.s0_axis_tdata(s0_axis_tdata),
+		.s0_axis_tvalid(s0_axis_tvalid),
+		.s0_axis_tready(s0_axis_tready),
+		.s0_axis_tlast(s0_axis_tlast),
+		
+		.s1_axis_tdata(s1_axis_tdata),
+		.s1_axis_tvalid(s1_axis_tvalid),
+		.s1_axis_tready(s1_axis_tready),
+		.s1_axis_tlast(s1_axis_tlast),
+
+		.m0_axis_tdata(m0_axis_tdata),
+		.m0_axis_tvalid(m0_axis_tvalid),
+		.m0_axis_tready(m0_axis_tready),
+		.m0_axis_tlast(m0_axis_tlast)
+	);
+
+	// Add user logic here
+
+	// User logic ends
+
+	endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/PE.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+
+module PE
+#(
+    parameter data_width = 8,           
+    parameter array_m = 16,             
+    parameter array_n = 16,              
+    parameter log2_array_m = 4
+)
+(
+    input                                                   clk,
+    input                                                   set_w,      
+    input                                                   rst_n,      
+    input signed [data_width-1:0]                           x_in,
+    input signed [data_width-1:0]                           w,
+    input signed [2*data_width+log2_array_m-1:0]            psum_in,   
+    output reg signed [data_width-1:0]                      x_out,
+    output reg signed [2*data_width+log2_array_m-1:0]       psum_out    
+);
+reg signed [data_width-1:0] reg_w;
+
+always @(posedge clk or negedge rst_n) begin
+    if(~rst_n)begin
+        psum_out <= 0;
+        reg_w <= 0;
+        x_out <= 0;
+    end
+    else begin
+        if(set_w) 
+            reg_w <=w;
+        psum_out <= psum_in + x_in*reg_w;
+        x_out <= x_in;
+    end
+end
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/PE_array.v

@@ -0,0 +1,129 @@
+`timescale 1ns / 1ps
+
+module PE_array
+(
+    clk,
+    rst_n,
+    set_w,
+    x_packed,
+    w_packed,
+    PE_out_packed
+);
+parameter integer data_width = 8;
+parameter integer array_m = 16;
+parameter integer array_n = 16;
+parameter integer log2_array_m = 4;
+
+
+input wire clk;
+input wire rst_n;
+input wire set_w;
+input [data_width*array_m-1:0]                     x_packed;
+input [array_m*array_n*data_width-1:0]             w_packed; 
+output [array_n*(log2_array_m+data_width*2)-1:0]   PE_out_packed;
+
+wire [array_n*data_width-1:0] w_line_array [array_m-1:0];
+wire [array_n*(log2_array_m+data_width*2)-1:0] psum_in_packed_array [array_m:0];
+
+wire [data_width-1:0] x_array [array_m-1:0];
+
+//assign PE_out_packed = psum_in_packed_array[array_m];
+wire [array_n*(log2_array_m+data_width*2)-1:0] psum_in_packed_last;
+assign psum_in_packed_last = psum_in_packed_array[array_m];
+genvar i;
+generate
+    for(i=array_n-1;i>=0;i=i-1) begin: buf_out
+        if(i==array_n-1)begin
+            assign PE_out_packed[(log2_array_m+data_width*2)*i +: (log2_array_m+data_width*2)] =  psum_in_packed_last[(log2_array_m+data_width*2)*i +: (log2_array_m+data_width*2)];
+        end
+        else begin
+            reg [(log2_array_m+data_width*2)-1:0] out_buf [array_n-2-i:0];
+            always @(posedge clk or negedge rst_n) begin
+                if(~rst_n)
+                    out_buf[0]<=0;
+                else
+                    out_buf[0]<=psum_in_packed_last[i*(log2_array_m+data_width*2) +: (log2_array_m+data_width*2)];
+            end
+            
+            genvar k;
+            for (k=1;k<=array_n-2-i;k=k+1)begin:out_buf_for
+                always@(posedge clk or negedge rst_n)begin
+                    if(~rst_n)
+                        out_buf[k]<=0;
+                    else
+                        out_buf[k]<=out_buf[k-1];
+                end
+            end
+            assign PE_out_packed[i*(log2_array_m+data_width*2) +: (log2_array_m+data_width*2)] = out_buf [array_n-2-i];
+        end
+    end
+endgenerate
+assign psum_in_packed_array[0] = 0;
+
+
+generate
+    for (i=0;i<array_m;i=i+1)begin:packed_to_array_1
+        assign x_array[i] = x_packed[data_width*i +: data_width];
+        assign w_line_array[i] = w_packed[(array_n*data_width)*i +: (array_n*data_width)];
+    end
+endgenerate
+
+generate
+    for (i=0; i<array_m; i=i+1) begin:array
+        if (i==0) begin
+            PE_line #(
+                .data_width (data_width),
+                .array_m(array_m),
+                .array_n(array_n),
+                .log2_array_m(log2_array_m)
+            )
+            PE_line_u
+            (
+                .clk(clk),
+                .rst_n(rst_n),
+                .set_w(set_w),
+                .x(x_array[i]),
+                .psum_in_packed(psum_in_packed_array[i]),
+                .w_packed(w_line_array[i]),
+                .psum_out_packed(psum_in_packed_array[i+1])
+            );            
+        end
+        else begin
+            reg [data_width-1:0] x_buf [i-1:0];
+            always @(posedge clk or negedge rst_n) begin
+                if(~rst_n)
+                    x_buf[0]<=0;
+                else
+                    x_buf[0]<=x_array[i];
+            end
+
+            genvar k;
+            for (k=1;k<=i-1;k=k+1)begin:x_buf_for
+                always@(posedge clk or negedge rst_n)begin
+                    if(~rst_n)
+                        x_buf[k]<=0;
+                    else
+                        x_buf[k]<=x_buf[k-1];
+                end
+            end
+
+             PE_line #(
+                .data_width (data_width),
+                .array_m(array_m),
+                .array_n(array_n),
+                .log2_array_m(log2_array_m)
+            )
+            PE_line_u
+            (
+                .clk(clk),
+                .rst_n(rst_n),
+                .set_w(set_w),
+                .x(x_buf[i-1]),
+                .psum_in_packed(psum_in_packed_array[i]),
+                .w_packed(w_line_array[i]),
+                .psum_out_packed(psum_in_packed_array[i+1])
+            );           
+        end
+    end
+endgenerate
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/PE_line.v

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+
+module PE_line
+#(
+    parameter array_m = 4, 
+    parameter array_n = 4, 
+    parameter data_width = 8,
+    parameter log2_array_m = 2
+)
+(
+    input                                               clk,
+    input                                               rst_n,
+    input                                               set_w,
+    input [data_width-1:0]                              x,
+    input [array_n*(log2_array_m+data_width*2)-1:0]     psum_in_packed,
+    input [array_n*data_width-1:0] w_packed,
+    output [array_n*(log2_array_m+data_width*2)-1:0]    psum_out_packed
+);
+
+wire [2*data_width+log2_array_m-1:0] psum_in_array [array_n-1:0];
+wire [2*data_width+log2_array_m-1:0] psum_out_array [array_n-1:0];
+wire [data_width-1:0] w_array [array_n-1:0];
+wire [data_width-1:0] x_array [array_n:0]; 
+
+assign x_array[0]=x;
+
+genvar i;
+generate
+    for(i=0;i<array_n;i=i+1)begin:packed_to_array_1
+        assign w_array[i] = w_packed[ data_width*i +: data_width];
+        assign psum_out_packed[(log2_array_m+data_width*2)*i +: (log2_array_m+data_width*2)] = psum_out_array[i];
+        assign psum_in_array[i] = psum_in_packed[(log2_array_m+data_width*2)*i +: (log2_array_m+data_width*2)];
+    end
+endgenerate
+
+generate
+    for(i=0;i<array_n;i=i+1)begin:array_line
+        PE#(
+            .data_width(data_width),
+            .array_m(array_m),
+            .array_n(array_n),   
+            .log2_array_m(log2_array_m)
+        )
+        PE_u(
+            .clk(clk),
+            .set_w(set_w),   
+            .rst_n(rst_n),   
+            .x_in(x_array[i]),
+            .w(w_array[i]),
+            .psum_in(psum_in_array[i]), 
+            .x_out(x_array[i+1]),
+            .psum_out(psum_out_array[i]) 
+        );
+    end
+endgenerate
+endmodule

Buck008_Transformer-Accelerator-Based-on-FPGA/src/right_shifter.v

@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+//��������
+module right_shifter
+#(
+    parameter before_data_width = 32,
+    parameter after_data_width = 8,
+    parameter shift_width = 5
+)
+(
+    shift,
+    data_in,
+    data_out
+);
+
+input wire [shift_width-1:0]shift;
+input wire signed [before_data_width-1:0] data_in;
+output reg signed[after_data_width-1:0] data_out;
+
+wire signed [before_data_width-1:0] temp1_out;
+wire signed [before_data_width-1:0] temp2_out;
+
+assign temp1_out = data_in >>> shift;
+assign temp2_out = data_in[shift-1] ? temp1_out + 1 : temp1_out;
+
+wire under_min = temp2_out[before_data_width-1] & (~(& temp2_out[before_data_width-2:after_data_width-1]));
+wire over_max = (~temp2_out[before_data_width-1]) & (|temp2_out[before_data_width-2:after_data_width-1]);
+
+wire under_min_S0 = data_in[before_data_width-1] & (~(& data_in[before_data_width-2:after_data_width-1]));
+wire over_max_S0 = (~data_in[before_data_width-1]) & (|data_in[before_data_width-2:after_data_width-1]);
+
+always @(*) begin
+    if(shift == 0)
+        case ({under_min_S0,over_max_S0})
+            2'b10: data_out = {1'b1,{(after_data_width-1){1'b0}}};//data_out = 8'b1000_0000;
+            2'b01: data_out = {1'b0,{(after_data_width-1){1'b1}}};//8'b0111_1111;
+            default: data_out = data_in;
+        endcase
+    else begin
+        case ({under_min,over_max})
+            2'b10: data_out = {1'b1,{(after_data_width-1){1'b0}}};//data_out = 8'b1000_0000;
+            2'b01: data_out = {1'b0,{(after_data_width-1){1'b1}}};//8'b0111_1111;
+            default: data_out = temp2_out[after_data_width-1:0];
+        endcase
+    end
+end
+
+endmodule
+

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/Defines.h

@@ -0,0 +1,55 @@
+#ifndef SRC_DEFINES_H_
+#define SRC_DEFINES_H_
+#include "xparameters.h"
+#include "xaxidma_hw.h"
+#define CACHE_LINE_SIZE 32
+#define DATA_TYPE s8
+#define MAX_LIMIT 127
+#define MIN_LIMIT -128
+
+#define MM_ADDR 			XPAR_MM_ULTRA_TOP_0_BASEADDR
+#define SHIFT_ADDR 			MM_ADDR
+#define FL_ADDR 			(MM_ADDR + 0x04)
+#define FWBN_ADDR 		    (MM_ADDR +0x08)
+#define WWBN_ADDR	        (MM_ADDR +0x0c)
+
+#define WEIGHT_DMA_ADDR 	XPAR_AXI_DMA_1_BASEADDR
+#define WEIGHT_MM2S_DMACR  	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
+#define WEIGHT_MM2S_DMASR  	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
+#define WEIGHT_MM2S_SA	    (WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
+#define WEIGHT_MM2S_LENGTH 	(WEIGHT_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
+
+#define FEATURE_DMA_ADDR 	XPAR_AXI_DMA_0_BASEADDR
+#define FEATURE_MM2S_DMACR  (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET) //MM2S DMA Control register
+#define FEATURE_MM2S_DMASR  (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET) //MM2S DMA Status register
+#define FEATURE_MM2S_SA	    (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //MM2S Source Address
+#define FEATURE_MM2S_LENGTH (FEATURE_DMA_ADDR + XAXIDMA_TX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //MM2S Transfer Length (Bytes)
+
+#define RESULT_DMA_ADDR		XPAR_AXI_DMA_2_BASEADDR
+#define RESULT_S2MM_DMACR  (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET) //S2MM DMA Control register
+#define RESULT_S2MM_DMASR  (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET) //S2MM DMA Status register
+#define RESULT_S2MM_DA	    (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_SRCADDR_OFFSET) //S2MM Destination Address
+#define RESULT_S2MM_LENGTH (RESULT_DMA_ADDR + XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET) //S2MM Transfer Length (Bytes)
+
+
+//SA parameters
+#define A_SIZE 16
+#define W_block_num 4096
+#define F_in_block_num 4096
+#define F_out_Block_num 4096
+#define F_length_width 10
+#define F_width_block_num_width 6
+#define W_width_block_num_width 6
+#define shift_width 5
+
+//matrix size limits
+#define F_IN_MATRIX_SIZE_MAX (F_in_block_num * A_SIZE)
+#define W_MATRIX_SIZE_MAX (W_block_num * A_SIZE)
+#define F_OUT_MATRIX_SIZE_MAX (F_out_Block_num * A_SIZE)
+#define F_LENGTH_MAX (2 ** F_length_width)
+#define F_WIDTH_MAX ((2 ** F_width_block_num_width) * A_SIZE)
+#define W_LENGTH_MAX F_WIDTH_MAX
+#define W_WIDTH_MAX ((2 ** W_width_block_num_width) * A_SIZE)
+
+
+#endif /* SRC_DEFINES_H_ */

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/Matrix.cpp

@@ -0,0 +1,165 @@
+#include "Matrix.h"
+#include "xparameters.h"
+#include "Defines.h"
+#include <stdio.h>
+#include "xil_io.h"
+#include "xtime_l.h"
+#include "xil_cache.h"
+#include <string.h>
+
+Matrix::Matrix(int rows, int cols) {
+	this->rows = rows;
+	this->cols= cols;
+	this->real_cols = (cols / A_SIZE + (cols % A_SIZE != 0 ? 1 : 0)) * A_SIZE;
+	this->real_rows = (rows / A_SIZE + (rows % A_SIZE != 0 ? 1 : 0)) * A_SIZE;
+	this->real_size = real_cols * real_rows;
+	this->base_addr = new DATA_TYPE[real_rows * real_cols](); //initialize to 0
+}
+
+Matrix::~Matrix() {
+    delete[] base_addr;
+}
+
+int Matrix::get_real_cols() const{
+	return this->real_cols;
+}
+
+int Matrix::get_real_rows() const{
+	return this->real_rows;
+}
+
+int Matrix::get_real_size() const{
+	return this->real_size;
+}
+
+DATA_TYPE * Matrix::get_base_addr() const{
+	return this->base_addr;
+}
+
+void Matrix::set_value(int row, int col, DATA_TYPE value){
+	*(this->base_addr + row * this->real_cols + col)=value;
+}
+
+DATA_TYPE Matrix::get_value(int row, int col){
+	return *(this->base_addr + row * this->real_cols + col);
+}
+
+void Matrix::mat_print(){
+	for(int i = 0; i < this->rows; i++){
+		for(int j = 0; j < this->cols; j++){
+			printf("%d, ", this->get_value(i,j));
+		}
+		printf("\n");
+	}
+}
+bool Matrix_compare(const Matrix &A, const Matrix &B){
+	if(A.rows != B.rows){
+		printf("size mismatch\n");
+	    return FALSE;
+	}
+	if(A.cols != B.cols){
+		printf("size mismatch\n");
+	    return FALSE;
+	}
+	int result = memcmp(A.get_base_addr(), B.get_base_addr(), A.get_real_size());
+	return (bool)result;
+}
+void Matrix_mul_soft(Matrix &A, Matrix &B, Matrix &C, int R_shift){ //A*B=C
+	if(A.cols != B.rows){
+		printf("size mismatch\n");
+	    return;
+	}
+	if(A.rows != C.rows || B.cols != C.cols){
+		printf("size mismatch\n");
+	    return;
+	}
+	int temp;
+	int i;
+	int j;
+	int k;
+
+	for (i=0;i<C.rows;i++){
+//    	printf("\n");
+		for(j=0;j<C.cols;j++){
+			temp=0;
+	        for(k=0;k<A.cols;k++){
+	        	temp = temp + A.get_value(i,k)*B.get_value(k,j);
+	        }
+//	        printf("temp: %d\n",temp);
+	        if(R_shift > 0){
+	        	temp = (temp+(1<<(R_shift-1))) >> R_shift; //rounding off
+	        }
+	        if (temp > MAX_LIMIT){
+	        	temp = MAX_LIMIT;
+	        }
+	        if (temp < MIN_LIMIT){
+	            temp = MIN_LIMIT;
+	        }
+//          printf("%d",temp);
+	        C.set_value(i,j,temp);
+	    }
+	}
+}
+
+void Matrix_mul_hard(Matrix &A, Matrix &B, Matrix &C, int R_shift){//A*B=C
+	if(A.cols != B.rows){
+		printf("size mismatch\n");
+	    return;
+	}
+	if(A.rows != C.rows || B.cols != C.cols){
+		printf("size mismatch\n");
+	    return;
+	}
+	u32 weight_buffer;
+	u32 feature_in_buffer;
+	u32 feature_out_buffer;
+	int weight_size;
+	int feature_in_size;
+	int feature_out_size;
+
+	weight_buffer = (u32)B.get_base_addr();
+	feature_in_buffer = (u32)A.get_base_addr();
+	feature_out_buffer = (u32)C.get_base_addr();
+
+	weight_size = B.get_real_size();
+	feature_in_size = A.get_real_size();
+	feature_out_size = C.get_real_size();
+
+	u32 shift = R_shift;
+	u32 in_rows_num = A.get_real_rows();
+	u32 F_width_block_num = A.get_real_cols() / A_SIZE;
+	u32 W_width_block_num = B.get_real_cols() / A_SIZE;
+
+	Xil_DCacheFlushRange(weight_buffer,weight_size);
+	Xil_DCacheFlushRange(feature_in_buffer,feature_in_size);
+	Xil_DCacheFlushRange(feature_out_buffer,feature_out_size);
+
+	//set control register value
+	Xil_Out32(SHIFT_ADDR,shift);
+	Xil_Out32(FL_ADDR,in_rows_num);
+	Xil_Out32(FWBN_ADDR,F_width_block_num);
+	Xil_Out32(WWBN_ADDR,W_width_block_num);
+
+	//first open receive channel
+	Xil_Out32(RESULT_S2MM_DMACR, 0x4);//reset
+	Xil_Out32(RESULT_S2MM_DA, feature_out_buffer); //set addr
+	Xil_Out32(RESULT_S2MM_DMACR, 0x1);  //open channel
+	Xil_Out32(RESULT_S2MM_LENGTH,feature_out_size); //set length
+
+	Xil_Out32(WEIGHT_MM2S_DMACR, 0x4);
+	Xil_Out32(WEIGHT_MM2S_SA, weight_buffer);
+	Xil_Out32(WEIGHT_MM2S_DMACR, 0x1);
+	Xil_Out32(WEIGHT_MM2S_LENGTH,weight_size);
+
+	Xil_Out32(FEATURE_MM2S_DMACR, 0x4);
+	Xil_Out32(FEATURE_MM2S_SA, feature_in_buffer);
+	Xil_Out32(FEATURE_MM2S_DMACR, 0x1);
+	Xil_Out32(FEATURE_MM2S_LENGTH,feature_in_size);
+
+
+	while((Xil_In32(RESULT_S2MM_DMASR) & XAXIDMA_IDLE_MASK) ? FALSE : TRUE){
+		printf("*\n");
+	};
+}
+
+

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/Matrix.h

@@ -0,0 +1,34 @@
+#ifndef MY_MATRIX_H
+#define MY_MATRIX_H
+#include "xil_types.h"
+#include "Defines.h"
+
+class Matrix {
+private:
+    int real_cols;
+    int real_rows;
+    int real_size;
+    DATA_TYPE * base_addr;
+
+public:
+    int rows;
+    int cols;
+    // constructor
+    Matrix(int rows, int cols);
+
+    // destructor
+    ~Matrix();
+
+    int get_real_cols() const;
+    int get_real_rows() const;
+    int get_real_size() const;
+    DATA_TYPE* get_base_addr() const;
+    void set_value(int row, int col, DATA_TYPE value);
+    DATA_TYPE get_value(int row, int col);
+    void mat_print();
+
+};
+void Matrix_mul_soft(Matrix &A, Matrix &B, Matrix &C, int R_shift); //A*B=C
+void Matrix_mul_hard(Matrix &A, Matrix &B, Matrix &C, int R_shift); //A*B=C
+bool  Matrix_compare(const Matrix &A, const Matrix &B);
+#endif

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/README.txt

@@ -0,0 +1 @@
+Empty application. Add your own sources.

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/Xilinx.spec

@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/lscript.ld

@@ -0,0 +1,291 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: 2018.3                                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2019 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                           */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1FFFFFFF;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_0
+
+.note.gnu.build-id : {
+   KEEP (*(.note.gnu.build-id))
+} > ps7_ddr_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_0
+
+_end = .;
+}
+

Buck008_Transformer-Accelerator-Based-on-FPGA/vitis/main.cpp

@@ -0,0 +1,45 @@
+#include "Matrix.h"
+#include "stdio.h"
+#include <stdlib.h>
+int main(){
+	u32 IN_ROWS_NUM = 121;
+	u32 IN_COLS_NUM = 311;
+	u32 OUT_COLS_NUM = 72;
+
+	int R_shift = 0;
+
+    u32 i;
+    u32 j;
+    Matrix A(IN_ROWS_NUM, IN_COLS_NUM);
+    Matrix B(IN_COLS_NUM, OUT_COLS_NUM);
+    Matrix C(IN_ROWS_NUM, OUT_COLS_NUM);
+    Matrix C_hard(IN_ROWS_NUM, OUT_COLS_NUM);
+	for(i=0;i<IN_ROWS_NUM;i++){
+		for(j=0;j<IN_COLS_NUM;j++){
+			DATA_TYPE value = rand()%256-128;//rand()%16-7;
+//			DATA_TYPE value = (i * A_SIZE +j + 128)%256 - 128;
+//			DATA_TYPE value = 1;
+			A.set_value(i,j,value);
+		}
+	}
+
+	for(i=0;i<IN_COLS_NUM;i++){
+		for(j=0;j<OUT_COLS_NUM;j++){
+			DATA_TYPE value = rand()%256-128;//rand()%16-7;
+//			DATA_TYPE value = (i * A_SIZE +j + 128)%256 - 128;
+//			DATA_TYPE value = 2;
+			B.set_value(i,j,value);
+		}
+	}
+
+	Matrix_mul_soft(A, B, C, R_shift);
+	Matrix_mul_hard(A, B, C_hard, R_shift);
+	bool result = Matrix_compare(C, C_hard);
+	if(result){
+		printf("Right!");
+	}else{
+		printf("Wrong!");
+	}
+
+	return 0;
+}