| # Enable Verilator in the RTL Simulation Flow for SweRV integration | |
| - Source URL: https://github.com/Lampro-Mellon/LM-RISCV-DV/issues/69 | |
| ## Fetched Issue/PR Details | |
| Title: Enable Verilator in the RTL Simulation Flow for SweRV integration (#69) | |
| Description: No description was provided in the original issue. | |
| Status: Closed (resolved via PR #81) | |
| Assignee: amnafayyaz28 | |
| Label: enhancement | |
| Reporter: haroon-shafique | |
| Opened: January 7, 2021 | |
| Comments: No comments, reactions, or additional context were visible on the page. | |
| Linked Issues: Resolving PR #81. The issue requests integration of Verilator (an open-source RTL simulator) into the RTL simulation workflow for SweRV core integration within the LM-RISCV-DV project. | |