issues/IEEE-UCF_Gaming-CPU-Project_pr42

# Subsystem: Design RAM Handler

- Source URL: https://github.com/IEEE-UCF/Gaming-CPU-Project/issues/27

**Purpose:** Orchestrate Double Data Rate (DDR) interactions between RAM and CPU system, including booting from ROM and connecting to AXI 

**Main File(s)**

- [SRAM Dualport](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/sram_dualport.sv)
- [Boot ROM](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/bootrom.sv)
- [DMA](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/subsys/dma_subsys.sv)

**Sub-Files**
- [MIG AXI Wrapper](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/mig_axi_wrap.sv)
- [MIG Calibration Status](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/calib_status_sync.sv)

**Related Sub-Issues (Dependencies)**
Bus: #6 
Input-Output: #26

**Co-Lead**
Evan Eichholz