| # Refactor the CR memory space | |
| - Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/679 | |
| ## Issue Title | |
| Refactor the CR memory space | |
| ## Issue Description | |
| Create a simple struct for the all CR! This shold solve the error in the readafter write issue we have. | |
| (The issue proposes organizing the Control Register (CR) memory space using a structured data type to address read-after-write synchronization problems in the FPGA-MAFIA project.) | |
| ## Issue Comments | |
| None. | |
| ## Issue Metadata | |
| - Status: Closed (linked to PR #680) | |
| - Assignee: amichai-bd | |
| - Labels: RTL design, build & env | |
| - Created: June 16, 2024 | |
| ## Linked Issues / PRs | |
| - PR #680 — the resolution implementation | |