| # Cache - support partiol read/write (byte enable) | |
| - Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/583 | |
| Cache - support partial read/write (byte enable) | |
| LHU, LBU, LW,LH,LB SW,SH,SB | |
| Also, support signed and unsigned extends for the memory load request. | |
| PR Title: modify chach_tasks.vh to support random partial reads and writes | |
| PR Number: #655 | |
| Status: Merged | |
| Repository: FPGA-MAFIA/fpga_mafia | |
| Description: | |
| No formal description was provided by the author. | |
| Comments: | |
| amichai-bd (May 28, 2024): | |
| "Small refactor into a single 'Case'" | |
| The reviewer noted a code consolidation effort with an accompanying image reference. | |
| amichai-bd (May 28, 2024): | |
| "I will also note that the verification env for this Cache is not really good.. It takes a long time to build and simulate - i suspect its due to something wring we did here.. Also a lot of code is duplicated - we should be able to use parameters to have different flavors of similar tasks." | |
| The reviewer raised concerns about verification environment performance and code duplication, suggesting future refactoring opportunities. | |
| Linked Issue: | |
| #583 - "Cache - support partiol read/write (byte enable)" (Closed by this PR) | |
| Commits Overview: | |
| 13 commits were merged, including initial test additions, byte offset support for D_CACHE, partial read/write handling, and byte enable offset fixes across fill requests. | |