| # writing MC (memory controller) for communication between host and SDRAM | |
| - Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/611 | |
| ** Goal | |
| - Create communication interface between host computer and SDRAM | |
| ** requirements | |
| - The controller will receive 128bit data (cache line) and transfer it to SDRAM at 16bit granularity. | |
| - The communication is bi-directional | |
| - The unit will take care of forwarding in case of RAW (read after write) that causes data hazard | |
| - The protocol designed to work with DE10-lite SDRAM | |
| - Support bursts | |
| **Further specifications will be added in the future** | |
| PR Title: Sdram controler for read/write 8 length bursts | |
| Description: | |
| The contributor submitted an FPGA design for an SDRAM controller supporting burst operations. Key details include: | |
| - Controller Location: source/mem_ss/sdram_ctrl_bursts | |
| - FPGA Design Location: /FPGA/sdram_full | |
| The author noted temporary additions would be removed once the complete memory subsystem is functional, including some FPGA folders and .vh files within source/mem_ss. | |
| Demonstration: | |
| The PR included three test case examples showing write/read functionality: | |
| - Writing to random address 0x0018 | |
| - Reading from that address | |
| - Screenshots displaying read/write data and address values during operation | |
| Commits: | |
| The PR merged 11 commits (May 1-9, 2024), including: | |
| - Controller implementation for burst operations | |
| - FPGA test directory additions | |
| - FSM implementations for random burst testing across addresses/banks | |
| - Debugging fixes and refresh logic enhancements | |
| Status: Merged on May 10, 2024 by roman012285 | |
| Assigned to: amichai-bd | |
| Related Issue: #611 - "writing MC (memory controller) for communication between host and SDRAM" | |