| # core_rrv - create a dedicated test for the timer interrupt during a illegal instruction trap |
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| - Source URL: https: |
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| Create a test that has both "illegal instruction trap" and "timer interrupts". |
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| I am hoping to see hit this case: |
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| - illegal instruction trap exception handler is in progress (MIE set to 0 by HW) |
| - Timer interrupt time condition met -> but MIE is 0, so no exception is taken yet |
| - illegal instruction handler return with MRET (MIE back to 1) |
| - Timer interrupt condition is still set so the timer interrupt exception handler takes place |
| - We return from the timer interrupts and continue execution |
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| PR Title: add test timer exception after illegal instruction trap + debug csr's |
| Status: Merged on Feb 14, 2024 |
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| Description: No description was provided in the pull request. |
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| Commits (7 total): |
| 1. "add clear and set csr macros" |
| 2. "add debud csrs. dpc, dcsr, dscratch0, dscratch1" |
| 3. "add test for checking alive illegal before timer interrupt" |
| 4. "disable mie to avoid timer exception while printing. may cause misses" |
| 5. "Merge branch 'main' into core_rrv" |
| 6. "modify regrees file" |
| 7. "add debug csrs, custom_mtime, custom_mtimecmp and custom_lfsr" |
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| Review Comments: |
| amichai-bd (reviewer/approver): |
| - Regarding cycle/instret counter synchronization: "The plan is to artificially match the ref model performance IPC with the DUT performance so the 2 tests can be compared correctly." |
| - On LFSR updates: Expected hardware LFSR updates "only when there is a read/write from the LFSR CSR" by moving logic into read/write cases |
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| roman012285 (author) response to LFSR comment: Indicated the fix hadn't been implemented yet ("ืขืื ืื ืืืขืชื ืืื") |
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| Linked Issue: |
| Issue #477: "create a dedicated test for the timer interrupt during a illegal instruction trap" |
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