issues/FPGA-MAFIA_fpga_mafia_pr473

# Disable correctly the interrupts & restore correctly the enable bits

- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/471

![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/f3c2ce04-1feb-4806-879b-0bba8f41c702)
This is wrong - after mret we dont need to enable the "csr_mie" this way..  we need to restore the mstatus correctly!

![image](https://github.com/FPGA-MAFIA/fpga_mafia/assets/81047407/b85930f0-e91d-4926-afbb-58b464701042)
This is also wrong - don't need to change the csr_mie - only the disable the mstatus

Please read carefully again:
## Timer Interrupt Handling
When a timer interrupt is taken, you correctly set the mcause with the MSB set to '1' indicating an interrupt, and the cause code for a timer interrupt (0x7). 
However, your handling of mie (Machine Interrupt Enable) and mstatus might not accurately reflect the typical behavior expected upon an interrupt.
Disabling interrupts by setting mie might not be necessary here; instead, interrupts are usually disabled by clearing the MIE bit in the mstatus register, not by directly manipulating mie.
The update to mstatus seems to intend to manipulate interrupt enable bits directly. Typically, upon taking an interrupt, the hardware would clear the MIE bit in mstatus, saving the previous state in MPIE, and update MPP if needed. Your comment regarding setting mstatus[7] equal to mstatus[3] seems to misunderstand the mstatus register's bit fields.
## Return from Interrupt (MRET)
Upon executing MRET, the typical behavior is to restore the previous interrupt enable state by copying MPIE to MIE in mstatus, not by directly setting mie. Your code seems to directly enable interrupts by setting mie and mstatus which might not correctly restore the previous state.
The mstatus update to 0x8 directly seems incorrect. The MRET instruction itself should handle the restoration of mstatus fields, specifically MIE and MPIE, based on their pre-interrupt values.
Clearing mip directly on MRET might not be necessary or correct, as mip reflects pending interrupts and is typically managed by acknowledging the interrupt source (like writing to a timer register to clear the timer interrupt).