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123e810 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 | Minimal fail-to-pass extraction for AUCOHL/Lighter PR 16, "bug fix in FF
Mapping cells".
The reduced snapshot models the sky130 `\$dffe` mapping cell. The buggy
mapping feeds `EN` directly into the clock-gate cell and ignores
`EN_POLARITY`, so an active-low enable does not capture data. The patch adds
the polarity-adjusted gate enable used by the real PR. The Verilator
testbench drives an active-low enable and checks capture/hold behavior.
## PR Content from GitHub
# Pull Request Summary
**PR Title:** bug fix in FF Mapping cells
**PR Number:** #16
**Status:** Merged (Sep 28, 2023)
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## PR Description
**Signed by:** Youssef Kandil
**Contributor:** @dineshannayya
**Context:**
The clock gating functionality of $SDFFE cells was causing validation failures. The issue stemmed from forced positive signaling of clock and enable signals.
**Changes:**
The fix implements polarity checking for both "clock" and "enable" signals, adjusting their signs accordingly. This resolves issue #2.
**Mentions:** @dineshannayya, @shalan
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## Linked Issue
**Title:** SDFFE mapping crashes validation
This PR successfully merged after closing the referenced issue.
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## Participants
- @kanndil (merged the PR)
- @dineshannayya (contributor)
No formal reviews were recorded, and no labels, assignees, or milestone were set for this pull request.
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