Publish Qwen3.8-Flash-CIRU-STRIX-IU4 model card and release metadata

.gitattributes

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+
+assets/qwen38-flash-ciru-strix-iu4.jpg filter=lfs diff=lfs merge=lfs -text

LICENSE

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+Qwen Community License 1.0
+
+Copyright (c) 2026 Qwen
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of this software, including the model weights, parameters, configuration files, inference code and associated documentation files (collectively, the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, sell, deploy, host, fine-tune, and create derivative works from (collectively, "Use" or "Using") copies of the Software; and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
+
+1. The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. If the Software (or any derivative works thereof) is Used for any of the licensee's commercial products or services that have more than 100,000,000 monthly active users or US$ 20,000,000 (or equivalent in other currencies) monthly revenue, respective model name must be prominently displayed on the user interface of such product or service; and,
+
+2. If the licensee or any of its affiliates conducts a Model as a Service or AI Work Assistant business, the licensee shall obtain a separate license from Qwen before Using the Software or its derivative works for any commercial purpose. The foregoing requirement shall not apply to the licensee's internal Use of the Software, provided that such Use does not make the Software, its outputs, or its underlying model capabilities available to any third party.
+
+"Model as a Service" means giving a third party access to language model inference or fine-tuning (e.g., via API or a hosted endpoint) in a manner that allows such third parties to exercise meaningful control over the inputs, parameters, or training data. This does not include the mere relaying of requests to models hosted by other third parties. 
+“AI Work Assistant” means an independent AI-powered product primarily designed for AI-assisted coding or office productivity (e.g., Qoder and QwenWork). It does not include: (a) a single-purpose AI tool (such as an AI translation tool); (b) an AI assistant primarily designed for a domain other than coding or office productivity (such as Taobao AI Shopping Assistant or AMap AI Chat); or (c) an AI assistant that is a feature of a product whose primary purpose is not AI-assisted coding or office productivity.
+
+THE SOFTWARE AND ANY OUTPUT AND RESULTS THEREFROM ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL QWEN, ITS AFFILIATES OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. THE USE OF THE SOFTWARE MUST COMPLY WITH APPLICABLE LAWS AND REGULATIONS, AND MUST NOT INFRINGE THE INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
+
+For any questions regarding this license, please contact model-business@notice.qwencloud.com.

NOTICE.md

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+# Notices
+
+## Model
+
+The model artifacts derive from Qwen3.8-Flash-Next and Qwen3.8-Flash-Next-FP8 at the revisions named in the model card. They are distributed under the included Qwen Community License 1.0.
+
+## Runtime
+
+The required runtime is published separately at <https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4>. It is based on llama.cpp and retains the MIT license. Included CIRU runtime changes incorporate or adapt MIT-licensed work from the llama.cpp community and AMD helper code whose source notices are preserved.
+
+Runtime credit includes Qwen; ggml-org and llama.cpp contributors; Ryan Monsurate for Qwen experimental/MTP integration work adapted by CIRU; AMD's open-source ROCm ecosystem; and the contributors named in the runtime's `THIRD_PARTY_NOTICES.md`.
+
+## Trademarks and affiliation
+
+Qwen and AMD names and logos belong to their respective owners. CIRU is an independent community research project and is not sponsored or endorsed by Qwen or AMD.
+

README.md

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+---
+license: other
+license_name: qwen-community-1.0
+license_link: LICENSE
+base_model:
+  - Qwen/Qwen3.8-Flash-Next
+  - Qwen/Qwen3.8-Flash-Next-FP8
+base_model_relation: quantized
+library_name: llama.cpp
+pipeline_tag: text-generation
+inference: false
+tags:
+  - qwen
+  - qwen3.8
+  - qwen3.8-flash-next
+  - gguf
+  - llama.cpp
+  - amd
+  - rocm
+  - gfx1151
+  - ryzen-ai-max-395
+  - strix-halo
+  - mixture-of-experts
+  - iu4
+  - mtp
+  - speculative-decoding
+  - nvme
+  - ple
+  - long-context
+  - local-inference
+---
+
+[![Qwen3.8 Flash CIRU Strix IU4](assets/qwen38-flash-ciru-strix-iu4.jpg)](https://llm.ciru.ai/research)
+
+# Qwen3.8-Flash-CIRU-STRIX-IU4
+
+**A quality-first, long-context Qwen3.8-Flash-Next build for fast local inference on AMD Strix Halo.**
+
+> [!IMPORTANT]
+> This is a text-only, custom-runtime release. The main GGUF is **not standalone**: it requires the CIRU [`llama.cpp` runtime](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4) and all three files under `ple/`. The MTP draft under `mtp/` enables the headline speculative-decoding profile. Stock `llama.cpp` and Hugging Face hosted inference cannot run this package correctly.
+
+## Headline results
+
+| Result | Score | Scope |
+|---|---:|---|
+| HumanEval | **160/164 (97.56%)** | Full 164-task local-custom chat run |
+| HumanEval+ | **155/164 (94.51%)** | Full 164-task EvalPlus run |
+| ARC-Challenge | **1,143/1,172 (97.53%)** | Full EvalScope dataset |
+| ToolEval Standard | **115/138 points (83.33%)** | 69 local-custom cases |
+| ToolEval Hard | **23/30 points (76.67%)** | 15 local-custom hard cases |
+| H121 8K cold prefill | **359.43 tok/s** | 8,192-token prompt |
+| H121 8K generation | **30.80 tok/s** | 128 generated tokens, MTP depth 3 |
+| Long-context coverage | **131,072 prompt tokens** | Cold exact-count context ladder |
+
+Quality suites used the same released model artifacts on the earlier H96 depth-1 runtime. H121 is a runtime-only allocator-lifetime correction; those quality suites have not yet been rerun on H121 depth 3. Local-custom and sampled results are labeled and are not claimed as canonical leaderboard submissions.
+
+## Why this build
+
+Qwen3.8-Flash-CIRU-STRIX-IU4 is designed around the Ryzen AI Max+ 395's large unified-memory envelope and gfx1151 matrix instructions:
+
+- **Quality-first mixed storage.** Routed expert weights use Q4_1 while the protected core remains Q5_K, Q5_1, Q8_0, BF16, or F32.
+- **Native IU4 execution.** Stored Q4_1 expert weights use a tuned unsigned-IU4 WMMA path on gfx1151. `IU4` describes runtime execution, not a uniform four-bit model or custom GGUF storage type.
+- **NVMe-paged exact FP8 PLE.** The mandatory CIRUPLE1 sidecar pages exact FP8 E4M3 PLE weights from SSD with a 4 GiB decoded-page cache.
+- **MTP speculation.** The included Q8_0 draft supports the public depth-3 speculative profile.
+- **Production caching.** The public profile enables prompt reuse, an 8 GiB RAM prompt cache, idle-slot caching, and long-context checkpoints.
+- **Long context.** Native server configuration is 262,144 tokens; cold performance has been measured through 131,072 prompt tokens.
+
+## H121 release correctness fix
+
+During sustained MTP depth-3 generation, the pre-release runtime could intermittently page fault in Q8_0 `GET_ROWS`. The root cause was allocator lifetime: reused Qwen4Exp M=1 token and hidden-state inputs were marked input-only, so their graph allocations could be recycled between continuation steps.
+
+H121 retains both tensors as graph outputs:
+
+```cpp
+ggml_set_output(inp->tokens);
+ggml_set_output(inp->h);
+```
+
+This adds no kernel, copy, synchronization, fallback, or model change. The corrected runtime completed a 6,009-token coding-generation stress test with no HSA, pager, nonfinite, or server failure, then reproduced the 8K+128 row at 359.4267 prefill tok/s and 30.7970 generation tok/s. The source and exact patch are published in runtime tag [`v1.0.0-h121`](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/releases/tag/v1.0.0-h121).
+
+## Download
+
+The complete package is 135,962,881,135 bytes (126.625 GiB):
+
+```bash
+python -m pip install -U "huggingface_hub[cli]"
+hf download jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4 \
+  --local-dir ./Qwen3.8-Flash-CIRU-STRIX-IU4
+cd Qwen3.8-Flash-CIRU-STRIX-IU4
+sha256sum -c checksums.sha256
+```
+
+Expected layout:
+
+```text
+Qwen3.8-Flash-CIRU-STRIX-IU4/
+├── Qwen3.8-Flash-CIRU-STRIX-IU4.gguf
+├── mtp/
+│   └── Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf
+└── ple/
+    ├── ple.manifest.json
+    ├── ple.payload.bin
+    └── ple.scale.bf16
+```
+
+| File | Bytes | GiB | SHA-256 |
+|---|---:|---:|---|
+| `Qwen3.8-Flash-CIRU-STRIX-IU4.gguf` | 79,397,818,720 | 73.944981 | `c0ea11e4e24d0f909720b6c4e7462aa1e6fbf5e0f6acc796063f2aed4cf46ed0` |
+| `mtp/Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf` | 4,135,893,248 | 3.851851 | `e6743badef1f2619fcb5addfa4344a2a3368cb75214735117e3af80c70b80642` |
+| `ple/ple.payload.bin` | 52,429,053,952 | 48.828362 | `687fc742efb6888c6cd7cf9c80cb4b1ac8cb4707b9409c206699c43363e239b2` |
+| `ple/ple.manifest.json` | 115,213 | 0.000107 | `eb7404ce5ef056729452df10ee888e0c300cd0459121444be3313c51788cc171` |
+| `ple/ple.scale.bf16` | 2 | <0.000001 | `c7c58bd6007672362da2106fdbfaf9f50629e4bdf8598169c598027394ef9791` |
+
+The target and `ple/` are mandatory. The MTP file may be omitted only when speculative decoding is disabled.
+
+## Build the runtime
+
+The measured path is Linux x86-64, AMD ROCm/TheRock 10-class toolchain, `gfx1151`, on a Ryzen AI Max+ 395 / Radeon 8060S.
+
+```bash
+git clone --branch v1.0.0-h121 \
+  https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4.git runtime
+cd runtime
+ROCM_ROOT=/opt/rocm ./scripts/ciru/build-linux-amd.sh
+```
+
+Cross-platform documentation:
+
+- [Linux, distro dependencies, NixOS, and WSL2](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/blob/v1.0.0-h121/docs/BUILD_LINUX.md)
+- [Native Windows CPU compatibility](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/blob/v1.0.0-h121/docs/BUILD_WINDOWS.md)
+- [macOS Metal compatibility](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/blob/v1.0.0-h121/docs/BUILD_MACOS.md)
+
+Ubuntu/Debian, Fedora/RHEL, Arch, and WSL2/ROCDXG are source-compatible but unvalidated for this release. Native Windows CPU and macOS Metal are portability paths and do not include the validated Strix HIP or Linux P16/`O_DIRECT` performance path. On WSL2, keep `ple/ple.payload.bin` on the Linux ext4 filesystem, not `/mnt/c`.
+
+## Run with public production settings
+
+From the runtime checkout:
+
+```bash
+MODEL_DIR=/absolute/path/to/Qwen3.8-Flash-CIRU-STRIX-IU4 \
+  ./scripts/ciru/run-server.sh
+```
+
+The public launcher uses:
+
+- PLE cache: 4 GiB, 16 pager workers.
+- Prompt cache: enabled, 8 GiB RAM cache, idle-slot caching.
+- Context checkpoints: 32, minimum spacing 8,192 tokens.
+- Context/batch/microbatch: 262,144 / 2,048 / 512.
+- One slot, F16 target KV, Q8_0 draft KV, flash attention on.
+- MTP depth 3 with `p_split=0.10`.
+- Loopback-only bind at `127.0.0.1:8080`.
+
+It does **not** copy the evaluation harness's `--ctx-checkpoints 0`, slot erases, `cache_prompt:false`, fixed seed, temperature 0, `ignore_eos`, or output caps. Published prefill rows are cold/uncached; repeated-prefix public traffic is supposed to use the cache.
+
+Expanded command, API examples, no-MTP mode, and network hardening are in [RUNNING.md](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/blob/v1.0.0-h121/docs/RUNNING.md).
+
+## Recommended sampling
+
+Upstream Qwen recommendations:
+
+| Mode | Temperature | Top-p | Top-k | Min-p | Presence penalty | Repetition penalty |
+|---|---:|---:|---:|---:|---:|---:|
+| Thinking, default | 1.0 | 0.95 | 20 | 0 | 0 | 1.0 |
+| Non-thinking | 0.7 | 0.80 | 20 | 0 | 1.5 | 1.0 |
+
+For non-thinking mode, send `"chat_template_kwargs":{"enable_thinking":false}`. Keep `cache_prompt:true` for normal reusable chat traffic.
+
+## Quality results
+
+| Benchmark | Result | Coverage and caveat |
+|---|---:|---|
+| HumanEval | **160/164 (97.561%)** | Full; local-custom chat, first sample, no retries/repairs |
+| HumanEval+ | **155/164 (94.512%)** | Full; EvalPlus 0.1.10 |
+| ARC-Challenge | **1,143/1,172 (97.526%)** | Full EvalScope dataset |
+| ToolEval Standard | **115/138 (83.33%)** | 69 local-custom cases; 0 runtime/transport errors |
+| ToolEval Hard | **23/30 (76.67%)** | 15 local-custom hard cases; 0 runtime/transport errors |
+| GPQA-Diamond | **46/50 (92.0%)** | Sampled first/default-order 50 of 198; not a full score |
+| MMLU-Pro | **61/70 (87.143%)** | Sampled 5 from each of 14 subjects |
+| GSM8K | **97/100 (97.0%)** | Sampled local run |
+| IFEval strict | **92/100 (92.0%)** | Sampled prompt-level-strict local run |
+
+HumanEval serving averages were 211.108 prefill tok/s and 31.531 generation tok/s, with depth-1 MTP acceptance of 19,618/20,098 (97.612%) and zero API, validation, pager, or slot-erase failures.
+
+The sampled GPQA, MMLU-Pro, GSM8K, and IFEval rows are **not full-suite or leaderboard-comparable claims**. ToolEval is a local functional rubric and recorded injection/safety misses in standard TC33/TC34 and hard TC81; do not use the aggregate as evidence for unsupervised tool safety.
+
+## Performance
+
+H121 current-runtime matched row:
+
+| Prompt + generation | Cold prefill | Generation | TTFP | MTP accepted |
+|---|---:|---:|---:|---:|
+| 8,192 + 128 | **359.4267 tok/s** | **30.7970 tok/s** | 22.807 s | 84/128 |
+
+Cold context ladder, same artifacts on the pre-fix H111 runtime, 128 generated tokens per row:
+
+| Prompt tokens | Prefill tok/s | Generation tok/s |
+|---:|---:|---:|
+| 512 | 298.3149 | 29.9648 |
+| 2,048 | 376.9801 | 24.3850 |
+| 4,096 | 378.9664 | 22.8458 |
+| 8,192 | 372.8099 | 32.1142 |
+| 16,384 | 295.0188 | 28.3220 |
+| 32,768 | 228.2670 | 23.2864 |
+| 65,536 | 174.6093 | 14.7909 |
+| 131,072 | 121.0477 | 11.3400 |
+
+All context rows were exact-count, real-source, cold prompts with no logged error. H121 changes MTP continuation-buffer lifetime, not prefill, but only the 8K release row has been repeated post-fix. The configured context is 262,144; the tested ladder stops at 131,072.
+
+## BF16 and Q5 diagnostic comparison
+
+On a small 64-position, four-domain full-vocabulary panel, the CIRU model tied the size-matched Q5 control at **59/64 (92.19%) BF16 top-token agreement**. On the shared 60-token observed-next-token slice:
+
+- BF16 PPL: 2.017988
+- CIRU IU4 PPL: **2.242104 (+11.106%)**
+- Q5 PPL: 2.341209 (+16.017%)
+
+The CIRU arm had lower observed-token PPL on this tiny slice, while Q5 had better aggregate full-distribution forward KL (0.170264 vs 0.223406 nats). This is diagnostic evidence, not a broad perplexity benchmark.
+
+## Architecture and storage
+
+The 1,223 target tensors are stored as:
+
+| Type | Tensors |
+|---|---:|
+| F32 | 388 |
+| Q5_K | 328 |
+| Q8_0 | 290 |
+| Q4_1 | 144 |
+| Q5_1 | 48 |
+| BF16 | 25 |
+
+The 144 Q4_1 routed-expert tensors occupy 75,497,472,000 bytes. The protected core occupies 3,900,335,968 bytes. The external PLE payload is exact FP8 E4M3 with one BF16 scale. GGUF names were mechanically rewritten for this public release without requantizing tensor arrays; full evaluated-to-public identity mapping is in [PROVENANCE.md](https://github.com/ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4/blob/v1.0.0-h121/docs/PROVENANCE.md).
+
+## Hardware and operational requirements
+
+- Intended: Ryzen AI Max+ 395 / Radeon 8060S with 128 GiB unified memory.
+- Fast NVMe is mandatory for the external PLE pager.
+- Allow at least 160 GiB free storage for model files and verification/work space.
+- Linux is required for the measured P16/`O_DIRECT` PLE prefill path.
+- The model is text-only; no projector is shipped.
+- Bind to loopback unless you add authentication, TLS, request limits, and a reverse proxy.
+
+## Lineage, license, and credit
+
+- Text lineage: [`Qwen/Qwen3.8-Flash-Next@f5d08274bafd880402bd16f5e3e6c514136ec06c`](https://huggingface.co/Qwen/Qwen3.8-Flash-Next/tree/f5d08274bafd880402bd16f5e3e6c514136ec06c)
+- PLE lineage: [`Qwen/Qwen3.8-Flash-Next-FP8@bcd9f01ddc9cff2316eb84281bebcd5b058bddce`](https://huggingface.co/Qwen/Qwen3.8-Flash-Next-FP8/tree/bcd9f01ddc9cff2316eb84281bebcd5b058bddce)
+- Runtime base: [`ggml-org/llama.cpp@f5e85d43a048f3d5adefb4c5e29867d8077fba62`](https://github.com/ggml-org/llama.cpp/commit/f5e85d43a048f3d5adefb4c5e29867d8077fba62)
+
+Model artifacts are distributed under the included **Qwen Community License 1.0**. The runtime repository retains the MIT license and third-party notices of its components.
+
+Thanks to Qwen, ggml-org and the `llama.cpp` community, Ryan Monsurate for Qwen MTP integration work adapted by the release runtime, AMD's open-source ROCm ecosystem, and the contributors identified in `NOTICE.md`.
+
+CIRU is an independent community research project. AMD and Qwen marks belong to their respective owners; their appearance does not imply sponsorship or endorsement.
+
+## Citation
+
+```bibtex
+@software{ciru_qwen38_flash_strix_iu4_2026,
+  title        = {Qwen3.8-Flash-CIRU-STRIX-IU4},
+  author       = {{CIRU}},
+  year         = {2026},
+  month        = {8},
+  url          = {https://huggingface.co/jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4},
+  version      = {1.0.0-h121}
+}
+```
+

checksums.sha256

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+e6743badef1f2619fcb5addfa4344a2a3368cb75214735117e3af80c70b80642  mtp/Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf
+687fc742efb6888c6cd7cf9c80cb4b1ac8cb4707b9409c206699c43363e239b2  ple/ple.payload.bin
+eb7404ce5ef056729452df10ee888e0c300cd0459121444be3313c51788cc171  ple/ple.manifest.json
+c7c58bd6007672362da2106fdbfaf9f50629e4bdf8598169c598027394ef9791  ple/ple.scale.bf16
+

ple/ple.scale.bf16

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+Q9

profiles/strix-halo-production.env

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+# Audited production environment. Verify checksums before using STRICT_SHA=0.
+GGML_CUDA_Q41_MOE_FORCE_J=32
+GGML_QWEN4EXP_PLE_WORKERS=16
+GGML_QWEN4EXP_PLE_STRICT_SHA=0
+ROCBLAS_USE_HIPBLASLT=1
+