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 # Video files - compressed
 *.mp4 filter=lfs diff=lfs merge=lfs -text
 *.webm filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-cipher-control-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-cipher-core-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-control-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-core-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-ctr-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-key-expand-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-mix-columns-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-prng-clearing-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-sbox-sub-bytes-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/aes-shift-rows-sel-buf-rtl/environment/workspace/code/spec/aes_standard.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-block-encrypt-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-cmd-stage-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-core-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-ctr-drbg-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-main-sm-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/csrng-state-db-rtl/environment/workspace/code/docs/NIST.SP.800-90Ar1.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-bus-monitor-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-controller-fsm-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-core-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-fifo-adapter-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-fifos-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text
+tasks/rtl/i2c-target-fsm-rtl/environment/workspace/code/spec/UM10204.pdf filter=lfs diff=lfs merge=lfs -text

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README.md

@@ -0,0 +1,283 @@
+---
+pretty_name: TitanBench
+language:
+  - en
+license: apache-2.0
+size_categories:
+  - n<1K
+task_categories:
+  - text-generation
+tags:
+  - benchmark
+  - agents
+  - hardware
+  - hardware-design
+  - rtl
+  - uvm
+  - opentitan
+  - harbor
+  - functional-verification
+  - code-generation
+gated: true
+extra_gated_heading: "Acknowledge to access TitanBench"
+extra_gated_description: |
+  TitanBench evaluates agentic AI systems on hardware design and
+  verification tasks derived from the OpenTitan open-source SoC.
+  Please share a few details about your intended use before
+  downloading.
+extra_gated_fields:
+  Affiliation: text
+  Intended use:
+    type: select
+    options:
+      - Academic research
+      - Industry research
+      - Educational use
+      - label: Other
+        value: other
+extra_gated_button_content: "Acknowledge and request access"
+citation: |
+  @misc{titanbench_2026,
+        title={TitanBench: A Benchmark for Agentic RTL Design and Verification},
+        author={Anonymous},
+        year={2026},
+        url={https://huggingface.co/datasets/billshockley/titanbench}}
+---
+
+# TitanBench: A Benchmark for Agentic RTL Design and Verification
+
+TitanBench evaluates agentic AI systems on long-horizon chip design and verification (DV) workflows. Where existing hardware benchmarks focus on isolated coding or reasoning, TitanBench grades agents inside a containerised OpenTitan source tree using the project's production UVM verification environment. The agent must locate the relevant RTL, register specifications, testplan descriptions, and testbench infrastructure on its own — like a human engineer joining the project — and submit a solution that survives the upstream regression flow.
+
+This dataset is a **read-only mirror** of the harness repository. Source of truth: <<anonymous-repo-url>>. Issues / PRs go there.
+
+## Why this benchmark
+
+Verification accounts for **60–70 % of engineering effort in modern chip development**, and a single bug missed before tape-out can require a respin costing millions of dollars. Despite that, no public benchmark grades AI agents against production-grade UVM testbenches, coverage closure targets, and the full repository context that human DV engineers operate in. Existing efforts evaluate single-file RTL generation against author-supplied testbenches (`VerilogEval`, `RTLLM`), or repository-scale completion via edit similarity (`RTL-Repo`), or bug repair from known failures (`HWE-Bench`). TitanBench fills the gap: completion-based RTL and stimulus tasks evaluated directly against OpenTitan's production scoreboards, assertions, and functional coverage.
+
+## Composition
+
+The dataset has two top-level directories, each split into stimulus / RTL families:
+
+```
+tasks/    108 benchmark tasks
+  ├── stimulus/<ip>-tp-<testpoint>/   × 50    stimulus tasks
+  └── rtl/<ip>-rtl/, <ip>-<module>-rtl/   × 58    RTL tasks
+
+images/   docker build recipes for the per-IP / per-task base images
+  ├── stimulus/<ip>/         × 14    builds titanbench-<ip>:latest
+  └── rtl/<task>/             × 31    builds titanbench-<task>-rtl:latest
+                                       (the other 27 RTL tasks reuse a
+                                        sibling's base via FROM)
+```
+
+| Family | Count | Pattern | What the agent does |
+|---|---:|---|---|
+| **Stimulus generation** | **50** | `tasks/stimulus/<ip>-tp-<testpoint>/` | Writes a UVM `*_vseq.sv` for a redacted testpoint |
+| **RTL module completion** | **58** | `tasks/rtl/<ip>-rtl/`, `tasks/rtl/<ip>-<module>-rtl/` | Reconstructs synthesizable SystemVerilog from a stubbed module + spec |
+
+`images/` is build infrastructure — not benchmark tasks. The harness consumes it via `build_images.sh` to produce the per-IP / per-task base images that each task's `environment/Dockerfile` references via `FROM`. The stimulus and RTL families are independent benchmarks; reviewers may evaluate either independently.
+
+### IPs covered
+
+14 OpenTitan IPs: `adc_ctrl`, `aes`, `alert_handler`, `aon_timer`, `csrng`, `dma`, `gpio`, `hmac`, `i2c`, `keymgr`, `rv_timer`, `sram_ctrl`, `uart`, `usbdev`. The subset prioritises industry-standard archetypes — serial protocols, cryptographic datapaths, DMA, memory control, timers, and entropy — whose specifications generalise across SoC designs. We exclude blocks that are OpenTitan-specific (`lc_ctrl`, `rom_ctrl`, `rv_dm`, `keymgr_dpe`) and niche accelerators (`otbn`, `ascon`) that do not transfer cleanly to other SoCs.
+
+### Per-task statistics (summary)
+
+Detailed per-task statistics are in the paper. Headline ranges:
+
+| | Stimulus (n=50) | RTL (n=58) |
+|---|---|---|
+| Target SLOC | 46 – 597 (mean 228) | 30 – 6 484 (mean 673) |
+| Registers / module ports | 0 – 17 regs | 5 – 713 ports |
+| Visible RTL files | — | 6 – 134 (mean 84) |
+| Visible spec / register files | — | 2 – 14 (mean 7) |
+| Oracle coverage bins | 0 – 3 096 (mean 348) | n/a |
+| Agent runtime budget | 3 600 s | 3 600 s |
+
+## Task layout (harbor convention)
+
+```
+<task-id>/
+├── instruction.md       natural-language prompt for the agent
+├── task.toml            harbor metadata (timeouts, env, tags)
+├── environment/
+│   ├── Dockerfile       per-trial container (FROM the per-IP base image)
+│   └── docker-compose.yaml
+├── solution/            reference / oracle answer (hidden from agent at runtime)
+│   ├── solve.sh         deploys the oracle into the workspace
+│   ├── golden_sequences/        # *.sv  (stimulus tasks)
+│   └── *.sv                     # golden RTL  (RTL tasks)
+└── tests/
+    ├── test.sh          verifier — runs dvsim, scores correctness + coverage
+    └── oracle_coverage_bins.json    (stimulus tasks only)
+```
+
+## Task family 1: Stimulus generation
+
+For a given IP, a stimulus task targets one testpoint from the OpenTitan testplan. The agent is dropped into a container built from an **ablated** copy of the IP's DV environment: every reference sequence except the base/common ones is deleted, the `vseq_list` and `sim_cfg.hjson` are emptied accordingly, and coverage-exclusion files are removed so the agent cannot infer which bins are unreachable. Crucially the **testbench surface remains visible** — UVM env, scoreboard, RAL model, virtual interfaces — because navigating that surface is part of the task: the sequence must extend the right base class, access the right registers, and drive the DUT in a way the scoreboard can predict.
+
+The agent receives an `instruction.md` stating the testpoint's behavioural intent (Stimulus + Checks lists) and a build entry point. It must produce two artefacts: a virtual sequence (`<task>_vseq.sv`) and a per-task simulation config (`agent_sim_cfg.hjson`).
+
+**Scoring.** The verifier inserts both files into a clean OpenTitan checkout, registers the sequence in the IP's `vseq_list` and FuseSoC manifest, merges the per-task config into the master `sim_cfg.hjson`, and runs Xcelium under `--build-mode cov --reseed 1`. Reward is the uniform average of correctness and oracle-normalised coverage:
+
+```
+p = 1  iff  the test compiles, simulates, and reports zero scoreboard failures, else 0
+c = |B_oracle ∩ B_agent| / |B_oracle|     (cover-bin intersection ratio)
+R = 0.5·p + 0.5·c                          (in [0, 1])
+```
+
+`B_oracle` is the bin set hit by the upstream golden sequence at the same seed (precomputed and shipped per task as `tests/oracle_coverage_bins.json`). Coverage is normalised against oracle bins, not the full testbench universe — a single testpoint is not expected to close every bin.
+
+### Example: `aes-tp-core_fi`
+
+```markdown
+# AES: core_fi
+
+> Fault injection targeting the AES core block. Verify that injected faults are
+> detected and trigger appropriate error responses.
+
+Write a UVM sequence that extends `aes_base_vseq` to verify the above.
+
+**Output:** `/home/dev/workspace/sequences/aes_core_fi_vseq.sv`
+        and `/home/dev/workspace/agent_sim_cfg.hjson`
+
+**Run:** `/home/dev/scripts/run_test.sh aes_core_fi`
+```
+
+The agent must understand AES fault-injection semantics, locate `aes_base_vseq` and the relevant error-status registers, write a sequence that injects a fault and observes the resulting error response, and produce a `sim_cfg.hjson` selecting the new test name. The verifier scores against 89 oracle coverage bins.
+
+## Task family 2: RTL module completion
+
+Each RTL task targets one synthesizable SystemVerilog module (e.g. `aes_cipher_core`) or a full IP block. The agent works in a containerised workspace with `rtl/`, `pkg/`, `prim/`, `tlul/`, `spec/`, and `run/` directories. **All sibling modules within the IP are pre-implemented** with the oracle versions; the target module is shipped as a *stub* — license header, module declaration, port list, body removed. The accompanying `instruction.md` specifies the file path of the stub, lists key behaviours, fixes any hierarchical instance names the testbench refers to, and points to the build entry point (`make compile` in `run/`).
+
+The **UVM testbench is hidden from the agent** at generation time to prevent reverse-engineering the spec by inspecting test expectations. To compensate, every external specification linked from the OpenTitan documentation is bundled locally under `spec/`, alongside the relevant typedef files. Internet access is disabled in the container; we observed agents attempting to fetch the upstream OpenTitan repo from GitHub during early experiments.
+
+**Scoring.** The verifier copies the candidate RTL into a clean upstream checkout, commits, and runs the IP's unmodified `dvsim` simulation config under Xcelium with `--reseed 1`. The test list is filtered to the subset of upstream tests that score 1.0 against the oracle RTL at `reseed=1` — excluding (i) shared CIP infrastructure tests, (ii) security-countermeasure tests requiring bind files we do not ship, (iii) random-reset stress tests flaky at a single seed, and (iv) any remaining test whose oracle run does not converge to 1.0. Reward is the fraction of the surviving tests that pass:
+
+```
+R = n_passed / n_total ∈ [0, 1]
+```
+
+A perfect score on the oracle is achievable by construction at this filter, so any drop below 1.0 is attributable to the agent's implementation.
+
+### Example: `aes-rtl` (full-IP variant)
+
+```markdown
+# RTL Implementation Task: AES Full IP
+
+You are working in `/home/dev/workspace/code/`. The layout is:
+
+  rtl/    -- AES RTL modules (you must implement 24 core modules here)
+  prim/   -- OpenTitan primitive library (provided, read-only)
+  tlul/   -- TileLink-UL bus modules     (provided, read-only)
+  pkg/    -- Package files                (provided, read-only)
+  spec/   -- AES specification            (provided, read-only)
+  run/    -- Makefile and filelist for compilation
+
+Implement the 24 core AES RTL modules. Stubs with exact port signatures
+are provided in rtl/. Read spec/aes_standard.pdf for the AES algorithm
+specification.
+
+(... full instruction lists 24 module names + descriptions across
+cipher datapath, control FSMs, and integration utilities. See the
+task's instruction.md for the complete spec.)
+
+Build commands:
+    cd /home/dev/workspace/code/run
+    make compile
+```
+
+The full instruction.md (in the task dir) walks through 24 modules grouped by datapath / control FSMs / integration, describes the sparse-encoding (sp2v) FSM convention OpenTitan uses for fault tolerance, and lists boilerplate the agent should not re-implement. Per-module `<ip>-<module>-rtl/` variants target a single module each, with the rest of the IP pre-implemented.
+
+## Headline results
+
+We evaluated three frontier agentic systems with 5 trials per task at `--reseed 1`:
+
+| Model | Harness | Stimulus mean reward | RTL mean reward |
+|---|---|---:|---:|
+| Anthropic Claude Opus 4.6 | claude-code | TBD | TBD |
+| OpenAI GPT-5.3 Codex | codex (no web search) | TBD | TBD |
+| Moonshot Kimi K2.5 | mini-swe-agent (Fireworks) | TBD | TBD |
+
+No model approaches saturation on either benchmark. Reward declines monotonically with the static complexity score on both task families (see paper §4), and on stimulus generation the **testbench surface** axis (size + structure of the surrounding UVM environment) has the strongest single-axis correlation with reward — substantially exceeding the SLOC axis. What makes a TitanBench task hard is not the volume of code the agent must emit, but the size of the verification environment it must navigate to emit code that integrates correctly.
+
+Numbers are filled in once the model sweep over the 6 task swap-ins finishes.
+
+## Running the benchmark
+
+This dataset is the evaluation contract — task definitions, oracles, verifier specs. Actually running it requires the **harness repo**, which provides the OpenTitan submodule, agent runners, and Cadence tool integration:
+
+```bash
+# 1. Download the harness tarball from <anonymous-repo-url>, extract, cd in.
+
+# 2. Fetch OpenTitan at the pinned SHA
+bash fetch_opentitan.sh
+
+# 3. Pull this dataset — populates tasks/ AND images/ at the harness root
+hf download billshockley/titanbench --repo-type dataset \
+    --include "tasks/*" --include "images/*" --local-dir .
+
+# 4. Build base images (titanbench-base + 14 stimulus + 31 RTL)
+bash build_images.sh
+
+# 5. Run a single task end-to-end
+export XCELIUM_PATH=/opt/cadence/installs/XCELIUM2403
+export VMANAGER_PATH=/opt/cadence/installs/VMANAGER2403
+export LM_LICENSE_FILE=5280@your-license-server
+export PYTHONPATH=runners
+
+# Stimulus: -p tasks/stimulus
+harbor run -p tasks/stimulus -a claude-code \
+    -m anthropic/claude-opus-4-6 \
+    -t aes-tp-core_fi --debug -y
+
+# RTL: -p tasks/rtl
+harbor run -p tasks/rtl -a claude-code \
+    -m anthropic/claude-opus-4-6 \
+    -t aes-rtl --debug -y
+```
+
+**Required commercial tools** (not provided): Cadence Xcelium 2403+ and Cadence vManager / IMC 2403+. The Xcelium dependency is a hard prerequisite — UVM coverage scoring at the fidelity TitanBench requires is not currently available on open-source simulators.
+
+## Source provenance
+
+- **Derived from**: [OpenTitan](https://github.com/lowRISC/opentitan) (Apache-2.0). The `opentitan/` submodule is pinned to a specific upstream SHA in the harness repo; that SHA is the reproducibility contract.
+- **Selection**: Stimulus testpoints were drawn from each IP's machine-readable `data/<ip>_testplan.hjson`. The 50-task subset was selected per-IP by ranking on `z(golden_loc) + z(registers_touched)` (independent within each IP) and keeping the top-K to match a pre-allocated budget summing to 50. RTL tasks are one full-IP entry per IP plus per-module sub-tasks for IPs whose top-level module is too large to attempt as a single task. Tasks where the upstream golden artefact does not reach reward = 1.0 at `reseed=1` were excluded; replacement candidates were oracle-validated before inclusion.
+- **No human annotation**: TitanBench is constructed mechanically from upstream artefacts. The `instruction.md` files for stimulus tasks paraphrase the testpoint's existing testplan entry; for RTL tasks they list module names and known interface conventions.
+
+## Limitations & Responsible AI
+
+- **Language**: English instructions only; no multilingual variants.
+- **Domain restrictions**: OpenTitan-specific. Findings on TitanBench should not be assumed to generalise to other RTL families (DSPs, ML accelerators, GPUs) without further evaluation.
+- **Closed-source tooling**: Cadence Xcelium is a hard requirement to run the verifier. This is a substantial barrier for academic reviewers and we treat it as a Limitation rather than a Mitigation.
+- **Coverage methodology**: We score normalised functional + line/toggle/FSM coverage as exposed by Xcelium / vManager. Formal verification, equivalence checking, and PPA (power / performance / area) are *not* part of the reward. A perfect TitanBench score does not certify a design for tape-out.
+- **Selection bias**: Tasks skew toward security-critical IPs (AES, KEYMGR, CSRNG, HMAC) because those have the most extensive UVM environments in OpenTitan. Mileage on simple peripherals will not reflect performance on those blocks.
+- **Contamination risk**: OpenTitan source is public. We mitigate by hiding the testbench at RTL-task time, disabling internet in the container, and grading on execution rather than string match — but we cannot fully exclude memorisation effects. Future versions may use unreleased OpenTitan revisions.
+- **No personal or sensitive data**: The dataset is synthetic hardware-engineering content only.
+- **Synthetic data**: `false`. All artefacts derive from OpenTitan's human-engineered RTL and DV environment.
+- **Intended use**: Comparing agent capability on hardware DV / RTL completion under a controlled budget. Not validated for: model training, formal verification, generalisation to non-UVM flows, generalisation outside OpenTitan-style CIP designs.
+- **Social impact**: Positive — standardised public benchmark for LLM-driven HDL/DV. Negative — risk of overstating production-readiness if results are reported without the limitations above.
+
+## Maintenance
+
+- **Maintainer**: TitanBench Team (see citation below for current authorship).
+- **Issues / PRs**: <<anonymous-repo-url>>.
+- **Versioning**: Dataset is versioned via git commits on this HF repo. The harness repo's submodule pin (`opentitan/`) and build flags determine which tests run; a fixed pair of (HF SHA, harness SHA) is the reproducibility contract.
+- **Plan**: Frozen at submission time for the NeurIPS review window. Post-acceptance updates batch into tagged releases (e.g. `v1.0`, `v1.1`).
+
+## Citation
+
+```bibtex
+@misc{titanbench_2026,
+      title={TitanBench: A Benchmark for Agentic RTL Design and Verification},
+      author={Anonymous},
+      year={2026},
+      url={https://huggingface.co/datasets/billshockley/titanbench}
+}
+```
+
+OpenTitan should be cited separately if you use the dataset in published work — see the [OpenTitan project](https://opentitan.org/) for the canonical bibliographic entry.
+
+## License
+
+Apache-2.0. Tasks derive from the upstream OpenTitan project (also Apache-2.0). See `LICENSE` for the full text.

images/rtl/adc_ctrl-core/Dockerfile

@@ -0,0 +1,30 @@
+# TitanBench ADC_CTRL-CORE-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/adc_ctrl-core/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-adc-ctrl-core-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+COPY --from=titanbench images/rtl/adc_ctrl-core/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench adc_ctrl-core-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/adc_ctrl-core/scripts/setup_workspace.sh

@@ -0,0 +1,250 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ADC_CTRL-CORE-RTL workspace with infrastructure + oracle RTL for
+# every module except adc_ctrl_core.sv (which is overlaid as a stub by the
+# environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating ADC_CTRL-CORE-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules ────────────────────────────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  prim_lc_sync.sv
+  prim_edge_detector.sv
+  prim_reg_cdc.sv
+  prim_reg_cdc_arb.sv
+  prim_pulse_sync.sv
+  prim_sync_reqack.sv
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules ────────────────────────────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ───────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"      "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"    "$WS/pkg/"
+
+cat > "$WS/pkg/ast_pkg.sv" << 'ASTPKG'
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Minimal ast_pkg stub exposing the ADC interface types used by adc_ctrl.
+package ast_pkg;
+  parameter int unsigned AdcChannels  = 2;
+  parameter int unsigned AdcDataWidth = 10;
+
+  typedef struct packed {
+    logic [AdcChannels-1:0]  channel_sel;
+    logic                    pd;
+  } adc_ast_req_t;
+
+  typedef struct packed {
+    logic [AdcDataWidth-1:0] data;
+    logic                    data_valid;
+  } adc_ast_rsp_t;
+endpackage
+ASTPKG
+
+echo "  Copied packages"
+
+# ── Spec documentation ──────────────────────────────────────────────
+echo "[4/6] Copying spec documentation..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/theory_of_operation.md"     "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/registers.md"               "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/interfaces.md"              "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/programmers_guide.md"       "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/adc_overview.svg"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/debug_cable_regions.svg"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/data/adc_ctrl_testplan.hjson"   "$WS/spec/"
+echo "  Copied spec docs"
+
+# ── RTL: boilerplate + oracle for every module except adc_ctrl_core.sv ─
+echo "[5/6] Copying RTL (all modules except adc_ctrl_core.sv)..."
+ADC_RTL="$REPO_TOP/hw/ip/adc_ctrl/rtl"
+cp "$ADC_RTL/adc_ctrl.sv"         "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_reg_top.sv" "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_fsm.sv"     "$WS/rtl/"   # oracle — agent must not modify
+cp "$ADC_RTL/adc_ctrl_intr.sv"    "$WS/rtl/"   # oracle — agent must not modify
+echo "  Copied 4 RTL files (adc_ctrl_core.sv is overlaid as a stub)"
+
+# ── Run directory ────────────────────────────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/ast_pkg.sv
+../pkg/adc_ctrl_reg_pkg.sv
+../pkg/adc_ctrl_pkg.sv
+
+// SECDED
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim leaf modules
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+
+// ADC_CTRL
+../rtl/adc_ctrl_reg_top.sv
+../rtl/adc_ctrl_fsm.sv
+../rtl/adc_ctrl_intr.sv
+../rtl/adc_ctrl_core.sv
+../rtl/adc_ctrl.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. adc_ctrl_core.sv stub added by environment Dockerfile. ==="

images/rtl/adc_ctrl-fsm/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench ADC_CTRL-FSM-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/adc_ctrl-fsm/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-adc-ctrl-fsm-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/adc_ctrl-fsm/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench adc_ctrl-fsm-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/adc_ctrl-fsm/scripts/setup_workspace.sh

@@ -0,0 +1,252 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ADC_CTRL-FSM-RTL workspace with infrastructure + oracle RTL for
+# every module except adc_ctrl_fsm.sv (which is overlaid as a stub by the
+# environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating ADC_CTRL-FSM-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules ────────────────────────────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  prim_lc_sync.sv
+  prim_edge_detector.sv
+  prim_reg_cdc.sv
+  prim_reg_cdc_arb.sv
+  prim_pulse_sync.sv
+  prim_sync_reqack.sv
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules ────────────────────────────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ───────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"      "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"    "$WS/pkg/"
+
+# Minimal ast_pkg exposing only the ADC-relevant types adc_ctrl needs.
+cat > "$WS/pkg/ast_pkg.sv" << 'ASTPKG'
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Minimal ast_pkg stub exposing the ADC interface types used by adc_ctrl.
+// This replaces the full earlgrey ast_pkg.sv for local elaboration feedback.
+package ast_pkg;
+  parameter int unsigned AdcChannels  = 2;
+  parameter int unsigned AdcDataWidth = 10;
+
+  typedef struct packed {
+    logic [AdcChannels-1:0]  channel_sel;
+    logic                    pd;
+  } adc_ast_req_t;
+
+  typedef struct packed {
+    logic [AdcDataWidth-1:0] data;
+    logic                    data_valid;
+  } adc_ast_rsp_t;
+endpackage
+ASTPKG
+
+echo "  Copied packages"
+
+# ── Spec documentation ──────────────────────────────────────────────
+echo "[4/6] Copying spec documentation..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/theory_of_operation.md"     "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/registers.md"               "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/interfaces.md"              "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/programmers_guide.md"       "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/adc_overview.svg"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/debug_cable_regions.svg"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/data/adc_ctrl_testplan.hjson"   "$WS/spec/"
+echo "  Copied spec docs"
+
+# ── RTL: boilerplate + oracle for every module except adc_ctrl_fsm.sv ─
+echo "[5/6] Copying RTL (all modules except adc_ctrl_fsm.sv)..."
+ADC_RTL="$REPO_TOP/hw/ip/adc_ctrl/rtl"
+cp "$ADC_RTL/adc_ctrl.sv"         "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_reg_top.sv" "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_core.sv"    "$WS/rtl/"   # oracle — agent must not modify
+cp "$ADC_RTL/adc_ctrl_intr.sv"    "$WS/rtl/"   # oracle — agent must not modify
+echo "  Copied 4 RTL files (adc_ctrl_fsm.sv is overlaid as a stub)"
+
+# ── Run directory ────────────────────────────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/ast_pkg.sv
+../pkg/adc_ctrl_reg_pkg.sv
+../pkg/adc_ctrl_pkg.sv
+
+// SECDED
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim leaf modules
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+
+// ADC_CTRL
+../rtl/adc_ctrl_reg_top.sv
+../rtl/adc_ctrl_fsm.sv
+../rtl/adc_ctrl_intr.sv
+../rtl/adc_ctrl_core.sv
+../rtl/adc_ctrl.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. adc_ctrl_fsm.sv stub added by environment Dockerfile. ==="

images/rtl/adc_ctrl-intr/Dockerfile

@@ -0,0 +1,30 @@
+# TitanBench ADC_CTRL-INTR-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/adc_ctrl-intr/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-adc-ctrl-intr-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+COPY --from=titanbench images/rtl/adc_ctrl-intr/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench adc_ctrl-intr-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/adc_ctrl-intr/scripts/setup_workspace.sh

@@ -0,0 +1,250 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ADC_CTRL-INTR-RTL workspace with infrastructure + oracle RTL for
+# every module except adc_ctrl_intr.sv (which is overlaid as a stub by the
+# environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating ADC_CTRL-INTR-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules ────────────────────────────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  prim_lc_sync.sv
+  prim_edge_detector.sv
+  prim_reg_cdc.sv
+  prim_reg_cdc_arb.sv
+  prim_pulse_sync.sv
+  prim_sync_reqack.sv
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules ────────────────────────────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ───────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/rtl/adc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"      "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"    "$WS/pkg/"
+
+cat > "$WS/pkg/ast_pkg.sv" << 'ASTPKG'
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Minimal ast_pkg stub exposing the ADC interface types used by adc_ctrl.
+package ast_pkg;
+  parameter int unsigned AdcChannels  = 2;
+  parameter int unsigned AdcDataWidth = 10;
+
+  typedef struct packed {
+    logic [AdcChannels-1:0]  channel_sel;
+    logic                    pd;
+  } adc_ast_req_t;
+
+  typedef struct packed {
+    logic [AdcDataWidth-1:0] data;
+    logic                    data_valid;
+  } adc_ast_rsp_t;
+endpackage
+ASTPKG
+
+echo "  Copied packages"
+
+# ── Spec documentation ──────────────────────────────────────────────
+echo "[4/6] Copying spec documentation..."
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/theory_of_operation.md"     "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/registers.md"               "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/interfaces.md"              "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/programmers_guide.md"       "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/adc_overview.svg"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/doc/debug_cable_regions.svg"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/adc_ctrl/data/adc_ctrl_testplan.hjson"   "$WS/spec/"
+echo "  Copied spec docs"
+
+# ── RTL: boilerplate + oracle for every module except adc_ctrl_intr.sv ─
+echo "[5/6] Copying RTL (all modules except adc_ctrl_intr.sv)..."
+ADC_RTL="$REPO_TOP/hw/ip/adc_ctrl/rtl"
+cp "$ADC_RTL/adc_ctrl.sv"         "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_reg_top.sv" "$WS/rtl/"
+cp "$ADC_RTL/adc_ctrl_fsm.sv"     "$WS/rtl/"   # oracle — agent must not modify
+cp "$ADC_RTL/adc_ctrl_core.sv"    "$WS/rtl/"   # oracle — agent must not modify
+echo "  Copied 4 RTL files (adc_ctrl_intr.sv is overlaid as a stub)"
+
+# ── Run directory ────────────────────────────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/ast_pkg.sv
+../pkg/adc_ctrl_reg_pkg.sv
+../pkg/adc_ctrl_pkg.sv
+
+// SECDED
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim leaf modules
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+
+// ADC_CTRL
+../rtl/adc_ctrl_reg_top.sv
+../rtl/adc_ctrl_fsm.sv
+../rtl/adc_ctrl_intr.sv
+../rtl/adc_ctrl_core.sv
+../rtl/adc_ctrl.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. adc_ctrl_intr.sv stub added by environment Dockerfile. ==="

images/rtl/adc_ctrl/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench ADC_CTRL-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/adc_ctrl/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-adc_ctrl-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench tasks_missing_rtl/adc_ctrl-rtl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench adc_ctrl-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/adc_ctrl/scripts/setup_workspace.sh

@@ -0,0 +1,116 @@
+#!/bin/bash
+set -euo pipefail
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+ADC_SRC="$REPO_TOP/hw/ip/adc_ctrl"
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv prim_subreg_pkg.sv prim_util_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh prim_flop_macros.sv
+  prim_cdc_rand_delay.sv prim_onehot_enc.sv prim_onehot_check.sv prim_subreg.sv prim_subreg_arb.sv
+  prim_subreg_ext.sv prim_reg_we_check.sv prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_intr_hw.sv prim_lc_sync.sv prim_edge_detector.sv prim_reg_cdc.sv
+  prim_reg_cdc_arb.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=(prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv)
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do cp "$TLUL_SRC/$f" "$WS/tlul/"; done
+cp "$ADC_SRC/rtl/adc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$ADC_SRC/rtl/adc_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv" "$WS/pkg/"
+cat > "$WS/pkg/ast_pkg.sv" <<'ASTPKG'
+package ast_pkg;
+  parameter int unsigned AdcChannels  = 2;
+  parameter int unsigned AdcDataWidth = 10;
+  typedef struct packed {
+    logic [AdcChannels-1:0]  channel_sel;
+    logic                    pd;
+  } adc_ast_req_t;
+  typedef struct packed {
+    logic [AdcDataWidth-1:0] data;
+    logic                    data_valid;
+  } adc_ast_rsp_t;
+endpackage
+ASTPKG
+for f in theory_of_operation.md registers.md interfaces.md programmers_guide.md adc_overview.svg debug_cable_regions.svg; do cp "$ADC_SRC/doc/$f" "$WS/spec/" 2>/dev/null || true; done
+cp "$ADC_SRC/data/adc_ctrl_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+cp "$ADC_SRC/rtl/adc_ctrl.sv" "$WS/rtl/"
+cp "$ADC_SRC/rtl/adc_ctrl_reg_top.sv" "$WS/rtl/"
+cat > "$WS/run/filelist.f" <<'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/ast_pkg.sv
+../pkg/adc_ctrl_reg_pkg.sv
+../pkg/adc_ctrl_pkg.sv
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../rtl/adc_ctrl_reg_top.sv
+../rtl/adc_ctrl_fsm.sv
+../rtl/adc_ctrl_intr.sv
+../rtl/adc_ctrl_core.sv
+../rtl/adc_ctrl.sv
+FILELIST
+cat > "$WS/run/Makefile" <<'MAKEFILE'
+.PHONY: compile clean
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate -f filelist.f -timescale 1ns/1ps -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE

images/rtl/aes/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench AES-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/aes/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-aes-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/aes/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench aes-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/aes/scripts/setup_workspace.sh

@@ -0,0 +1,343 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the AES-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, and spec docs — but NOT ground-truth RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating AES-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ─────────────────────────────
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+# Files from hw/ip/prim/rtl/
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_cipher_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_trivium_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # FIFO / memory
+  prim_fifo_assert.svh
+  prim_fifo_sync.sv
+  prim_fifo_sync_cnt.sv
+  prim_packer_fifo.sv
+  prim_ram_1p_adv.sv
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_sparse_fsm_flop.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_onehot_mux.sv
+  prim_count.sv
+  prim_diff_decode.sv
+  prim_blanker.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  # Security
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_const.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # Synchronization
+  prim_lc_dec.sv
+  prim_lc_sync.sv
+  prim_sync_reqack.sv
+  prim_sync_reqack_data.sv
+  prim_mubi4_dec.sv
+  prim_mubi4_sender.sv
+  prim_mubi4_sync.sv
+  prim_mubi8_dec.sv
+  prim_mubi8_sender.sv
+  prim_mubi8_sync.sv
+  # Crypto / LFSR
+  prim_dom_and_2share.sv
+  prim_double_lfsr.sv
+  prim_edn_req.sv
+  prim_gf_mult.sv
+  prim_lfsr.sv
+  prim_subst_perm.sv
+  prim_trivium.sv
+  # Arbitration
+  prim_arbiter_fixed.sv
+  prim_arbiter_tree.sv
+  # SECDED (integrity)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc headers
+  prim_util_memload.svh
+)
+
+# Files from hw/ip/prim_generic/rtl/ (technology-independent implementations)
+PRIM_GENERIC_FILES=(
+  prim_and2.sv
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_flop_en.sv
+  prim_ram_1p.sv
+  prim_ram_1p_pkg.sv
+  prim_xnor2.sv
+  prim_xor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ─────────────────────────────
+echo "[2/5] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files (from various IPs) ────────────────────────────────
+echo "[3/5] Copying package files..."
+
+# AES-specific
+cp "$REPO_TOP/hw/ip/aes/rtl/aes_pkg.sv"               "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/aes/rtl/aes_reg_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/aes/rtl/aes_sbox_canright_pkg.sv"  "$WS/pkg/"
+
+# CSRNG / EDN / Entropy / KeyMgr dependencies
+cp "$REPO_TOP/hw/ip/csrng/rtl/csrng_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/csrng/rtl/csrng_reg_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/entropy_src/rtl/entropy_src_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv"      "$WS/pkg/"
+
+# Shared
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+
+echo "  Copied 14 package files"
+
+# ── Spec documentation (from hw/ip/aes/doc/) ────────────────────────
+echo "[4/5] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/aes/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/doc/programmers_guide.md"   "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/data/aes_testplan.hjson"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/data/aes.hjson"             "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aes/data/aes_sec_cm_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+echo "  Copied spec docs"
+
+# ── Run directory (filelist + Makefile) ──────────────────────────────
+echo "[5/6] Creating run directory..."
+mkdir -p "$WS/run"
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters - dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_ram_1p_pkg.sv
+../prim/prim_cipher_pkg.sv
+../prim/prim_trivium_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/entropy_src_pkg.sv
+../pkg/csrng_reg_pkg.sv
+../pkg/csrng_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/keymgr_reg_pkg.sv
+../pkg/keymgr_pkg.sv
+../pkg/aes_sbox_canright_pkg.sv
+../pkg/aes_reg_pkg.sv
+../pkg/aes_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_and2.sv
+../prim/prim_xor2.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_en.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_onehot_mux.sv
+../prim/prim_count.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_sec_anchor_const.sv
+../prim/prim_diff_decode.sv
+../prim/prim_alert_sender.sv
+../prim/prim_lc_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_sync_reqack_data.sv
+../prim/prim_lfsr.sv
+../prim/prim_trivium.sv
+../prim/prim_blanker.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_gf_mult.sv
+
+// AES RTL (boilerplate - provided)
+../rtl/aes_reg_top.sv
+../rtl/aes_ctrl_reg_shadowed.sv
+../rtl/aes_ctrl_gcm_reg_shadowed.sv
+../rtl/aes_reg_status.sv
+../rtl/aes_ghash.sv
+../rtl/aes_ghash_wrap.sv
+
+// AES RTL (agent-written)
+../rtl/aes_sbox_lut.sv
+../rtl/aes_sbox.sv
+../rtl/aes_sub_bytes.sv
+../rtl/aes_shift_rows.sv
+../rtl/aes_mix_single_column.sv
+../rtl/aes_mix_columns.sv
+../rtl/aes_key_expand.sv
+../rtl/aes_reduced_round.sv
+../rtl/aes_sel_buf_chk.sv
+../rtl/aes_prng_clearing.sv
+../rtl/aes_cipher_control_fsm_p.sv
+../rtl/aes_cipher_control_fsm_n.sv
+../rtl/aes_cipher_control_fsm.sv
+../rtl/aes_cipher_control.sv
+../rtl/aes_cipher_core.sv
+../rtl/aes_ctr_fsm_p.sv
+../rtl/aes_ctr_fsm_n.sv
+../rtl/aes_ctr_fsm.sv
+../rtl/aes_ctr.sv
+../rtl/aes_control_fsm_p.sv
+../rtl/aes_control_fsm_n.sv
+../rtl/aes_control_fsm.sv
+../rtl/aes_control.sv
+../rtl/aes_core.sv
+../rtl/aes.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ─────────────────────────────────────────────────────
+echo "[6/6] Verifying workspace..."
+
+EXPECTED_DIRS=(prim tlul pkg spec run)
+for d in "${EXPECTED_DIRS[@]}"; do
+  count=$(find "$WS/$d" -type f | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stubs, PDFs, and run/ added by environment Dockerfile. ==="

images/rtl/alert_handler-accu/Dockerfile

@@ -0,0 +1,29 @@
+# TitanBench ALERT_HANDLER-ACCU-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# docker build -f images/rtl/alert_handler-accu/image/Dockerfile \
+#   --build-context titanbench=/path/to/titanbench \
+#   -t titanbench-alert_handler-accu-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore autogen files for non-Earlgrey tops that .dockerignore excludes
+# but fusesoc needs when building alert_handler DV.
+COPY --from=titanbench joe_exp/ot_autogen_fix/hw/ /home/dev/src/hw/
+
+COPY --from=titanbench images/rtl/alert_handler-accu/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-accu-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler-accu/scripts/setup_workspace.sh

@@ -0,0 +1,200 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ALERT_HANDLER-ACCU-RTL workspace with infrastructure + oracle RTL for every
+# module except alert_handler_accu.sv (overlaid as a stub by the environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+
+echo "=== TitanBench: Populating ALERT_HANDLER-ACCU-RTL workspace ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv
+  prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh
+  prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv
+  prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv
+  prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_mubi4_sync.sv
+  prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv
+  prim_reg_cdc.sv prim_reg_cdc_arb.sv
+  prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=( prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv )
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || echo "  missing $f"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+echo "  Copied prims"
+
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || echo "  missing $f"
+done
+
+echo "[3/6] Copying package files..."
+cp "$AH_RTL/alert_handler_reg_pkg.sv"                  "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv"                      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+
+echo "[4/6] Copying spec documentation..."
+cp "$AH_DOC/theory_of_operation.md" "$WS/spec/"
+cp "$AH_DOC/programmers_guide.md"   "$WS/spec/"
+cp "$AH_DOC/alert_handler_alert_rxtx.svg"       "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_block_diagram.svg"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_escalation_rxtx.svg"  "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lpg_ctrl.svg"         "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lp_overview.svg"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_receiver_fsm.svg"     "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_testplan.hjson"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson"                   "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/checklist.md"                            "$WS/spec/" 2>/dev/null || true
+
+cp "$AH_RTL/../README.md"                        "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+
+echo "[5/6] Copying RTL (all except alert_handler_accu.sv)..."
+for f in alert_handler.sv alert_handler_reg_top.sv alert_handler_reg_wrap.sv \
+         alert_handler_accu.sv alert_handler_class.sv alert_handler_esc_timer.sv \
+         alert_handler_lpg_ctrl.sv alert_handler_ping_timer.sv; do
+  if [ "$f" = "alert_handler_accu.sv" ]; then
+    echo "  skipping $f (agent stub)"
+    continue
+  fi
+  cp "$AH_RTL/$f" "$WS/rtl/"
+done
+
+echo "[6/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  echo "  $d/: $(find $WS/$d -type f 2>/dev/null | wc -l) files"
+done
+echo ""
+echo "=== Workspace populated. alert_handler_accu.sv stub added by environment Dockerfile. ==="

images/rtl/alert_handler-class/Dockerfile

@@ -0,0 +1,29 @@
+# TitanBench ALERT_HANDLER-CLASS-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# docker build -f images/rtl/alert_handler-class/image/Dockerfile \
+#   --build-context titanbench=/path/to/titanbench \
+#   -t titanbench-alert_handler-class-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore autogen files for non-Earlgrey tops that .dockerignore excludes
+# but fusesoc needs when building alert_handler DV.
+COPY --from=titanbench joe_exp/ot_autogen_fix/hw/ /home/dev/src/hw/
+
+COPY --from=titanbench images/rtl/alert_handler-class/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-class-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler-class/scripts/setup_workspace.sh

@@ -0,0 +1,200 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ALERT_HANDLER-CLASS-RTL workspace with infrastructure + oracle RTL for every
+# module except alert_handler_class.sv (overlaid as a stub by the environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+
+echo "=== TitanBench: Populating ALERT_HANDLER-CLASS-RTL workspace ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv
+  prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh
+  prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv
+  prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv
+  prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_mubi4_sync.sv
+  prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv
+  prim_reg_cdc.sv prim_reg_cdc_arb.sv
+  prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=( prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv )
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || echo "  missing $f"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+echo "  Copied prims"
+
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || echo "  missing $f"
+done
+
+echo "[3/6] Copying package files..."
+cp "$AH_RTL/alert_handler_reg_pkg.sv"                  "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv"                      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+
+echo "[4/6] Copying spec documentation..."
+cp "$AH_DOC/theory_of_operation.md" "$WS/spec/"
+cp "$AH_DOC/programmers_guide.md"   "$WS/spec/"
+cp "$AH_DOC/alert_handler_alert_rxtx.svg"       "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_block_diagram.svg"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_escalation_rxtx.svg"  "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lpg_ctrl.svg"         "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lp_overview.svg"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_receiver_fsm.svg"     "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_testplan.hjson"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson"                   "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/checklist.md"                            "$WS/spec/" 2>/dev/null || true
+
+cp "$AH_RTL/../README.md"                        "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+
+echo "[5/6] Copying RTL (all except alert_handler_class.sv)..."
+for f in alert_handler.sv alert_handler_reg_top.sv alert_handler_reg_wrap.sv \
+         alert_handler_accu.sv alert_handler_class.sv alert_handler_esc_timer.sv \
+         alert_handler_lpg_ctrl.sv alert_handler_ping_timer.sv; do
+  if [ "$f" = "alert_handler_class.sv" ]; then
+    echo "  skipping $f (agent stub)"
+    continue
+  fi
+  cp "$AH_RTL/$f" "$WS/rtl/"
+done
+
+echo "[6/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  echo "  $d/: $(find $WS/$d -type f 2>/dev/null | wc -l) files"
+done
+echo ""
+echo "=== Workspace populated. alert_handler_class.sv stub added by environment Dockerfile. ==="

images/rtl/alert_handler-esc-timer/Dockerfile

@@ -0,0 +1,29 @@
+# TitanBench ALERT_HANDLER-ESC-TIMER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# docker build -f images/rtl/alert_handler-esc-timer/image/Dockerfile \
+#   --build-context titanbench=/path/to/titanbench \
+#   -t titanbench-alert_handler-esc-timer-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore autogen files for non-Earlgrey tops that .dockerignore excludes
+# but fusesoc needs when building alert_handler DV.
+COPY --from=titanbench joe_exp/ot_autogen_fix/hw/ /home/dev/src/hw/
+
+COPY --from=titanbench images/rtl/alert_handler-esc-timer/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-esc-timer-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler-esc-timer/scripts/setup_workspace.sh

@@ -0,0 +1,200 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ALERT_HANDLER-ESC-TIMER-RTL workspace with infrastructure + oracle RTL for every
+# module except alert_handler_esc_timer.sv (overlaid as a stub by the environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+
+echo "=== TitanBench: Populating ALERT_HANDLER-ESC-TIMER-RTL workspace ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv
+  prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh
+  prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv
+  prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv
+  prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_mubi4_sync.sv
+  prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv
+  prim_reg_cdc.sv prim_reg_cdc_arb.sv
+  prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=( prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv )
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || echo "  missing $f"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+echo "  Copied prims"
+
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || echo "  missing $f"
+done
+
+echo "[3/6] Copying package files..."
+cp "$AH_RTL/alert_handler_reg_pkg.sv"                  "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv"                      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+
+echo "[4/6] Copying spec documentation..."
+cp "$AH_DOC/theory_of_operation.md" "$WS/spec/"
+cp "$AH_DOC/programmers_guide.md"   "$WS/spec/"
+cp "$AH_DOC/alert_handler_alert_rxtx.svg"       "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_block_diagram.svg"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_escalation_rxtx.svg"  "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lpg_ctrl.svg"         "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lp_overview.svg"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_receiver_fsm.svg"     "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_testplan.hjson"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson"                   "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/checklist.md"                            "$WS/spec/" 2>/dev/null || true
+
+cp "$AH_RTL/../README.md"                        "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+
+echo "[5/6] Copying RTL (all except alert_handler_esc_timer.sv)..."
+for f in alert_handler.sv alert_handler_reg_top.sv alert_handler_reg_wrap.sv \
+         alert_handler_accu.sv alert_handler_class.sv alert_handler_esc_timer.sv \
+         alert_handler_lpg_ctrl.sv alert_handler_ping_timer.sv; do
+  if [ "$f" = "alert_handler_esc_timer.sv" ]; then
+    echo "  skipping $f (agent stub)"
+    continue
+  fi
+  cp "$AH_RTL/$f" "$WS/rtl/"
+done
+
+echo "[6/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  echo "  $d/: $(find $WS/$d -type f 2>/dev/null | wc -l) files"
+done
+echo ""
+echo "=== Workspace populated. alert_handler_esc_timer.sv stub added by environment Dockerfile. ==="

images/rtl/alert_handler-lpg-ctrl/Dockerfile

@@ -0,0 +1,29 @@
+# TitanBench ALERT_HANDLER-LPG-CTRL-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# docker build -f images/rtl/alert_handler-lpg-ctrl/image/Dockerfile \
+#   --build-context titanbench=/path/to/titanbench \
+#   -t titanbench-alert_handler-lpg-ctrl-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore autogen files for non-Earlgrey tops that .dockerignore excludes
+# but fusesoc needs when building alert_handler DV.
+COPY --from=titanbench joe_exp/ot_autogen_fix/hw/ /home/dev/src/hw/
+
+COPY --from=titanbench images/rtl/alert_handler-lpg-ctrl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-lpg-ctrl-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler-lpg-ctrl/scripts/setup_workspace.sh

@@ -0,0 +1,200 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ALERT_HANDLER-LPG-CTRL-RTL workspace with infrastructure + oracle RTL for every
+# module except alert_handler_lpg_ctrl.sv (overlaid as a stub by the environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+
+echo "=== TitanBench: Populating ALERT_HANDLER-LPG-CTRL-RTL workspace ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv
+  prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh
+  prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv
+  prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv
+  prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_mubi4_sync.sv
+  prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv
+  prim_reg_cdc.sv prim_reg_cdc_arb.sv
+  prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=( prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv )
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || echo "  missing $f"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+echo "  Copied prims"
+
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || echo "  missing $f"
+done
+
+echo "[3/6] Copying package files..."
+cp "$AH_RTL/alert_handler_reg_pkg.sv"                  "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv"                      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+
+echo "[4/6] Copying spec documentation..."
+cp "$AH_DOC/theory_of_operation.md" "$WS/spec/"
+cp "$AH_DOC/programmers_guide.md"   "$WS/spec/"
+cp "$AH_DOC/alert_handler_alert_rxtx.svg"       "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_block_diagram.svg"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_escalation_rxtx.svg"  "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lpg_ctrl.svg"         "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lp_overview.svg"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_receiver_fsm.svg"     "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_testplan.hjson"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson"                   "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/checklist.md"                            "$WS/spec/" 2>/dev/null || true
+
+cp "$AH_RTL/../README.md"                        "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+
+echo "[5/6] Copying RTL (all except alert_handler_lpg_ctrl.sv)..."
+for f in alert_handler.sv alert_handler_reg_top.sv alert_handler_reg_wrap.sv \
+         alert_handler_accu.sv alert_handler_class.sv alert_handler_esc_timer.sv \
+         alert_handler_lpg_ctrl.sv alert_handler_ping_timer.sv; do
+  if [ "$f" = "alert_handler_lpg_ctrl.sv" ]; then
+    echo "  skipping $f (agent stub)"
+    continue
+  fi
+  cp "$AH_RTL/$f" "$WS/rtl/"
+done
+
+echo "[6/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  echo "  $d/: $(find $WS/$d -type f 2>/dev/null | wc -l) files"
+done
+echo ""
+echo "=== Workspace populated. alert_handler_lpg_ctrl.sv stub added by environment Dockerfile. ==="

images/rtl/alert_handler-ping-timer/Dockerfile

@@ -0,0 +1,29 @@
+# TitanBench ALERT_HANDLER-PING-TIMER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# docker build -f images/rtl/alert_handler-ping-timer/image/Dockerfile \
+#   --build-context titanbench=/path/to/titanbench \
+#   -t titanbench-alert_handler-ping-timer-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore autogen files for non-Earlgrey tops that .dockerignore excludes
+# but fusesoc needs when building alert_handler DV.
+COPY --from=titanbench joe_exp/ot_autogen_fix/hw/ /home/dev/src/hw/
+
+COPY --from=titanbench images/rtl/alert_handler-ping-timer/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-ping-timer-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler-ping-timer/scripts/setup_workspace.sh

@@ -0,0 +1,200 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the ALERT_HANDLER-PING-TIMER-RTL workspace with infrastructure + oracle RTL for every
+# module except alert_handler_ping_timer.sv (overlaid as a stub by the environment Dockerfile).
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+
+echo "=== TitanBench: Populating ALERT_HANDLER-PING-TIMER-RTL workspace ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv
+  prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh
+  prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv
+  prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv
+  prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv
+  prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv
+  prim_mubi4_sync.sv
+  prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv
+  prim_reg_cdc.sv prim_reg_cdc_arb.sv
+  prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv
+  prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=( prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv )
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || echo "  missing $f"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+echo "  Copied prims"
+
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || echo "  missing $f"
+done
+
+echo "[3/6] Copying package files..."
+cp "$AH_RTL/alert_handler_reg_pkg.sv"                  "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv"                      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+
+echo "[4/6] Copying spec documentation..."
+cp "$AH_DOC/theory_of_operation.md" "$WS/spec/"
+cp "$AH_DOC/programmers_guide.md"   "$WS/spec/"
+cp "$AH_DOC/alert_handler_alert_rxtx.svg"       "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_block_diagram.svg"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_escalation_rxtx.svg"  "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lpg_ctrl.svg"         "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_lp_overview.svg"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/alert_handler_receiver_fsm.svg"     "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_testplan.hjson"      "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson"                   "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson"    "$WS/spec/" 2>/dev/null || true
+cp "$AH_DOC/checklist.md"                            "$WS/spec/" 2>/dev/null || true
+
+cp "$AH_RTL/../README.md"                        "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+
+echo "[5/6] Copying RTL (all except alert_handler_ping_timer.sv)..."
+for f in alert_handler.sv alert_handler_reg_top.sv alert_handler_reg_wrap.sv \
+         alert_handler_accu.sv alert_handler_class.sv alert_handler_esc_timer.sv \
+         alert_handler_lpg_ctrl.sv alert_handler_ping_timer.sv; do
+  if [ "$f" = "alert_handler_ping_timer.sv" ]; then
+    echo "  skipping $f (agent stub)"
+    continue
+  fi
+  cp "$AH_RTL/$f" "$WS/rtl/"
+done
+
+echo "[6/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  echo "  $d/: $(find $WS/$d -type f 2>/dev/null | wc -l) files"
+done
+echo ""
+echo "=== Workspace populated. alert_handler_ping_timer.sv stub added by environment Dockerfile. ==="

images/rtl/alert_handler/Dockerfile

@@ -0,0 +1,37 @@
+# TitanBench ALERT_HANDLER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/alert_handler/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-alert_handler-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Restore top_englishbreakfast autogen files that the OpenTitan .dockerignore
+# excludes but alert_handler DV still references during setup.
+COPY --from=titanbench opentitan/hw/top_englishbreakfast/ /home/dev/src/hw/top_englishbreakfast/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench tasks_missing_rtl/alert_handler-rtl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench alert_handler-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/alert_handler/scripts/setup_workspace.sh

@@ -0,0 +1,121 @@
+#!/bin/bash
+set -euo pipefail
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+AH_RTL="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/rtl"
+AH_DATA="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/data"
+AH_DOC="$REPO_TOP/hw/top_earlgrey/ip_autogen/alert_handler/doc"
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_esc_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv prim_subreg_pkg.sv prim_util_pkg.sv prim_count_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_onehot_enc.sv prim_onehot_check.sv prim_subreg.sv prim_subreg_arb.sv prim_subreg_ext.sv prim_subreg_shadow.sv prim_reg_we_check.sv
+  prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv prim_alert_sender.sv prim_alert_receiver.sv prim_esc_sender.sv prim_intr_hw.sv prim_edn_req.sv
+  prim_lc_sync.sv prim_edge_detector.sv prim_pulse_sync.sv prim_sync_reqack.sv prim_mubi4_sync.sv prim_count.sv prim_sparse_fsm_flop.sv prim_double_lfsr.sv prim_lfsr.sv prim_reg_cdc.sv prim_reg_cdc_arb.sv prim_packer_fifo.sv prim_fifo_sync.sv prim_max_tree.sv prim_diff_decode.sv
+  prim_secded_inv_22_16_dec.sv prim_secded_inv_22_16_enc.sv prim_secded_inv_28_22_dec.sv prim_secded_inv_28_22_enc.sv prim_secded_inv_39_32_dec.sv prim_secded_inv_39_32_enc.sv prim_secded_inv_64_57_dec.sv prim_secded_inv_64_57_enc.sv prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv prim_secded_inv_hamming_22_16_dec.sv prim_secded_inv_hamming_22_16_enc.sv prim_secded_inv_hamming_39_32_dec.sv prim_secded_inv_hamming_39_32_enc.sv prim_secded_inv_hamming_72_64_dec.sv prim_secded_inv_hamming_72_64_enc.sv prim_secded_inv_hamming_76_68_dec.sv prim_secded_inv_hamming_76_68_enc.sv prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=(prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv)
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || true; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/"; done
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_adapter_reg_shadowed.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do cp "$TLUL_SRC/$f" "$WS/tlul/" 2>/dev/null || true; done
+cp "$AH_RTL/alert_handler_reg_pkg.sv" "$WS/pkg/"
+cp "$AH_RTL/alert_handler_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv" "$WS/pkg/"
+for f in theory_of_operation.md programmers_guide.md checklist.md alert_handler_alert_rxtx.svg alert_handler_block_diagram.svg alert_handler_escalation_rxtx.svg alert_handler_lpg_ctrl.svg alert_handler_lp_overview.svg alert_handler_receiver_fsm.svg; do cp "$AH_DOC/$f" "$WS/spec/" 2>/dev/null || true; done
+cp "$AH_DATA/alert_handler_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler.hjson" "$WS/spec/" 2>/dev/null || true
+cp "$AH_DATA/alert_handler_sec_cm_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+cp "$AH_RTL/../README.md" "$WS/spec/alert_handler_README.md" 2>/dev/null || true
+cp "$AH_RTL/alert_handler.sv" "$WS/rtl/"
+cp "$AH_RTL/alert_handler_reg_top.sv" "$WS/rtl/"
+cp "$AH_RTL/alert_handler_reg_wrap.sv" "$WS/rtl/"
+cat > "$WS/run/filelist.f" <<'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_esc_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/alert_handler_reg_pkg.sv
+../pkg/alert_handler_pkg.sv
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_reg_shadowed.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_alert_receiver.sv
+../prim/prim_esc_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_pulse_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_max_tree.sv
+../prim/prim_diff_decode.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_lfsr.sv
+../prim/prim_double_lfsr.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+../rtl/alert_handler_reg_top.sv
+../rtl/alert_handler_reg_wrap.sv
+../rtl/alert_handler_accu.sv
+../rtl/alert_handler_class.sv
+../rtl/alert_handler_lpg_ctrl.sv
+../rtl/alert_handler_esc_timer.sv
+../rtl/alert_handler_ping_timer.sv
+../rtl/alert_handler.sv
+FILELIST
+cat > "$WS/run/Makefile" <<'MAKEFILE'
+.PHONY: compile clean
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate -f filelist.f -timescale 1ns/1ps -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE

images/rtl/aon-timer/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench AON-TIMER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/aon-timer/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-aon-timer-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/aon-timer/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench aon-timer-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/aon-timer/scripts/setup_workspace.sh

@@ -0,0 +1,237 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the AON-TIMER-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, spec, and boilerplate RTL — but NOT the modules to be implemented.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating AON-TIMER-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules (from hw/ip/prim/rtl/ and hw/ip/prim_generic/rtl/) ──
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  # Security
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # CDC and synchronization
+  prim_lc_sync.sv
+  prim_edge_detector.sv
+  prim_reg_cdc.sv
+  prim_reg_cdc_arb.sv
+  # SECDED (integrity — used by TLUL)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ──────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ─────────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+
+cp "$REPO_TOP/hw/ip/aon_timer/rtl/aon_timer_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"              "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"      "$WS/pkg/"
+
+echo "  Copied 6 package files"
+
+# ── Spec documentation ────────────────────────────────────────────────
+echo "[4/6] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/aon_timer/doc/theory_of_operation.md"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aon_timer/doc/registers.md"              "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aon_timer/doc/interfaces.md"             "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aon_timer/doc/programmers_guide.md"      "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aon_timer/doc/aon_timer_block_diagram.svg" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/aon_timer/data/aon_timer_testplan.hjson" "$WS/spec/"
+
+echo "  Copied spec docs"
+
+# ── Boilerplate RTL (provided complete — do not stub) ─────────────────
+echo "[5/6] Copying boilerplate RTL..."
+
+cp "$REPO_TOP/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv" "$WS/rtl/"
+
+echo "  Copied aon_timer_reg_top.sv"
+
+# ── Run directory (filelist + Makefile) ───────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/aon_timer_reg_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edge_detector.sv
+../prim/prim_reg_cdc_arb.sv
+../prim/prim_reg_cdc.sv
+
+// AON_TIMER boilerplate (provided — do not modify)
+../rtl/aon_timer_reg_top.sv
+
+// AON_TIMER core (agent-written — implement this)
+../rtl/aon_timer_core.sv
+
+// AON_TIMER top (agent-written — implement this)
+../rtl/aon_timer.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verify ────────────────────────────────────────────────────────────
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. aon_timer_core.sv and aon_timer.sv stubs added by environment Dockerfile. ==="

images/rtl/csrng/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench CSRNG-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/csrng/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-csrng-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/csrng/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench csrng-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/csrng/scripts/setup_workspace.sh

@@ -0,0 +1,372 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the CSRNG-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, aes, pkg, and spec docs — but NOT ground-truth CSRNG RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating CSRNG-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,aes,pkg,spec}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ─────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_cipher_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_trivium_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # FIFO / memory
+  prim_fifo_assert.svh
+  prim_fifo_sync.sv
+  prim_fifo_sync_cnt.sv
+  prim_packer_fifo.sv
+  prim_ram_1p_adv.sv
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_sparse_fsm_flop.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_onehot_mux.sv
+  prim_count.sv
+  prim_diff_decode.sv
+  prim_blanker.sv
+  prim_edge_detector.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  # Security
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_const.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # Synchronization
+  prim_lc_dec.sv
+  prim_lc_sync.sv
+  prim_sync_reqack.sv
+  prim_sync_reqack_data.sv
+  prim_mubi4_dec.sv
+  prim_mubi4_sender.sv
+  prim_mubi4_sync.sv
+  prim_mubi8_dec.sv
+  prim_mubi8_sender.sv
+  prim_mubi8_sync.sv
+  # Crypto / LFSR
+  prim_dom_and_2share.sv
+  prim_double_lfsr.sv
+  prim_edn_req.sv
+  prim_gf_mult.sv
+  prim_lfsr.sv
+  prim_subst_perm.sv
+  prim_trivium.sv
+  # Arbitration
+  prim_arbiter_fixed.sv
+  prim_arbiter_ppc.sv
+  prim_arbiter_tree.sv
+  # SECDED (integrity)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc headers
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_and2.sv
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_flop_en.sv
+  prim_ram_1p.sv
+  prim_ram_1p_pkg.sv
+  prim_xnor2.sv
+  prim_xor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ─────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── AES cipher core modules (used by csrng_block_encrypt) ───────────
+echo "[3/6] Copying AES cipher core modules..."
+AES_SRC="$REPO_TOP/hw/ip/aes/rtl"
+
+AES_FILES=(
+  aes_cipher_core.sv
+  aes_cipher_control.sv
+  aes_cipher_control_fsm.sv
+  aes_cipher_control_fsm_p.sv
+  aes_cipher_control_fsm_n.sv
+  aes_sub_bytes.sv
+  aes_sbox.sv
+  aes_sbox_lut.sv
+  aes_shift_rows.sv
+  aes_mix_columns.sv
+  aes_mix_single_column.sv
+  aes_key_expand.sv
+  aes_reduced_round.sv
+  aes_sel_buf_chk.sv
+)
+
+for f in "${AES_FILES[@]}"; do
+  cp "$AES_SRC/$f" "$WS/aes/"
+done
+echo "  Copied ${#AES_FILES[@]} AES files"
+
+# ── Package files (from various IPs) ────────────────────────────────
+echo "[4/6] Copying package files..."
+
+# AES packages (needed by csrng_block_encrypt and AES cipher core)
+cp "$REPO_TOP/hw/ip/aes/rtl/aes_pkg.sv"               "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/aes/rtl/aes_sbox_canright_pkg.sv"  "$WS/pkg/"
+
+# CSRNG packages
+cp "$REPO_TOP/hw/ip/csrng/rtl/csrng_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/csrng/rtl/csrng_reg_pkg.sv"        "$WS/pkg/"
+
+# Entropy/EDN packages (CSRNG interfaces)
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv"                "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/entropy_src/rtl/entropy_src_pkg.sv" "$WS/pkg/"
+
+# Shared packages
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"  "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+
+echo "  Copied 11 package files"
+
+# ── Spec documentation ───────────────────────────────────────────────
+echo "[5/6] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/csrng/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/csrng/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/csrng/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/csrng/doc/programmers_guide.md"   "$WS/spec/"
+
+# Testplan, register spec, and security countermeasures
+cp "$REPO_TOP/hw/ip/csrng/data/csrng_testplan.hjson"        "$WS/spec/"
+cp "$REPO_TOP/hw/ip/csrng/data/csrng.hjson"                 "$WS/spec/"
+cp "$REPO_TOP/hw/ip/csrng/data/csrng_sec_cm_testplan.hjson" "$WS/spec/"
+
+# SVG diagrams
+for svg in "$REPO_TOP/hw/ip/csrng/doc/"*.svg; do
+  [ -f "$svg" ] && cp "$svg" "$WS/spec/"
+done
+
+echo "  Copied spec docs and diagrams"
+
+# ── Run directory (filelist + Makefile) ──────────────────────────────
+echo "[6/6] Creating run directory..."
+mkdir -p "$WS/run"
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters - dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_ram_1p_pkg.sv
+../prim/prim_cipher_pkg.sv
+../prim/prim_trivium_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/entropy_src_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/aes_sbox_canright_pkg.sv
+../pkg/aes_pkg.sv
+../pkg/csrng_reg_pkg.sv
+../pkg/csrng_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_and2.sv
+../prim/prim_xor2.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_en.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_onehot_mux.sv
+../prim/prim_count.sv
+../prim/prim_edge_detector.sv
+../prim/prim_fifo_sync_cnt.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_sec_anchor_const.sv
+../prim/prim_diff_decode.sv
+../prim/prim_alert_sender.sv
+../prim/prim_lc_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_sync_reqack_data.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_mubi8_sync.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_blanker.sv
+../prim/prim_gf_mult.sv
+../prim/prim_intr_hw.sv
+../prim/prim_arbiter_ppc.sv
+../prim/prim_arbiter_tree.sv
+../prim/prim_arbiter_fixed.sv
+
+// AES cipher core modules (read-only, used by csrng_block_encrypt)
+../aes/aes_sel_buf_chk.sv
+../aes/aes_sbox_lut.sv
+../aes/aes_sbox.sv
+../aes/aes_sub_bytes.sv
+../aes/aes_shift_rows.sv
+../aes/aes_mix_single_column.sv
+../aes/aes_mix_columns.sv
+../aes/aes_key_expand.sv
+../aes/aes_reduced_round.sv
+../aes/aes_cipher_control_fsm_p.sv
+../aes/aes_cipher_control_fsm_n.sv
+../aes/aes_cipher_control_fsm.sv
+../aes/aes_cipher_control.sv
+../aes/aes_cipher_core.sv
+
+// CSRNG RTL (boilerplate)
+../rtl/csrng_reg_top.sv
+
+// CSRNG RTL (agent-written)
+../rtl/csrng_state_db.sv
+../rtl/csrng_main_sm.sv
+../rtl/csrng_block_encrypt.sv
+../rtl/csrng_cmd_stage.sv
+../rtl/csrng_ctr_drbg.sv
+../rtl/csrng_core.sv
+../rtl/csrng.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ─────────────────────────────────────────────────────
+echo "[7/7] Verifying workspace..."
+
+EXPECTED_DIRS=(prim tlul aes pkg spec run)
+for d in "${EXPECTED_DIRS[@]}"; do
+  count=$(find "$WS/$d" -type f | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stubs and run/ added by environment Dockerfile. ==="

images/rtl/dma/Dockerfile

@@ -0,0 +1,56 @@
+# TitanBench DMA-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/dma/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-dma-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Fix the RAL spec path in dma_sim_cfg.hjson: the upstream file references
+# rvscs/rtl/ip/dma/data/dma.hjson which is a product-specific path not present
+# in the open-source repo. Redirect it to the canonical hw/ip path.
+RUN sed -i 's|rvscs/rtl/ip/dma/data/dma.hjson|hw/ip/dma/data/dma.hjson|g' \
+    /home/dev/src/hw/ip/dma/dv/dma_sim_cfg.hjson
+
+# Remove dma_cov_bind from sim_tops — it probes the internal `reg2hw` signal
+# which will differ in agent implementations and cause elaboration failure.
+RUN sed -i 's|sim_tops: \["dma_cov_bind", "dma_bind"\]|sim_tops: ["dma_bind"]|g' \
+    /home/dev/src/hw/ip/dma/dv/dma_sim_cfg.hjson
+
+# Disable the 'did-you-bind-your-alert?' self-check present in five prim
+# modules (prim_onehot_check, prim_sparse_fsm_flop, prim_count, prim_double_lfsr,
+# prim_fifo_sync). Each has an ASSERT_INIT_NET(AssertConnected_A, ...) that
+# fires at t=1ps unless the user instantiates ASSERT_PRIM_*_ERROR_TRIGGER_ALERT
+# at the top level. That is a testbench-bookkeeping requirement, not an RTL
+# correctness property, so we comment out the assertion lines entirely.
+RUN for f in prim_onehot_check.sv prim_sparse_fsm_flop.sv prim_count.sv \
+             prim_double_lfsr.sv prim_fifo_sync.sv; do \
+      sed -i '/ASSERT_INIT_NET(AssertConnected_A/d' \
+        /home/dev/src/hw/ip/prim/rtl/$f; \
+    done
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/dma/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench dma-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/dma/scripts/setup_workspace.sh

@@ -0,0 +1,311 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the DMA-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, and spec docs — but NOT ground-truth RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating DMA-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ─────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_cipher_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_sha2_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # Flops / macros
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_sparse_fsm_flop.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_onehot_mux.sv
+  prim_diff_decode.sv
+  prim_blanker.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  # Security / alerts / interrupts
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_sec_anchor_const.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # Synchronization
+  prim_lc_sync.sv
+  prim_sync_reqack.sv
+  prim_sync_reqack_data.sv
+  prim_mubi4_dec.sv
+  prim_mubi4_sender.sv
+  prim_mubi4_sync.sv
+  # SHA-2 engine
+  prim_sha2_pad.sv
+  prim_sha2.sv
+  prim_sha2_32.sv
+  # SECDED (integrity — used by TLUL)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc
+  prim_util_memload.svh
+  prim_count.sv
+  prim_lfsr.sv
+  prim_packer_fifo.sv
+  prim_fifo_sync.sv
+  prim_fifo_sync_cnt.sv
+  prim_fifo_assert.svh
+)
+
+# Files from hw/ip/prim_generic/rtl/ (technology-independent implementations)
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_and2.sv
+  prim_const_sec.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_flop_en.sv
+  prim_clock_gating.sv
+  prim_xnor2.sv
+  prim_xor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ─────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_adapter_host.sv
+  tlul_cmd_intg_chk.sv
+  tlul_cmd_intg_gen.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_chk.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ─────────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+
+cp "$REPO_TOP/hw/ip/dma/rtl/dma_pkg.sv"          "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/dma/rtl/dma_reg_pkg.sv"       "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"   "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"     "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+
+echo "  Copied 7 package files"
+
+# ── Boilerplate RTL (fully implemented — provided to agent) ───────────
+echo "[4/6] Copying boilerplate RTL..."
+
+# dma_reg_top.sv is auto-generated; agent must not implement it
+cp "$REPO_TOP/hw/ip/dma/rtl/dma_reg_top.sv" "$WS/rtl/"
+
+echo "  Copied dma_reg_top.sv"
+
+# ── Spec documentation ─────────────────────────��──────────────────────
+echo "[5/6] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/dma/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/dma/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/dma/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/dma/doc/programmers_guide.md"   "$WS/spec/"
+cp "$REPO_TOP/hw/ip/dma/data/dma_testplan.hjson"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/dma/data/dma.hjson"             "$WS/spec/"
+# SVG diagrams
+for svg in "$REPO_TOP/hw/ip/dma/doc/"*.svg; do
+  [ -f "$svg" ] && cp "$svg" "$WS/spec/" || true
+done
+
+echo "  Copied spec docs"
+
+# ── Run directory (filelist + Makefile) ───────────────────────────────
+echo "[6/6] Creating run directory..."
+mkdir -p "$WS/run"
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_cipher_pkg.sv
+../prim/prim_sha2_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/dma_reg_pkg.sv
+../pkg/dma_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+../prim/prim_secded_inv_72_64_enc.sv
+../prim/prim_secded_inv_72_64_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_cmd_intg_gen.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_rsp_intg_chk.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_adapter_host.sv
+
+// Prim leaf modules (no cross-dependencies)
+../prim/prim_buf.sv
+../prim/prim_and2.sv
+../prim/prim_const_sec.sv
+../prim/prim_xor2.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_en.sv
+../prim/prim_clock_gating.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_onehot_mux.sv
+../prim/prim_count.sv
+../prim/prim_diff_decode.sv
+../prim/prim_blanker.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_sec_anchor_const.sv
+../prim/prim_alert_sender.sv
+../prim/prim_mubi4_dec.sv
+../prim/prim_mubi4_sender.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_lc_sync.sv
+../prim/prim_sync_reqack.sv
+../prim/prim_sync_reqack_data.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lfsr.sv
+../prim/prim_packer_fifo.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_fifo_sync_cnt.sv
+
+// SHA-2 engine
+../prim/prim_sha2_pad.sv
+../prim/prim_sha2.sv
+../prim/prim_sha2_32.sv
+
+// DMA boilerplate (provided, fully implemented)
+../rtl/dma_reg_top.sv
+
+// DMA RTL (agent-written)
+../rtl/dma.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ──────────────────────────────────────────────────────
+echo "[done] Verifying workspace..."
+
+EXPECTED_DIRS=(prim tlul pkg spec run rtl)
+for d in "${EXPECTED_DIRS[@]}"; do
+  count=$(find "$WS/$d" -type f | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stub added by environment Dockerfile. ==="

images/rtl/gpio/Dockerfile

@@ -0,0 +1,52 @@
+# TitanBench GPIO-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/gpio/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-gpio-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Remove prim_filter_ctr: forces the agent to implement their own input-debounce
+# filter rather than delegating to the OpenTitan primitive. The spec describes
+# the filter behaviour without naming the module, so removing it does not
+# invalidate any spec references. GPIO is the only consumer of prim_filter_ctr.
+RUN rm -f /home/dev/src/hw/ip/prim/rtl/prim_filter_ctr.sv \
+    && sed -i '/rtl\/prim_filter_ctr\.sv/d' /home/dev/src/hw/ip/prim/prim.core
+
+# Remove coverage exclusion file that probes internal signal names; these names
+# will differ in agent implementations.
+RUN rm -f /home/dev/src/hw/top_earlgrey/ip_autogen/gpio/dv/cov/gpio_cov_excl.el
+
+# Disable the 'did-you-bind-your-alert?' self-check in prim_onehot_check.
+# The assertion (AssertConnected_A at t=1ps) fires unless the user wraps
+# every prim_onehot_check instance with ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT.
+# That is a testbench-bookkeeping requirement, not an RTL correctness property,
+# so we flip the parameter default to 0 to let agents focus on functional logic.
+RUN sed -i 's/parameter bit EnableAlertTriggerSVA = 1/parameter bit EnableAlertTriggerSVA = 0/' \
+    /home/dev/src/hw/ip/prim/rtl/prim_onehot_check.sv
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/gpio/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench gpio-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/gpio/scripts/setup_workspace.sh

@@ -0,0 +1,250 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the GPIO-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, and spec docs — but NOT ground-truth RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+GPIO_SRC="$REPO_TOP/hw/top_earlgrey/ip_autogen/gpio"
+
+echo "=== TitanBench: Populating GPIO-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules ─────────────────────────────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # Flops / macros
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  prim_sparse_fsm_flop.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_onehot_mux.sv
+  prim_diff_decode.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_subreg_shadow.sv
+  prim_reg_we_check.sv
+  # Security / alerts / interrupts
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_sec_anchor_const.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # Synchronization
+  prim_lc_sync.sv
+  prim_mubi4_dec.sv
+  prim_mubi4_sender.sv
+  prim_mubi4_sync.sv
+  # SECDED (used by TLUL integrity)
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  # Misc
+  prim_count.sv
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_and2.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_flop_en.sv
+  prim_xnor2.sv
+  prim_xor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules ─────────────────────────────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ─────────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+
+cp "$GPIO_SRC/rtl/gpio_pkg.sv"                   "$WS/pkg/"
+cp "$GPIO_SRC/rtl/gpio_reg_pkg.sv"               "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"    "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+
+echo "  Copied 4 package files"
+
+# ── Boilerplate RTL (fully implemented — provided to agent) ───────────
+echo "[4/6] Copying boilerplate RTL..."
+
+# gpio_reg_top.sv is auto-generated; agent must not implement it
+cp "$GPIO_SRC/rtl/gpio_reg_top.sv" "$WS/rtl/"
+
+echo "  Copied gpio_reg_top.sv"
+
+# ── Spec documentation ────────────────────────────────────────────────
+echo "[5/6] Copying spec documentation..."
+
+cp "$GPIO_SRC/doc/theory_of_operation.md" "$WS/spec/"
+cp "$GPIO_SRC/doc/registers.md"           "$WS/spec/"
+cp "$GPIO_SRC/doc/interfaces.md"          "$WS/spec/"
+cp "$GPIO_SRC/doc/programmers_guide.md"   "$WS/spec/"
+# SVG diagrams
+for svg in "$GPIO_SRC/doc/"*.svg; do
+  [ -f "$svg" ] && cp "$svg" "$WS/spec/" || true
+done
+# Testplan if present
+[ -f "$GPIO_SRC/data/gpio_testplan.hjson" ] && cp "$GPIO_SRC/data/gpio_testplan.hjson" "$WS/spec/" || true
+
+echo "  Copied spec docs"
+
+# ── Run directory (filelist + Makefile) ───────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/gpio_reg_pkg.sv
+../pkg/gpio_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+../prim/prim_secded_inv_72_64_enc.sv
+../prim/prim_secded_inv_72_64_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim leaf modules
+../prim/prim_buf.sv
+../prim/prim_and2.sv
+../prim/prim_xor2.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_en.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_onehot_mux.sv
+../prim/prim_count.sv
+../prim/prim_diff_decode.sv
+../prim/prim_sparse_fsm_flop.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_sec_anchor_const.sv
+../prim/prim_alert_sender.sv
+../prim/prim_mubi4_dec.sv
+../prim/prim_mubi4_sender.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_lc_sync.sv
+../prim/prim_intr_hw.sv
+
+// GPIO boilerplate (provided, fully implemented)
+../rtl/gpio_reg_top.sv
+
+// GPIO RTL (agent-written)
+../rtl/gpio.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ──────────────────────────────────────────────────────
+echo "[done] Verifying workspace..."
+for d in prim tlul pkg spec run rtl; do
+  count=$(find "$WS/$d" -type f | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stub added by environment Dockerfile. ==="

images/rtl/hmac/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench HMAC-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/hmac/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-hmac-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/hmac/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench hmac-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/hmac/scripts/setup_workspace.sh

@@ -0,0 +1,260 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the HMAC-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, and spec docs — but NOT ground-truth RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating HMAC-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ─────────────────────────────
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_sha2_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # FIFO
+  prim_fifo_assert.svh
+  prim_fifo_sync.sv
+  prim_fifo_sync_cnt.sv
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  # Combinational / counters
+  prim_count.sv
+  prim_diff_decode.sv
+  prim_onehot_check.sv
+  prim_onehot_enc.sv
+  # Subreg
+  prim_reg_we_check.sv
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  # Packer
+  prim_packer.sv
+  # SHA-2
+  prim_sha2.sv
+  prim_sha2_32.sv
+  prim_sha2_pad.sv
+  # Interrupts / alerts
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  # SECDED (for TLUL integrity)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ─────────────────────────────
+echo "[2/5] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_adapter_sram.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_err_resp.sv
+  tlul_fifo_sync.sv
+  tlul_rsp_intg_gen.sv
+  tlul_socket_1n.sv
+  tlul_sram_byte.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ────────────────────────────────────────────────────
+echo "[3/5] Copying package files..."
+
+cp "$REPO_TOP/hw/ip/hmac/rtl/hmac_reg_pkg.sv"       "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"       "$WS/pkg/"
+
+echo "  Copied 2 package files"
+
+# ── Spec documentation ───────────────────────────────────────────────
+echo "[4/5] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/hmac/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/hmac/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/hmac/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/hmac/doc/programmers_guide.md"   "$WS/spec/"
+cp "$REPO_TOP/hw/ip/hmac/data/hmac_testplan.hjson"   "$WS/spec/"
+cp "$REPO_TOP/hw/ip/hmac/data/hmac.hjson"            "$WS/spec/"
+
+# SVG diagrams (copy all that exist)
+for svg in "$REPO_TOP/hw/ip/hmac/doc/"*.svg; do
+  [ -f "$svg" ] && cp "$svg" "$WS/spec/"
+done
+
+echo "  Copied spec docs and diagrams"
+
+# ── Run directory (filelist + Makefile) ──────────────────────────────
+echo "[5/5] Creating run directory..."
+mkdir -p "$WS/run"
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters - dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_sha2_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/hmac_reg_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_err_resp.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../tlul/tlul_fifo_sync.sv
+../tlul/tlul_socket_1n.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_count.sv
+../prim/prim_fifo_sync_cnt.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_diff_decode.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_packer.sv
+../prim/prim_sha2_pad.sv
+../prim/prim_sha2.sv
+../prim/prim_sha2_32.sv
+
+// TLUL adapter SRAM (used by hmac top for MSG_FIFO window)
+../tlul/tlul_sram_byte.sv
+../tlul/tlul_adapter_sram.sv
+
+// HMAC RTL (boilerplate - auto-generated register top)
+../rtl/hmac_reg_top.sv
+
+// HMAC RTL (agent-written)
+../rtl/hmac_core.sv
+../rtl/hmac.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ─────────────────────────────────────────────────────
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stubs and boilerplate RTL added by environment Dockerfile. ==="

images/rtl/i2c/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench I2C-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/i2c/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-i2c-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/i2c/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench i2c-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/i2c/scripts/setup_workspace.sh

@@ -0,0 +1,265 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the I2C-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, and spec docs — but NOT ground-truth RTL.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating I2C-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ─────────────────────────────
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+# Files from hw/ip/prim/rtl/
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_count_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # FIFO / memory
+  prim_fifo_assert.svh
+  prim_fifo_sync.sv
+  prim_fifo_sync_cnt.sv
+  prim_ram_1p_adv.sv
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  prim_count.sv
+  prim_diff_decode.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  # Security
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # Arbitration
+  prim_arbiter_fixed.sv
+  prim_arbiter_tree.sv
+  # SECDED (integrity)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc headers
+  prim_util_memload.svh
+)
+
+# Files from hw/ip/prim_generic/rtl/ (technology-independent implementations)
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_ram_1p.sv
+  prim_ram_1p_pkg.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ─────────────────────────────
+echo "[2/5] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files (from various IPs) ────────────────────────────────
+echo "[3/5] Copying package files..."
+
+cp "$REPO_TOP/hw/ip/i2c/rtl/i2c_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/i2c/rtl/i2c_reg_pkg.sv"         "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"     "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"       "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+
+echo "  Copied 7 package files"
+
+# ── Spec documentation (from hw/ip/i2c/doc/ and data/) ──────────────
+echo "[4/5] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/i2c/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/i2c/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/i2c/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/i2c/data/i2c_testplan.hjson"    "$WS/spec/"
+cp "$REPO_TOP/hw/ip/i2c/data/i2c.hjson"             "$WS/spec/"
+cp "$REPO_TOP/hw/ip/i2c/data/i2c_sec_cm_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+# SVG diagrams (copy all that exist)
+for svg in "$REPO_TOP/hw/ip/i2c/doc/"*.svg; do
+  [ -f "$svg" ] && cp "$svg" "$WS/spec/"
+done
+
+echo "  Copied spec docs and diagrams"
+
+# ── Run directory (filelist + Makefile) ──────────────────────────────
+echo "[5/6] Creating run directory..."
+mkdir -p "$WS/run"
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters - dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_ram_1p_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/i2c_pkg.sv
+../pkg/i2c_reg_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_count.sv
+../prim/prim_fifo_sync_cnt.sv
+../prim/prim_fifo_sync.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_diff_decode.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_ram_1p.sv
+../prim/prim_ram_1p_adv.sv
+../prim/prim_arbiter_tree.sv
+../prim/prim_arbiter_fixed.sv
+
+// I2C RTL (boilerplate)
+../rtl/i2c_reg_top.sv
+
+// I2C RTL (agent-written)
+../rtl/i2c_bus_monitor.sv
+../rtl/i2c_fifo_sync_sram_adapter.sv
+../rtl/i2c_fifos.sv
+../rtl/i2c_controller_fsm.sv
+../rtl/i2c_target_fsm.sv
+../rtl/i2c_core.sv
+../rtl/i2c.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	@xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1; \
+	STATUS=$$?; \
+	if [ $$STATUS -eq 0 ]; then \
+	  echo "COMPILE PASSED"; \
+	else \
+	  echo "COMPILE FAILED (see compile_log/compile.log)"; \
+	  grep 'xmvlog: \*E\|xmelab: \*E' compile_log/compile.log 2>/dev/null; \
+	  exit 1; \
+	fi
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verification ─────────────────────────────────────────────────────
+echo "[6/6] Verifying workspace..."
+
+EXPECTED_DIRS=(prim tlul pkg spec run)
+for d in "${EXPECTED_DIRS[@]}"; do
+  count=$(find "$WS/$d" -type f | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. Agent stubs, PDFs, and run/ added by environment Dockerfile. ==="

images/rtl/keymgr-ctrl/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench KEYMGR-CTRL-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/keymgr-ctrl/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-keymgr-ctrl-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/keymgr-ctrl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench keymgr-ctrl-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/keymgr-ctrl/scripts/setup_workspace.sh

@@ -0,0 +1,95 @@
+#!/bin/bash
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating KEYMGR-CTRL-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,pkg,spec,run,rtl}
+
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+for f in prim_assert.sv prim_util_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv \
+          prim_count_pkg.sv \
+          prim_assert_sec_cm.svh prim_assert_standard_macros.svh \
+          prim_flop_macros.sv \
+          prim_cdc_rand_delay.sv prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv \
+          prim_count.sv prim_mubi4_sender.sv \
+          prim_secded_inv_72_64_enc.sv prim_secded_inv_72_64_dec.sv; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+
+# prim_flop_2sync lives in prim_generic
+cp "$PRIM_GEN_SRC/prim_flop_2sync.sv" "$WS/prim/"
+
+# These may be in prim_generic or prim
+for f in prim_buf.sv prim_flop.sv prim_xnor2.sv; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+
+echo "[2/6] Copying package files..."
+cp "$REPO_TOP/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv"     "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv"     "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_pkg.sv"         "$WS/pkg/"
+
+echo "[3/6] Copying boilerplate RTL modules..."
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_op_state_ctrl.sv"  "$WS/rtl/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_data_en_state.sv"  "$WS/rtl/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_err.sv"            "$WS/rtl/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_reseed_ctrl.sv"    "$WS/rtl/"
+
+echo "[4/6] Copying spec documentation..."
+for f in theory_of_operation.md registers.md interfaces.md; do
+  cp "$REPO_TOP/hw/ip/keymgr/doc/$f" "$WS/spec/" 2>/dev/null || true
+done
+cp "$REPO_TOP/hw/ip/keymgr/data/keymgr_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+echo "[5/6] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_flop_macros.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_mubi4_sender.sv
+../prim/prim_count.sv
+../prim/prim_secded_inv_72_64_enc.sv
+../prim/prim_secded_inv_72_64_dec.sv
+../pkg/otp_ctrl_pkg.sv
+../pkg/keymgr_reg_pkg.sv
+../pkg/keymgr_pkg.sv
+../rtl/keymgr_err.sv
+../rtl/keymgr_data_en_state.sv
+../rtl/keymgr_op_state_ctrl.sv
+../rtl/keymgr_reseed_ctrl.sv
+../rtl/keymgr_ctrl.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "[6/6] Workspace populated."

images/rtl/keymgr-err/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench KEYMGR-ERR-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/keymgr-err/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-keymgr-err-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/keymgr-err/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench keymgr-err-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/keymgr-err/scripts/setup_workspace.sh

@@ -0,0 +1,63 @@
+#!/bin/bash
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating KEYMGR-ERR-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,pkg,spec,run,rtl}
+
+# Prim files (minimal set needed)
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+for f in prim_assert.sv prim_util_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv \
+          prim_assert_sec_cm.svh prim_assert_standard_macros.svh \
+          prim_flop_macros.sv; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+cp "$PRIM_GEN_SRC/prim_buf.sv" "$WS/prim/"
+
+echo "[2/5] Copying package files..."
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_pkg.sv"     "$WS/pkg/"
+
+echo "[3/5] Copying spec documentation..."
+mkdir -p "$WS/spec"
+for f in theory_of_operation.md registers.md interfaces.md; do
+  cp "$REPO_TOP/hw/ip/keymgr/doc/$f" "$WS/spec/" 2>/dev/null || true
+done
+cp "$REPO_TOP/hw/ip/keymgr/data/keymgr_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+echo "[4/5] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_flop_macros.sv
+../prim/prim_buf.sv
+../pkg/keymgr_reg_pkg.sv
+../pkg/keymgr_pkg.sv
+../rtl/keymgr_err.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "[5/5] Workspace populated."

images/rtl/keymgr-kmac-if/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench KEYMGR-KMAC-IF-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/keymgr-kmac-if/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-keymgr-kmac-if-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/keymgr-kmac-if/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench keymgr-kmac-if-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/keymgr-kmac-if/scripts/setup_workspace.sh

@@ -0,0 +1,79 @@
+#!/bin/bash
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating KEYMGR-KMAC-IF-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,pkg,spec,run,rtl}
+
+# Prim files
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+for f in prim_assert.sv prim_util_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv \
+          prim_count_pkg.sv \
+          prim_assert_sec_cm.svh prim_assert_standard_macros.svh \
+          prim_flop_macros.sv \
+          prim_cdc_rand_delay.sv prim_sec_anchor_buf.sv prim_sec_anchor_flop.sv \
+          prim_count.sv; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+
+for f in prim_flop.sv prim_buf.sv prim_xnor2.sv; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+
+echo "[2/5] Copying package files..."
+cp "$REPO_TOP/hw/ip/kmac/rtl/sha3_pkg.sv"         "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/kmac/rtl/kmac_pkg.sv"         "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_pkg.sv"     "$WS/pkg/"
+
+echo "[3/5] Copying spec documentation..."
+mkdir -p "$WS/spec"
+for f in theory_of_operation.md registers.md interfaces.md; do
+  cp "$REPO_TOP/hw/ip/keymgr/doc/$f" "$WS/spec/" 2>/dev/null || true
+done
+cp "$REPO_TOP/hw/ip/keymgr/data/keymgr_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+echo "[4/5] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../prim/prim_flop_macros.sv
+../pkg/sha3_pkg.sv
+../pkg/kmac_pkg.sv
+../pkg/keymgr_pkg.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_count.sv
+../rtl/keymgr_kmac_if.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "[5/5] Workspace populated."

images/rtl/keymgr-sideload-key-ctrl/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench KEYMGR-SIDELOAD-KEY-CTRL-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/keymgr-sideload-key-ctrl/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-keymgr-sideload-key-ctrl-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/keymgr-sideload-key-ctrl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench keymgr-sideload-key-ctrl-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/keymgr-sideload-key-ctrl/scripts/setup_workspace.sh

@@ -0,0 +1,68 @@
+#!/bin/bash
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating KEYMGR-SIDELOAD-KEY-CTRL-RTL workspace from OpenTitan ==="
+
+mkdir -p "$WS"/{prim,pkg,spec,run,rtl}
+
+echo "[1/5] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+for f in prim_assert.sv prim_util_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv \
+          prim_assert_sec_cm.svh prim_assert_standard_macros.svh \
+          prim_flop_macros.sv prim_mubi4_sync.sv; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in prim_buf.sv prim_flop.sv prim_xnor2.sv prim_cdc_rand_delay.sv; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/" 2>/dev/null || cp "$PRIM_SRC/$f" "$WS/prim/" 2>/dev/null || true
+done
+
+echo "[2/5] Copying package files..."
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_pkg.sv" "$WS/pkg/"
+
+echo "[3/5] Copying boilerplate RTL..."
+cp "$REPO_TOP/hw/ip/keymgr/rtl/keymgr_sideload_key.sv" "$WS/rtl/"
+
+echo "[4/5] Copying spec documentation..."
+for f in theory_of_operation.md registers.md interfaces.md; do
+  cp "$REPO_TOP/hw/ip/keymgr/doc/$f" "$WS/spec/" 2>/dev/null || true
+done
+cp "$REPO_TOP/hw/ip/keymgr/data/keymgr_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+
+echo "[5/5] Creating run directory..."
+cat > "$WS/run/filelist.f" << 'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_flop_macros.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_mubi4_sync.sv
+../pkg/keymgr_pkg.sv
+../rtl/keymgr_sideload_key.sv
+../rtl/keymgr_sideload_key_ctrl.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "=== Workspace populated ==="

images/rtl/keymgr/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench KEYMGR-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/keymgr/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-keymgr-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench tasks_missing_rtl/keymgr-rtl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench keymgr-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/keymgr/scripts/setup_workspace.sh

@@ -0,0 +1,108 @@
+#!/bin/bash
+set -euo pipefail
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+KM_SRC="$REPO_TOP/hw/ip/keymgr"
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+PRIM_FILES=(
+  prim_alert_pkg.sv prim_count_pkg.sv prim_mubi_pkg.sv prim_secded_pkg.sv prim_subreg_pkg.sv prim_util_pkg.sv
+  prim_assert.sv prim_assert_sec_cm.svh prim_assert_standard_macros.svh prim_flop_macros.sv prim_cdc_rand_delay.sv
+  prim_subreg.sv prim_subreg_ext.sv prim_subreg_shadow.sv prim_reg_we_check.sv prim_alert_sender.sv prim_intr_hw.sv
+  prim_lc_sync.sv prim_edn_req.sv prim_count.sv prim_lfsr.sv prim_sec_anchor_buf.sv prim_sec_anchor_const.sv
+  prim_mubi4_sender.sv prim_mubi4_sync.sv prim_secded_inv_72_64_dec.sv prim_secded_inv_72_64_enc.sv prim_util_memload.svh
+)
+PRIM_GENERIC_FILES=(prim_buf.sv prim_flop.sv prim_flop_2sync.sv prim_xnor2.sv prim_msb_extend.sv)
+for f in "${PRIM_FILES[@]}"; do cp "$PRIM_SRC/$f" "$WS/prim/"; done
+for f in "${PRIM_GENERIC_FILES[@]}"; do cp "$PRIM_GEN_SRC/$f" "$WS/prim/" 2>/dev/null || cp "$PRIM_SRC/$f" "$WS/prim/"; done
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+for f in tlul_pkg.sv tlul_adapter_reg.sv tlul_cmd_intg_chk.sv tlul_data_integ_dec.sv tlul_data_integ_enc.sv tlul_err.sv tlul_rsp_intg_gen.sv; do cp "$TLUL_SRC/$f" "$WS/tlul/"; done
+cp "$KM_SRC/rtl/keymgr_pkg.sv" "$WS/pkg/"
+cp "$KM_SRC/rtl/keymgr_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/kmac/rtl/kmac_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/rom_ctrl/rtl/rom_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/edn/rtl/edn_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv" "$WS/pkg/"
+for f in theory_of_operation.md registers.md interfaces.md; do cp "$KM_SRC/doc/$f" "$WS/spec/" 2>/dev/null || true; done
+cp "$KM_SRC/data/keymgr_testplan.hjson" "$WS/spec/" 2>/dev/null || true
+cp "$KM_SRC/rtl/keymgr_reg_top.sv" "$WS/rtl/"
+cp "$KM_SRC/rtl/keymgr_cfg_en.sv" "$WS/rtl/"
+cp "$KM_SRC/rtl/keymgr_data_en_state.sv" "$WS/rtl/"
+cp "$KM_SRC/rtl/keymgr_op_state_ctrl.sv" "$WS/rtl/"
+cp "$KM_SRC/rtl/keymgr_reseed_ctrl.sv" "$WS/rtl/"
+cp "$KM_SRC/rtl/keymgr_sideload_key.sv" "$WS/rtl/"
+cat > "$WS/run/filelist.f" <<'FILELIST'
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../prim/prim_count_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/edn_pkg.sv
+../pkg/kmac_pkg.sv
+../pkg/otp_ctrl_pkg.sv
+../pkg/flash_ctrl_pkg.sv
+../pkg/rom_ctrl_pkg.sv
+../pkg/keymgr_reg_pkg.sv
+../pkg/keymgr_pkg.sv
+../prim/prim_secded_inv_72_64_enc.sv
+../prim/prim_secded_inv_72_64_dec.sv
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_subreg_shadow.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+../prim/prim_lc_sync.sv
+../prim/prim_edn_req.sv
+../prim/prim_count.sv
+../prim/prim_lfsr.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_const.sv
+../prim/prim_mubi4_sender.sv
+../prim/prim_mubi4_sync.sv
+../prim/prim_msb_extend.sv
+../rtl/keymgr_reg_top.sv
+../rtl/keymgr_cfg_en.sv
+../rtl/keymgr_data_en_state.sv
+../rtl/keymgr_op_state_ctrl.sv
+../rtl/keymgr_reseed_ctrl.sv
+../rtl/keymgr_sideload_key.sv
+../rtl/keymgr_err.sv
+../rtl/keymgr_ctrl.sv
+../rtl/keymgr_input_checks.sv
+../rtl/keymgr_kmac_if.sv
+../rtl/keymgr_sideload_key_ctrl.sv
+../rtl/keymgr.sv
+FILELIST
+cat > "$WS/run/Makefile" <<'MAKEFILE'
+.PHONY: compile clean
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate -f filelist.f -timescale 1ns/1ps -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE

images/rtl/rv-timer-core/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench RV-TIMER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/rv-timer-core/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-rv-timer-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench images/rtl/rv-timer-core/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench rv-timer-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]

images/rtl/rv-timer-core/scripts/setup_workspace.sh

@@ -0,0 +1,229 @@
+#!/bin/bash
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Populates the RV-TIMER-RTL workspace with infrastructure files from OpenTitan.
+# Copies prim, tlul, pkg, spec, and boilerplate RTL — but NOT timer_core.sv.
+#
+# Run at image build time. Build context = OpenTitan repo root.
+
+set -euo pipefail
+
+REPO_TOP="/home/dev/src"
+WS="/home/dev/workspace/code"
+
+echo "=== TitanBench: Populating RV-TIMER-RTL workspace from OpenTitan ==="
+
+# ── Create workspace directories ─────────────────────────────────────
+mkdir -p "$WS"/{prim,tlul,pkg,spec,run,rtl}
+
+# ── Prim modules (from hw/ip/prim/rtl/) ──────────────────────────────
+echo "[1/6] Copying prim modules..."
+PRIM_SRC="$REPO_TOP/hw/ip/prim/rtl"
+PRIM_GEN_SRC="$REPO_TOP/hw/ip/prim_generic/rtl"
+
+PRIM_FILES=(
+  # Packages
+  prim_alert_pkg.sv
+  prim_mubi_pkg.sv
+  prim_secded_pkg.sv
+  prim_subreg_pkg.sv
+  prim_util_pkg.sv
+  # Assertion headers
+  prim_assert.sv
+  prim_assert_sec_cm.svh
+  prim_assert_standard_macros.svh
+  # Flops
+  prim_flop_macros.sv
+  prim_cdc_rand_delay.sv
+  # Combinational
+  prim_onehot_enc.sv
+  prim_onehot_check.sv
+  # Subreg
+  prim_subreg.sv
+  prim_subreg_arb.sv
+  prim_subreg_ext.sv
+  prim_reg_we_check.sv
+  # Security
+  prim_sec_anchor_buf.sv
+  prim_sec_anchor_flop.sv
+  prim_alert_sender.sv
+  prim_intr_hw.sv
+  # SECDED (integrity — used by TLUL)
+  prim_secded_inv_22_16_dec.sv
+  prim_secded_inv_22_16_enc.sv
+  prim_secded_inv_28_22_dec.sv
+  prim_secded_inv_28_22_enc.sv
+  prim_secded_inv_39_32_dec.sv
+  prim_secded_inv_39_32_enc.sv
+  prim_secded_inv_64_57_dec.sv
+  prim_secded_inv_64_57_enc.sv
+  prim_secded_inv_72_64_dec.sv
+  prim_secded_inv_72_64_enc.sv
+  prim_secded_inv_hamming_22_16_dec.sv
+  prim_secded_inv_hamming_22_16_enc.sv
+  prim_secded_inv_hamming_39_32_dec.sv
+  prim_secded_inv_hamming_39_32_enc.sv
+  prim_secded_inv_hamming_72_64_dec.sv
+  prim_secded_inv_hamming_72_64_enc.sv
+  prim_secded_inv_hamming_76_68_dec.sv
+  prim_secded_inv_hamming_76_68_enc.sv
+  # Misc
+  prim_util_memload.svh
+)
+
+PRIM_GENERIC_FILES=(
+  prim_buf.sv
+  prim_flop.sv
+  prim_flop_2sync.sv
+  prim_xnor2.sv
+)
+
+for f in "${PRIM_FILES[@]}"; do
+  cp "$PRIM_SRC/$f" "$WS/prim/"
+done
+for f in "${PRIM_GENERIC_FILES[@]}"; do
+  cp "$PRIM_GEN_SRC/$f" "$WS/prim/"
+done
+echo "  Copied $((${#PRIM_FILES[@]} + ${#PRIM_GENERIC_FILES[@]})) prim files"
+
+# ── TLUL modules (from hw/ip/tlul/rtl/) ──────────────────────────────
+echo "[2/6] Copying TLUL modules..."
+TLUL_SRC="$REPO_TOP/hw/ip/tlul/rtl"
+
+TLUL_FILES=(
+  tlul_pkg.sv
+  tlul_adapter_reg.sv
+  tlul_cmd_intg_chk.sv
+  tlul_data_integ_dec.sv
+  tlul_data_integ_enc.sv
+  tlul_err.sv
+  tlul_rsp_intg_gen.sv
+)
+
+for f in "${TLUL_FILES[@]}"; do
+  cp "$TLUL_SRC/$f" "$WS/tlul/"
+done
+echo "  Copied ${#TLUL_FILES[@]} TLUL files"
+
+# ── Package files ─────────────────────────────────────────────────────
+echo "[3/6] Copying package files..."
+
+cp "$REPO_TOP/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv"      "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/top_pkg.sv"              "$WS/pkg/"
+cp "$REPO_TOP/hw/top_earlgrey/rtl/autogen/top_racl_pkg.sv" "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_pkg.sv"            "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv"        "$WS/pkg/"
+cp "$REPO_TOP/hw/ip/lc_ctrl/rtl/lc_ctrl_state_pkg.sv"      "$WS/pkg/"
+
+echo "  Copied 6 package files"
+
+# ── Spec documentation ────────────────────────────────────────────────
+echo "[4/6] Copying spec documentation..."
+
+cp "$REPO_TOP/hw/ip/rv_timer/doc/theory_of_operation.md" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/rv_timer/doc/registers.md"           "$WS/spec/"
+cp "$REPO_TOP/hw/ip/rv_timer/doc/interfaces.md"          "$WS/spec/"
+cp "$REPO_TOP/hw/ip/rv_timer/doc/programmers_guide.md"   "$WS/spec/"
+cp "$REPO_TOP/hw/ip/rv_timer/doc/timer_block_diagram.svg" "$WS/spec/"
+cp "$REPO_TOP/hw/ip/rv_timer/data/rv_timer_testplan.hjson" "$WS/spec/"
+
+echo "  Copied spec docs"
+
+# ── Boilerplate RTL (provided complete — do not stub) ─────────────────
+echo "[5/6] Copying boilerplate RTL..."
+
+cp "$REPO_TOP/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv" "$WS/rtl/"
+cp "$REPO_TOP/hw/ip/rv_timer/rtl/rv_timer.sv"         "$WS/rtl/"
+
+echo "  Copied rv_timer.sv and rv_timer_reg_top.sv"
+
+# ── Run directory (filelist + Makefile) ───────────────────────────────
+echo "[6/6] Creating run directory..."
+
+cat > "$WS/run/filelist.f" << 'FILELIST'
+// Packages (order matters — dependencies first)
++incdir+../prim
+../prim/prim_assert.sv
+../prim/prim_util_pkg.sv
+../prim/prim_mubi_pkg.sv
+../prim/prim_alert_pkg.sv
+../prim/prim_subreg_pkg.sv
+../prim/prim_secded_pkg.sv
+../pkg/top_pkg.sv
+../tlul/tlul_pkg.sv
+../pkg/lc_ctrl_state_pkg.sv
+../pkg/lc_ctrl_reg_pkg.sv
+../pkg/lc_ctrl_pkg.sv
+../pkg/top_racl_pkg.sv
+../pkg/rv_timer_reg_pkg.sv
+
+// SECDED encoder/decoder modules (used by TLUL integrity)
+../prim/prim_secded_inv_64_57_enc.sv
+../prim/prim_secded_inv_64_57_dec.sv
+../prim/prim_secded_inv_39_32_enc.sv
+../prim/prim_secded_inv_39_32_dec.sv
+
+// TLUL modules
+../tlul/tlul_err.sv
+../tlul/tlul_cmd_intg_chk.sv
+../tlul/tlul_rsp_intg_gen.sv
+../tlul/tlul_data_integ_dec.sv
+../tlul/tlul_data_integ_enc.sv
+../tlul/tlul_adapter_reg.sv
+
+// Prim modules (leaf first)
+../prim/prim_buf.sv
+../prim/prim_xnor2.sv
+../prim/prim_flop.sv
+../prim/prim_cdc_rand_delay.sv
+../prim/prim_flop_2sync.sv
+../prim/prim_onehot_enc.sv
+../prim/prim_onehot_check.sv
+../prim/prim_subreg_arb.sv
+../prim/prim_subreg.sv
+../prim/prim_subreg_ext.sv
+../prim/prim_reg_we_check.sv
+../prim/prim_sec_anchor_buf.sv
+../prim/prim_sec_anchor_flop.sv
+../prim/prim_alert_sender.sv
+../prim/prim_intr_hw.sv
+
+// RV_TIMER boilerplate (provided — do not modify)
+../rtl/rv_timer_reg_top.sv
+
+// RV_TIMER core (agent-written — implement this)
+../rtl/timer_core.sv
+
+// RV_TIMER top (provided — do not modify)
+../rtl/rv_timer.sv
+FILELIST
+
+cat > "$WS/run/Makefile" << 'MAKEFILE'
+.PHONY: compile clean
+
+compile:
+	@mkdir -p compile_log
+	xrun -c -64 -sv -access +rwc -elaborate \
+	  -f filelist.f \
+	  -timescale 1ns/1ps \
+	  -l compile_log/compile.log 2>&1 || true
+	@echo "Check compile_log/compile.log"
+
+clean:
+	rm -rf xcelium.d compile_log
+MAKEFILE
+
+echo "  Created filelist.f and Makefile"
+
+# ── Verify ────────────────────────────────────────────────────────────
+echo ""
+echo "[verify] Workspace contents:"
+for d in prim tlul pkg spec rtl run; do
+  count=$(find "$WS/$d" -type f 2>/dev/null | wc -l)
+  echo "  $d/: $count files"
+done
+
+echo ""
+echo "=== Workspace populated. timer_core.sv stub added by environment Dockerfile. ==="

images/rtl/rv_timer/Dockerfile

@@ -0,0 +1,33 @@
+# TitanBench RV_TIMER-RTL — extends titanbench-base with OpenTitan infrastructure.
+#
+# Uses two build contexts:
+#   - default context (.) = OpenTitan repo root
+#   - titanbench          = titanbench repo root
+#
+# Usage:
+#   docker build -f images/rtl/rv_timer/image/Dockerfile \
+#     --build-context titanbench=/path/to/titanbench \
+#     -t titanbench-rv_timer-rtl /path/to/opentitan
+
+FROM titanbench-base:latest
+
+# Copy the OpenTitan repo
+COPY --chown=dev:dev . /home/dev/src/
+
+# Copy the setup script from the titanbench repo
+COPY --from=titanbench tasks_missing_rtl/rv_timer-rtl/scripts/setup_workspace.sh /home/dev/scripts/setup_workspace.sh
+RUN chmod +x /home/dev/scripts/setup_workspace.sh \
+    && bash /home/dev/scripts/setup_workspace.sh
+
+# Git setup — dvsim requires a git repo with at least one commit
+RUN git config --global --add safe.directory /home/dev/src \
+    && git config --global user.email "titanbench@opentitan.org" \
+    && git config --global user.name "TitanBench" \
+    && cd /home/dev/src \
+    && git init \
+    && git add -A \
+    && git commit -m "titanbench rv_timer-rtl base"
+
+WORKDIR /home/dev/workspace/code
+ENTRYPOINT []
+CMD ["sh", "-c", "sleep infinity"]