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alu_w16_7ops_sky130_1000mhz/flow/extracted/drc_labels.json

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+[{"run_id": "alu_w16_7ops_sky130_1000mhz", "pdk": "sky130", "violation_type": "clean", "violation_count": 0}]

alu_w16_7ops_sky130_1000mhz/flow/extracted/mesoscale_blocks.json

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alu_w16_7ops_sky130_1000mhz/flow/extracted/pin_access.json

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alu_w16_7ops_sky130_1000mhz/flow/extracted/power_grid.json

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alu_w16_7ops_sky130_1000mhz/flow/extracted/timing_contexts.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w16_7ops_sky130_1000mhz", "pdk": "sky130", "freq_mhz": 1000, "wns_ns": null, "tns_ns": null, "utilization": 0.56, "num_instances": 850, "area_um2": 2643.0, "multi_corner": ["ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]"], "power_mw": null, "drc_clean": true, "lvs_clean": true}]

alu_w16_7ops_sky130_500mhz/flow/alu_w16_7ops.gds.gz

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+version https://git-lfs.github.com/spec/v1
+oid sha256:fdbaa614268db8159f505421fdcf8989e05f1ee82f3b074977b9f420780e8353
+size 120557

alu_w16_7ops_sky130_500mhz/flow/alu_w16_7ops.spef.gz

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+version https://git-lfs.github.com/spec/v1
+oid sha256:c684c1a49ff3ae875bfc6ed7c2e9e0a4f362ece923b231b9a0f286aeabb8f295
+size 138540

alu_w16_7ops_sky130_500mhz/flow/design_only.cdl.gz

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+version https://git-lfs.github.com/spec/v1
+oid sha256:030bffc1d1876175b1b1c6673a41141feeec6b386039ca6d2dfd23fad8353173
+size 5470

alu_w16_7ops_sky130_500mhz/flow/flow_log.txt

@@ -0,0 +1,94 @@
+╔══════════════════════════════════════════╗
+║          Zyphar Flow v1.0.0              ║
+║    Complete RTL-to-GDSII Toolchain       ║
+╚══════════════════════════════════════════╝
+
+Configuration:
+  Input:     /tmp/datagen_designs/alu_w16_7ops/alu_w16_7ops.v
+  Top:       alu_w16_7ops
+  PDK:       Sky130
+  Frequency: 500 MHz
+  Clock:     clk
+  Output:    /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow
+
+Starting flow...
+
+=== Step 1/3: Synthesis ===
+Synthesis complete: 365 cells, 0.00 um^2
+  Wires: 353, Modules: 1
+  Netlist: /tmp/zyphar_netlist_936091.v
+  Duration: 0.6s
+
+--- CDC Analysis ---
+  No clock domain crossings detected
+
+--- Native Re-Optimization ---
+  Skipped (no Liberty file provided, use --liberty)
+
+=== Step 2/3: Place and Route ===
+  Input netlist: /tmp/zyphar_netlist_936091.v
+  PDK: Sky130, Freq: 500 MHz, Clock: clk
+  Utilization: 45%, Aspect ratio: 1.0, Placement density: 0.80 (auto)
+  PDN: true, Detailed route: true, Fillers: true, Antenna: true
+PnR complete: 850 instances, 0.56 utilization
+  DEF: /tmp/zyphar_pnr_936091.def
+  WNS: N/A (combinational)
+  Duration: 340.5s
+
+--- Multi-Corner STA ---
+  Using post-PnR netlist with SPEF back-annotation
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+--- Power Analysis ---
+  Power analysis skipped: No Liberty file available (use --liberty or set SKY130_LIBERTY)
+
+=== Step 3/3: GDS Generation ===
+GDS generation complete: /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/alu_w16_7ops.gds
+
+=== Signoff Checks ===
+
+--- DRC ---
+  DRC: CLEAN
+
+--- LVS ---
+  LVS: CLEAN
+
+═══════════════════════════════════════════
+                  RESULTS                  
+═══════════════════════════════════════════
+
+Synthesis:
+  Cells:     365
+  Netlist:   /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/netlist.v
+
+Place & Route:
+  DEF:       /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/output.def
+  WNS:       N/A (combinational)
+  Util:      56.0%
+  Instances: 850
+  Area:      2643.00 um^2
+
+GDSII:       /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/alu_w16_7ops.gds
+
+Multi-Corner STA:
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+SPEF:        /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/alu_w16_7ops.spef
+
+Duration:    352.49s
+
+Signoff:
+  Timing:         N/A (combinational)
+  DRC:            CLEAN
+  DRC report:     /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/drc_report.rpt
+  LVS:            CLEAN
+  LVS report:     /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/lvs_report.lyrdb
+
+  SIGNOFF: PASS
+
+Flow completed successfully!
+

alu_w16_7ops_sky130_500mhz/flow/klayout_lvs.log

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+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:119
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:120
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:121
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:122
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:123
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:126
+    Polygons (raw): 369 (flat)  62 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"&" in: lvs_deck_patched.lylvs:130
+    Polygons (raw): 418 (flat)  78 (hierarchical)
+    Elapsed: 0.010s  Memory: 1138.00M
+"&" in: lvs_deck_patched.lylvs:130
+    Polygons (raw): 418 (flat)  78 (hierarchical)
+    Elapsed: 0.000s  Memory: 1148.00M
+"&" in: lvs_deck_patched.lylvs:131
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1168.00M
+"&" in: lvs_deck_patched.lylvs:131
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1148.00M
+"&" in: lvs_deck_patched.lylvs:132
+    Polygons (raw): 1347 (flat)  312 (hierarchical)
+    Elapsed: 0.010s  Memory: 1148.00M
+"-" in: lvs_deck_patched.lylvs:133
+    Polygons (raw): 1765 (flat)  390 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1158.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 426 (flat)  64 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 426 (flat)  64 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"&" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 1347 (flat)  312 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1169.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"&" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 425 (flat)  78 (hierarchical)
+    Elapsed: 0.030s  Memory: 1149.00M
+"&" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 423 (flat)  76 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1159.00M
+"&" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 1169.00M
+"&" in: lvs_deck_patched.lylvs:140
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.010s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:141
+    Polygons (raw): 1765 (flat)  386 (hierarchical)
+    Elapsed: 0.010s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.010s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 1342 (flat)  310 (hierarchical)
+    Elapsed: 0.010s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"extract_devices" in: lvs_deck_patched.lylvs:151
+    Elapsed: 0.010s  Memory: 1141.00M
+"extract_devices" in: lvs_deck_patched.lylvs:152
+    Elapsed: 0.020s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:153
+    Elapsed: 0.020s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:156
+    Elapsed: 0.020s  Memory: 1143.00M
+"extract_devices" in: lvs_deck_patched.lylvs:157
+    Elapsed: 0.020s  Memory: 1143.00M
+"extract_devices" in: lvs_deck_patched.lylvs:158
+    Elapsed: 0.010s  Memory: 1143.00M
+"extract_devices" in: lvs_deck_patched.lylvs:159
+    Elapsed: 0.020s  Memory: 1143.00M
+"netlist" in: lvs_deck_patched.lylvs:199
+    Elapsed: 0.140s  Memory: 1149.00M
+Flatten layout cell (no schematic): VIA_L1M1_PR_MR
+Flatten layout cell (no schematic): VIA_M1M2_PR
+Flatten layout cell (no schematic): VIA_M2M3_PR
+Flatten layout cell (no schematic): VIA_via3_4_1600_480_1_4_400_400
+Flatten layout cell (no schematic): VIA_via2_3_1600_480_1_5_320_320
+Flatten layout cell (no schematic): VIA_via5_6_1600_1600_1_1_1600_1600
+Flatten layout cell (no schematic): VIA_via4_5_1600_480_1_4_400_400
+Flatten layout cell (no schematic): VIA_M3M4_PR
+Flatten layout cell (no schematic): VIA_L1M1_PR
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A222OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DIODE_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD1_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S2S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S4S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S6S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCIN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCON_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_BLEEDER_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MACRO_SPARECELL
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CONB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBEC_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBE_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_4
+Writing netlist: /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/lvs_extracted.cir ..
+Writing LVS database: /tmp/datagen_output/alu_w16_7ops_sky130_500mhz/flow/lvs_report.lyrdb ..
+Total elapsed: 0.750s  Memory: 1157.00M
+INFO : Congratulations! Netlists match.
+
+=== stderr ===

alu_w16_7ops_sky130_500mhz/flow/lvs_cleaned.gds.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:588eb15060dd126568ac242f90dde6a67050b21af3733922ff29dbbf03245d22
+size 115191

alu_w16_7ops_sky130_500mhz/flow/lvs_deck_patched.lylvs

@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>lvs</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>lvs_scripts</group-name>
+ <menu-path>tools_menu.lvs.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
+ <text>#
+# Extraction for SKY130
+#
+############################
+
+# optionnal for a batch launch :   klayout -b -rd in_gds=my_layout.gds -rd report_file=my_report.lyrdb -rd cdl_file=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r sky130.lylvs
+if $in_gds
+  source($in_gds)
+end
+
+if $report_file
+  report_lvs($report_file)
+else
+  report_lvs("lvs_report.lvsdb")
+end
+
+if $cdl_file
+#reference netlist
+   schematic($cdl_file)
+else 
+   schematic("sky130hd.cdl")
+end
+
+# true: use net names instead of numbers
+# false: use numbers for nets
+spice_with_net_names = true
+
+# true: put in comments with details
+# false: no comments
+spice_with_comments = false
+
+if $target_netlist
+  target_netlist($target_netlist)
+else
+   # target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.") 
+   target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments),  "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
+end
+
+# Hierarchical mode
+deep
+# Use 4 CPU cores
+threads(4)
+# Print details
+verbose(true)
+
+
+# layers definitions
+########################
+BOUND  = polygons(235, 4)
+DNWELL  = polygons(64, 18)
+PWRES  = polygons(64, 13)
+NWELL  = polygons(64, 20)
+NWELLTXT  = input(64, 5)
+NWELLPIN  = polygons(64, 16)
+SUBTXT  = input(122, 5)
+SUBPIN  = input(64, 59)
+DIFF  = polygons(65, 20)
+TAP  = polygons(65, 44)
+PSDM  = polygons(94, 20)
+NSDM  = polygons(93, 44)
+LVTN  = polygons(125, 44)
+HVTR  = polygons(18, 20)
+HVTP  = polygons(78, 44)
+SONOS  = polygons(80, 20)
+COREID  = polygons(81, 2)
+STDCELL  = polygons(81, 4)
+NPNID  = polygons(82, 20)
+PNPID  = polygons(82, 44)
+RPM  = polygons(86, 20)
+URPM  = polygons(79, 20)
+LDNTM  = polygons(11, 44)
+HVNTM  = polygons(125, 20)
+POLY  = polygons(66, 20)
+POLYTXT  = input(66, 5)
+POLYPIN  = polygons(66, 16)
+HVI  = polygons(75, 20)
+LICON  = polygons(66, 44)
+NPC  = polygons(95, 20)
+DIFFRES  = polygons(65, 13)
+POLYRES  = polygons(66, 13)
+POLYSHO  = polygons(66, 15)
+DIODE  = polygons(81, 23)
+LI  = polygons(67, 20)
+LITXT  = input(67, 5)
+LIPIN  = polygons(67, 16)
+LIRES  = polygons(67, 13)
+MCON  = polygons(67, 44)
+MET1  = polygons(68, 20)
+MET1TXT  = input(68, 5)
+MET1PIN  = polygons(68, 16)
+MET1RES  = polygons(68, 13)
+VIA1  = polygons(68, 44)
+MET2  = polygons(69, 20)
+MET2TXT  = input(69, 5)
+MET2PIN  = polygons(69, 16)
+MET2RES  = polygons(69, 13)
+VIA2  = polygons(69, 44)
+MET3  = polygons(70, 20)
+MET3TXT  = input(70, 5)
+MET3PIN  = polygons(70, 16)
+MET3RES  = polygons(70, 13)
+VIA3  = polygons(70, 44)
+MET4  = polygons(71, 20)
+MET4TXT  = input(71, 5)
+MET4PIN  = polygons(71, 16)
+MET4RES  = polygons(71, 13)
+VIA4  = polygons(71, 44)
+MET5  = polygons(72, 20)
+MET5TXT  = input(72, 5)
+MET5PIN  = polygons(72, 16)
+MET5RES  = polygons(72, 13)
+RDL  = polygons(74, 20)
+RDLTXT  = input(74, 5)
+RDLPIN  = polygons(74, 16)
+GLASS  = polygons(76, 20)
+CAPM  = polygons(89, 44)
+CAPM2  = polygons(97, 44)
+LOWTAPD  = polygons(81, 14)
+FILLOBSM1  = polygons(62, 24)
+FILLOBSM2  = polygons(105, 52)
+FILLOBSM3  = polygons(107, 24)
+FILLOBSM4  = polygons(112, 4)
+NCM = polygons(92, 44)
+
+# Bulk layer for terminal provisioning
+SUB = polygons(236, 0)
+# SUB = polygon_layer
+
+# Computed layers
+PDIFF = DIFF &amp; NWELL &amp; PSDM
+NTAP = TAP &amp; NWELL &amp; NSDM
+PGATE = PDIFF &amp; POLY
+PSD = PDIFF - PGATE
+STD_PGATE = PGATE - HVTP - NCM - HVI
+HVT_PGATE = PGATE &amp; HVTP - NCM - HVI
+HV5_PGATE = PGATE - HVTP - NCM &amp; HVI
+  
+NDIFF = DIFF - NWELL &amp; NSDM
+PTAP = TAP - NWELL &amp; PSDM
+NGATE = NDIFF &amp; POLY
+NSD = NDIFF - NGATE
+STD_NGATE = NGATE - NCM - LVTN - HVI
+LVT_NGATE = NGATE - NCM &amp; LVTN - HVI
+HV5_NGATE = NGATE - NCM - LVTN &amp; HVI
+HV5NA_NGATE = NGATE - NCM &amp; LVTN &amp; HVI
+
+# drawing to physical
+device_scaling(1000000)
+
+# PMOS transistor device extraction
+extract_devices(mos4("pfet_01v8"), { "SD" =&gt; PSD, "G" =&gt; STD_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_01v8_hvt"), { "SD" =&gt; PSD, "G" =&gt; HVT_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_g5v0d10v5"), { "SD" =&gt; PSD, "G" =&gt; HV5_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+
+# NMOS transistor device extraction
+extract_devices(mos4("nfet_01v8"), { "SD" =&gt; NSD, "G" =&gt; STD_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_lvt"), { "SD" =&gt; NSD, "G" =&gt; LVT_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_g5v0d10v5"), { "SD" =&gt; NSD, "G" =&gt; HV5_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_nvt"), { "SD" =&gt; NSD, "G" =&gt; HV5NA_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(SUB,  PTAP)
+connect(NWELL,  NTAP)
+connect(LICON,   PTAP)
+connect(LICON,   NTAP)
+connect(PSD,    LICON)
+connect(NSD,    LICON)
+connect(POLY,   LICON)
+connect(LICON,   LI)
+connect(LI, MCON)
+connect(MCON,   MET1)
+connect(MET1,VIA1)
+connect(VIA1,   MET2)
+connect(MET2, VIA2)
+connect(VIA2,   MET3)
+connect(MET3, VIA3)
+connect(VIA3,   MET4)
+connect(MET4, VIA4)
+connect(VIA4,   MET5)
+# Attaching labels
+connect(SUB, SUBTXT)
+connect(SUB, SUBPIN)
+connect(NWELL, NWELLTXT)
+connect(POLY, POLYTXT)
+connect(LI, LITXT)
+connect(MET1, MET1TXT)
+connect(MET2, MET2TXT)
+connect(MET3, MET3TXT)
+connect(MET4, MET4TXT)
+connect(MET5, MET5TXT)
+
+# Global
+connect_global(SUB, "VNB")
+
+# Actually performs the extraction
+netlist # ... not really required
+
+# Flatten cells which are present in one netlist only
+align
+
+# Flat LVS: flatten all cells to transistor level.
+# This avoids hierarchical port identification issues where
+# KLayout misses output pins on cells whose LI shapes are
+# only on the PIN datatype (67/16) not DRAWING (67/20).
+netlist.flatten_circuit("*")
+schematic.flatten_circuit("*")
+
+netlist.make_top_level_pins
+netlist.combine_devices
+netlist.purge
+schematic.combine_devices
+schematic.purge
+
+# Tolerances for the devices extracted parameters
+#  tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance])
+tolerance("pfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+
+# NangateOpenCellLibrary Digital gates input equivalence :
+equivalent_pins("*AND2_1", "A", "B")
+equivalent_pins("*AND2_2", "A", "B")
+equivalent_pins("*AND2_4", "A", "B")
+equivalent_pins("*AND3_1", "A", "B", "C")
+equivalent_pins("*AND3_2", "A", "B", "C")
+equivalent_pins("*AND3_4", "A", "B", "C")
+equivalent_pins("*AND4_1", "A", "B", "C", "D")
+equivalent_pins("*AND4_2", "A", "B", "C", "D")
+equivalent_pins("*AND4_4", "A", "B", "C", "D")
+equivalent_pins("*NAND2_1", "A", "B")
+equivalent_pins("*NAND2_2", "A", "B")
+equivalent_pins("*NAND2_4", "A", "B")
+equivalent_pins("*NAND3_1", "A", "B", "C")
+equivalent_pins("*NAND3_2", "A", "B", "C")
+equivalent_pins("*NAND3_4", "A", "B", "C")
+equivalent_pins("*NAND4_X1", "A", "B", "C", "D")
+equivalent_pins("*NAND4_2", "A", "B", "C", "D")
+equivalent_pins("*NAND4_4", "A", "B", "C", "D")
+equivalent_pins("*OR2_1", "A", "B")
+equivalent_pins("*OR2_2", "A", "B")
+equivalent_pins("*OR2_4", "A", "B")
+equivalent_pins("*OR3_1", "A", "B", "C")
+equivalent_pins("*OR3_2", "A", "B", "C")
+equivalent_pins("*OR3_4", "A", "B", "C")
+equivalent_pins("*OR4_1", "A", "B", "C", "D")
+equivalent_pins("*OR4_2", "A", "B", "C", "D")
+equivalent_pins("*OR4_4", "A", "B", "C", "D")
+equivalent_pins("*NOR2_1", "A", "B")
+equivalent_pins("*NOR2_2", "A", "B")
+equivalent_pins("*NOR2_4", "A", "B")
+equivalent_pins("*NOR3_1", "A", "B", "C")
+equivalent_pins("*NOR3_2", "A", "B", "C")
+equivalent_pins("*NOR3_4", "A", "B", "C")
+equivalent_pins("*NOR4_1", "A", "B", "C", "D")
+equivalent_pins("*NOR4_2", "A", "B", "C", "D")
+equivalent_pins("*NOR4_4", "A", "B", "C", "D")
+equivalent_pins("*XOR2_1", "A", "B")
+equivalent_pins("*XOR2_2", "A", "B")
+equivalent_pins("*XNOR2_1", "A", "B")
+equivalent_pins("*XNOR2_2", "A", "B")
+
+#max_res(1000000)
+#min_caps(1e-15)
+
+if ! compare 
+  #raise "ERROR : Netlists don't match"
+  puts "ERROR : Netlists don't match"
+else
+  puts "INFO : Congratulations! Netlists match."
+end</text>
+</klayout-macro>

alu_w16_7ops_sky130_500mhz/flow/lvs_reference.cdl.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d628037aa289decb89b4d29091b16bfd3098cc13c78dbb6c468cf225fe7ce316
+size 29359

alu_w16_7ops_sky130_500mhz/flow/lvs_report.lyrdb

@@ -0,0 +1,4516 @@
+#%lvsdb-klayout
+J(
+ W(alu_w16_7ops)
+ U(0.001)
+ L(l3 '64/20')
+ L(l29 '64/5')
+ L(l27)
+ L(l28 '64/59')
+ L(l4 '66/20')
+ L(l30)
+ L(l15 '66/44')
+ L(l16 '67/20')
+ L(l31 '67/5')
+ L(l17 '67/44')
+ L(l18 '68/20')
+ L(l32 '68/5')
+ L(l19 '68/44')
+ L(l20 '69/20')
+ L(l33 '69/5')
+ L(l21 '69/44')
+ L(l22 '70/20')
+ L(l34)
+ L(l23 '70/44')
+ L(l24 '71/20')
+ L(l35)
+ L(l25 '71/44')
+ L(l26 '72/20')
+ L(l36 '72/5')
+ L(l9 '236/0')
+ L(l14)
+ L(l2)
+ L(l13)
+ L(l8)
+ C(l3 l3 l29 l14)
+ C(l29 l3 l29)
+ C(l27 l27 l9)
+ C(l28 l28 l9)
+ C(l4 l4 l30 l15)
+ C(l30 l4 l30)
+ C(l15 l4 l15 l16 l14 l2 l13 l8)
+ C(l16 l15 l16 l31 l17)
+ C(l31 l16 l31)
+ C(l17 l16 l17 l18)
+ C(l18 l17 l18 l32 l19)
+ C(l32 l18 l32)
+ C(l19 l18 l19 l20)
+ C(l20 l19 l20 l33 l21)
+ C(l33 l20 l33)
+ C(l21 l20 l21 l22)
+ C(l22 l21 l22 l34 l23)
+ C(l34 l22 l34)
+ C(l23 l22 l23 l24)
+ C(l24 l23 l24 l35 l25)
+ C(l35 l24 l35)
+ C(l25 l24 l25 l26)
+ C(l26 l25 l26 l36)
+ C(l36 l26 l36)
+ C(l9 l27 l28 l9 l13)
+ C(l14 l3 l15 l14)
+ C(l2 l15 l2)
+ C(l13 l15 l9 l13)
+ C(l8 l15 l8)
+ G(l9 VNB)
+ K(pfet_01v8 MOS4)
+ K(pfet_01v8_hvt MOS4)
+ K(pfet_g5v0d10v5 MOS4)
+ K(nfet_01v8 MOS4)
+ K(nfet_01v8_lvt MOS4)
+ K(nfet_g5v0d10v5 MOS4)
+ K(nfet_01v8_nvt MOS4)
+ D(D$pfet_01v8_hvt pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$1 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$2 pfet_01v8_hvt
+  T(S
+   R(l2 (-365 -500) (290 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$3 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$4 pfet_01v8_hvt
+  T(S
+   R(l2 (-380 -500) (305 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (395 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$5 pfet_01v8_hvt
+  T(S
+   R(l2 (-470 -500) (395 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (600 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$6 pfet_01v8_hvt
+  T(S
+   R(l2 (-675 -500) (600 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$7 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$8 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$9 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$10 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (295 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$11 pfet_01v8_hvt
+  T(S
+   R(l2 (-370 -500) (295 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$12 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$13 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (130 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$14 pfet_01v8_hvt
+  T(S
+   Q(l2 (-465 -500) (0 420) (130 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$15 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$16 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$17 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$18 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$19 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (340 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$20 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$21 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (310 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$22 pfet_01v8_hvt
+  T(S
+   R(l2 (-385 -500) (310 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (275 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$23 pfet_01v8_hvt
+  T(S
+   R(l2 (-350 -500) (275 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (455 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$24 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (225 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$25 pfet_01v8_hvt
+  T(S
+   R(l2 (-300 -500) (225 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (465 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$26 pfet_01v8_hvt
+  T(S
+   R(l2 (-540 -500) (465 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$27 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$28 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$29 pfet_01v8_hvt
+  T(S
+   R(l2 (-380 -500) (305 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$30 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$31 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (730 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$32 pfet_01v8_hvt
+  T(S
+   R(l2 (-805 -500) (730 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$33 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$34 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (360 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$35 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$36 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$37 pfet_01v8_hvt
+  T(S
+   Q(l2 (165 -430) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-285 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$38 pfet_01v8_hvt
+  T(S
+   Q(l2 (-550 -500) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (365 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$39 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (785 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$40 pfet_01v8_hvt
+  T(S
+   R(l2 (-860 -500) (785 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$41 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (430 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$42 pfet_01v8_hvt
+  T(S
+   R(l2 (-505 -500) (430 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$43 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$44 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$45 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -420) (260 840))
+  )
+  T(G
+   R(l4 (-75 -420) (150 840))
+  )
+  T(D
+   R(l2 (75 -420) (270 840))
+  )
+  T(B
+   R(l3 (-75 -420) (150 840))
+  )
+ )
+ D(D$pfet_01v8_hvt$46 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -420) (270 840))
+  )
+  T(G
+   R(l4 (-75 -420) (150 840))
+  )
+  T(D
+   R(l2 (75 -420) (280 840))
+  )
+  T(B
+   R(l3 (-75 -420) (150 840))
+  )
+ )
+ D(D$pfet_01v8_hvt$47 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (275 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$48 pfet_01v8_hvt
+  T(S
+   R(l2 (-350 -500) (275 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$49 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$50 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$51 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$52 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$53 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$54 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -320) (265 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (240 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$55 pfet_01v8_hvt
+  T(S
+   R(l2 (-315 -320) (240 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (280 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$56 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -320) (280 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (285 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$57 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   Q(l2 (75 -500) (0 1000) (390 0) (0 -700) (-140 0) (0 -300))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$58 pfet_01v8_hvt
+  T(S
+   Q(l2 (-465 -650) (0 1000) (390 0) (0 -700) (-140 0) (0 -300))
+  )
+  T(G
+   R(l4 (-75 -350) (150 700))
+  )
+  T(D
+   R(l2 (75 -350) (260 700))
+  )
+  T(B
+   R(l3 (-75 -350) (150 700))
+  )
+ )
+ D(D$pfet_01v8_hvt$59 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$60 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$61 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$62 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (635 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$63 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (760 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$64 pfet_01v8_hvt
+  T(S
+   R(l2 (-835 -500) (760 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (240 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$65 pfet_01v8_hvt
+  T(S
+   R(l2 (-315 -500) (240 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (450 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$66 pfet_01v8_hvt
+  T(S
+   R(l2 (-525 -500) (450 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$67 pfet_01v8_hvt
+  T(S
+   R(l2 (-410 -500) (335 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$68 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$69 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (410 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$70 pfet_01v8_hvt
+  T(S
+   R(l2 (-485 -500) (410 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$71 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$72 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$73 pfet_01v8_hvt
+  T(S
+   R(l2 (-380 -500) (305 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (325 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$74 pfet_01v8_hvt
+  T(S
+   R(l2 (-400 -500) (325 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$75 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -375) (0 1000) (260 0) (0 -415) (75 0) (0 -420) (-75 0) (0 -165))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (260 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$76 pfet_01v8_hvt
+  T(S
+   R(l2 (-395 -500) (320 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$77 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   Q(l2 (75 -500) (0 1000) (260 0) (0 -415) (75 0) (0 -420) (-75 0) (0 -165))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$78 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (310 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$79 pfet_01v8_hvt
+  T(S
+   R(l2 (-385 -500) (310 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$80 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$81 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (655 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$82 pfet_01v8_hvt
+  T(S
+   R(l2 (-730 -500) (655 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$83 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$84 pfet_01v8_hvt
+  T(S
+   R(l2 (-380 -500) (305 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$85 pfet_01v8_hvt
+  T(S
+   Q(l2 (-325 -210) (0 70) (-75 0) (0 420) (250 0) (0 -70) (75 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 285) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$86 pfet_01v8_hvt
+  T(S
+   Q(l2 (-335 -210) (0 350) (10 0) (0 70) (250 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$87 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -280) (0 70) (-75 0) (0 420) (250 0) (0 -70) (75 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-345 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$88 pfet_01v8_hvt
+  T(S
+   Q(l2 (-400 -500) (0 420) (75 0) (0 285) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$89 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (260 0) (0 -370) (-10 0) (0 -50))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$90 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -790) (0 580) (-75 0) (0 420) (395 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-335 -210) (260 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$91 pfet_01v8_hvt
+  T(S
+   Q(l2 (-395 -500) (0 580) (-75 0) (0 420) (395 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$92 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$93 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$94 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$95 pfet_01v8_hvt
+  T(S
+   Q(l2 (155 -580) (0 370) (-80 0) (0 420) (130 0) (0 210) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-345 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$96 pfet_01v8_hvt
+  T(S
+   Q(l2 (-385 -500) (0 370) (-80 0) (0 420) (130 0) (0 210) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (475 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$97 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (330 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$98 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$99 pfet_01v8_hvt
+  T(S
+   Q(l2 (-415 -500) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$100 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (350 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$101 pfet_01v8_hvt
+  T(S
+   R(l2 (-425 -500) (350 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$102 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (285 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$103 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$104 pfet_01v8_hvt
+  T(S
+   R(l2 (-390 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-125 -500) (250 1000))
+  )
+  T(D
+   R(l2 (125 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-125 -500) (250 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$105 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-125 -500) (250 1000))
+  )
+  T(D
+   R(l2 (125 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-125 -500) (250 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$106 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-125 -500) (250 1000))
+  )
+  T(D
+   R(l2 (125 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-125 -500) (250 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$107 pfet_01v8_hvt
+  T(S
+   Q(l2 (-470 -595) (0 1000) (260 0) (0 -195) (135 0) (0 -420) (-135 0) (0 -385))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (365 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$108 pfet_01v8_hvt
+  T(S
+   R(l2 (-440 -210) (365 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (920 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$109 pfet_01v8_hvt
+  T(S
+   R(l2 (-995 -210) (920 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$110 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (280 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$111 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   Q(l2 (75 -500) (0 1000) (260 0) (0 -195) (135 0) (0 -420) (-135 0) (0 -385))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$112 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (385 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$113 pfet_01v8_hvt
+  T(S
+   R(l2 (-460 -500) (385 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$114 pfet_01v8_hvt
+  T(S
+   R(l2 (-360 -500) (285 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (285 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$115 pfet_01v8_hvt
+  T(S
+   R(l2 (-360 -500) (285 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$116 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (610 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$117 pfet_01v8_hvt
+  T(S
+   R(l2 (-685 -500) (610 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (325 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$118 pfet_01v8_hvt
+  T(S
+   R(l2 (-400 -500) (325 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (415 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$119 pfet_01v8_hvt
+  T(S
+   R(l2 (-490 -500) (415 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$120 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$121 pfet_01v8_hvt
+  T(S
+   Q(l2 (-435 -450) (0 1000) (285 0) (0 -340) (75 0) (0 -420) (-75 0) (0 -240))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (285 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$122 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (375 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$123 pfet_01v8_hvt
+  T(S
+   R(l2 (-450 -500) (375 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$124 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (355 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$125 pfet_01v8_hvt
+  T(S
+   R(l2 (-430 -500) (355 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$126 pfet_01v8_hvt
+  T(S
+   R(l2 (-365 -500) (290 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$127 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   Q(l2 (75 -500) (0 1000) (285 0) (0 -340) (75 0) (0 -420) (-75 0) (0 -240))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$128 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -525) (0 315) (-75 0) (0 420) (75 0) (0 265) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-335 -210) (260 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$129 pfet_01v8_hvt
+  T(S
+   Q(l2 (-335 -500) (0 315) (-75 0) (0 420) (75 0) (0 265) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$130 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (745 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$131 pfet_01v8_hvt
+  T(S
+   R(l2 (-820 -500) (745 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (235 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$132 pfet_01v8_hvt
+  T(S
+   R(l2 (-310 -500) (235 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (470 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$133 pfet_01v8_hvt
+  T(S
+   R(l2 (-545 -500) (470 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$134 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$135 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (345 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$136 pfet_01v8_hvt
+  T(S
+   R(l2 (-420 -500) (345 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$137 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (330 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$138 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$139 pfet_01v8_hvt
+  T(S
+   Q(l2 (-415 -500) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$140 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$141 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$142 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (380 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$143 pfet_01v8_hvt
+  T(S
+   R(l2 (-455 -500) (380 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$144 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (625 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$145 pfet_01v8_hvt
+  T(S
+   R(l2 (-700 -500) (625 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$146 pfet_01v8_hvt
+  T(S
+   R(l2 (-425 -500) (350 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$147 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (265 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$148 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (290 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$149 pfet_01v8_hvt
+  T(S
+   Q(l2 (205 -430) (0 220) (-130 0) (0 420) (620 0) (0 -640))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-365 -210) (290 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$150 pfet_01v8_hvt
+  T(S
+   Q(l2 (-565 -320) (0 220) (-130 0) (0 420) (620 0) (0 -640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (265 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$151 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (520 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$152 pfet_01v8_hvt
+  T(S
+   R(l2 (-595 -500) (520 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$153 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$154 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$155 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (315 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$156 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -225) (0 15) (-75 0) (0 420) (75 0) (0 270) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-390 -210) (315 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$157 pfet_01v8_hvt
+  T(S
+   Q(l2 (-325 -500) (0 15) (-75 0) (0 420) (75 0) (0 270) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$158 pfet_01v8_hvt
+  T(S
+   R(l2 (-350 -500) (275 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$159 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$nfet_01v8 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$1 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$2 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$3 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$4 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$5 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (295 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$6 nfet_01v8
+  T(S
+   R(l8 (-370 -325) (295 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$7 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$8 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$9 nfet_01v8
+  T(S
+   Q(l8 (-410 -325) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$10 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$11 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$12 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$13 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$14 nfet_01v8
+  T(S
+   Q(l8 (-410 -325) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$15 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$16 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (310 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$17 nfet_01v8
+  T(S
+   R(l8 (-385 -325) (310 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$18 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (455 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$19 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (285 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$20 nfet_01v8
+  T(S
+   R(l8 (-360 -325) (285 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (355 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$21 nfet_01v8
+  T(S
+   R(l8 (-430 -325) (355 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$22 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (305 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$23 nfet_01v8
+  T(S
+   R(l8 (-380 -325) (305 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (305 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$24 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (325 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$25 nfet_01v8
+  T(S
+   R(l8 (-400 -325) (325 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (215 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$26 nfet_01v8
+  T(S
+   R(l8 (-290 -325) (215 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$27 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (300 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$28 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$29 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$30 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$31 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$32 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$33 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$34 nfet_01v8
+  T(S
+   Q(l8 (-640 -325) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$35 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (610 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$36 nfet_01v8
+  T(S
+   R(l8 (-685 -325) (610 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (340 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$37 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (230 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$38 nfet_01v8
+  T(S
+   R(l8 (-305 -325) (230 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (470 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$39 nfet_01v8
+  T(S
+   R(l8 (-545 -325) (470 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (220 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$40 nfet_01v8
+  T(S
+   R(l8 (-295 -325) (220 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$41 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (285 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$42 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (790 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$43 nfet_01v8
+  T(S
+   R(l8 (-865 -325) (790 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$44 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$45 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$46 nfet_01v8
+  T(S
+   Q(l8 (150 -440) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-335 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$47 nfet_01v8
+  T(S
+   Q(l8 (-335 -325) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$48 nfet_01v8
+  T(S
+   R(l8 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (280 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$49 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (280 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$50 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (265 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$51 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$52 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$53 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$54 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$55 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$56 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (605 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$57 nfet_01v8
+  T(S
+   Q(l8 (-325 -325) (0 380) (-10 0) (0 270) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$58 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (360 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$59 nfet_01v8
+  T(S
+   R(l8 (-435 -325) (360 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$60 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   Q(l8 (75 -325) (0 650) (250 0) (0 -360) (10 0) (0 -290))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$61 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$62 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (410 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$63 nfet_01v8
+  T(S
+   R(l8 (-485 -325) (410 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (290 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$64 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$65 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$66 nfet_01v8
+  T(S
+   R(l8 (-440 -325) (365 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (325 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$67 nfet_01v8
+  T(S
+   R(l8 (-400 -325) (325 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$68 nfet_01v8
+  T(S
+   R(l8 (-415 -325) (340 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$69 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   Q(l8 (75 -325) (0 650) (335 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$70 nfet_01v8
+  T(S
+   Q(l8 (-410 -440) (0 650) (335 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$71 nfet_01v8
+  T(S
+   R(l8 (-485 -325) (410 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$72 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$73 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (310 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$74 nfet_01v8
+  T(S
+   R(l8 (-385 -325) (310 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$75 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (360 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$76 nfet_01v8
+  T(S
+   R(l8 (-305 -325) (230 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$77 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (310 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$78 nfet_01v8
+  T(S
+   R(l8 (-385 -325) (310 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$79 nfet_01v8
+  T(S
+   Q(l8 (-335 -210) (0 280) (5 0) (0 5) (5 0) (0 135) (250 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$80 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (255 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$81 nfet_01v8
+  T(S
+   Q(l8 (240 -240) (0 30) (-165 0) (0 420) (150 0) (0 200) (280 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-330 -210) (255 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$82 nfet_01v8
+  T(S
+   Q(l8 (-340 -325) (0 30) (-165 0) (0 420) (150 0) (0 200) (280 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$83 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (260 0) (0 -285) (-10 0) (0 -135))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$84 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (320 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$85 nfet_01v8
+  T(S
+   Q(l8 (-470 -325) (0 420) (75 0) (0 230) (320 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$86 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (770 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$87 nfet_01v8
+  T(S
+   R(l8 (-845 -325) (770 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (320 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$88 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (790 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$89 nfet_01v8
+  T(S
+   R(l8 (-865 -325) (790 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$90 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (350 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$91 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$92 nfet_01v8
+  T(S
+   Q(l8 (205 -350) (0 140) (-130 0) (0 420) (130 0) (0 90) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-345 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$93 nfet_01v8
+  T(S
+   Q(l8 (-335 -325) (0 140) (-130 0) (0 420) (130 0) (0 90) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$94 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$95 nfet_01v8
+  T(S
+   Q(l8 (150 -240) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-345 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$96 nfet_01v8
+  T(S
+   Q(l8 (-340 -325) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$97 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$98 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (350 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$99 nfet_01v8
+  T(S
+   R(l8 (-425 -325) (350 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$100 nfet_01v8
+  T(S
+   R(l8 (-340 -275) (265 550))
+  )
+  T(G
+   R(l4 (-75 -275) (150 550))
+  )
+  T(D
+   R(l8 (75 -275) (210 550))
+  )
+  T(B
+   R(l9 (-75 -275) (150 550))
+  )
+ )
+ D(D$nfet_01v8$101 nfet_01v8
+  T(S
+   R(l8 (-285 -275) (210 550))
+  )
+  T(G
+   R(l4 (-75 -275) (150 550))
+  )
+  T(D
+   R(l8 (75 -275) (280 550))
+  )
+  T(B
+   R(l9 (-75 -275) (150 550))
+  )
+ )
+ D(D$nfet_01v8$102 nfet_01v8
+  T(S
+   R(l8 (-355 -275) (280 550))
+  )
+  T(G
+   R(l4 (-75 -275) (150 550))
+  )
+  T(D
+   R(l8 (75 -275) (210 550))
+  )
+  T(B
+   R(l9 (-75 -275) (150 550))
+  )
+ )
+ D(D$nfet_01v8$103 nfet_01v8
+  T(S
+   R(l8 (-285 -275) (210 550))
+  )
+  T(G
+   R(l4 (-75 -275) (150 550))
+  )
+  T(D
+   R(l8 (75 -275) (265 550))
+  )
+  T(B
+   R(l9 (-75 -275) (150 550))
+  )
+ )
+ D(D$nfet_01v8$104 nfet_01v8
+  T(S
+   Q(l8 (-470 -210) (0 650) (260 0) (0 -230) (135 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (330 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$105 nfet_01v8
+  T(S
+   R(l8 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (475 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$106 nfet_01v8
+  T(S
+   R(l8 (-550 -210) (475 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (330 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$107 nfet_01v8
+  T(S
+   R(l8 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (690 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$108 nfet_01v8
+  T(S
+   R(l8 (-765 -210) (690 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$109 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   Q(l8 (75 -325) (0 650) (260 0) (0 -230) (135 0) (0 -420))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$110 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (385 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$111 nfet_01v8
+  T(S
+   R(l8 (-460 -325) (385 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$112 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (345 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$113 nfet_01v8
+  T(S
+   R(l8 (-420 -325) (345 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (385 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$114 nfet_01v8
+  T(S
+   R(l8 (-460 -325) (385 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (520 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$115 nfet_01v8
+  T(S
+   R(l8 (-595 -325) (520 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (325 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$116 nfet_01v8
+  T(S
+   R(l8 (-400 -325) (325 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (415 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$117 nfet_01v8
+  T(S
+   R(l8 (-490 -325) (415 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$118 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (300 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$119 nfet_01v8
+  T(S
+   R(l8 (-380 -325) (305 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (375 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$120 nfet_01v8
+  T(S
+   R(l8 (-450 -325) (375 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (230 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$121 nfet_01v8
+  T(S
+   R(l8 (-305 -325) (230 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (425 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$122 nfet_01v8
+  T(S
+   R(l8 (-500 -325) (425 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$123 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   Q(l8 (75 -325) (0 650) (360 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$124 nfet_01v8
+  T(S
+   Q(l8 (-435 -440) (0 650) (360 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (355 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$125 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$126 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (355 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$127 nfet_01v8
+  T(S
+   R(l8 (-430 -325) (355 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (345 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$128 nfet_01v8
+  T(S
+   R(l8 (-420 -325) (345 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$129 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (330 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$130 nfet_01v8
+  T(S
+   R(l8 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$131 nfet_01v8
+  T(S
+   Q(l8 (-340 -325) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$132 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (305 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$133 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$134 nfet_01v8
+  T(S
+   R(l8 (-440 -325) (365 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$135 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$136 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (625 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$137 nfet_01v8
+  T(S
+   R(l8 (-700 -325) (625 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$138 nfet_01v8
+  T(S
+   R(l8 (-425 -325) (350 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$139 nfet_01v8
+  T(S
+   R(l8 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (265 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$140 nfet_01v8
+  T(S
+   Q(l8 (-415 -325) (0 420) (75 0) (0 230) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (440 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$141 nfet_01v8
+  T(S
+   R(l8 (-515 -325) (440 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$142 nfet_01v8
+  T(S
+   R(l8 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$143 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (460 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$144 nfet_01v8
+  T(S
+   R(l8 (-535 -210) (460 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (265 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$145 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (300 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$146 nfet_01v8
+  T(S
+   R(l8 (-375 -325) (300 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$147 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (520 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$148 nfet_01v8
+  T(S
+   R(l8 (-595 -325) (520 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$149 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$150 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (240 0) (0 230) (250 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$151 nfet_01v8
+  T(S
+   Q(l8 (-565 -325) (0 420) (240 0) (0 230) (250 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$152 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (305 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$153 nfet_01v8
+  T(S
+   R(l8 (-380 -325) (305 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$154 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$155 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (290 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$156 nfet_01v8
+  T(S
+   R(l8 (-365 -325) (290 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+)
+H(
+ K(NFET_01V8 MOS4)
+ K(PFET_01V8_HVT MOS4)
+ K(RES RES)
+)
+Z(
+)

alu_w16_7ops_sky130_500mhz/flow/output.def.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:68aeafe5a0f4df8d3de9ae50c91ca8240f914e77ef185d5f3e37c99bbccc4e8f
+size 58171

alu_w16_7ops_sky130_500mhz/result.json

@@ -0,0 +1,45 @@
+{
+  "run_id": "alu_w16_7ops_sky130_500mhz",
+  "design": "alu_w16_7ops",
+  "pdk": "sky130",
+  "frequency_mhz": 500,
+  "status": "success",
+  "metadata": {
+    "type": "alu",
+    "width": 16,
+    "ops": [
+      "add",
+      "sub",
+      "and",
+      "or",
+      "xor",
+      "shl",
+      "shr"
+    ],
+    "sel_width": 3,
+    "combinational": true,
+    "name": "alu_w16_7ops",
+    "files": {
+      "design": "alu_w16_7ops.v",
+      "testbench": "alu_w16_7ops_tb.v"
+    }
+  },
+  "timings": {
+    "flow_total": 0.0,
+    "note": "reused_existing_flow",
+    "extraction": 0.31371402740478516
+  },
+  "errors": [],
+  "extracted": {
+    "geometry_patches": 51,
+    "physics_labels": 400,
+    "drc_labels": 1,
+    "pin_access": 53,
+    "cell_neighborhoods": 213,
+    "timing_contexts": 1,
+    "power_grid": 374,
+    "mesoscale_blocks": 16,
+    "trajectory_snapshots": 9,
+    "deepgate_aig": 1
+  }
+}