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Xenn007
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synth-layout-v1

Tasks:
Other
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1B<n<10B
Tags:
eda
chip-design
vlsi
synthesis
place-and-route
drc
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  1. alu_w4_5ops_sky130_50mhz/flow/output.def.gz +3 -0
  2. shiftreg_w16_d4_sipo_sky130_1000mhz/flow/design_only.cdl.gz +3 -0
  3. shiftreg_w16_d4_siso_sky130_1000mhz/flow/lvs_cleaned.gds.gz +3 -0
  4. shiftreg_w16_d4_siso_sky130_1000mhz/flow/lvs_reference.cdl.gz +3 -0
  5. shiftreg_w16_d4_siso_sky130_1000mhz/flow/output.def.gz +3 -0
  6. shiftreg_w16_d4_siso_sky130_1000mhz/flow/shiftreg_w16_d4_siso.gds.gz +3 -0
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  8. shiftreg_w16_d4_siso_sky130_100mhz/flow/design_only.cdl.gz +3 -0
  9. shiftreg_w16_d4_siso_sky130_100mhz/flow/lvs_cleaned.gds.gz +3 -0
  10. shiftreg_w16_d4_siso_sky130_100mhz/flow/lvs_reference.cdl.gz +3 -0
  11. shiftreg_w16_d4_siso_sky130_100mhz/flow/output.def.gz +3 -0
  12. shiftreg_w16_d4_siso_sky130_100mhz/flow/shiftreg_w16_d4_siso.gds.gz +3 -0
  13. shiftreg_w16_d4_siso_sky130_100mhz/flow/shiftreg_w16_d4_siso.spef.gz +3 -0
  14. shiftreg_w16_d4_siso_sky130_200mhz/flow/lvs_cleaned.gds.gz +3 -0
  15. shiftreg_w16_d4_siso_sky130_500mhz/flow/output.def.gz +3 -0
  16. shiftreg_w16_d4_siso_sky130_50mhz/flow/lvs_reference.cdl.gz +3 -0
  17. shiftreg_w16_d4_siso_sky130_50mhz/flow/shiftreg_w16_d4_siso.spef.gz +3 -0
  18. shiftreg_w16_d8_sipo_sky130_1000mhz/flow/lvs_cleaned.gds.gz +3 -0
  19. shiftreg_w16_d8_sipo_sky130_1000mhz/flow/shiftreg_w16_d8_sipo.spef.gz +3 -0
  20. shiftreg_w16_d8_sipo_sky130_100mhz/flow/design_only.cdl.gz +3 -0
  21. shiftreg_w16_d8_sipo_sky130_100mhz/flow/lvs_cleaned.gds.gz +3 -0
  22. shiftreg_w16_d8_sipo_sky130_100mhz/flow/lvs_reference.cdl.gz +3 -0
  23. shiftreg_w16_d8_sipo_sky130_100mhz/flow/output.def.gz +3 -0
  24. shiftreg_w16_d8_sipo_sky130_100mhz/flow/shiftreg_w16_d8_sipo.gds.gz +3 -0
  25. shiftreg_w16_d8_sipo_sky130_100mhz/flow/shiftreg_w16_d8_sipo.spef.gz +3 -0
  26. shiftreg_w16_d8_sipo_sky130_200mhz/flow/design_only.cdl.gz +3 -0
  27. shiftreg_w16_d8_sipo_sky130_200mhz/flow/lvs_cleaned.gds.gz +3 -0
  28. shiftreg_w16_d8_sipo_sky130_200mhz/flow/lvs_reference.cdl.gz +3 -0
  29. shiftreg_w16_d8_sipo_sky130_200mhz/flow/output.def.gz +3 -0
  30. shiftreg_w16_d8_sipo_sky130_200mhz/flow/shiftreg_w16_d8_sipo.gds.gz +3 -0
  31. shiftreg_w16_d8_sipo_sky130_200mhz/flow/shiftreg_w16_d8_sipo.spef.gz +3 -0
  32. shiftreg_w16_d8_sipo_sky130_500mhz/flow/design_only.cdl.gz +3 -0
  33. shiftreg_w16_d8_sipo_sky130_500mhz/flow/lvs_cleaned.gds.gz +3 -0
  34. shiftreg_w16_d8_sipo_sky130_500mhz/flow/lvs_reference.cdl.gz +3 -0
  35. shiftreg_w16_d8_sipo_sky130_500mhz/flow/output.def.gz +3 -0
  36. shiftreg_w16_d8_sipo_sky130_500mhz/flow/shiftreg_w16_d8_sipo.gds.gz +3 -0
  37. shiftreg_w16_d8_sipo_sky130_500mhz/flow/shiftreg_w16_d8_sipo.spef.gz +3 -0
  38. shiftreg_w16_d8_sipo_sky130_50mhz/flow/design_only.cdl.gz +3 -0
  39. shiftreg_w16_d8_sipo_sky130_50mhz/flow/lvs_cleaned.gds.gz +3 -0
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  41. shiftreg_w16_d8_sipo_sky130_50mhz/flow/output.def.gz +3 -0
  42. shiftreg_w16_d8_sipo_sky130_50mhz/flow/shiftreg_w16_d8_sipo.gds.gz +3 -0
  43. shiftreg_w16_d8_sipo_sky130_50mhz/flow/shiftreg_w16_d8_sipo.spef.gz +3 -0
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  47. shiftreg_w16_d8_siso_sky130_50mhz/flow/output.def.gz +3 -0
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