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Xenn007
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synth-layout-v1

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Other
Size:
1B<n<10B
Tags:
eda
chip-design
vlsi
synthesis
place-and-route
drc
License:
Dataset card Data Studio Files
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  2. alu_w32_2ops_sky130_1000mhz/flow/design_only.cdl.gz +3 -0
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  5. counter_w4_down_sky130_100mhz/flow/design_only.cdl.gz +3 -0
  6. counter_w4_down_sky130_100mhz/flow/lvs_reference.cdl.gz +3 -0
  7. counter_w4_updown_sky130_1000mhz/flow/counter_w4_updown.gds.gz +3 -0
  8. counter_w4_updown_sky130_1000mhz/flow/counter_w4_updown.spef.gz +3 -0
  9. counter_w4_updown_sky130_1000mhz/flow/design_only.cdl.gz +3 -0
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  13. counter_w8_down_sky130_50mhz/flow/counter_w8_down.spef.gz +3 -0
  14. counter_w8_down_sky130_50mhz/flow/design_only.cdl.gz +3 -0
  15. counter_w8_down_sky130_50mhz/flow/lvs_reference.cdl.gz +3 -0
  16. decoder_6to64_one_hot_sky130_500mhz/flow/lvs_reference.cdl.gz +3 -0
  17. decoder_6to64_one_hot_sky130_500mhz/flow/output.def.gz +3 -0
  18. decoder_6to64_priority_sky130_1000mhz/flow/lvs_cleaned.gds.gz +3 -0
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  22. shiftreg_w4_d8_sipo_sky130_100mhz/flow/lvs_cleaned.gds.gz +3 -0
  23. shiftreg_w4_d8_sipo_sky130_100mhz/flow/shiftreg_w4_d8_sipo.gds.gz +3 -0
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